Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3994578

1

T1

2713

T2

32

T3

2360

auto[1]

1500979

1

T1

4423

T3

413

T4

5828

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1464269

1

T1

4425

T3

2550

T4

5257

auto[1]

4031288

1

T1

2711

T2

32

T3

223

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3267806

1

T3

2047

T4

4136

T5

61

auto[1]

2227751

1

T1

7136

T2

32

T3

726

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	4608670	1			T1	4353		T2	30		T3	2689
fifo_depth[1]	157054	1			T1	299		T2	2		T3	14
fifo_depth[2]	123604	1			T1	312		T3	13		T4	173
fifo_depth[3]	96942	1			T1	303		T3	12		T4	146
fifo_depth[4]	78770	1			T1	298		T3	10		T4	172
fifo_depth[5]	67387	1			T1	298		T3	9		T4	153
fifo_depth[6]	62967	1			T1	281		T3	9		T4	166
fifo_depth[7]	52373	1			T1	252		T3	8		T4	137

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

886887

1

T1

2783

T2

2

T3

84

auto[1]

4608670

1

T1

4353

T2

30

T3

2689

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5490690

1

T1

7136

T2

32

T3

2773

auto[1]

4867

1

T16

32

T29

9

T30

20

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

41379

1

T9

32

T10

3

T6

998

auto[0]

auto[0]

auto[0]

auto[1]

36017

1

T3

31

T4

116

T9

21

auto[0]

auto[0]

auto[1]

auto[0]

490054

1

T4

345

T9

5

T10

62

auto[0]

auto[0]

auto[1]

auto[1]

50651

1

T4

94

T9

2

T10

4

auto[0]

auto[1]

auto[0]

auto[0]

61298

1

T4

868

T5

14

T9

5

auto[0]

auto[1]

auto[0]

auto[1]

62640

1

T1

1849

T4

112

T15

1

auto[0]

auto[1]

auto[1]

auto[0]

70147

1

T1

934

T2

2

T3

32

auto[0]

auto[1]

auto[1]

auto[1]

74701

1

T3

21

T9

8

T10

95

auto[1]

auto[0]

auto[0]

auto[0]

146616

1

T3

1814

T4

215

T5

13

auto[1]

auto[0]

auto[0]

auto[1]

151922

1

T3

202

T4

644

T5

25

auto[1]

auto[0]

auto[1]

auto[0]

2207984

1

T4

1476

T9

605

T10

1538

auto[1]

auto[0]

auto[1]

auto[1]

143183

1

T4

1246

T5

23

T9

2349

auto[1]

auto[1]

auto[0]

auto[0]

485612

1

T1

6

T3

420

T4

2429

auto[1]

auto[1]

auto[0]

auto[1]

478785

1

T1

2570

T3

83

T4

873

auto[1]

auto[1]

auto[1]

auto[0]

491488

1

T1

1773

T2

30

T3

94

auto[1]

auto[1]

auto[1]

auto[1]

503080

1

T1

4

T3

76

T4

2743

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

187659

1

T3

1814

T4

215

T5

13

auto[0]

auto[0]

auto[0]

auto[1]

187233

1

T3

233

T4

760

T5

25

auto[0]

auto[0]

auto[1]

auto[0]

2697765

1

T4

1821

T9

610

T10

1600

auto[0]

auto[0]

auto[1]

auto[1]

193288

1

T4

1340

T5

23

T9

2351

auto[0]

auto[1]

auto[0]

auto[0]

546176

1

T1

6

T3

420

T4

3297

auto[0]

auto[1]

auto[0]

auto[1]

540990

1

T1

4419

T3

83

T4

985

auto[0]

auto[1]

auto[1]

auto[0]

561514

1

T1

2707

T2

32

T3

126

auto[0]

auto[1]

auto[1]

auto[1]

576065

1

T1

4

T3

97

T4

2743

auto[1]

auto[0]

auto[0]

auto[0]

336

1

T30

1

T130

85

T143

10

auto[1]

auto[0]

auto[0]

auto[1]

706

1

T51

1

T119

31

T130

11

auto[1]

auto[0]

auto[1]

auto[0]

273

1

T29

9

T30

19

T51

2

auto[1]

auto[0]

auto[1]

auto[1]

546

1

T103

9

T17

1

T36

1

auto[1]

auto[1]

auto[0]

auto[0]

734

1

T18

1

T119

90

T130

15

auto[1]

auto[1]

auto[0]

auto[1]

435

1

T16

1

T143

349

T68

1

auto[1]

auto[1]

auto[1]

auto[0]

121

1

T16

2

T36

5

T68

7

auto[1]

auto[1]

auto[1]

auto[1]

1716

1

T16

29

T130

496

T68

5

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	146616	1			T3	1814		T4	215		T5	13
fifo_depth[0]	auto[0]	auto[0]	auto[1]	151922	1			T3	202		T4	644		T5	25
fifo_depth[0]	auto[0]	auto[1]	auto[0]	2207984	1			T4	1476		T9	605		T10	1538
fifo_depth[0]	auto[0]	auto[1]	auto[1]	143183	1			T4	1246		T5	23		T9	2349
fifo_depth[0]	auto[1]	auto[0]	auto[0]	485612	1			T1	6		T3	420		T4	2429
fifo_depth[0]	auto[1]	auto[0]	auto[1]	478785	1			T1	2570		T3	83		T4	873
fifo_depth[0]	auto[1]	auto[1]	auto[0]	491488	1			T1	1773		T2	30		T3	94
fifo_depth[0]	auto[1]	auto[1]	auto[1]	503080	1			T1	4		T3	76		T4	2743
fifo_depth[1]	auto[0]	auto[0]	auto[0]	3322	1			T9	21		T10	3		T6	107
fifo_depth[1]	auto[0]	auto[0]	auto[1]	3129	1			T3	4		T4	11		T9	15
fifo_depth[1]	auto[0]	auto[1]	auto[0]	119819	1			T4	47		T9	3		T10	44
fifo_depth[1]	auto[0]	auto[1]	auto[1]	3460	1			T4	11		T9	1		T10	3
fifo_depth[1]	auto[1]	auto[0]	auto[0]	5701	1			T4	90		T5	2		T9	4
fifo_depth[1]	auto[1]	auto[0]	auto[1]	7018	1			T1	204		T4	12		T15	1
fifo_depth[1]	auto[1]	auto[1]	auto[0]	7468	1			T1	95		T2	2		T3	6
fifo_depth[1]	auto[1]	auto[1]	auto[1]	7137	1			T3	4		T9	7		T10	55
fifo_depth[2]	auto[0]	auto[0]	auto[0]	3142	1			T9	7		T6	110		T16	6
fifo_depth[2]	auto[0]	auto[0]	auto[1]	3088	1			T3	4		T4	15		T9	5
fifo_depth[2]	auto[0]	auto[1]	auto[0]	88516	1			T4	43		T9	1		T10	13
fifo_depth[2]	auto[0]	auto[1]	auto[1]	3226	1			T4	8		T9	1		T10	1
fifo_depth[2]	auto[1]	auto[0]	auto[0]	5467	1			T4	97		T5	1		T9	1
fifo_depth[2]	auto[1]	auto[0]	auto[1]	6418	1			T1	208		T4	10		T10	12
fifo_depth[2]	auto[1]	auto[1]	auto[0]	7064	1			T1	104		T3	4		T9	3
fifo_depth[2]	auto[1]	auto[1]	auto[1]	6683	1			T3	5		T9	1		T10	31
fifo_depth[3]	auto[0]	auto[0]	auto[0]	2552	1			T9	3		T6	130		T30	1
fifo_depth[3]	auto[0]	auto[0]	auto[1]	2244	1			T3	5		T4	14		T9	1
fifo_depth[3]	auto[0]	auto[1]	auto[0]	66076	1			T4	39		T9	1		T10	5
fifo_depth[3]	auto[0]	auto[1]	auto[1]	2629	1			T4	9		T6	35		T16	2
fifo_depth[3]	auto[1]	auto[0]	auto[0]	4664	1			T4	74		T5	1		T52	1
fifo_depth[3]	auto[1]	auto[0]	auto[1]	5849	1			T1	198		T4	10		T10	8
fifo_depth[3]	auto[1]	auto[1]	auto[0]	6526	1			T1	105		T3	5		T5	1
fifo_depth[3]	auto[1]	auto[1]	auto[1]	6402	1			T3	2		T10	6		T6	15
fifo_depth[4]	auto[0]	auto[0]	auto[0]	2639	1			T9	1		T6	121		T29	20
fifo_depth[4]	auto[0]	auto[0]	auto[1]	2240	1			T3	3		T4	13		T6	35
fifo_depth[4]	auto[0]	auto[1]	auto[0]	47839	1			T4	36		T6	10		T16	17
fifo_depth[4]	auto[0]	auto[1]	auto[1]	2699	1			T4	10		T6	33		T16	5
fifo_depth[4]	auto[1]	auto[0]	auto[0]	4878	1			T4	96		T5	3		T52	1
fifo_depth[4]	auto[1]	auto[0]	auto[1]	5730	1			T1	197		T4	17		T16	50
fifo_depth[4]	auto[1]	auto[1]	auto[0]	6553	1			T1	101		T3	4		T5	2
fifo_depth[4]	auto[1]	auto[1]	auto[1]	6192	1			T3	3		T10	2		T6	22
fifo_depth[5]	auto[0]	auto[0]	auto[0]	2179	1			T6	108		T29	1		T30	5
fifo_depth[5]	auto[0]	auto[0]	auto[1]	1882	1			T3	4		T4	7		T6	39
fifo_depth[5]	auto[0]	auto[1]	auto[0]	38877	1			T4	43		T6	13		T16	14
fifo_depth[5]	auto[0]	auto[1]	auto[1]	2470	1			T4	4		T6	38		T16	3
fifo_depth[5]	auto[1]	auto[0]	auto[0]	4312	1			T4	87		T5	2		T16	9
fifo_depth[5]	auto[1]	auto[0]	auto[1]	5430	1			T1	196		T4	12		T16	14
fifo_depth[5]	auto[1]	auto[1]	auto[0]	6240	1			T1	102		T3	3		T5	1
fifo_depth[5]	auto[1]	auto[1]	auto[1]	5997	1			T3	2		T10	1		T6	11
fifo_depth[6]	auto[0]	auto[0]	auto[0]	2426	1			T6	108		T16	8		T29	22
fifo_depth[6]	auto[0]	auto[0]	auto[1]	2112	1			T3	3		T4	4		T6	28
fifo_depth[6]	auto[0]	auto[1]	auto[0]	33284	1			T4	40		T6	16		T16	22
fifo_depth[6]	auto[0]	auto[1]	auto[1]	2932	1			T4	10		T6	29		T16	36
fifo_depth[6]	auto[1]	auto[0]	auto[0]	4581	1			T4	100		T16	17		T48	75
fifo_depth[6]	auto[1]	auto[0]	auto[1]	5593	1			T1	194		T4	12		T10	1
fifo_depth[6]	auto[1]	auto[1]	auto[0]	6167	1			T1	87		T3	4		T5	2
fifo_depth[6]	auto[1]	auto[1]	auto[1]	5872	1			T3	2		T6	18		T16	16
fifo_depth[7]	auto[0]	auto[0]	auto[0]	2050	1			T6	84		T16	2		T29	1
fifo_depth[7]	auto[0]	auto[0]	auto[1]	1643	1			T3	3		T4	15		T6	21
fifo_depth[7]	auto[0]	auto[1]	auto[0]	26115	1			T4	34		T6	12		T16	14
fifo_depth[7]	auto[0]	auto[1]	auto[1]	2493	1			T4	12		T6	29		T16	2
fifo_depth[7]	auto[1]	auto[0]	auto[0]	4013	1			T4	70		T16	36		T48	79
fifo_depth[7]	auto[1]	auto[0]	auto[1]	4793	1			T1	173		T4	6		T16	14
fifo_depth[7]	auto[1]	auto[1]	auto[0]	5651	1			T1	79		T3	3		T5	2
fifo_depth[7]	auto[1]	auto[1]	auto[1]	5615	1			T3	2		T6	19		T16	52