Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7891582	1			T1	7315		T2	94		T3	1419
all_pins[1]	7891582	1			T1	7315		T2	94		T3	1419
all_pins[2]	7891582	1			T1	7315		T2	94		T3	1419

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21319144	1			T1	21862		T2	270		T3	3276
values[0x1]	2355602	1			T1	83		T2	12		T3	981
transitions[0x0=>0x1]	2355524	1			T1	83		T2	12		T3	981
transitions[0x1=>0x0]	2355532	1			T1	83		T2	12		T3	981

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	7871815	1			T1	7305		T2	90		T3	1415
all_pins[0]	values[0x1]	19767	1			T1	10		T2	4		T3	4
all_pins[0]	transitions[0x0=>0x1]	19729	1			T1	10		T2	4		T3	4
all_pins[0]	transitions[0x1=>0x0]	2335637	1			T1	73		T2	8		T3	977
all_pins[1]	values[0x0]	7891414	1			T1	7315		T2	94		T3	1419
all_pins[1]	values[0x1]	168	1			T16	1		T29	1		T34	7
all_pins[1]	transitions[0x0=>0x1]	151	1			T16	1		T29	1		T34	5
all_pins[1]	transitions[0x1=>0x0]	19750	1			T1	10		T2	4		T3	4
all_pins[2]	values[0x0]	5555915	1			T1	7242		T2	86		T3	442
all_pins[2]	values[0x1]	2335667	1			T1	73		T2	8		T3	977
all_pins[2]	transitions[0x0=>0x1]	2335644	1			T1	73		T2	8		T3	977
all_pins[2]	transitions[0x1=>0x0]	145	1			T16	1		T29	1		T34	5