Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 509 1 T34 18 T35 4 T68 7
all_values[1] 509 1 T34 18 T35 4 T68 7
all_values[2] 509 1 T34 18 T35 4 T68 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 803 1 T34 18 T35 8 T68 10
auto[1] 724 1 T34 36 T35 4 T68 11


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 558 1 T34 21 T35 7 T68 9
auto[1] 969 1 T34 33 T35 5 T68 12


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 864 1 T34 32 T35 8 T68 13
auto[1] 663 1 T34 22 T35 4 T68 8


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 98 1 T34 1 T35 3 T68 4
all_values[0] auto[0] auto[0] auto[1] 53 1 T34 1 T132 1 T13 1
all_values[0] auto[0] auto[1] auto[0] 80 1 T34 6 T68 1 T132 2
all_values[0] auto[0] auto[1] auto[1] 44 1 T34 1 T132 4 T13 2
all_values[0] auto[1] auto[0] auto[1] 124 1 T34 7 T35 1 T68 2
all_values[0] auto[1] auto[1] auto[1] 110 1 T34 2 T132 5 T13 2
all_values[1] auto[0] auto[0] auto[0] 104 1 T34 2 T132 1 T13 1
all_values[1] auto[0] auto[0] auto[1] 56 1 T34 1 T35 1 T68 1
all_values[1] auto[0] auto[1] auto[0] 77 1 T34 3 T35 2 T68 1
all_values[1] auto[0] auto[1] auto[1] 65 1 T34 3 T68 2 T132 3
all_values[1] auto[1] auto[0] auto[1] 107 1 T34 2 T35 1 T68 1
all_values[1] auto[1] auto[1] auto[1] 100 1 T34 7 T68 2 T132 3
all_values[2] auto[0] auto[0] auto[0] 99 1 T34 3 T68 1 T132 4
all_values[2] auto[0] auto[0] auto[1] 44 1 T132 3 T13 1 T95 1
all_values[2] auto[0] auto[1] auto[0] 100 1 T34 6 T35 2 T68 2
all_values[2] auto[0] auto[1] auto[1] 44 1 T34 5 T68 1 T13 1
all_values[2] auto[1] auto[0] auto[1] 118 1 T34 1 T35 2 T68 1
all_values[2] auto[1] auto[1] auto[1] 104 1 T34 3 T68 2 T132 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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