Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
60.78	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	4	16	80.00
Crosses	82	36	46	56.10

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	2	3	60.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	1	6	85.71	100	1	1	0
sha_en	2	1	1	50.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	8	0	8	100.00	100	1	1	0
hmac_dis_x_sha_en	4	2	2	50.00	100	1	1	0
key_x_digest_mismatch	35	17	18	51.43	100	1	1	0
key_length_x_digest_size	35	17	18	51.43	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	2	3	60.00

User Defined Bins for digest_size

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
sha2_invalid	0	1	1
sha2_none	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_512	1826	1			T3	2		T4	3		T5	1
sha2_384	1743	1			T1	3		T3	2		T4	3
sha2_256	14855	1			T1	4		T2	4		T4	4

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15911

1

T1

4

T2

4

T3

2

auto[1]

2513

1

T1

3

T3

2

T4

5

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2518

1

T1

3

T3

2

T4

6

auto[1]

15906

1

T1

4

T2

4

T3

2

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

2660

1

T1

7

T2

4

T3

2

disabled

15764

1

T3

2

T4

5

T5

4

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for key_length

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
key_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	875	1			T4	2		T5	2		T9	4
key_1024	746	1			T4	2		T15	1		T5	1
key_512	856	1			T1	1		T3	2		T4	3
key_384	919	1			T1	1		T4	1		T5	1
key_256	14156	1			T1	2		T2	4		T3	2
key_128	872	1			T1	3		T5	1		T9	1

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for sha_en

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
disabled	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

18424

1

T1

7

T2

4

T3

4

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
enabled	auto[0]	auto[0]	556	1			T4	3		T5	3		T9	1
enabled	auto[0]	auto[1]	597	1			T1	3		T4	2		T15	1
enabled	auto[1]	auto[0]	910	1			T1	4		T2	4		T3	1
enabled	auto[1]	auto[1]	597	1			T3	1		T9	4		T10	2
disabled	auto[0]	auto[0]	702	1			T3	1		T5	1		T9	5
disabled	auto[0]	auto[1]	663	1			T3	1		T4	1		T5	1
disabled	auto[1]	auto[0]	13743	1			T4	2		T9	1		T10	4
disabled	auto[1]	auto[1]	656	1			T4	2		T5	2		T9	2

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	2	2	50.00	2
Automatically Generated Cross Bins	3	2	1	33.33	2
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Element holes

hmac_en	sha_en	COUNT	AT LEAST	NUMBER	STATUS
*	[disabled]	--	--	2

Covered bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

2660

1

T1

7

T2

4

T3

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

15764

1

T3

2

T4

5

T5

4

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	17	18	51.43	17
Automatically Generated Cross Bins	34	17	17	50.00	17
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid , sha2_none]	--	--	12

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_512	295	1			T4	1		T9	1		T10	1
key_none	sha2_384	277	1			T4	1		T5	1		T9	2
key_none	sha2_256	303	1			T5	1		T9	1		T10	1
key_1024	sha2_512	305	1			T4	1		T9	1		T10	1
key_1024	sha2_384	302	1			T15	1		T9	2		T52	1
key_512	sha2_512	306	1			T3	1		T4	1		T6	1
key_512	sha2_384	289	1			T3	1		T4	1		T5	1
key_512	sha2_256	261	1			T1	1		T4	1		T9	1
key_384	sha2_512	305	1			T9	1		T16	1		T29	1
key_384	sha2_384	321	1			T1	1		T4	1		T5	1
key_384	sha2_256	293	1			T9	1		T10	4		T6	1
key_256	sha2_512	311	1			T3	1		T5	1		T9	2
key_256	sha2_384	278	1			T1	1		T3	1		T5	1
key_256	sha2_256	13567	1			T1	1		T2	4		T4	2
key_128	sha2_512	304	1			T10	1		T6	1		T64	2
key_128	sha2_384	276	1			T1	1		T5	1		T9	1
key_128	sha2_256	292	1			T1	2		T10	1		T6	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

139

1

T4

1

T5

1

T9

2

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	17	18	51.43	17

Automatically Generated Cross Bins for key_length_x_digest_size

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid , sha2_none]	--	--	12

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_512	295	1			T4	1		T9	1		T10	1
key_none	sha2_384	277	1			T4	1		T5	1		T9	2
key_none	sha2_256	303	1			T5	1		T9	1		T10	1
key_1024	sha2_512	305	1			T4	1		T9	1		T10	1
key_1024	sha2_384	302	1			T15	1		T9	2		T52	1
key_1024	sha2_256	139	1			T4	1		T5	1		T9	2
key_512	sha2_512	306	1			T3	1		T4	1		T6	1
key_512	sha2_384	289	1			T3	1		T4	1		T5	1
key_512	sha2_256	261	1			T1	1		T4	1		T9	1
key_384	sha2_512	305	1			T9	1		T16	1		T29	1
key_384	sha2_384	321	1			T1	1		T4	1		T5	1
key_384	sha2_256	293	1			T9	1		T10	4		T6	1
key_256	sha2_512	311	1			T3	1		T5	1		T9	2
key_256	sha2_384	278	1			T1	1		T3	1		T5	1
key_256	sha2_256	13567	1			T1	1		T2	4		T4	2
key_128	sha2_512	304	1			T10	1		T6	1		T64	2
key_128	sha2_384	276	1			T1	1		T5	1		T9	1
key_128	sha2_256	292	1			T1	2		T10	1		T6	1