Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.76 95.58 93.55 100.00 76.32 91.33 99.49 72.04


Total test records in report: 653
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T529 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3291969150 May 23 12:57:37 PM PDT 24 May 23 12:57:42 PM PDT 24 94896258 ps
T530 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3201261062 May 23 12:57:56 PM PDT 24 May 23 12:58:00 PM PDT 24 104151099 ps
T531 /workspace/coverage/cover_reg_top/17.hmac_intr_test.4104025531 May 23 12:57:53 PM PDT 24 May 23 12:57:56 PM PDT 24 15870338 ps
T90 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2957848919 May 23 12:57:53 PM PDT 24 May 23 12:57:56 PM PDT 24 66861180 ps
T532 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2084735015 May 23 12:57:36 PM PDT 24 May 23 12:57:40 PM PDT 24 110737358 ps
T104 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2612208554 May 23 12:57:35 PM PDT 24 May 23 12:57:38 PM PDT 24 14793844 ps
T533 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.478158402 May 23 12:57:36 PM PDT 24 May 23 12:57:41 PM PDT 24 130698593 ps
T534 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1587886000 May 23 12:58:08 PM PDT 24 May 23 12:58:14 PM PDT 24 14709740 ps
T65 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.4069878705 May 23 12:57:56 PM PDT 24 May 23 12:58:03 PM PDT 24 281356498 ps
T105 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2644700784 May 23 12:57:36 PM PDT 24 May 23 12:57:39 PM PDT 24 33426299 ps
T535 /workspace/coverage/cover_reg_top/28.hmac_intr_test.4095270122 May 23 12:58:05 PM PDT 24 May 23 12:58:09 PM PDT 24 40100250 ps
T536 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1060829400 May 23 12:57:24 PM PDT 24 May 23 12:57:28 PM PDT 24 634909916 ps
T537 /workspace/coverage/cover_reg_top/20.hmac_intr_test.192884969 May 23 12:58:07 PM PDT 24 May 23 12:58:13 PM PDT 24 16608572 ps
T538 /workspace/coverage/cover_reg_top/36.hmac_intr_test.1018257948 May 23 12:58:09 PM PDT 24 May 23 12:58:15 PM PDT 24 18944111 ps
T539 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2787744109 May 23 12:58:08 PM PDT 24 May 23 12:58:14 PM PDT 24 25050135 ps
T540 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.222344103 May 23 12:57:57 PM PDT 24 May 23 12:58:00 PM PDT 24 49710226 ps
T541 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2617851724 May 23 12:57:40 PM PDT 24 May 23 12:57:46 PM PDT 24 431324747 ps
T91 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.164708695 May 23 12:57:54 PM PDT 24 May 23 12:57:58 PM PDT 24 278797605 ps
T92 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.38585120 May 23 12:57:25 PM PDT 24 May 23 12:57:44 PM PDT 24 17394177715 ps
T93 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2066216219 May 23 12:57:55 PM PDT 24 May 23 12:57:59 PM PDT 24 41164311 ps
T542 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1201439061 May 23 12:58:08 PM PDT 24 May 23 12:58:14 PM PDT 24 117839726 ps
T543 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3385967432 May 23 12:57:52 PM PDT 24 May 23 12:57:56 PM PDT 24 286151119 ps
T106 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2403865715 May 23 12:57:20 PM PDT 24 May 23 12:57:22 PM PDT 24 50061538 ps
T544 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2784607963 May 23 12:57:55 PM PDT 24 May 23 12:58:00 PM PDT 24 176758804 ps
T66 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1993446023 May 23 12:57:54 PM PDT 24 May 23 12:58:01 PM PDT 24 226352484 ps
T545 /workspace/coverage/cover_reg_top/12.hmac_intr_test.537257257 May 23 12:57:54 PM PDT 24 May 23 12:57:58 PM PDT 24 14592278 ps
T546 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1077505592 May 23 12:58:08 PM PDT 24 May 23 01:05:43 PM PDT 24 128168279877 ps
T67 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3484821814 May 23 12:58:05 PM PDT 24 May 23 12:58:10 PM PDT 24 331377572 ps
T133 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3249820248 May 23 12:57:53 PM PDT 24 May 23 12:57:57 PM PDT 24 348016157 ps
T547 /workspace/coverage/cover_reg_top/11.hmac_intr_test.983557453 May 23 12:57:58 PM PDT 24 May 23 12:58:01 PM PDT 24 50113082 ps
T548 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2461795796 May 23 12:57:53 PM PDT 24 May 23 12:57:57 PM PDT 24 143746777 ps
T549 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2784448934 May 23 12:57:53 PM PDT 24 May 23 12:57:57 PM PDT 24 34211344 ps
T113 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2803827249 May 23 12:57:35 PM PDT 24 May 23 12:57:48 PM PDT 24 1447826090 ps
T550 /workspace/coverage/cover_reg_top/24.hmac_intr_test.282093155 May 23 12:58:06 PM PDT 24 May 23 12:58:10 PM PDT 24 13614739 ps
T551 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2218464121 May 23 12:58:13 PM PDT 24 May 23 12:58:17 PM PDT 24 58318587 ps
T107 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1404990837 May 23 12:57:38 PM PDT 24 May 23 12:57:42 PM PDT 24 189828213 ps
T552 /workspace/coverage/cover_reg_top/10.hmac_intr_test.3800582102 May 23 12:57:56 PM PDT 24 May 23 12:57:59 PM PDT 24 49152214 ps
T108 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1478474988 May 23 12:57:25 PM PDT 24 May 23 12:57:30 PM PDT 24 946437244 ps
T553 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1342671415 May 23 12:57:56 PM PDT 24 May 23 12:58:02 PM PDT 24 1307070942 ps
T554 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2231350745 May 23 12:57:25 PM PDT 24 May 23 12:57:27 PM PDT 24 12964767 ps
T555 /workspace/coverage/cover_reg_top/35.hmac_intr_test.2623614893 May 23 12:58:07 PM PDT 24 May 23 12:58:12 PM PDT 24 13638169 ps
T556 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1965482368 May 23 12:57:40 PM PDT 24 May 23 12:57:45 PM PDT 24 217591368 ps
T557 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.525980069 May 23 12:57:52 PM PDT 24 May 23 12:57:54 PM PDT 24 51251186 ps
T558 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3683196523 May 23 12:57:37 PM PDT 24 May 23 12:57:42 PM PDT 24 113718573 ps
T559 /workspace/coverage/cover_reg_top/3.hmac_intr_test.92313556 May 23 12:57:39 PM PDT 24 May 23 12:57:43 PM PDT 24 12810178 ps
T560 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.658975862 May 23 12:57:41 PM PDT 24 May 23 12:57:45 PM PDT 24 21749754 ps
T561 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2257941455 May 23 12:57:37 PM PDT 24 May 23 12:57:42 PM PDT 24 137121043 ps
T137 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3460497164 May 23 12:57:37 PM PDT 24 May 23 12:57:41 PM PDT 24 48502681 ps
T562 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1519161859 May 23 12:57:53 PM PDT 24 May 23 12:57:57 PM PDT 24 39326886 ps
T563 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.490981125 May 23 12:57:38 PM PDT 24 May 23 12:57:42 PM PDT 24 84164406 ps
T109 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.589239493 May 23 12:57:39 PM PDT 24 May 23 12:57:43 PM PDT 24 15239386 ps
T564 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.396981858 May 23 12:57:51 PM PDT 24 May 23 12:57:54 PM PDT 24 96743206 ps
T565 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.459891203 May 23 12:57:36 PM PDT 24 May 23 12:57:40 PM PDT 24 41342719 ps
T566 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.333394350 May 23 12:57:53 PM PDT 24 May 23 12:58:00 PM PDT 24 138237762 ps
T567 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3172211737 May 23 12:58:06 PM PDT 24 May 23 12:58:10 PM PDT 24 12435178 ps
T110 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.4095789173 May 23 12:57:22 PM PDT 24 May 23 12:57:24 PM PDT 24 110995873 ps
T568 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3777455169 May 23 12:57:38 PM PDT 24 May 23 12:57:42 PM PDT 24 14923037 ps
T111 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2985395328 May 23 12:57:36 PM PDT 24 May 23 12:57:45 PM PDT 24 628870327 ps
T569 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3980719583 May 23 12:57:52 PM PDT 24 May 23 12:57:57 PM PDT 24 443711318 ps
T570 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3197650097 May 23 12:57:54 PM PDT 24 May 23 12:57:59 PM PDT 24 280651118 ps
T571 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.260289189 May 23 12:57:21 PM PDT 24 May 23 12:57:32 PM PDT 24 1483011671 ps
T572 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2487276455 May 23 12:58:05 PM PDT 24 May 23 12:58:09 PM PDT 24 46353246 ps
T573 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.825576335 May 23 12:57:54 PM PDT 24 May 23 12:58:01 PM PDT 24 572118612 ps
T574 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3624498731 May 23 12:57:38 PM PDT 24 May 23 01:15:45 PM PDT 24 385579832315 ps
T575 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.4287959062 May 23 12:57:24 PM PDT 24 May 23 12:57:27 PM PDT 24 23871005 ps
T576 /workspace/coverage/cover_reg_top/41.hmac_intr_test.991852683 May 23 12:58:09 PM PDT 24 May 23 12:58:15 PM PDT 24 99099274 ps
T577 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2569388122 May 23 12:57:53 PM PDT 24 May 23 12:57:56 PM PDT 24 149406524 ps
T578 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2291548854 May 23 12:57:23 PM PDT 24 May 23 12:57:26 PM PDT 24 311828472 ps
T579 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3159271900 May 23 12:57:52 PM PDT 24 May 23 12:57:58 PM PDT 24 329817331 ps
T580 /workspace/coverage/cover_reg_top/25.hmac_intr_test.1018051790 May 23 12:58:12 PM PDT 24 May 23 12:58:17 PM PDT 24 19440514 ps
T581 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2516669973 May 23 12:57:37 PM PDT 24 May 23 12:57:40 PM PDT 24 413188907 ps
T112 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3744460963 May 23 12:57:21 PM PDT 24 May 23 12:57:23 PM PDT 24 64042875 ps
T582 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3442298249 May 23 12:57:34 PM PDT 24 May 23 12:57:38 PM PDT 24 370730404 ps
T583 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2523036186 May 23 12:58:09 PM PDT 24 May 23 12:58:15 PM PDT 24 75705084 ps
T114 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1195912496 May 23 12:57:24 PM PDT 24 May 23 12:57:27 PM PDT 24 97192790 ps
T584 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1118122372 May 23 12:57:55 PM PDT 24 May 23 12:58:39 PM PDT 24 30020001776 ps
T135 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3430666753 May 23 12:57:55 PM PDT 24 May 23 12:58:02 PM PDT 24 246237982 ps
T585 /workspace/coverage/cover_reg_top/47.hmac_intr_test.2117668977 May 23 12:58:07 PM PDT 24 May 23 12:58:13 PM PDT 24 21747409 ps
T586 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1417835165 May 23 12:57:23 PM PDT 24 May 23 12:57:26 PM PDT 24 176933152 ps
T587 /workspace/coverage/cover_reg_top/8.hmac_intr_test.252880057 May 23 12:57:37 PM PDT 24 May 23 12:57:40 PM PDT 24 30723966 ps
T588 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3825709114 May 23 12:58:07 PM PDT 24 May 23 12:58:12 PM PDT 24 32474299 ps
T589 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1706322673 May 23 12:57:38 PM PDT 24 May 23 12:57:47 PM PDT 24 437991341 ps
T590 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1729695328 May 23 12:57:55 PM PDT 24 May 23 12:57:59 PM PDT 24 24773004 ps
T591 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1317559551 May 23 12:58:08 PM PDT 24 May 23 12:58:14 PM PDT 24 11395626 ps
T592 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2677166811 May 23 12:57:26 PM PDT 24 May 23 12:57:38 PM PDT 24 1797472836 ps
T593 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.116332462 May 23 12:57:21 PM PDT 24 May 23 12:57:25 PM PDT 24 360159297 ps
T594 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1289366015 May 23 12:57:51 PM PDT 24 May 23 12:57:53 PM PDT 24 18540927 ps
T138 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3324165299 May 23 12:57:38 PM PDT 24 May 23 12:57:45 PM PDT 24 225663790 ps
T595 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1400478995 May 23 12:57:41 PM PDT 24 May 23 12:57:46 PM PDT 24 164759951 ps
T596 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.12130768 May 23 12:57:37 PM PDT 24 May 23 12:57:44 PM PDT 24 745717364 ps
T597 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1921867894 May 23 12:57:37 PM PDT 24 May 23 01:05:56 PM PDT 24 48163632298 ps
T598 /workspace/coverage/cover_reg_top/26.hmac_intr_test.2136697839 May 23 12:58:05 PM PDT 24 May 23 12:58:08 PM PDT 24 17410498 ps
T115 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3449169453 May 23 12:57:37 PM PDT 24 May 23 12:57:48 PM PDT 24 491364823 ps
T599 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2418699376 May 23 12:57:36 PM PDT 24 May 23 12:57:39 PM PDT 24 199975004 ps
T600 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1273026600 May 23 12:57:38 PM PDT 24 May 23 12:57:42 PM PDT 24 204010038 ps
T601 /workspace/coverage/cover_reg_top/48.hmac_intr_test.3065275766 May 23 12:58:10 PM PDT 24 May 23 12:58:16 PM PDT 24 20183016 ps
T602 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1140591377 May 23 12:57:40 PM PDT 24 May 23 12:57:45 PM PDT 24 308035800 ps
T603 /workspace/coverage/cover_reg_top/42.hmac_intr_test.620252823 May 23 12:58:06 PM PDT 24 May 23 12:58:10 PM PDT 24 137048388 ps
T116 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2918812796 May 23 12:57:38 PM PDT 24 May 23 12:57:42 PM PDT 24 41160843 ps
T604 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3345267897 May 23 12:57:53 PM PDT 24 May 23 12:57:57 PM PDT 24 478027572 ps
T605 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1876011398 May 23 12:57:52 PM PDT 24 May 23 12:57:54 PM PDT 24 21978326 ps
T606 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2630198156 May 23 12:57:58 PM PDT 24 May 23 12:58:02 PM PDT 24 23596916 ps
T607 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.852196696 May 23 12:58:04 PM PDT 24 May 23 12:58:09 PM PDT 24 75279599 ps
T608 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3556829678 May 23 12:57:53 PM PDT 24 May 23 12:57:56 PM PDT 24 27459684 ps
T139 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2847184087 May 23 12:57:52 PM PDT 24 May 23 12:57:56 PM PDT 24 160169370 ps
T134 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1386332825 May 23 12:57:37 PM PDT 24 May 23 12:57:42 PM PDT 24 582737411 ps
T609 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.725528093 May 23 12:57:24 PM PDT 24 May 23 12:57:28 PM PDT 24 115803599 ps
T610 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.351378674 May 23 12:58:09 PM PDT 24 May 23 12:58:15 PM PDT 24 131898347 ps
T611 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.766299032 May 23 12:58:06 PM PDT 24 May 23 12:58:12 PM PDT 24 44712913 ps
T612 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1680862353 May 23 12:57:37 PM PDT 24 May 23 12:57:41 PM PDT 24 199507120 ps
T613 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3632427164 May 23 12:57:38 PM PDT 24 May 23 12:57:44 PM PDT 24 996801996 ps
T614 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1791493463 May 23 12:57:38 PM PDT 24 May 23 12:57:44 PM PDT 24 90616529 ps
T615 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.71808966 May 23 12:57:37 PM PDT 24 May 23 01:20:26 PM PDT 24 273045069769 ps
T616 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.4104847826 May 23 12:57:58 PM PDT 24 May 23 12:58:02 PM PDT 24 98407322 ps
T617 /workspace/coverage/cover_reg_top/29.hmac_intr_test.3366245479 May 23 12:58:07 PM PDT 24 May 23 12:58:12 PM PDT 24 66955200 ps
T618 /workspace/coverage/cover_reg_top/27.hmac_intr_test.947409043 May 23 12:58:05 PM PDT 24 May 23 12:58:09 PM PDT 24 40380508 ps
T619 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1467496965 May 23 12:57:56 PM PDT 24 May 23 12:58:03 PM PDT 24 278684292 ps
T620 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2328898669 May 23 12:57:24 PM PDT 24 May 23 12:57:27 PM PDT 24 28115649 ps
T621 /workspace/coverage/cover_reg_top/49.hmac_intr_test.815513182 May 23 12:58:05 PM PDT 24 May 23 12:58:09 PM PDT 24 15385853 ps
T622 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2407169106 May 23 12:57:55 PM PDT 24 May 23 12:58:00 PM PDT 24 44629698 ps
T623 /workspace/coverage/cover_reg_top/16.hmac_intr_test.2695146839 May 23 12:57:55 PM PDT 24 May 23 12:57:59 PM PDT 24 24547007 ps
T624 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3211780017 May 23 12:58:05 PM PDT 24 May 23 12:58:08 PM PDT 24 12871091 ps
T625 /workspace/coverage/cover_reg_top/23.hmac_intr_test.4214436918 May 23 12:58:06 PM PDT 24 May 23 12:58:11 PM PDT 24 43186812 ps
T626 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1499205764 May 23 12:57:39 PM PDT 24 May 23 12:57:45 PM PDT 24 332821059 ps
T627 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3783042470 May 23 12:57:54 PM PDT 24 May 23 12:58:00 PM PDT 24 48585046 ps
T628 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1993966298 May 23 12:58:07 PM PDT 24 May 23 12:58:13 PM PDT 24 26454306 ps
T629 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3310223811 May 23 12:57:54 PM PDT 24 May 23 12:57:59 PM PDT 24 589538833 ps
T630 /workspace/coverage/cover_reg_top/1.hmac_intr_test.2484535126 May 23 12:57:25 PM PDT 24 May 23 12:57:27 PM PDT 24 19765461 ps
T631 /workspace/coverage/cover_reg_top/40.hmac_intr_test.2267944723 May 23 12:58:06 PM PDT 24 May 23 12:58:09 PM PDT 24 117870368 ps
T632 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2486948752 May 23 12:57:35 PM PDT 24 May 23 12:57:37 PM PDT 24 17310583 ps
T633 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.419492341 May 23 12:57:55 PM PDT 24 May 23 12:57:59 PM PDT 24 104641429 ps
T140 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2891272286 May 23 12:57:23 PM PDT 24 May 23 12:57:28 PM PDT 24 311381727 ps
T136 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.177308014 May 23 12:57:51 PM PDT 24 May 23 12:57:56 PM PDT 24 502326888 ps
T634 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1191814992 May 23 12:57:56 PM PDT 24 May 23 12:57:59 PM PDT 24 34808267 ps
T635 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2575023657 May 23 12:57:58 PM PDT 24 May 23 12:58:03 PM PDT 24 67969545 ps
T636 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2859391910 May 23 12:57:22 PM PDT 24 May 23 12:57:28 PM PDT 24 246402096 ps
T637 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2140426815 May 23 12:57:56 PM PDT 24 May 23 12:58:02 PM PDT 24 283031059 ps
T638 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3838451894 May 23 12:57:54 PM PDT 24 May 23 12:57:57 PM PDT 24 12308221 ps
T639 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.4009701313 May 23 12:57:42 PM PDT 24 May 23 12:57:47 PM PDT 24 356614394 ps
T640 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.4256228597 May 23 12:57:36 PM PDT 24 May 23 12:57:39 PM PDT 24 31993096 ps
T641 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.819972980 May 23 12:57:54 PM PDT 24 May 23 12:57:58 PM PDT 24 36867371 ps
T642 /workspace/coverage/cover_reg_top/44.hmac_intr_test.140851099 May 23 12:58:10 PM PDT 24 May 23 12:58:16 PM PDT 24 21660957 ps
T643 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3473175017 May 23 12:57:37 PM PDT 24 May 23 12:57:42 PM PDT 24 103382813 ps
T644 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.578341741 May 23 12:57:24 PM PDT 24 May 23 12:57:28 PM PDT 24 85699291 ps
T645 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1890223280 May 23 12:58:06 PM PDT 24 May 23 12:58:11 PM PDT 24 184948125 ps
T646 /workspace/coverage/cover_reg_top/6.hmac_intr_test.4024005378 May 23 12:57:38 PM PDT 24 May 23 12:57:42 PM PDT 24 15632459 ps
T647 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3024481959 May 23 12:58:07 PM PDT 24 May 23 12:58:15 PM PDT 24 343567515 ps
T648 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2745977314 May 23 12:57:38 PM PDT 24 May 23 12:57:42 PM PDT 24 42784944 ps
T649 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2789324287 May 23 12:58:06 PM PDT 24 May 23 12:58:10 PM PDT 24 12125056 ps
T650 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.195886043 May 23 12:57:52 PM PDT 24 May 23 12:57:55 PM PDT 24 167658484 ps
T651 /workspace/coverage/cover_reg_top/4.hmac_intr_test.518228465 May 23 12:57:38 PM PDT 24 May 23 12:57:41 PM PDT 24 31833347 ps
T652 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3451047379 May 23 12:57:36 PM PDT 24 May 23 12:57:39 PM PDT 24 60008253 ps
T653 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3987064146 May 23 12:58:05 PM PDT 24 May 23 12:58:08 PM PDT 24 13497524 ps

Test location /workspace/coverage/default/2.hmac_long_msg.3739902251
Short name T4
Test name
Test status
Simulation time 26034586265 ps
CPU time 72.02 seconds
Started May 23 01:02:56 PM PDT 24
Finished May 23 01:04:10 PM PDT 24
Peak memory 200152 kb
Host smart-e4839216-5115-45cc-b3a7-cb1a6d766c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739902251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3739902251
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/191.hmac_stress_all_with_rand_reset.2637776163
Short name T13
Test name
Test status
Simulation time 25492861805 ps
CPU time 632.49 seconds
Started May 23 01:05:02 PM PDT 24
Finished May 23 01:15:39 PM PDT 24
Peak memory 463868 kb
Host smart-bb6453b2-d58f-4a2a-88e1-380ef55b8578
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2637776163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.hmac_stress_all_with_rand_reset.2637776163
Directory /workspace/191.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3399717256
Short name T16
Test name
Test status
Simulation time 2610847098 ps
CPU time 32.71 seconds
Started May 23 01:03:57 PM PDT 24
Finished May 23 01:04:37 PM PDT 24
Peak memory 199956 kb
Host smart-1ae7b7f2-9ba2-4c30-8063-67cecd5edad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399717256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3399717256
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2996315501
Short name T33
Test name
Test status
Simulation time 126187611 ps
CPU time 0.78 seconds
Started May 23 01:02:39 PM PDT 24
Finished May 23 01:02:40 PM PDT 24
Peak memory 217960 kb
Host smart-2a230058-fd6b-427a-8a77-a351191b5ad8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996315501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2996315501
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/62.hmac_stress_all_with_rand_reset.867289491
Short name T11
Test name
Test status
Simulation time 22442373885 ps
CPU time 495.98 seconds
Started May 23 01:04:42 PM PDT 24
Finished May 23 01:13:01 PM PDT 24
Peak memory 389272 kb
Host smart-f389236f-fab3-4c1d-9016-8b92d29e7352
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=867289491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.hmac_stress_all_with_rand_reset.867289491
Directory /workspace/62.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1051560473
Short name T39
Test name
Test status
Simulation time 3441254535 ps
CPU time 61.17 seconds
Started May 23 01:04:00 PM PDT 24
Finished May 23 01:05:08 PM PDT 24
Peak memory 199904 kb
Host smart-472695d4-14ef-49ef-9ad5-425a3512ea54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051560473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1051560473
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.4069878705
Short name T65
Test name
Test status
Simulation time 281356498 ps
CPU time 4.35 seconds
Started May 23 12:57:56 PM PDT 24
Finished May 23 12:58:03 PM PDT 24
Peak memory 200048 kb
Host smart-97a350ce-dd45-4f80-8b6d-bb71913896b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069878705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.4069878705
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/11.hmac_stress_all_with_rand_reset.2511250399
Short name T14
Test name
Test status
Simulation time 62555687396 ps
CPU time 1761.72 seconds
Started May 23 01:03:09 PM PDT 24
Finished May 23 01:32:33 PM PDT 24
Peak memory 249120 kb
Host smart-c089ffcf-c2ce-4a4e-a3ec-cc43583b4e40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2511250399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all_with_rand_reset.2511250399
Directory /workspace/11.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1883994148
Short name T17
Test name
Test status
Simulation time 1646621992 ps
CPU time 13.75 seconds
Started May 23 01:03:26 PM PDT 24
Finished May 23 01:03:43 PM PDT 24
Peak memory 208252 kb
Host smart-a085a3b1-2149-4bed-82ac-d0bc63ad7c96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1883994148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1883994148
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2956851785
Short name T34
Test name
Test status
Simulation time 18809213779 ps
CPU time 1208.77 seconds
Started May 23 01:03:25 PM PDT 24
Finished May 23 01:23:37 PM PDT 24
Peak memory 630700 kb
Host smart-328c2694-e6c4-4fae-ba9a-6bec17bc1429
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956851785 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2956851785
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1478474988
Short name T108
Test name
Test status
Simulation time 946437244 ps
CPU time 3.3 seconds
Started May 23 12:57:25 PM PDT 24
Finished May 23 12:57:30 PM PDT 24
Peak memory 199944 kb
Host smart-2a1f989c-0816-4e6e-9201-23e9169d5706
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478474988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1478474988
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/default/1.hmac_alert_test.527600590
Short name T31
Test name
Test status
Simulation time 81258589 ps
CPU time 0.61 seconds
Started May 23 01:03:11 PM PDT 24
Finished May 23 01:03:13 PM PDT 24
Peak memory 196412 kb
Host smart-f5b6e98f-dcda-44ee-ab49-0c8aa9eb7a42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527600590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.527600590
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1485015653
Short name T29
Test name
Test status
Simulation time 726307363 ps
CPU time 17.39 seconds
Started May 23 01:03:53 PM PDT 24
Finished May 23 01:04:17 PM PDT 24
Peak memory 200084 kb
Host smart-d3b239e2-b943-40cb-aa67-753145d4b3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485015653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1485015653
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.2274945353
Short name T41
Test name
Test status
Simulation time 136773725 ps
CPU time 0.95 seconds
Started May 23 01:03:04 PM PDT 24
Finished May 23 01:03:07 PM PDT 24
Peak memory 217980 kb
Host smart-2a2a7fb5-d103-45e1-8479-59e0df26f8f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274945353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2274945353
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.3168815563
Short name T122
Test name
Test status
Simulation time 7517909286 ps
CPU time 87.46 seconds
Started May 23 01:03:51 PM PDT 24
Finished May 23 01:05:25 PM PDT 24
Peak memory 200116 kb
Host smart-21b377ea-fc8f-4897-95fe-3ecc55b41c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168815563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3168815563
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2279073245
Short name T124
Test name
Test status
Simulation time 4344398729 ps
CPU time 56.48 seconds
Started May 23 01:03:54 PM PDT 24
Finished May 23 01:04:58 PM PDT 24
Peak memory 230748 kb
Host smart-2ae413c9-3e9f-471e-a7a7-50ce6dd1c06a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2279073245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2279073245
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.4258769479
Short name T1
Test name
Test status
Simulation time 3277391277 ps
CPU time 218.57 seconds
Started May 23 01:03:05 PM PDT 24
Finished May 23 01:06:45 PM PDT 24
Peak memory 659940 kb
Host smart-9168981b-3e56-47c0-8c8e-3d529ed65aff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4258769479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.4258769479
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3430666753
Short name T135
Test name
Test status
Simulation time 246237982 ps
CPU time 4.25 seconds
Started May 23 12:57:55 PM PDT 24
Finished May 23 12:58:02 PM PDT 24
Peak memory 200032 kb
Host smart-1b80dbf6-683a-49cd-8c19-75102391a33c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430666753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3430666753
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2847184087
Short name T139
Test name
Test status
Simulation time 160169370 ps
CPU time 1.81 seconds
Started May 23 12:57:52 PM PDT 24
Finished May 23 12:57:56 PM PDT 24
Peak memory 199912 kb
Host smart-83dbb757-ee66-48fb-989d-947891931533
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847184087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2847184087
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.4197281939
Short name T127
Test name
Test status
Simulation time 18901247639 ps
CPU time 69.6 seconds
Started May 23 01:03:22 PM PDT 24
Finished May 23 01:04:33 PM PDT 24
Peak memory 200116 kb
Host smart-ae1d6853-20c3-4acb-b2bf-a35e8f20f5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197281939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.4197281939
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_long_msg.841570595
Short name T123
Test name
Test status
Simulation time 11066815219 ps
CPU time 126.58 seconds
Started May 23 01:03:19 PM PDT 24
Finished May 23 01:05:27 PM PDT 24
Peak memory 200096 kb
Host smart-809d1186-d6da-4491-b777-d4aff03cb118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841570595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.841570595
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2355004069
Short name T8
Test name
Test status
Simulation time 1636080211 ps
CPU time 16.31 seconds
Started May 23 01:03:23 PM PDT 24
Finished May 23 01:03:41 PM PDT 24
Peak memory 199896 kb
Host smart-299c1718-6e8e-4465-9860-1e4e39557db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355004069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2355004069
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_error.2962031820
Short name T27
Test name
Test status
Simulation time 10408575689 ps
CPU time 141.37 seconds
Started May 23 01:03:24 PM PDT 24
Finished May 23 01:05:47 PM PDT 24
Peak memory 200168 kb
Host smart-e6a33a3f-051b-4ad0-b777-e7e17dcda0c9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962031820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2962031820
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.3326438798
Short name T154
Test name
Test status
Simulation time 37389173579 ps
CPU time 499.62 seconds
Started May 23 01:03:21 PM PDT 24
Finished May 23 01:11:42 PM PDT 24
Peak memory 200024 kb
Host smart-e4f278a7-fc55-421e-908d-e15bae30e101
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326438798 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.3326438798
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_stress_all.1621228347
Short name T117
Test name
Test status
Simulation time 97183186301 ps
CPU time 2612.12 seconds
Started May 23 01:03:25 PM PDT 24
Finished May 23 01:46:59 PM PDT 24
Peak memory 796864 kb
Host smart-4ee180e1-15a7-429c-a655-c42fe05a8635
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621228347 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1621228347
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1368849511
Short name T173
Test name
Test status
Simulation time 21016847134 ps
CPU time 1305.28 seconds
Started May 23 01:03:37 PM PDT 24
Finished May 23 01:25:24 PM PDT 24
Peak memory 723952 kb
Host smart-f5cfecd6-7f6c-4b85-bbf3-97854c8c0a02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1368849511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1368849511
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.38585120
Short name T92
Test name
Test status
Simulation time 17394177715 ps
CPU time 17.15 seconds
Started May 23 12:57:25 PM PDT 24
Finished May 23 12:57:44 PM PDT 24
Peak memory 200064 kb
Host smart-e275eb50-84aa-4a78-85de-cf6b7ba1c2d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38585120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.38585120
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1195912496
Short name T114
Test name
Test status
Simulation time 97192790 ps
CPU time 0.84 seconds
Started May 23 12:57:24 PM PDT 24
Finished May 23 12:57:27 PM PDT 24
Peak memory 199300 kb
Host smart-19f1c2d4-cec3-4f0b-80d9-52dfd345f9b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195912496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1195912496
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.116332462
Short name T593
Test name
Test status
Simulation time 360159297 ps
CPU time 2.27 seconds
Started May 23 12:57:21 PM PDT 24
Finished May 23 12:57:25 PM PDT 24
Peak memory 200164 kb
Host smart-7e8ba800-d07f-4adc-b2bf-a7fbfbfe2230
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116332462 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.116332462
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.4095789173
Short name T110
Test name
Test status
Simulation time 110995873 ps
CPU time 0.79 seconds
Started May 23 12:57:22 PM PDT 24
Finished May 23 12:57:24 PM PDT 24
Peak memory 199036 kb
Host smart-39a3b05e-3e75-4aef-ba1d-0361f6f010b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095789173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.4095789173
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2669384882
Short name T527
Test name
Test status
Simulation time 27180706 ps
CPU time 0.62 seconds
Started May 23 12:57:26 PM PDT 24
Finished May 23 12:57:29 PM PDT 24
Peak memory 194760 kb
Host smart-9bfd3458-62b4-410e-b710-588429814ede
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669384882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2669384882
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.4287959062
Short name T575
Test name
Test status
Simulation time 23871005 ps
CPU time 1.08 seconds
Started May 23 12:57:24 PM PDT 24
Finished May 23 12:57:27 PM PDT 24
Peak memory 198500 kb
Host smart-20e5e680-825b-4882-a59c-63de7bc19610
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287959062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.4287959062
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1060829400
Short name T536
Test name
Test status
Simulation time 634909916 ps
CPU time 2.93 seconds
Started May 23 12:57:24 PM PDT 24
Finished May 23 12:57:28 PM PDT 24
Peak memory 200036 kb
Host smart-a1470fa3-5e8d-4d39-9c9f-7d9e17c9d705
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060829400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1060829400
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2891272286
Short name T140
Test name
Test status
Simulation time 311381727 ps
CPU time 2.99 seconds
Started May 23 12:57:23 PM PDT 24
Finished May 23 12:57:28 PM PDT 24
Peak memory 200104 kb
Host smart-54ec3cff-cf15-4ec2-92e6-b512c0bb45bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891272286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2891272286
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.725528093
Short name T609
Test name
Test status
Simulation time 115803599 ps
CPU time 3.05 seconds
Started May 23 12:57:24 PM PDT 24
Finished May 23 12:57:28 PM PDT 24
Peak memory 198960 kb
Host smart-4465732a-2916-4ea1-97e4-83e595d04d43
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725528093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.725528093
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2677166811
Short name T592
Test name
Test status
Simulation time 1797472836 ps
CPU time 10.59 seconds
Started May 23 12:57:26 PM PDT 24
Finished May 23 12:57:38 PM PDT 24
Peak memory 199936 kb
Host smart-c4f99c5c-541c-4b46-ac91-53032bc2c7f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677166811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2677166811
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2403865715
Short name T106
Test name
Test status
Simulation time 50061538 ps
CPU time 0.86 seconds
Started May 23 12:57:20 PM PDT 24
Finished May 23 12:57:22 PM PDT 24
Peak memory 199380 kb
Host smart-b30d5d44-2a46-44e3-9ac1-6528f5aa6f0f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403865715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2403865715
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2157932479
Short name T70
Test name
Test status
Simulation time 115192781 ps
CPU time 1.14 seconds
Started May 23 12:57:22 PM PDT 24
Finished May 23 12:57:25 PM PDT 24
Peak memory 199876 kb
Host smart-4b3ae1f0-2117-490a-a1f4-c0b2ffaa2a8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157932479 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2157932479
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3744460963
Short name T112
Test name
Test status
Simulation time 64042875 ps
CPU time 0.71 seconds
Started May 23 12:57:21 PM PDT 24
Finished May 23 12:57:23 PM PDT 24
Peak memory 197476 kb
Host smart-afdc0545-dc70-4a4d-af54-356d5f5ee36c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744460963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.3744460963
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2484535126
Short name T630
Test name
Test status
Simulation time 19765461 ps
CPU time 0.61 seconds
Started May 23 12:57:25 PM PDT 24
Finished May 23 12:57:27 PM PDT 24
Peak memory 194840 kb
Host smart-1959a3d1-4084-493d-9a20-d2f405182090
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484535126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2484535126
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.578341741
Short name T644
Test name
Test status
Simulation time 85699291 ps
CPU time 1.77 seconds
Started May 23 12:57:24 PM PDT 24
Finished May 23 12:57:28 PM PDT 24
Peak memory 199796 kb
Host smart-52a40b8b-3747-459f-8891-1101fa71cf0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578341741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.578341741
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2291548854
Short name T578
Test name
Test status
Simulation time 311828472 ps
CPU time 1.57 seconds
Started May 23 12:57:23 PM PDT 24
Finished May 23 12:57:26 PM PDT 24
Peak memory 200132 kb
Host smart-de01d247-9146-440c-af79-01a9d334d900
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291548854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2291548854
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2859391910
Short name T636
Test name
Test status
Simulation time 246402096 ps
CPU time 3.84 seconds
Started May 23 12:57:22 PM PDT 24
Finished May 23 12:57:28 PM PDT 24
Peak memory 200100 kb
Host smart-b0d29fce-ca85-4fb8-befb-97b791bd82c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859391910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2859391910
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.164708695
Short name T91
Test name
Test status
Simulation time 278797605 ps
CPU time 1.6 seconds
Started May 23 12:57:54 PM PDT 24
Finished May 23 12:57:58 PM PDT 24
Peak memory 200004 kb
Host smart-f8a66b8b-4db8-4584-84e0-70dbf4971490
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164708695 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.164708695
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.819972980
Short name T641
Test name
Test status
Simulation time 36867371 ps
CPU time 0.94 seconds
Started May 23 12:57:54 PM PDT 24
Finished May 23 12:57:58 PM PDT 24
Peak memory 199816 kb
Host smart-6062a9da-fcfc-4f44-8c9f-cd1c691e6930
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819972980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.819972980
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3800582102
Short name T552
Test name
Test status
Simulation time 49152214 ps
CPU time 0.59 seconds
Started May 23 12:57:56 PM PDT 24
Finished May 23 12:57:59 PM PDT 24
Peak memory 194804 kb
Host smart-a0971e9f-2fdf-440f-8882-1426db7eef98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800582102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3800582102
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2784448934
Short name T549
Test name
Test status
Simulation time 34211344 ps
CPU time 1.58 seconds
Started May 23 12:57:53 PM PDT 24
Finished May 23 12:57:57 PM PDT 24
Peak memory 200060 kb
Host smart-9a85d943-e5af-4d2a-b9b6-8bb199a4e39c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784448934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2784448934
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.93443078
Short name T76
Test name
Test status
Simulation time 181808344 ps
CPU time 2.57 seconds
Started May 23 12:57:53 PM PDT 24
Finished May 23 12:57:58 PM PDT 24
Peak memory 200008 kb
Host smart-ede6f571-71e4-413e-b847-16950dd894c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93443078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.93443078
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2066216219
Short name T93
Test name
Test status
Simulation time 41164311 ps
CPU time 1.17 seconds
Started May 23 12:57:55 PM PDT 24
Finished May 23 12:57:59 PM PDT 24
Peak memory 199864 kb
Host smart-a2d4f87e-4276-4d7c-9aa0-e3387d19b81f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066216219 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.2066216219
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2957848919
Short name T90
Test name
Test status
Simulation time 66861180 ps
CPU time 0.99 seconds
Started May 23 12:57:53 PM PDT 24
Finished May 23 12:57:56 PM PDT 24
Peak memory 199892 kb
Host smart-6e2f0ade-d304-424f-af3a-9879a9a54ef7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957848919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2957848919
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.983557453
Short name T547
Test name
Test status
Simulation time 50113082 ps
CPU time 0.59 seconds
Started May 23 12:57:58 PM PDT 24
Finished May 23 12:58:01 PM PDT 24
Peak memory 194848 kb
Host smart-e0ca3b44-195b-41c9-a700-d0fe24ca7805
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983557453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.983557453
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3201261062
Short name T530
Test name
Test status
Simulation time 104151099 ps
CPU time 1.16 seconds
Started May 23 12:57:56 PM PDT 24
Finished May 23 12:58:00 PM PDT 24
Peak memory 199996 kb
Host smart-375c6bc4-989b-44c7-821c-5b63a7ec3a08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201261062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3201261062
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3385967432
Short name T543
Test name
Test status
Simulation time 286151119 ps
CPU time 3.45 seconds
Started May 23 12:57:52 PM PDT 24
Finished May 23 12:57:56 PM PDT 24
Peak memory 200004 kb
Host smart-f4510320-bedc-4e59-9e2a-ce2b09197c4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385967432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3385967432
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1993446023
Short name T66
Test name
Test status
Simulation time 226352484 ps
CPU time 4.22 seconds
Started May 23 12:57:54 PM PDT 24
Finished May 23 12:58:01 PM PDT 24
Peak memory 199964 kb
Host smart-477e1646-2c11-4938-a932-1984ffe6541d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993446023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1993446023
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1519161859
Short name T562
Test name
Test status
Simulation time 39326886 ps
CPU time 1.24 seconds
Started May 23 12:57:53 PM PDT 24
Finished May 23 12:57:57 PM PDT 24
Peak memory 199804 kb
Host smart-838c605a-41c7-4d83-a54c-76378b3a479b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519161859 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1519161859
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3838451894
Short name T638
Test name
Test status
Simulation time 12308221 ps
CPU time 0.68 seconds
Started May 23 12:57:54 PM PDT 24
Finished May 23 12:57:57 PM PDT 24
Peak memory 197700 kb
Host smart-64ae2668-87a3-4089-ac76-09a3cb3b255b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838451894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3838451894
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.537257257
Short name T545
Test name
Test status
Simulation time 14592278 ps
CPU time 0.61 seconds
Started May 23 12:57:54 PM PDT 24
Finished May 23 12:57:58 PM PDT 24
Peak memory 194928 kb
Host smart-303ef7ad-1bd4-4dfd-9ab9-d9871b2fc5a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537257257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.537257257
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.195886043
Short name T650
Test name
Test status
Simulation time 167658484 ps
CPU time 1.58 seconds
Started May 23 12:57:52 PM PDT 24
Finished May 23 12:57:55 PM PDT 24
Peak memory 200076 kb
Host smart-ff9c1335-33d9-4ad8-a8df-02b46519e58a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195886043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.195886043
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.333394350
Short name T566
Test name
Test status
Simulation time 138237762 ps
CPU time 4.52 seconds
Started May 23 12:57:53 PM PDT 24
Finished May 23 12:58:00 PM PDT 24
Peak memory 199992 kb
Host smart-d620d412-e160-4883-8500-bd145c944f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333394350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.333394350
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3249820248
Short name T133
Test name
Test status
Simulation time 348016157 ps
CPU time 1.87 seconds
Started May 23 12:57:53 PM PDT 24
Finished May 23 12:57:57 PM PDT 24
Peak memory 200008 kb
Host smart-12e737ff-7851-4e36-b076-70aab206160a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249820248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3249820248
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2569388122
Short name T577
Test name
Test status
Simulation time 149406524 ps
CPU time 1.08 seconds
Started May 23 12:57:53 PM PDT 24
Finished May 23 12:57:56 PM PDT 24
Peak memory 199804 kb
Host smart-75464887-764d-449e-8f60-4311f17235ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569388122 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2569388122
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.222344103
Short name T540
Test name
Test status
Simulation time 49710226 ps
CPU time 0.8 seconds
Started May 23 12:57:57 PM PDT 24
Finished May 23 12:58:00 PM PDT 24
Peak memory 199844 kb
Host smart-5917d624-126a-4612-98f9-a804f3ca3934
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222344103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.222344103
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3556829678
Short name T608
Test name
Test status
Simulation time 27459684 ps
CPU time 0.6 seconds
Started May 23 12:57:53 PM PDT 24
Finished May 23 12:57:56 PM PDT 24
Peak memory 194824 kb
Host smart-3015e2ba-c6cb-4e76-b8dd-5b6da8387a8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556829678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3556829678
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3345267897
Short name T604
Test name
Test status
Simulation time 478027572 ps
CPU time 2.34 seconds
Started May 23 12:57:53 PM PDT 24
Finished May 23 12:57:57 PM PDT 24
Peak memory 199968 kb
Host smart-c67102e8-1b0f-4551-a68f-6e469663d3c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345267897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3345267897
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3310223811
Short name T629
Test name
Test status
Simulation time 589538833 ps
CPU time 2.81 seconds
Started May 23 12:57:54 PM PDT 24
Finished May 23 12:57:59 PM PDT 24
Peak memory 200044 kb
Host smart-d461b786-643b-41e8-8373-54ba63f422a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310223811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3310223811
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.177308014
Short name T136
Test name
Test status
Simulation time 502326888 ps
CPU time 4.06 seconds
Started May 23 12:57:51 PM PDT 24
Finished May 23 12:57:56 PM PDT 24
Peak memory 200060 kb
Host smart-0fb95a8e-8961-4800-9d02-dcf18a9ae11e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177308014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.177308014
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2575023657
Short name T635
Test name
Test status
Simulation time 67969545 ps
CPU time 1.79 seconds
Started May 23 12:57:58 PM PDT 24
Finished May 23 12:58:03 PM PDT 24
Peak memory 200108 kb
Host smart-35d1de04-2864-44af-9f61-b2a1baf665a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575023657 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2575023657
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2150840421
Short name T69
Test name
Test status
Simulation time 18453770 ps
CPU time 0.96 seconds
Started May 23 12:57:56 PM PDT 24
Finished May 23 12:58:00 PM PDT 24
Peak memory 199696 kb
Host smart-e0592422-aefa-4f1f-a447-48ee9d368310
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150840421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2150840421
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1191814992
Short name T634
Test name
Test status
Simulation time 34808267 ps
CPU time 0.55 seconds
Started May 23 12:57:56 PM PDT 24
Finished May 23 12:57:59 PM PDT 24
Peak memory 194876 kb
Host smart-56c1c21c-a655-478a-bd7d-c55ecdbba4b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191814992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1191814992
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3980719583
Short name T569
Test name
Test status
Simulation time 443711318 ps
CPU time 2.4 seconds
Started May 23 12:57:52 PM PDT 24
Finished May 23 12:57:57 PM PDT 24
Peak memory 199960 kb
Host smart-a15b469e-79bf-47fb-b86d-26235d02a6d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980719583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3980719583
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.422801630
Short name T528
Test name
Test status
Simulation time 495736480 ps
CPU time 2.53 seconds
Started May 23 12:57:55 PM PDT 24
Finished May 23 12:58:00 PM PDT 24
Peak memory 199904 kb
Host smart-dd41b34f-72af-4110-8a02-975260daebb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422801630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.422801630
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2630198156
Short name T606
Test name
Test status
Simulation time 23596916 ps
CPU time 1.49 seconds
Started May 23 12:57:58 PM PDT 24
Finished May 23 12:58:02 PM PDT 24
Peak memory 200044 kb
Host smart-4196475c-4461-4507-a412-d6b080a5eb6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630198156 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2630198156
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1876011398
Short name T605
Test name
Test status
Simulation time 21978326 ps
CPU time 0.72 seconds
Started May 23 12:57:52 PM PDT 24
Finished May 23 12:57:54 PM PDT 24
Peak memory 197684 kb
Host smart-7824169a-faf4-462c-a1af-a566d1f6b52c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876011398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1876011398
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1289366015
Short name T594
Test name
Test status
Simulation time 18540927 ps
CPU time 0.61 seconds
Started May 23 12:57:51 PM PDT 24
Finished May 23 12:57:53 PM PDT 24
Peak memory 194748 kb
Host smart-db5dbedb-fd28-45e7-b912-8293eed5f71b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289366015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1289366015
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2407169106
Short name T622
Test name
Test status
Simulation time 44629698 ps
CPU time 2.11 seconds
Started May 23 12:57:55 PM PDT 24
Finished May 23 12:58:00 PM PDT 24
Peak memory 199976 kb
Host smart-20bfbe67-c6c1-474c-b3e7-576b6bc2e4d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407169106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2407169106
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.825576335
Short name T573
Test name
Test status
Simulation time 572118612 ps
CPU time 3.22 seconds
Started May 23 12:57:54 PM PDT 24
Finished May 23 12:58:01 PM PDT 24
Peak memory 200048 kb
Host smart-97cacfea-9a7a-4b42-9762-848106bea6f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825576335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.825576335
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1342671415
Short name T553
Test name
Test status
Simulation time 1307070942 ps
CPU time 2.78 seconds
Started May 23 12:57:56 PM PDT 24
Finished May 23 12:58:02 PM PDT 24
Peak memory 200072 kb
Host smart-67f87730-9c45-48c4-874d-cb73a7dc33ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342671415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1342671415
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1118122372
Short name T584
Test name
Test status
Simulation time 30020001776 ps
CPU time 40.71 seconds
Started May 23 12:57:55 PM PDT 24
Finished May 23 12:58:39 PM PDT 24
Peak memory 215620 kb
Host smart-f111b0b1-4995-4f04-8e70-e8b5b9bc4a7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118122372 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.1118122372
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.525980069
Short name T557
Test name
Test status
Simulation time 51251186 ps
CPU time 0.79 seconds
Started May 23 12:57:52 PM PDT 24
Finished May 23 12:57:54 PM PDT 24
Peak memory 199124 kb
Host smart-cf653c97-db16-415a-8c24-44041137569a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525980069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.525980069
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.2695146839
Short name T623
Test name
Test status
Simulation time 24547007 ps
CPU time 0.6 seconds
Started May 23 12:57:55 PM PDT 24
Finished May 23 12:57:59 PM PDT 24
Peak memory 194784 kb
Host smart-96a1e037-eefd-4bf8-9b1b-f4dbfdd23318
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695146839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2695146839
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3197650097
Short name T570
Test name
Test status
Simulation time 280651118 ps
CPU time 1.13 seconds
Started May 23 12:57:54 PM PDT 24
Finished May 23 12:57:59 PM PDT 24
Peak memory 199680 kb
Host smart-66fc5420-e802-4b4c-b1cf-305688822151
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197650097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3197650097
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3159271900
Short name T579
Test name
Test status
Simulation time 329817331 ps
CPU time 4.04 seconds
Started May 23 12:57:52 PM PDT 24
Finished May 23 12:57:58 PM PDT 24
Peak memory 199992 kb
Host smart-b88d680b-c233-4cad-84fd-b564bfd73d7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159271900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3159271900
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2461795796
Short name T548
Test name
Test status
Simulation time 143746777 ps
CPU time 2.36 seconds
Started May 23 12:57:53 PM PDT 24
Finished May 23 12:57:57 PM PDT 24
Peak memory 208244 kb
Host smart-83881109-e871-4199-97f3-58538b41fd6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461795796 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2461795796
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.419492341
Short name T633
Test name
Test status
Simulation time 104641429 ps
CPU time 0.82 seconds
Started May 23 12:57:55 PM PDT 24
Finished May 23 12:57:59 PM PDT 24
Peak memory 199184 kb
Host smart-ba9cfdad-99f1-4ddf-b33c-bdfbbccaafe9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419492341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.419492341
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.4104025531
Short name T531
Test name
Test status
Simulation time 15870338 ps
CPU time 0.61 seconds
Started May 23 12:57:53 PM PDT 24
Finished May 23 12:57:56 PM PDT 24
Peak memory 194924 kb
Host smart-9a281fa6-8202-4f33-9ba6-5912ac72e4a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104025531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.4104025531
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3783042470
Short name T627
Test name
Test status
Simulation time 48585046 ps
CPU time 2.12 seconds
Started May 23 12:57:54 PM PDT 24
Finished May 23 12:58:00 PM PDT 24
Peak memory 199920 kb
Host smart-f575d1c0-8c25-4148-8b82-32a45606c38b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783042470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3783042470
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.396981858
Short name T564
Test name
Test status
Simulation time 96743206 ps
CPU time 1.31 seconds
Started May 23 12:57:51 PM PDT 24
Finished May 23 12:57:54 PM PDT 24
Peak memory 200064 kb
Host smart-b45eb68f-02a6-420e-9296-a2e8f018850b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396981858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.396981858
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1467496965
Short name T619
Test name
Test status
Simulation time 278684292 ps
CPU time 4 seconds
Started May 23 12:57:56 PM PDT 24
Finished May 23 12:58:03 PM PDT 24
Peak memory 200116 kb
Host smart-671c8a0b-9eb1-4060-ba85-eeed58b0ed7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467496965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1467496965
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1077505592
Short name T546
Test name
Test status
Simulation time 128168279877 ps
CPU time 449.65 seconds
Started May 23 12:58:08 PM PDT 24
Finished May 23 01:05:43 PM PDT 24
Peak memory 216660 kb
Host smart-07c64440-fe55-4f60-86d0-5a1a54bc85d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077505592 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1077505592
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2523036186
Short name T583
Test name
Test status
Simulation time 75705084 ps
CPU time 0.88 seconds
Started May 23 12:58:09 PM PDT 24
Finished May 23 12:58:15 PM PDT 24
Peak memory 199456 kb
Host smart-e731c014-a85e-47e7-9bcb-f788408861d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523036186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2523036186
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2789324287
Short name T649
Test name
Test status
Simulation time 12125056 ps
CPU time 0.59 seconds
Started May 23 12:58:06 PM PDT 24
Finished May 23 12:58:10 PM PDT 24
Peak memory 194808 kb
Host smart-14522f4b-4ef5-46e8-b8a0-2bb40f12263e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789324287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2789324287
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.766299032
Short name T611
Test name
Test status
Simulation time 44712913 ps
CPU time 2.28 seconds
Started May 23 12:58:06 PM PDT 24
Finished May 23 12:58:12 PM PDT 24
Peak memory 199248 kb
Host smart-6b4a37db-5ae4-4b70-97b3-6e99335b9680
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766299032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.766299032
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4149319175
Short name T77
Test name
Test status
Simulation time 80774873 ps
CPU time 1.39 seconds
Started May 23 12:57:54 PM PDT 24
Finished May 23 12:57:58 PM PDT 24
Peak memory 199976 kb
Host smart-a04783c8-9959-43ae-8150-55a6739d91f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149319175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.4149319175
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2140426815
Short name T637
Test name
Test status
Simulation time 283031059 ps
CPU time 2.98 seconds
Started May 23 12:57:56 PM PDT 24
Finished May 23 12:58:02 PM PDT 24
Peak memory 200052 kb
Host smart-543709b7-6af8-4a70-8153-d22b15e1ea7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140426815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2140426815
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3024481959
Short name T647
Test name
Test status
Simulation time 343567515 ps
CPU time 2.69 seconds
Started May 23 12:58:07 PM PDT 24
Finished May 23 12:58:15 PM PDT 24
Peak memory 208320 kb
Host smart-6835f4b9-09cd-4e1b-b2ef-f579f772ba05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024481959 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3024481959
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1890223280
Short name T645
Test name
Test status
Simulation time 184948125 ps
CPU time 0.8 seconds
Started May 23 12:58:06 PM PDT 24
Finished May 23 12:58:11 PM PDT 24
Peak memory 199256 kb
Host smart-64d2ddfe-3d27-453d-bf7d-3f80406a676a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890223280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1890223280
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2487276455
Short name T572
Test name
Test status
Simulation time 46353246 ps
CPU time 0.61 seconds
Started May 23 12:58:05 PM PDT 24
Finished May 23 12:58:09 PM PDT 24
Peak memory 194876 kb
Host smart-86ac7bb5-d49f-4957-a3b9-f2f724bb6338
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487276455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2487276455
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.852196696
Short name T607
Test name
Test status
Simulation time 75279599 ps
CPU time 1.67 seconds
Started May 23 12:58:04 PM PDT 24
Finished May 23 12:58:09 PM PDT 24
Peak memory 199952 kb
Host smart-8db8f057-feed-48ce-a9aa-8021e88a5f0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852196696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.852196696
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.351378674
Short name T610
Test name
Test status
Simulation time 131898347 ps
CPU time 1.62 seconds
Started May 23 12:58:09 PM PDT 24
Finished May 23 12:58:15 PM PDT 24
Peak memory 199976 kb
Host smart-8989e637-d0ca-4f9f-9345-77210078cd00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351378674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.351378674
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3484821814
Short name T67
Test name
Test status
Simulation time 331377572 ps
CPU time 2.93 seconds
Started May 23 12:58:05 PM PDT 24
Finished May 23 12:58:10 PM PDT 24
Peak memory 200132 kb
Host smart-e879221f-b7b8-474f-9896-5953e6e71844
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484821814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3484821814
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3449169453
Short name T115
Test name
Test status
Simulation time 491364823 ps
CPU time 8.12 seconds
Started May 23 12:57:37 PM PDT 24
Finished May 23 12:57:48 PM PDT 24
Peak memory 199540 kb
Host smart-d0430ff1-d78d-43ba-966a-da9fd6205646
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449169453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3449169453
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.260289189
Short name T571
Test name
Test status
Simulation time 1483011671 ps
CPU time 9.62 seconds
Started May 23 12:57:21 PM PDT 24
Finished May 23 12:57:32 PM PDT 24
Peak memory 200068 kb
Host smart-fb42d654-9e80-41dc-be2b-e2213c83648c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260289189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.260289189
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3449637776
Short name T71
Test name
Test status
Simulation time 19676989 ps
CPU time 0.73 seconds
Started May 23 12:57:25 PM PDT 24
Finished May 23 12:57:27 PM PDT 24
Peak memory 198092 kb
Host smart-68a40ef1-d9fa-4fbc-bb50-3eaf5d522b0a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449637776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3449637776
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.658975862
Short name T560
Test name
Test status
Simulation time 21749754 ps
CPU time 1.45 seconds
Started May 23 12:57:41 PM PDT 24
Finished May 23 12:57:45 PM PDT 24
Peak memory 200068 kb
Host smart-c24eb26c-23a7-47ab-8007-49616ef1986d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658975862 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.658975862
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2328898669
Short name T620
Test name
Test status
Simulation time 28115649 ps
CPU time 0.95 seconds
Started May 23 12:57:24 PM PDT 24
Finished May 23 12:57:27 PM PDT 24
Peak memory 199704 kb
Host smart-3c3a4106-459d-4e51-bae0-26088071ee52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328898669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2328898669
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2231350745
Short name T554
Test name
Test status
Simulation time 12964767 ps
CPU time 0.59 seconds
Started May 23 12:57:25 PM PDT 24
Finished May 23 12:57:27 PM PDT 24
Peak memory 194900 kb
Host smart-f428fca2-cd12-486f-9a49-54f74e114f34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231350745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2231350745
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1140591377
Short name T602
Test name
Test status
Simulation time 308035800 ps
CPU time 1.81 seconds
Started May 23 12:57:40 PM PDT 24
Finished May 23 12:57:45 PM PDT 24
Peak memory 199808 kb
Host smart-a3c5e25d-ae3d-46f4-ac99-d7586592725b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140591377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1140591377
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3308999655
Short name T75
Test name
Test status
Simulation time 207402605 ps
CPU time 2.23 seconds
Started May 23 12:57:22 PM PDT 24
Finished May 23 12:57:26 PM PDT 24
Peak memory 199992 kb
Host smart-e2caad5e-a2dc-4590-bd21-bc105c3158bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308999655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3308999655
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1417835165
Short name T586
Test name
Test status
Simulation time 176933152 ps
CPU time 1.75 seconds
Started May 23 12:57:23 PM PDT 24
Finished May 23 12:57:26 PM PDT 24
Peak memory 200140 kb
Host smart-d6c09d3c-d962-432f-8c28-0ce05c0c8dfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417835165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.1417835165
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.192884969
Short name T537
Test name
Test status
Simulation time 16608572 ps
CPU time 0.63 seconds
Started May 23 12:58:07 PM PDT 24
Finished May 23 12:58:13 PM PDT 24
Peak memory 194952 kb
Host smart-1a27ca17-0861-4d12-a526-2ae446045474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192884969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.192884969
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1587886000
Short name T534
Test name
Test status
Simulation time 14709740 ps
CPU time 0.62 seconds
Started May 23 12:58:08 PM PDT 24
Finished May 23 12:58:14 PM PDT 24
Peak memory 194728 kb
Host smart-bc0b5065-ff5d-4942-a37f-72492b512316
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587886000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1587886000
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1383608266
Short name T526
Test name
Test status
Simulation time 24411638 ps
CPU time 0.61 seconds
Started May 23 12:58:08 PM PDT 24
Finished May 23 12:58:14 PM PDT 24
Peak memory 194776 kb
Host smart-feaef85b-4386-4149-853f-9333d2191317
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383608266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1383608266
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.4214436918
Short name T625
Test name
Test status
Simulation time 43186812 ps
CPU time 0.58 seconds
Started May 23 12:58:06 PM PDT 24
Finished May 23 12:58:11 PM PDT 24
Peak memory 194784 kb
Host smart-d32a6283-d3af-4355-b4f3-dea06f21c212
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214436918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.4214436918
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.282093155
Short name T550
Test name
Test status
Simulation time 13614739 ps
CPU time 0.59 seconds
Started May 23 12:58:06 PM PDT 24
Finished May 23 12:58:10 PM PDT 24
Peak memory 194860 kb
Host smart-b7b8ba6c-078e-45e8-be26-516e077638fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282093155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.282093155
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1018051790
Short name T580
Test name
Test status
Simulation time 19440514 ps
CPU time 0.62 seconds
Started May 23 12:58:12 PM PDT 24
Finished May 23 12:58:17 PM PDT 24
Peak memory 194888 kb
Host smart-5c6691d0-2cce-4de3-a45c-0ee065551fd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018051790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1018051790
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.2136697839
Short name T598
Test name
Test status
Simulation time 17410498 ps
CPU time 0.63 seconds
Started May 23 12:58:05 PM PDT 24
Finished May 23 12:58:08 PM PDT 24
Peak memory 194836 kb
Host smart-21003c13-d14c-4111-b4ae-ae6f92c02ed7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136697839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2136697839
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.947409043
Short name T618
Test name
Test status
Simulation time 40380508 ps
CPU time 0.54 seconds
Started May 23 12:58:05 PM PDT 24
Finished May 23 12:58:09 PM PDT 24
Peak memory 194868 kb
Host smart-e65c486c-e126-4896-a672-9fab9b948347
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947409043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.947409043
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.4095270122
Short name T535
Test name
Test status
Simulation time 40100250 ps
CPU time 0.59 seconds
Started May 23 12:58:05 PM PDT 24
Finished May 23 12:58:09 PM PDT 24
Peak memory 194952 kb
Host smart-9c9e61ed-4a5d-4829-b3c5-0c36c113a752
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095270122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.4095270122
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3366245479
Short name T617
Test name
Test status
Simulation time 66955200 ps
CPU time 0.6 seconds
Started May 23 12:58:07 PM PDT 24
Finished May 23 12:58:12 PM PDT 24
Peak memory 194792 kb
Host smart-a0ebc00e-720b-40a2-99e1-f5e6681dd0b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366245479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3366245479
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2985395328
Short name T111
Test name
Test status
Simulation time 628870327 ps
CPU time 7.89 seconds
Started May 23 12:57:36 PM PDT 24
Finished May 23 12:57:45 PM PDT 24
Peak memory 199976 kb
Host smart-b8180225-a3d5-42f6-8740-aff207daf200
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985395328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2985395328
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2220527830
Short name T72
Test name
Test status
Simulation time 4067398475 ps
CPU time 6.14 seconds
Started May 23 12:57:36 PM PDT 24
Finished May 23 12:57:44 PM PDT 24
Peak memory 199652 kb
Host smart-787ff0eb-fccc-439e-b184-843d9e127a8b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220527830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2220527830
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2918812796
Short name T116
Test name
Test status
Simulation time 41160843 ps
CPU time 0.75 seconds
Started May 23 12:57:38 PM PDT 24
Finished May 23 12:57:42 PM PDT 24
Peak memory 197836 kb
Host smart-27eda089-2652-471c-98af-307551fd8553
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918812796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2918812796
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.71808966
Short name T615
Test name
Test status
Simulation time 273045069769 ps
CPU time 1365.61 seconds
Started May 23 12:57:37 PM PDT 24
Finished May 23 01:20:26 PM PDT 24
Peak memory 227084 kb
Host smart-2f60e724-398e-4636-83fc-b75f1ec82d2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71808966 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.71808966
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1404990837
Short name T107
Test name
Test status
Simulation time 189828213 ps
CPU time 0.8 seconds
Started May 23 12:57:38 PM PDT 24
Finished May 23 12:57:42 PM PDT 24
Peak memory 199768 kb
Host smart-4354de78-845e-4496-b98b-9b184dc79635
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404990837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1404990837
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.92313556
Short name T559
Test name
Test status
Simulation time 12810178 ps
CPU time 0.62 seconds
Started May 23 12:57:39 PM PDT 24
Finished May 23 12:57:43 PM PDT 24
Peak memory 194832 kb
Host smart-5ec011e7-af7e-4332-b1ba-d902b8917d27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92313556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.92313556
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.459891203
Short name T565
Test name
Test status
Simulation time 41342719 ps
CPU time 1.12 seconds
Started May 23 12:57:36 PM PDT 24
Finished May 23 12:57:40 PM PDT 24
Peak memory 199968 kb
Host smart-f436d70b-5ead-44f9-b4a0-6209356243ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459891203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.459891203
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.4256228597
Short name T640
Test name
Test status
Simulation time 31993096 ps
CPU time 1.59 seconds
Started May 23 12:57:36 PM PDT 24
Finished May 23 12:57:39 PM PDT 24
Peak memory 200004 kb
Host smart-05db8e39-98ec-4aa1-81db-3864beeae330
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256228597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.4256228597
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3473175017
Short name T643
Test name
Test status
Simulation time 103382813 ps
CPU time 1.8 seconds
Started May 23 12:57:37 PM PDT 24
Finished May 23 12:57:42 PM PDT 24
Peak memory 200016 kb
Host smart-d24e9416-d0be-4f51-9b22-6eeb648b961c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473175017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.3473175017
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1993966298
Short name T628
Test name
Test status
Simulation time 26454306 ps
CPU time 0.59 seconds
Started May 23 12:58:07 PM PDT 24
Finished May 23 12:58:13 PM PDT 24
Peak memory 194824 kb
Host smart-75f23dd6-5c7e-4475-99d6-6a30107c92d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993966298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1993966298
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3825709114
Short name T588
Test name
Test status
Simulation time 32474299 ps
CPU time 0.63 seconds
Started May 23 12:58:07 PM PDT 24
Finished May 23 12:58:12 PM PDT 24
Peak memory 194940 kb
Host smart-c541224f-186c-4c2d-b961-36840df05de9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825709114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3825709114
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1201439061
Short name T542
Test name
Test status
Simulation time 117839726 ps
CPU time 0.6 seconds
Started May 23 12:58:08 PM PDT 24
Finished May 23 12:58:14 PM PDT 24
Peak memory 194872 kb
Host smart-f0492e92-fa46-4094-b3bd-3e467399cf55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201439061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1201439061
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3211780017
Short name T624
Test name
Test status
Simulation time 12871091 ps
CPU time 0.61 seconds
Started May 23 12:58:05 PM PDT 24
Finished May 23 12:58:08 PM PDT 24
Peak memory 194956 kb
Host smart-9d2f201a-f6e8-454a-8d9f-b6077ac21a9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211780017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3211780017
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1317559551
Short name T591
Test name
Test status
Simulation time 11395626 ps
CPU time 0.6 seconds
Started May 23 12:58:08 PM PDT 24
Finished May 23 12:58:14 PM PDT 24
Peak memory 194972 kb
Host smart-3a4dfcdc-3d6c-4e4d-91a4-57f1ee1e6e0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317559551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1317559551
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2623614893
Short name T555
Test name
Test status
Simulation time 13638169 ps
CPU time 0.59 seconds
Started May 23 12:58:07 PM PDT 24
Finished May 23 12:58:12 PM PDT 24
Peak memory 194936 kb
Host smart-74f2e18e-a80b-419d-b6dc-7a3a27061012
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623614893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2623614893
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.1018257948
Short name T538
Test name
Test status
Simulation time 18944111 ps
CPU time 0.58 seconds
Started May 23 12:58:09 PM PDT 24
Finished May 23 12:58:15 PM PDT 24
Peak memory 194804 kb
Host smart-619a30d4-2c58-44b4-bb81-63145b78291e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018257948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1018257948
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2787744109
Short name T539
Test name
Test status
Simulation time 25050135 ps
CPU time 0.58 seconds
Started May 23 12:58:08 PM PDT 24
Finished May 23 12:58:14 PM PDT 24
Peak memory 194796 kb
Host smart-cffee2be-1948-400f-8479-dc4fc508534c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787744109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2787744109
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2218464121
Short name T551
Test name
Test status
Simulation time 58318587 ps
CPU time 0.6 seconds
Started May 23 12:58:13 PM PDT 24
Finished May 23 12:58:17 PM PDT 24
Peak memory 194848 kb
Host smart-9676e7e1-5da0-4798-9d26-c581ef70e1a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218464121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2218464121
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3987064146
Short name T653
Test name
Test status
Simulation time 13497524 ps
CPU time 0.58 seconds
Started May 23 12:58:05 PM PDT 24
Finished May 23 12:58:08 PM PDT 24
Peak memory 194888 kb
Host smart-fb739394-c1ae-4e86-b5d9-eaa2622bb2e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987064146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3987064146
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1706322673
Short name T589
Test name
Test status
Simulation time 437991341 ps
CPU time 5.62 seconds
Started May 23 12:57:38 PM PDT 24
Finished May 23 12:57:47 PM PDT 24
Peak memory 200108 kb
Host smart-42c42c1d-0e9e-4528-8436-1955d429bdd9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706322673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1706322673
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2803827249
Short name T113
Test name
Test status
Simulation time 1447826090 ps
CPU time 11.43 seconds
Started May 23 12:57:35 PM PDT 24
Finished May 23 12:57:48 PM PDT 24
Peak memory 199076 kb
Host smart-14c317b7-d2ec-4d26-864d-23e31a311d32
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803827249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2803827249
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2644700784
Short name T105
Test name
Test status
Simulation time 33426299 ps
CPU time 0.83 seconds
Started May 23 12:57:36 PM PDT 24
Finished May 23 12:57:39 PM PDT 24
Peak memory 199072 kb
Host smart-ab55ac2c-1f71-4210-a625-3858392490ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644700784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2644700784
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2084735015
Short name T532
Test name
Test status
Simulation time 110737358 ps
CPU time 1.64 seconds
Started May 23 12:57:36 PM PDT 24
Finished May 23 12:57:40 PM PDT 24
Peak memory 200168 kb
Host smart-7e7ca724-daa8-4a93-9c25-b2929a536657
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084735015 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.2084735015
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.490981125
Short name T563
Test name
Test status
Simulation time 84164406 ps
CPU time 0.82 seconds
Started May 23 12:57:38 PM PDT 24
Finished May 23 12:57:42 PM PDT 24
Peak memory 198832 kb
Host smart-0dabb139-c54a-40a3-abd6-4ac8df6169ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490981125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.490981125
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.518228465
Short name T651
Test name
Test status
Simulation time 31833347 ps
CPU time 0.57 seconds
Started May 23 12:57:38 PM PDT 24
Finished May 23 12:57:41 PM PDT 24
Peak memory 194844 kb
Host smart-9a944ebb-f7fa-44b8-8f4d-91587b0a0baa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518228465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.518228465
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2516669973
Short name T581
Test name
Test status
Simulation time 413188907 ps
CPU time 1.09 seconds
Started May 23 12:57:37 PM PDT 24
Finished May 23 12:57:40 PM PDT 24
Peak memory 199856 kb
Host smart-f3ce4bda-3c87-411d-b128-cde42b47312b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516669973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.2516669973
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.478158402
Short name T533
Test name
Test status
Simulation time 130698593 ps
CPU time 2.61 seconds
Started May 23 12:57:36 PM PDT 24
Finished May 23 12:57:41 PM PDT 24
Peak memory 200004 kb
Host smart-01958f89-d90a-4a16-8bcf-ec097de0f72d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478158402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.478158402
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2257941455
Short name T561
Test name
Test status
Simulation time 137121043 ps
CPU time 1.9 seconds
Started May 23 12:57:37 PM PDT 24
Finished May 23 12:57:42 PM PDT 24
Peak memory 200048 kb
Host smart-66ac4997-6d8d-4ce1-9a9b-c5f934994b85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257941455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2257941455
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.2267944723
Short name T631
Test name
Test status
Simulation time 117870368 ps
CPU time 0.63 seconds
Started May 23 12:58:06 PM PDT 24
Finished May 23 12:58:09 PM PDT 24
Peak memory 194960 kb
Host smart-368fc77f-8d9a-44e1-99cd-c16b301d9d04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267944723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2267944723
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.991852683
Short name T576
Test name
Test status
Simulation time 99099274 ps
CPU time 0.6 seconds
Started May 23 12:58:09 PM PDT 24
Finished May 23 12:58:15 PM PDT 24
Peak memory 194936 kb
Host smart-7400dc5a-9aca-461d-a1c2-9a464729697b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991852683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.991852683
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.620252823
Short name T603
Test name
Test status
Simulation time 137048388 ps
CPU time 0.64 seconds
Started May 23 12:58:06 PM PDT 24
Finished May 23 12:58:10 PM PDT 24
Peak memory 194924 kb
Host smart-5538e96b-22b5-40e7-af0a-75614f4adbfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620252823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.620252823
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.827523136
Short name T89
Test name
Test status
Simulation time 64255401 ps
CPU time 0.61 seconds
Started May 23 12:58:07 PM PDT 24
Finished May 23 12:58:12 PM PDT 24
Peak memory 194856 kb
Host smart-bd0d7b9b-b196-4ca6-bbc8-5f48811f75ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827523136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.827523136
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.140851099
Short name T642
Test name
Test status
Simulation time 21660957 ps
CPU time 0.6 seconds
Started May 23 12:58:10 PM PDT 24
Finished May 23 12:58:16 PM PDT 24
Peak memory 194952 kb
Host smart-55094f22-9463-4e48-af05-b370b4a282ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140851099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.140851099
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3576345009
Short name T88
Test name
Test status
Simulation time 26594649 ps
CPU time 0.6 seconds
Started May 23 12:58:06 PM PDT 24
Finished May 23 12:58:11 PM PDT 24
Peak memory 194780 kb
Host smart-8ea078ac-6d2d-4212-952e-2e392ea524aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576345009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3576345009
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3172211737
Short name T567
Test name
Test status
Simulation time 12435178 ps
CPU time 0.56 seconds
Started May 23 12:58:06 PM PDT 24
Finished May 23 12:58:10 PM PDT 24
Peak memory 194884 kb
Host smart-a47c73d8-64cc-497e-9469-f8e6dcb3442e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172211737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3172211737
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.2117668977
Short name T585
Test name
Test status
Simulation time 21747409 ps
CPU time 0.59 seconds
Started May 23 12:58:07 PM PDT 24
Finished May 23 12:58:13 PM PDT 24
Peak memory 194760 kb
Host smart-000035e7-fe36-4ab2-a055-ddb72d57e93b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117668977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2117668977
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.3065275766
Short name T601
Test name
Test status
Simulation time 20183016 ps
CPU time 0.64 seconds
Started May 23 12:58:10 PM PDT 24
Finished May 23 12:58:16 PM PDT 24
Peak memory 194776 kb
Host smart-fab58d8e-fef3-4671-afc6-4dbe23274a29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065275766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3065275766
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.815513182
Short name T621
Test name
Test status
Simulation time 15385853 ps
CPU time 0.58 seconds
Started May 23 12:58:05 PM PDT 24
Finished May 23 12:58:09 PM PDT 24
Peak memory 194784 kb
Host smart-009f5db7-857f-4097-88b3-079a6407c624
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815513182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.815513182
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1680862353
Short name T612
Test name
Test status
Simulation time 199507120 ps
CPU time 2.26 seconds
Started May 23 12:57:37 PM PDT 24
Finished May 23 12:57:41 PM PDT 24
Peak memory 200000 kb
Host smart-bf4fe1a3-5e3f-4619-a0d3-67325afa09df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680862353 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.1680862353
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2418699376
Short name T599
Test name
Test status
Simulation time 199975004 ps
CPU time 0.79 seconds
Started May 23 12:57:36 PM PDT 24
Finished May 23 12:57:39 PM PDT 24
Peak memory 199264 kb
Host smart-cf7a5257-0a9b-47c0-ac8a-26cfc2fe15c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418699376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2418699376
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3777455169
Short name T568
Test name
Test status
Simulation time 14923037 ps
CPU time 0.57 seconds
Started May 23 12:57:38 PM PDT 24
Finished May 23 12:57:42 PM PDT 24
Peak memory 194856 kb
Host smart-17861493-5361-4006-9c5f-75fb0c9b782a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777455169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3777455169
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1400478995
Short name T595
Test name
Test status
Simulation time 164759951 ps
CPU time 2.18 seconds
Started May 23 12:57:41 PM PDT 24
Finished May 23 12:57:46 PM PDT 24
Peak memory 199940 kb
Host smart-64df38e8-228e-4333-915e-625711557c67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400478995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1400478995
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3442298249
Short name T582
Test name
Test status
Simulation time 370730404 ps
CPU time 2.1 seconds
Started May 23 12:57:34 PM PDT 24
Finished May 23 12:57:38 PM PDT 24
Peak memory 200140 kb
Host smart-d9c691d2-0970-4854-acd2-6266a5062b9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442298249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3442298249
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3460497164
Short name T137
Test name
Test status
Simulation time 48502681 ps
CPU time 1.75 seconds
Started May 23 12:57:37 PM PDT 24
Finished May 23 12:57:41 PM PDT 24
Peak memory 200048 kb
Host smart-231ac2c2-c9c3-4d4b-9c93-5f5917e23ca4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460497164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3460497164
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1921867894
Short name T597
Test name
Test status
Simulation time 48163632298 ps
CPU time 497.03 seconds
Started May 23 12:57:37 PM PDT 24
Finished May 23 01:05:56 PM PDT 24
Peak memory 215756 kb
Host smart-e8888e87-522f-4d94-b7e0-9c794895d32e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921867894 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1921867894
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.589239493
Short name T109
Test name
Test status
Simulation time 15239386 ps
CPU time 0.71 seconds
Started May 23 12:57:39 PM PDT 24
Finished May 23 12:57:43 PM PDT 24
Peak memory 198100 kb
Host smart-95564166-7add-41a8-be52-f47596164228
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589239493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.589239493
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.4024005378
Short name T646
Test name
Test status
Simulation time 15632459 ps
CPU time 0.59 seconds
Started May 23 12:57:38 PM PDT 24
Finished May 23 12:57:42 PM PDT 24
Peak memory 194952 kb
Host smart-d6147a46-073b-4f8e-836e-0d8a9ead1d38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024005378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.4024005378
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3683196523
Short name T558
Test name
Test status
Simulation time 113718573 ps
CPU time 1.59 seconds
Started May 23 12:57:37 PM PDT 24
Finished May 23 12:57:42 PM PDT 24
Peak memory 200028 kb
Host smart-c21e14c7-f812-4fb7-8879-fbb530bb4014
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683196523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.3683196523
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.4009701313
Short name T639
Test name
Test status
Simulation time 356614394 ps
CPU time 3.62 seconds
Started May 23 12:57:42 PM PDT 24
Finished May 23 12:57:47 PM PDT 24
Peak memory 200004 kb
Host smart-be511bf2-863e-4259-ab0e-c196472b80db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009701313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.4009701313
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1386332825
Short name T134
Test name
Test status
Simulation time 582737411 ps
CPU time 2.84 seconds
Started May 23 12:57:37 PM PDT 24
Finished May 23 12:57:42 PM PDT 24
Peak memory 200088 kb
Host smart-7d45cdc1-0ee7-4cf2-a9b4-e3c368f3e2ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386332825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1386332825
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1273026600
Short name T600
Test name
Test status
Simulation time 204010038 ps
CPU time 1.19 seconds
Started May 23 12:57:38 PM PDT 24
Finished May 23 12:57:42 PM PDT 24
Peak memory 199976 kb
Host smart-c9b49fed-e91a-400e-b6b1-8037a1e42bbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273026600 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1273026600
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2612208554
Short name T104
Test name
Test status
Simulation time 14793844 ps
CPU time 0.84 seconds
Started May 23 12:57:35 PM PDT 24
Finished May 23 12:57:38 PM PDT 24
Peak memory 199848 kb
Host smart-35f38f14-3d2f-4cd5-b237-49e5c477045d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612208554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2612208554
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2486948752
Short name T632
Test name
Test status
Simulation time 17310583 ps
CPU time 0.6 seconds
Started May 23 12:57:35 PM PDT 24
Finished May 23 12:57:37 PM PDT 24
Peak memory 194800 kb
Host smart-6c738b7d-bc88-496f-9602-3745b2bc81bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486948752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2486948752
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1965482368
Short name T556
Test name
Test status
Simulation time 217591368 ps
CPU time 1.99 seconds
Started May 23 12:57:40 PM PDT 24
Finished May 23 12:57:45 PM PDT 24
Peak memory 200008 kb
Host smart-a85e806f-07ac-4750-8655-2580bfd45483
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965482368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.1965482368
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1499205764
Short name T626
Test name
Test status
Simulation time 332821059 ps
CPU time 3 seconds
Started May 23 12:57:39 PM PDT 24
Finished May 23 12:57:45 PM PDT 24
Peak memory 199984 kb
Host smart-f233d17b-51ca-41d1-a14f-1061978b2d68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499205764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1499205764
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3632427164
Short name T613
Test name
Test status
Simulation time 996801996 ps
CPU time 3.09 seconds
Started May 23 12:57:38 PM PDT 24
Finished May 23 12:57:44 PM PDT 24
Peak memory 200100 kb
Host smart-149703c4-d071-441c-8c21-9b4a5294bce2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632427164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3632427164
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3624498731
Short name T574
Test name
Test status
Simulation time 385579832315 ps
CPU time 1084.28 seconds
Started May 23 12:57:38 PM PDT 24
Finished May 23 01:15:45 PM PDT 24
Peak memory 216500 kb
Host smart-7c5905d7-21d2-412f-8d35-f4b86115de0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624498731 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3624498731
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3451047379
Short name T652
Test name
Test status
Simulation time 60008253 ps
CPU time 0.89 seconds
Started May 23 12:57:36 PM PDT 24
Finished May 23 12:57:39 PM PDT 24
Peak memory 199912 kb
Host smart-77c87e62-44eb-4d01-8aa5-d69528528c16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451047379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3451047379
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.252880057
Short name T587
Test name
Test status
Simulation time 30723966 ps
CPU time 0.61 seconds
Started May 23 12:57:37 PM PDT 24
Finished May 23 12:57:40 PM PDT 24
Peak memory 194892 kb
Host smart-ad67efe1-f418-4559-aa15-c3b897bb7910
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252880057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.252880057
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3291969150
Short name T529
Test name
Test status
Simulation time 94896258 ps
CPU time 1.93 seconds
Started May 23 12:57:37 PM PDT 24
Finished May 23 12:57:42 PM PDT 24
Peak memory 200016 kb
Host smart-0f439d7c-bb54-4d47-b514-ee8669534df2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291969150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3291969150
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.12130768
Short name T596
Test name
Test status
Simulation time 745717364 ps
CPU time 3.52 seconds
Started May 23 12:57:37 PM PDT 24
Finished May 23 12:57:44 PM PDT 24
Peak memory 199968 kb
Host smart-a54052ac-08e2-4488-906f-4cf13db26a35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12130768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.12130768
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1791493463
Short name T614
Test name
Test status
Simulation time 90616529 ps
CPU time 2.93 seconds
Started May 23 12:57:38 PM PDT 24
Finished May 23 12:57:44 PM PDT 24
Peak memory 199996 kb
Host smart-27891944-4688-4c2e-9a9d-c6b93346d8aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791493463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1791493463
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.4104847826
Short name T616
Test name
Test status
Simulation time 98407322 ps
CPU time 1.68 seconds
Started May 23 12:57:58 PM PDT 24
Finished May 23 12:58:02 PM PDT 24
Peak memory 200032 kb
Host smart-ad1954ef-59ec-49e8-b6dd-370a2352cff0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104847826 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.4104847826
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1729695328
Short name T590
Test name
Test status
Simulation time 24773004 ps
CPU time 0.69 seconds
Started May 23 12:57:55 PM PDT 24
Finished May 23 12:57:59 PM PDT 24
Peak memory 197960 kb
Host smart-032c8833-8fc8-464e-91eb-f6a93b1bf64c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729695328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1729695328
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2745977314
Short name T648
Test name
Test status
Simulation time 42784944 ps
CPU time 0.57 seconds
Started May 23 12:57:38 PM PDT 24
Finished May 23 12:57:42 PM PDT 24
Peak memory 194952 kb
Host smart-9c4aa167-70fd-415f-9b8c-e55cca26e3f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745977314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2745977314
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2784607963
Short name T544
Test name
Test status
Simulation time 176758804 ps
CPU time 2.32 seconds
Started May 23 12:57:55 PM PDT 24
Finished May 23 12:58:00 PM PDT 24
Peak memory 199604 kb
Host smart-7273cfb8-5cef-4936-9487-844acf66ed83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784607963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2784607963
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2617851724
Short name T541
Test name
Test status
Simulation time 431324747 ps
CPU time 3.09 seconds
Started May 23 12:57:40 PM PDT 24
Finished May 23 12:57:46 PM PDT 24
Peak memory 200132 kb
Host smart-757004f5-a964-45c6-8d2b-27e824336093
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617851724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2617851724
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3324165299
Short name T138
Test name
Test status
Simulation time 225663790 ps
CPU time 4.3 seconds
Started May 23 12:57:38 PM PDT 24
Finished May 23 12:57:45 PM PDT 24
Peak memory 199976 kb
Host smart-b50d3cc5-40ef-4ddb-95f2-35aef25a2c09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324165299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.3324165299
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1649293180
Short name T167
Test name
Test status
Simulation time 44493791 ps
CPU time 0.59 seconds
Started May 23 01:02:56 PM PDT 24
Finished May 23 01:02:58 PM PDT 24
Peak memory 195552 kb
Host smart-d21c05c0-4d2c-49c8-85aa-de9d66a8638e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649293180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1649293180
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.1180625094
Short name T332
Test name
Test status
Simulation time 516655570 ps
CPU time 24.85 seconds
Started May 23 01:02:36 PM PDT 24
Finished May 23 01:03:02 PM PDT 24
Peak memory 208156 kb
Host smart-17ee461d-e6eb-48ac-85e9-d363ea9d2e22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1180625094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.1180625094
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3809523053
Short name T413
Test name
Test status
Simulation time 2377851726 ps
CPU time 11.62 seconds
Started May 23 01:03:01 PM PDT 24
Finished May 23 01:03:14 PM PDT 24
Peak memory 200092 kb
Host smart-fac9c7fd-f03e-4228-80fa-79b457a75588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809523053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3809523053
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.434055358
Short name T287
Test name
Test status
Simulation time 5620480215 ps
CPU time 384.7 seconds
Started May 23 01:02:51 PM PDT 24
Finished May 23 01:09:16 PM PDT 24
Peak memory 652968 kb
Host smart-97f44c9d-be1c-4f31-b96d-6e1d372a9441
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=434055358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.434055358
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1923135406
Short name T278
Test name
Test status
Simulation time 40331679310 ps
CPU time 86.68 seconds
Started May 23 01:03:03 PM PDT 24
Finished May 23 01:04:31 PM PDT 24
Peak memory 200076 kb
Host smart-b22df263-1906-4afd-938a-0f61a0e0f9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923135406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1923135406
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.666216995
Short name T382
Test name
Test status
Simulation time 168712325 ps
CPU time 2.47 seconds
Started May 23 01:02:52 PM PDT 24
Finished May 23 01:02:55 PM PDT 24
Peak memory 199892 kb
Host smart-e7886177-3b1f-43ce-b529-8a6d5b75b801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666216995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.666216995
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.1707107606
Short name T166
Test name
Test status
Simulation time 57736452 ps
CPU time 1.29 seconds
Started May 23 01:03:01 PM PDT 24
Finished May 23 01:03:04 PM PDT 24
Peak memory 200000 kb
Host smart-cdea70d0-5e5c-4adf-a7ff-b64e662c6224
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707107606 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.1707107606
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.2562199780
Short name T79
Test name
Test status
Simulation time 237243283194 ps
CPU time 532.38 seconds
Started May 23 01:02:36 PM PDT 24
Finished May 23 01:11:29 PM PDT 24
Peak memory 200024 kb
Host smart-064800e1-3527-4363-b0ed-36da0da159d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562199780 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.2562199780
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.453833239
Short name T216
Test name
Test status
Simulation time 22790479676 ps
CPU time 72.93 seconds
Started May 23 01:02:47 PM PDT 24
Finished May 23 01:04:00 PM PDT 24
Peak memory 200204 kb
Host smart-4b272d12-46e6-4a4e-937f-2e6820688509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453833239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.453833239
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3691446212
Short name T360
Test name
Test status
Simulation time 344434264 ps
CPU time 20 seconds
Started May 23 01:03:00 PM PDT 24
Finished May 23 01:03:22 PM PDT 24
Peak memory 216212 kb
Host smart-f5ef0dcb-3ec9-4656-8c04-cecc7cdec23c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3691446212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3691446212
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2918162717
Short name T307
Test name
Test status
Simulation time 341037468 ps
CPU time 6.65 seconds
Started May 23 01:02:45 PM PDT 24
Finished May 23 01:02:53 PM PDT 24
Peak memory 199916 kb
Host smart-bc164a95-5c4f-4eb1-a09b-d2b339401a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918162717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2918162717
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3312390525
Short name T357
Test name
Test status
Simulation time 68670656 ps
CPU time 2.88 seconds
Started May 23 01:03:05 PM PDT 24
Finished May 23 01:03:09 PM PDT 24
Peak memory 211456 kb
Host smart-0eb50dd8-a67f-4acc-8585-62dcfeba2113
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3312390525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3312390525
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_long_msg.447427214
Short name T176
Test name
Test status
Simulation time 3781835884 ps
CPU time 50.21 seconds
Started May 23 01:03:10 PM PDT 24
Finished May 23 01:04:02 PM PDT 24
Peak memory 200204 kb
Host smart-4ef84c36-c3b8-4337-9ead-dcd20f2b2095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447427214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.447427214
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_smoke.1427681875
Short name T313
Test name
Test status
Simulation time 384574268 ps
CPU time 5.96 seconds
Started May 23 01:02:54 PM PDT 24
Finished May 23 01:03:00 PM PDT 24
Peak memory 200092 kb
Host smart-b5b1ae4c-62a9-47b8-b869-c455cf174fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427681875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1427681875
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.694162085
Short name T462
Test name
Test status
Simulation time 245393400 ps
CPU time 1.41 seconds
Started May 23 01:03:06 PM PDT 24
Finished May 23 01:03:10 PM PDT 24
Peak memory 199912 kb
Host smart-5b50a51f-6c62-4e9a-80f1-2e28a47d4068
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694162085 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_hmac_vectors.694162085
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.2201565405
Short name T438
Test name
Test status
Simulation time 40177836963 ps
CPU time 521.94 seconds
Started May 23 01:03:00 PM PDT 24
Finished May 23 01:11:44 PM PDT 24
Peak memory 200080 kb
Host smart-30b510b4-3ae9-455c-a69e-e72e0f073a06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201565405 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.2201565405
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.4190293157
Short name T174
Test name
Test status
Simulation time 3417136198 ps
CPU time 7.06 seconds
Started May 23 01:02:54 PM PDT 24
Finished May 23 01:03:02 PM PDT 24
Peak memory 200156 kb
Host smart-5a86f970-7a0d-4c42-b6e4-36d62441fcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190293157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.4190293157
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.507801970
Short name T20
Test name
Test status
Simulation time 10941959 ps
CPU time 0.59 seconds
Started May 23 01:03:17 PM PDT 24
Finished May 23 01:03:20 PM PDT 24
Peak memory 195728 kb
Host smart-98e1c698-5cec-469f-8203-edecde180bd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507801970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.507801970
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3522344873
Short name T238
Test name
Test status
Simulation time 1450709420 ps
CPU time 38.52 seconds
Started May 23 01:03:19 PM PDT 24
Finished May 23 01:03:59 PM PDT 24
Peak memory 216336 kb
Host smart-163b9388-79da-4e44-a0aa-c0b0e7bdf644
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3522344873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3522344873
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.4081909675
Short name T500
Test name
Test status
Simulation time 10456110180 ps
CPU time 46.96 seconds
Started May 23 01:03:18 PM PDT 24
Finished May 23 01:04:07 PM PDT 24
Peak memory 200068 kb
Host smart-bdec4409-2757-472c-a0ce-662ec4438714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081909675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.4081909675
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1254214849
Short name T334
Test name
Test status
Simulation time 4098571586 ps
CPU time 1011.14 seconds
Started May 23 01:03:07 PM PDT 24
Finished May 23 01:20:01 PM PDT 24
Peak memory 711108 kb
Host smart-cca36a9a-76ce-45bc-b052-7c7cc2d4c33c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1254214849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1254214849
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3602092158
Short name T24
Test name
Test status
Simulation time 1660953298 ps
CPU time 7.66 seconds
Started May 23 01:03:10 PM PDT 24
Finished May 23 01:03:20 PM PDT 24
Peak memory 199872 kb
Host smart-4b56c9c4-dfcc-47a9-b1e6-c521b2c791cb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602092158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3602092158
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.2827752623
Short name T10
Test name
Test status
Simulation time 8184866387 ps
CPU time 108.07 seconds
Started May 23 01:03:09 PM PDT 24
Finished May 23 01:04:59 PM PDT 24
Peak memory 200112 kb
Host smart-82f15005-94e9-4e5a-8e74-5b8cba474676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827752623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2827752623
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1812457606
Short name T252
Test name
Test status
Simulation time 40813841 ps
CPU time 1.51 seconds
Started May 23 01:03:14 PM PDT 24
Finished May 23 01:03:17 PM PDT 24
Peak memory 200004 kb
Host smart-158a53e8-b251-4842-8008-8fda6fe73dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812457606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1812457606
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.2518870028
Short name T209
Test name
Test status
Simulation time 72383958 ps
CPU time 1.23 seconds
Started May 23 01:03:06 PM PDT 24
Finished May 23 01:03:10 PM PDT 24
Peak memory 199828 kb
Host smart-426ec354-3696-4228-8e78-41b2b1b282c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518870028 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.2518870028
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.1012752587
Short name T163
Test name
Test status
Simulation time 3140880034 ps
CPU time 67.16 seconds
Started May 23 01:03:08 PM PDT 24
Finished May 23 01:04:17 PM PDT 24
Peak memory 199928 kb
Host smart-3ae6dcb6-3e46-4496-a577-04f2d6fda836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012752587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1012752587
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3832172606
Short name T426
Test name
Test status
Simulation time 13813351 ps
CPU time 0.61 seconds
Started May 23 01:03:08 PM PDT 24
Finished May 23 01:03:11 PM PDT 24
Peak memory 195632 kb
Host smart-3ef3ebca-1e78-4a09-9492-53488809503b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832172606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3832172606
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2419938581
Short name T201
Test name
Test status
Simulation time 3835707201 ps
CPU time 53.21 seconds
Started May 23 01:03:14 PM PDT 24
Finished May 23 01:04:08 PM PDT 24
Peak memory 216340 kb
Host smart-4c8e5782-d4c7-4305-89d0-6066396f519d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2419938581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2419938581
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.1204227012
Short name T444
Test name
Test status
Simulation time 1318384088 ps
CPU time 10.21 seconds
Started May 23 01:03:15 PM PDT 24
Finished May 23 01:03:26 PM PDT 24
Peak memory 199896 kb
Host smart-c41eee4c-7052-40ab-aa94-11499dc98953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204227012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1204227012
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.2016340211
Short name T365
Test name
Test status
Simulation time 4516437640 ps
CPU time 1065.88 seconds
Started May 23 01:03:10 PM PDT 24
Finished May 23 01:20:58 PM PDT 24
Peak memory 734940 kb
Host smart-df3c887f-7469-4352-9aeb-ee7cdfb8fa2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2016340211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2016340211
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2151523692
Short name T324
Test name
Test status
Simulation time 8760565806 ps
CPU time 83.19 seconds
Started May 23 01:03:10 PM PDT 24
Finished May 23 01:04:35 PM PDT 24
Peak memory 200092 kb
Host smart-489084ea-e7ae-4e98-a9f9-5fae4eb48dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151523692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2151523692
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1130854820
Short name T511
Test name
Test status
Simulation time 1105948694 ps
CPU time 3.53 seconds
Started May 23 01:03:16 PM PDT 24
Finished May 23 01:03:21 PM PDT 24
Peak memory 199948 kb
Host smart-ca7ff4d6-a234-48f9-b00a-dbfacec6aece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130854820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1130854820
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.1353446528
Short name T430
Test name
Test status
Simulation time 249742713 ps
CPU time 1.23 seconds
Started May 23 01:03:18 PM PDT 24
Finished May 23 01:03:21 PM PDT 24
Peak memory 199940 kb
Host smart-8217cfe3-9fdf-423b-9694-82a4fafe2bf8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353446528 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.1353446528
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.748330710
Short name T369
Test name
Test status
Simulation time 17384422959 ps
CPU time 487.22 seconds
Started May 23 01:03:13 PM PDT 24
Finished May 23 01:11:21 PM PDT 24
Peak memory 200096 kb
Host smart-14aa86e8-7a4b-4d3a-8fec-0ab32cfca458
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748330710 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.748330710
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.58438807
Short name T178
Test name
Test status
Simulation time 2695282617 ps
CPU time 29.68 seconds
Started May 23 01:03:09 PM PDT 24
Finished May 23 01:03:40 PM PDT 24
Peak memory 199980 kb
Host smart-20104248-8299-4860-adcb-190db8cd8681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58438807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.58438807
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1482399348
Short name T364
Test name
Test status
Simulation time 28243999 ps
CPU time 0.57 seconds
Started May 23 01:03:09 PM PDT 24
Finished May 23 01:03:11 PM PDT 24
Peak memory 194704 kb
Host smart-760800a5-7ac7-46a1-bc64-0b61a6fc5ac8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482399348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1482399348
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.296575947
Short name T478
Test name
Test status
Simulation time 214758169 ps
CPU time 8.65 seconds
Started May 23 01:03:13 PM PDT 24
Finished May 23 01:03:23 PM PDT 24
Peak memory 216068 kb
Host smart-38c283aa-4d93-4934-9d46-9e4d886eed2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=296575947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.296575947
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1497230059
Short name T119
Test name
Test status
Simulation time 1250587071 ps
CPU time 34.75 seconds
Started May 23 01:03:16 PM PDT 24
Finished May 23 01:03:52 PM PDT 24
Peak memory 199988 kb
Host smart-bdcdddbf-c0f7-41a2-91f8-748d2c7ac5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497230059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1497230059
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.4063887090
Short name T225
Test name
Test status
Simulation time 1999831785 ps
CPU time 535.7 seconds
Started May 23 01:03:15 PM PDT 24
Finished May 23 01:12:12 PM PDT 24
Peak memory 694064 kb
Host smart-654a9876-3a87-4265-854e-6b6c4710f28a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4063887090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.4063887090
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_long_msg.2487710594
Short name T423
Test name
Test status
Simulation time 17632050972 ps
CPU time 58.25 seconds
Started May 23 01:03:18 PM PDT 24
Finished May 23 01:04:19 PM PDT 24
Peak memory 200144 kb
Host smart-502311b2-0aa5-4693-b041-4f0720bd64fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487710594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2487710594
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.2111919933
Short name T204
Test name
Test status
Simulation time 1658111938 ps
CPU time 5.41 seconds
Started May 23 01:03:15 PM PDT 24
Finished May 23 01:03:22 PM PDT 24
Peak memory 199964 kb
Host smart-62d0c666-4249-4b00-8b87-30bbf89dd4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111919933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2111919933
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.3795235877
Short name T271
Test name
Test status
Simulation time 46422412 ps
CPU time 0.99 seconds
Started May 23 01:03:12 PM PDT 24
Finished May 23 01:03:15 PM PDT 24
Peak memory 199564 kb
Host smart-33405dfa-d5e3-41ae-a19b-f1576a9370b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795235877 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.3795235877
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.2693499023
Short name T257
Test name
Test status
Simulation time 26223738188 ps
CPU time 507.71 seconds
Started May 23 01:03:17 PM PDT 24
Finished May 23 01:11:46 PM PDT 24
Peak memory 199972 kb
Host smart-226e8da4-833c-43c5-a7b5-3d4abb14d2f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693499023 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.2693499023
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.910358627
Short name T378
Test name
Test status
Simulation time 7563704271 ps
CPU time 17.55 seconds
Started May 23 01:03:08 PM PDT 24
Finished May 23 01:03:28 PM PDT 24
Peak memory 200004 kb
Host smart-3ab38d8b-3258-4eb7-a131-a3c90dbbdcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910358627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.910358627
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3100803077
Short name T289
Test name
Test status
Simulation time 15181227 ps
CPU time 0.63 seconds
Started May 23 01:03:28 PM PDT 24
Finished May 23 01:03:31 PM PDT 24
Peak memory 195728 kb
Host smart-836a7501-eb02-42c4-890c-61b333921a78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100803077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3100803077
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2477313417
Short name T498
Test name
Test status
Simulation time 841521835 ps
CPU time 43.55 seconds
Started May 23 01:03:20 PM PDT 24
Finished May 23 01:04:05 PM PDT 24
Peak memory 212744 kb
Host smart-6ee4c934-9d7e-44ac-9fdc-3ed4229ec1dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2477313417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2477313417
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1845001067
Short name T64
Test name
Test status
Simulation time 4537180488 ps
CPU time 21.75 seconds
Started May 23 01:03:21 PM PDT 24
Finished May 23 01:03:44 PM PDT 24
Peak memory 199948 kb
Host smart-90a83d11-807d-417d-b9ef-cf563493f428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845001067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1845001067
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_error.1750531622
Short name T26
Test name
Test status
Simulation time 5806858418 ps
CPU time 25.87 seconds
Started May 23 01:03:19 PM PDT 24
Finished May 23 01:03:47 PM PDT 24
Peak memory 200084 kb
Host smart-3b29caf0-4b14-4375-9f56-11ddb52f36bd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750531622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1750531622
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2702785901
Short name T15
Test name
Test status
Simulation time 102337902 ps
CPU time 2.3 seconds
Started May 23 01:03:22 PM PDT 24
Finished May 23 01:03:26 PM PDT 24
Peak memory 200136 kb
Host smart-b2c39b00-e2c8-4807-8c56-9f48abdb35f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702785901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2702785901
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2475458020
Short name T339
Test name
Test status
Simulation time 117326303 ps
CPU time 1.96 seconds
Started May 23 01:03:07 PM PDT 24
Finished May 23 01:03:12 PM PDT 24
Peak memory 200036 kb
Host smart-fccfba56-db1f-4adf-9d61-be1776cebc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475458020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2475458020
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.2100422705
Short name T288
Test name
Test status
Simulation time 243320086 ps
CPU time 1.05 seconds
Started May 23 01:03:27 PM PDT 24
Finished May 23 01:03:31 PM PDT 24
Peak memory 199048 kb
Host smart-18356f39-85c1-4d85-9faa-d95957d59211
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100422705 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.2100422705
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.3486530410
Short name T245
Test name
Test status
Simulation time 40902257885 ps
CPU time 505.22 seconds
Started May 23 01:03:18 PM PDT 24
Finished May 23 01:11:45 PM PDT 24
Peak memory 199260 kb
Host smart-cd125d3a-593b-4fdf-a231-8bb87083b0aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486530410 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.3486530410
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3679005727
Short name T510
Test name
Test status
Simulation time 4250608620 ps
CPU time 38.66 seconds
Started May 23 01:03:27 PM PDT 24
Finished May 23 01:04:08 PM PDT 24
Peak memory 199944 kb
Host smart-d37feff2-7502-47ec-9ec2-f722646fcf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679005727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3679005727
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.681198858
Short name T272
Test name
Test status
Simulation time 28066267 ps
CPU time 0.6 seconds
Started May 23 01:03:16 PM PDT 24
Finished May 23 01:03:18 PM PDT 24
Peak memory 195652 kb
Host smart-95333489-0f7c-414d-ade1-0bca3303d73a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681198858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.681198858
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.299513188
Short name T376
Test name
Test status
Simulation time 875277566 ps
CPU time 18.21 seconds
Started May 23 01:03:16 PM PDT 24
Finished May 23 01:03:36 PM PDT 24
Peak memory 216424 kb
Host smart-20f83dd2-fb9a-4e3f-9c1a-6e216d72b0e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=299513188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.299513188
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.99356703
Short name T329
Test name
Test status
Simulation time 7731455923 ps
CPU time 461.61 seconds
Started May 23 01:03:16 PM PDT 24
Finished May 23 01:10:59 PM PDT 24
Peak memory 681536 kb
Host smart-c7c0b26e-1a01-47a7-bfa8-89124bdc9b9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99356703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.99356703
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3495320047
Short name T516
Test name
Test status
Simulation time 450199325 ps
CPU time 13.28 seconds
Started May 23 01:03:20 PM PDT 24
Finished May 23 01:03:35 PM PDT 24
Peak memory 199828 kb
Host smart-aaaa8897-c02f-4de0-8b87-3d95a6229c28
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495320047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3495320047
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.2802135873
Short name T281
Test name
Test status
Simulation time 4519102900 ps
CPU time 128.66 seconds
Started May 23 01:03:19 PM PDT 24
Finished May 23 01:05:29 PM PDT 24
Peak memory 200068 kb
Host smart-718e0be0-60ad-4a6c-b307-2cb21ec1ab85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802135873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2802135873
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.2565831352
Short name T212
Test name
Test status
Simulation time 88580706 ps
CPU time 2.81 seconds
Started May 23 01:03:23 PM PDT 24
Finished May 23 01:03:28 PM PDT 24
Peak memory 200036 kb
Host smart-7467a039-a5e8-418c-a1e4-567af063da22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565831352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2565831352
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.1319773090
Short name T217
Test name
Test status
Simulation time 60229726 ps
CPU time 1.35 seconds
Started May 23 01:03:25 PM PDT 24
Finished May 23 01:03:29 PM PDT 24
Peak memory 199908 kb
Host smart-c9230596-21be-42d1-9314-15718f365e1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319773090 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.1319773090
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.3780996058
Short name T471
Test name
Test status
Simulation time 7553624868 ps
CPU time 428.77 seconds
Started May 23 01:03:23 PM PDT 24
Finished May 23 01:10:33 PM PDT 24
Peak memory 200148 kb
Host smart-4fbdb57a-255c-424d-9a99-8ad0208c4ce2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780996058 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.3780996058
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2356675393
Short name T172
Test name
Test status
Simulation time 6300294242 ps
CPU time 51.4 seconds
Started May 23 01:03:18 PM PDT 24
Finished May 23 01:04:11 PM PDT 24
Peak memory 199092 kb
Host smart-4662028f-f063-4d96-a999-d06844c0983a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356675393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2356675393
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.4265682013
Short name T177
Test name
Test status
Simulation time 59020740 ps
CPU time 0.6 seconds
Started May 23 01:03:26 PM PDT 24
Finished May 23 01:03:30 PM PDT 24
Peak memory 196352 kb
Host smart-2ecb4654-e501-45e7-9a29-0ad4ba8b18df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265682013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.4265682013
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1448605197
Short name T374
Test name
Test status
Simulation time 833950819 ps
CPU time 40.13 seconds
Started May 23 01:03:24 PM PDT 24
Finished May 23 01:04:06 PM PDT 24
Peak memory 216276 kb
Host smart-a3901c7b-779d-4502-8f3f-0c39fee24ec4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1448605197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1448605197
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1698475593
Short name T208
Test name
Test status
Simulation time 446274217 ps
CPU time 5.95 seconds
Started May 23 01:03:21 PM PDT 24
Finished May 23 01:03:29 PM PDT 24
Peak memory 199828 kb
Host smart-d7b5c6d0-b036-47e6-bd4b-a4f35845bfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698475593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1698475593
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.4143233647
Short name T310
Test name
Test status
Simulation time 5374386152 ps
CPU time 629.41 seconds
Started May 23 01:03:23 PM PDT 24
Finished May 23 01:13:54 PM PDT 24
Peak memory 501768 kb
Host smart-a00abde9-cce1-4282-b557-859de7e2d317
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4143233647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.4143233647
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1414321728
Short name T243
Test name
Test status
Simulation time 5512650770 ps
CPU time 76.66 seconds
Started May 23 01:03:18 PM PDT 24
Finished May 23 01:04:36 PM PDT 24
Peak memory 200120 kb
Host smart-920d2f4a-a42c-4e45-956e-031eeea0554c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414321728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1414321728
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1350508335
Short name T448
Test name
Test status
Simulation time 1836308634 ps
CPU time 4.33 seconds
Started May 23 01:03:23 PM PDT 24
Finished May 23 01:03:29 PM PDT 24
Peak memory 199960 kb
Host smart-7bf10cb5-2712-4a20-b4a8-8728616cbbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350508335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1350508335
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.4123166565
Short name T425
Test name
Test status
Simulation time 32968824 ps
CPU time 1.19 seconds
Started May 23 01:03:25 PM PDT 24
Finished May 23 01:03:29 PM PDT 24
Peak memory 200076 kb
Host smart-e77f83a8-e4b5-4df9-b467-321b4cda8a77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123166565 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.4123166565
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.342672323
Short name T351
Test name
Test status
Simulation time 48871835062 ps
CPU time 436.36 seconds
Started May 23 01:03:37 PM PDT 24
Finished May 23 01:10:55 PM PDT 24
Peak memory 200168 kb
Host smart-6305e81b-8506-4b70-8275-ec2761960c7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342672323 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.342672323
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.2289610133
Short name T37
Test name
Test status
Simulation time 210165252 ps
CPU time 3.18 seconds
Started May 23 01:03:21 PM PDT 24
Finished May 23 01:03:26 PM PDT 24
Peak memory 199972 kb
Host smart-c8676503-91dc-4e71-9ee7-6476fb815b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289610133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.2289610133
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.1806071846
Short name T330
Test name
Test status
Simulation time 38537555 ps
CPU time 0.59 seconds
Started May 23 01:03:26 PM PDT 24
Finished May 23 01:03:30 PM PDT 24
Peak memory 195636 kb
Host smart-70de73b7-bffc-441f-9831-e08dfd65dcaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806071846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.1806071846
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.3426892972
Short name T383
Test name
Test status
Simulation time 288068992 ps
CPU time 7.24 seconds
Started May 23 01:03:21 PM PDT 24
Finished May 23 01:03:29 PM PDT 24
Peak memory 216036 kb
Host smart-270bc586-6c9e-40e7-9d7e-b030b65f5ab6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3426892972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.3426892972
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2665873596
Short name T146
Test name
Test status
Simulation time 4538179983 ps
CPU time 14.47 seconds
Started May 23 01:03:25 PM PDT 24
Finished May 23 01:03:43 PM PDT 24
Peak memory 200172 kb
Host smart-aff0e83b-84e8-41aa-b9d3-b4066545d09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665873596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2665873596
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.1643839009
Short name T300
Test name
Test status
Simulation time 36441812 ps
CPU time 2.69 seconds
Started May 23 01:03:28 PM PDT 24
Finished May 23 01:03:33 PM PDT 24
Peak memory 200048 kb
Host smart-72fecfb4-0133-42e7-a485-4c2616f32032
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1643839009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1643839009
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_long_msg.4013200662
Short name T446
Test name
Test status
Simulation time 19181884761 ps
CPU time 92.97 seconds
Started May 23 01:03:25 PM PDT 24
Finished May 23 01:05:01 PM PDT 24
Peak memory 200084 kb
Host smart-89d53414-4c2a-44eb-8d73-7fb3e5896d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013200662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.4013200662
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.1535163614
Short name T502
Test name
Test status
Simulation time 236204483 ps
CPU time 2.3 seconds
Started May 23 01:03:23 PM PDT 24
Finished May 23 01:03:27 PM PDT 24
Peak memory 200032 kb
Host smart-308e3804-254e-4a1e-98b9-adcec3c5936c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535163614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1535163614
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.2409904652
Short name T86
Test name
Test status
Simulation time 386618986432 ps
CPU time 1878.91 seconds
Started May 23 01:03:17 PM PDT 24
Finished May 23 01:34:38 PM PDT 24
Peak memory 651392 kb
Host smart-9c590e5d-1413-421f-8c0e-e27dcece0422
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409904652 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2409904652
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.2732994042
Short name T280
Test name
Test status
Simulation time 183888583 ps
CPU time 1.19 seconds
Started May 23 01:03:18 PM PDT 24
Finished May 23 01:03:21 PM PDT 24
Peak memory 200040 kb
Host smart-23d27e3e-d675-45fe-9859-1952c000b8be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732994042 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.2732994042
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.1246319101
Short name T78
Test name
Test status
Simulation time 443224530317 ps
CPU time 493.02 seconds
Started May 23 01:03:28 PM PDT 24
Finished May 23 01:11:43 PM PDT 24
Peak memory 199932 kb
Host smart-486fc8ec-1d45-44b0-ba3c-9ac0d6a9a021
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246319101 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.1246319101
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_alert_test.422022743
Short name T490
Test name
Test status
Simulation time 27554616 ps
CPU time 0.57 seconds
Started May 23 01:03:27 PM PDT 24
Finished May 23 01:03:31 PM PDT 24
Peak memory 194608 kb
Host smart-e6786d9a-6c0a-4f2a-93e3-f2ab72e507ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422022743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.422022743
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2988156200
Short name T349
Test name
Test status
Simulation time 3698185904 ps
CPU time 44.75 seconds
Started May 23 01:03:17 PM PDT 24
Finished May 23 01:04:03 PM PDT 24
Peak memory 208264 kb
Host smart-858f9ee0-3a41-4ca1-986b-ee9a20095812
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2988156200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2988156200
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1393629837
Short name T487
Test name
Test status
Simulation time 1632881539 ps
CPU time 39.17 seconds
Started May 23 01:03:19 PM PDT 24
Finished May 23 01:04:06 PM PDT 24
Peak memory 199968 kb
Host smart-ab2eb30d-b459-4ace-bd85-0297b5377934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393629837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1393629837
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2586378530
Short name T282
Test name
Test status
Simulation time 2481068042 ps
CPU time 613.96 seconds
Started May 23 01:03:24 PM PDT 24
Finished May 23 01:13:40 PM PDT 24
Peak memory 713108 kb
Host smart-81c12834-3690-4692-86db-502501a0f12c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2586378530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2586378530
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_long_msg.4280384213
Short name T102
Test name
Test status
Simulation time 41615991042 ps
CPU time 102.47 seconds
Started May 23 01:03:20 PM PDT 24
Finished May 23 01:05:04 PM PDT 24
Peak memory 200000 kb
Host smart-b5d863bd-6da7-42a2-a2d2-798c4f816f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280384213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.4280384213
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2240982172
Short name T5
Test name
Test status
Simulation time 64586683 ps
CPU time 2.06 seconds
Started May 23 01:03:21 PM PDT 24
Finished May 23 01:03:24 PM PDT 24
Peak memory 200044 kb
Host smart-ecc6f009-7d2a-4ada-92d7-cd5b57a8e82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240982172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2240982172
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.3877713481
Short name T220
Test name
Test status
Simulation time 994175158 ps
CPU time 1.36 seconds
Started May 23 01:03:22 PM PDT 24
Finished May 23 01:03:25 PM PDT 24
Peak memory 200076 kb
Host smart-2cb8e54d-3a7e-47ee-997c-71cf1972c8cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877713481 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.3877713481
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.711179293
Short name T301
Test name
Test status
Simulation time 24817524746 ps
CPU time 466.67 seconds
Started May 23 01:03:21 PM PDT 24
Finished May 23 01:11:09 PM PDT 24
Peak memory 199988 kb
Host smart-5c41ee22-d90f-46a6-a8ce-dc134ec93a9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711179293 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.711179293
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1110605356
Short name T335
Test name
Test status
Simulation time 2224949918 ps
CPU time 10.37 seconds
Started May 23 01:03:21 PM PDT 24
Finished May 23 01:03:33 PM PDT 24
Peak memory 200064 kb
Host smart-16cdef84-8a37-49b3-8759-1a9c4acae782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110605356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1110605356
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2988456656
Short name T469
Test name
Test status
Simulation time 12944315 ps
CPU time 0.57 seconds
Started May 23 01:03:25 PM PDT 24
Finished May 23 01:03:27 PM PDT 24
Peak memory 195304 kb
Host smart-649e501c-d7f8-48c0-b9b4-ffaa9c6e34aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988456656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2988456656
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.3064364199
Short name T436
Test name
Test status
Simulation time 2385633094 ps
CPU time 18.77 seconds
Started May 23 01:03:18 PM PDT 24
Finished May 23 01:03:38 PM PDT 24
Peak memory 224696 kb
Host smart-19db3aeb-d904-4d39-8970-be450f24f76f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3064364199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.3064364199
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.407203200
Short name T361
Test name
Test status
Simulation time 1351077605 ps
CPU time 7.29 seconds
Started May 23 01:03:27 PM PDT 24
Finished May 23 01:03:37 PM PDT 24
Peak memory 199896 kb
Host smart-61b17f95-08f2-414d-bf54-51d10559deff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407203200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.407203200
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1221973865
Short name T391
Test name
Test status
Simulation time 15301973818 ps
CPU time 494.7 seconds
Started May 23 01:03:21 PM PDT 24
Finished May 23 01:11:38 PM PDT 24
Peak memory 670112 kb
Host smart-257099cf-ac17-474d-81eb-3329255bcdad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1221973865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1221973865
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1592699097
Short name T184
Test name
Test status
Simulation time 611380247 ps
CPU time 1.89 seconds
Started May 23 01:03:19 PM PDT 24
Finished May 23 01:03:23 PM PDT 24
Peak memory 199968 kb
Host smart-328038cd-a2e7-41e3-9195-79608165a8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592699097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1592699097
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.1860708901
Short name T59
Test name
Test status
Simulation time 216337173 ps
CPU time 2.67 seconds
Started May 23 01:03:25 PM PDT 24
Finished May 23 01:03:31 PM PDT 24
Peak memory 199876 kb
Host smart-7fd57546-babb-4aa7-ac2d-29216104920f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860708901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1860708901
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1358702834
Short name T141
Test name
Test status
Simulation time 180836304615 ps
CPU time 1638.77 seconds
Started May 23 01:03:22 PM PDT 24
Finished May 23 01:30:43 PM PDT 24
Peak memory 772028 kb
Host smart-2e37eb3f-d2c4-4f56-9292-1c1c169f202f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358702834 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1358702834
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.447844802
Short name T337
Test name
Test status
Simulation time 53756901 ps
CPU time 1.1 seconds
Started May 23 01:03:18 PM PDT 24
Finished May 23 01:03:32 PM PDT 24
Peak memory 198920 kb
Host smart-902f38f2-633f-41b3-a149-1d38271be072
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447844802 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_hmac_vectors.447844802
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.228007291
Short name T477
Test name
Test status
Simulation time 28966808894 ps
CPU time 521.25 seconds
Started May 23 01:03:28 PM PDT 24
Finished May 23 01:12:12 PM PDT 24
Peak memory 199912 kb
Host smart-c6cf996f-dba7-4d71-b86d-b38088be0f08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228007291 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.228007291
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.1381960126
Short name T259
Test name
Test status
Simulation time 4270130505 ps
CPU time 58.41 seconds
Started May 23 01:03:20 PM PDT 24
Finished May 23 01:04:19 PM PDT 24
Peak memory 199936 kb
Host smart-e755173a-188c-4f19-a826-944b3c1c1be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381960126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1381960126
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/185.hmac_stress_all_with_rand_reset.749872633
Short name T74
Test name
Test status
Simulation time 304626692269 ps
CPU time 1243.48 seconds
Started May 23 01:05:01 PM PDT 24
Finished May 23 01:25:48 PM PDT 24
Peak memory 531780 kb
Host smart-300b8f55-3f57-414f-9386-7b3108b52e0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=749872633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.hmac_stress_all_with_rand_reset.749872633
Directory /workspace/185.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.138603864
Short name T148
Test name
Test status
Simulation time 14220018 ps
CPU time 0.59 seconds
Started May 23 01:03:42 PM PDT 24
Finished May 23 01:03:45 PM PDT 24
Peak memory 195628 kb
Host smart-3782785f-2148-4759-a15e-346d70368853
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138603864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.138603864
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3017276022
Short name T246
Test name
Test status
Simulation time 3681814359 ps
CPU time 20.28 seconds
Started May 23 01:03:24 PM PDT 24
Finished May 23 01:03:46 PM PDT 24
Peak memory 216484 kb
Host smart-385c6ac6-55bc-4ef1-a85b-34b1ac985ede
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3017276022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3017276022
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1979328765
Short name T396
Test name
Test status
Simulation time 4920096977 ps
CPU time 63.69 seconds
Started May 23 01:03:26 PM PDT 24
Finished May 23 01:04:33 PM PDT 24
Peak memory 199996 kb
Host smart-299191a4-9b50-4fda-bdb4-cf7eae28d2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979328765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1979328765
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.853306376
Short name T223
Test name
Test status
Simulation time 2691549814 ps
CPU time 141.87 seconds
Started May 23 01:03:25 PM PDT 24
Finished May 23 01:05:50 PM PDT 24
Peak memory 443736 kb
Host smart-3d352d55-b802-41e0-8e75-81e1d785c042
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=853306376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.853306376
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_smoke.1494160300
Short name T370
Test name
Test status
Simulation time 380247087 ps
CPU time 5.9 seconds
Started May 23 01:03:54 PM PDT 24
Finished May 23 01:04:07 PM PDT 24
Peak memory 200072 kb
Host smart-46579455-eb28-4723-9770-60dc98d807f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494160300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1494160300
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.1276219592
Short name T449
Test name
Test status
Simulation time 889755402 ps
CPU time 1.25 seconds
Started May 23 01:03:27 PM PDT 24
Finished May 23 01:03:31 PM PDT 24
Peak memory 199864 kb
Host smart-740e1d7b-b65b-47ff-8d1d-648ca8535b2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276219592 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.1276219592
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.1802692070
Short name T504
Test name
Test status
Simulation time 34231471151 ps
CPU time 438.88 seconds
Started May 23 01:03:28 PM PDT 24
Finished May 23 01:10:49 PM PDT 24
Peak memory 200100 kb
Host smart-0812cb4d-93a9-4795-b2dd-3440575610ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802692070 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.1802692070
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1165634977
Short name T319
Test name
Test status
Simulation time 428184615 ps
CPU time 21.42 seconds
Started May 23 01:03:29 PM PDT 24
Finished May 23 01:03:53 PM PDT 24
Peak memory 199964 kb
Host smart-77526bae-a152-4f9a-a998-1b2bf5752f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165634977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1165634977
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/194.hmac_stress_all_with_rand_reset.2380019113
Short name T12
Test name
Test status
Simulation time 3338459939 ps
CPU time 26.76 seconds
Started May 23 01:05:09 PM PDT 24
Finished May 23 01:05:37 PM PDT 24
Peak memory 208528 kb
Host smart-6b282dd6-a19f-480d-a872-86532633280c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2380019113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.hmac_stress_all_with_rand_reset.2380019113
Directory /workspace/194.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.3258508800
Short name T237
Test name
Test status
Simulation time 15215655 ps
CPU time 0.58 seconds
Started May 23 01:03:03 PM PDT 24
Finished May 23 01:03:05 PM PDT 24
Peak memory 194676 kb
Host smart-99c80076-38fb-4ce7-8fa4-2c05903b4472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258508800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3258508800
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.387629684
Short name T525
Test name
Test status
Simulation time 900434047 ps
CPU time 12.73 seconds
Started May 23 01:03:03 PM PDT 24
Finished May 23 01:03:18 PM PDT 24
Peak memory 216280 kb
Host smart-d456299c-ffb6-4582-b9cd-e51e3d8059b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=387629684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.387629684
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3800694845
Short name T325
Test name
Test status
Simulation time 1455240691 ps
CPU time 18.48 seconds
Started May 23 01:03:06 PM PDT 24
Finished May 23 01:03:26 PM PDT 24
Peak memory 199948 kb
Host smart-1059f05f-5b16-4abf-9159-4e87ed9eace9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800694845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3800694845
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.2727182631
Short name T517
Test name
Test status
Simulation time 2155472816 ps
CPU time 592.08 seconds
Started May 23 01:02:57 PM PDT 24
Finished May 23 01:12:50 PM PDT 24
Peak memory 749052 kb
Host smart-cc195563-13fc-490e-90d5-7c83189cc793
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2727182631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2727182631
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.4112864065
Short name T40
Test name
Test status
Simulation time 115356912 ps
CPU time 0.99 seconds
Started May 23 01:02:55 PM PDT 24
Finished May 23 01:02:57 PM PDT 24
Peak memory 217860 kb
Host smart-58842ac5-71a4-407f-9069-3f289996307a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112864065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.4112864065
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.4202628260
Short name T85
Test name
Test status
Simulation time 118956987 ps
CPU time 3.51 seconds
Started May 23 01:03:03 PM PDT 24
Finished May 23 01:03:08 PM PDT 24
Peak memory 199920 kb
Host smart-78cff02b-31a7-40c7-9f1d-2211928eff1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202628260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.4202628260
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.1469441150
Short name T483
Test name
Test status
Simulation time 367312223 ps
CPU time 1.02 seconds
Started May 23 01:02:55 PM PDT 24
Finished May 23 01:02:57 PM PDT 24
Peak memory 199176 kb
Host smart-e298d19e-b876-453c-a313-0452f82cb9a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469441150 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.1469441150
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.883387464
Short name T147
Test name
Test status
Simulation time 282402671552 ps
CPU time 502.88 seconds
Started May 23 01:03:05 PM PDT 24
Finished May 23 01:11:30 PM PDT 24
Peak memory 200004 kb
Host smart-9ac9af59-c3a5-4ee1-9744-76eeb4dc252d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883387464 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.883387464
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.1943761409
Short name T292
Test name
Test status
Simulation time 7104606682 ps
CPU time 78.91 seconds
Started May 23 01:02:51 PM PDT 24
Finished May 23 01:04:10 PM PDT 24
Peak memory 200096 kb
Host smart-90acaa27-0241-4b41-83f5-844f26b89c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943761409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1943761409
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.393610493
Short name T21
Test name
Test status
Simulation time 27428216 ps
CPU time 0.54 seconds
Started May 23 01:03:33 PM PDT 24
Finished May 23 01:03:36 PM PDT 24
Peak memory 195428 kb
Host smart-bd4aadfa-aaeb-4be1-b6c5-ccfa1e31fbb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393610493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.393610493
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3349293781
Short name T131
Test name
Test status
Simulation time 20085905211 ps
CPU time 68.76 seconds
Started May 23 01:03:52 PM PDT 24
Finished May 23 01:05:06 PM PDT 24
Peak memory 199972 kb
Host smart-c96291d2-8816-47b4-8bfe-15cda91e11b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349293781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3349293781
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.2920804839
Short name T275
Test name
Test status
Simulation time 21207526629 ps
CPU time 763.1 seconds
Started May 23 01:03:26 PM PDT 24
Finished May 23 01:16:12 PM PDT 24
Peak memory 742744 kb
Host smart-9cf437c9-2933-428e-9d54-1c1afcba8cb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2920804839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2920804839
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1915000940
Short name T171
Test name
Test status
Simulation time 7652932537 ps
CPU time 74.36 seconds
Started May 23 01:03:33 PM PDT 24
Finished May 23 01:04:49 PM PDT 24
Peak memory 200100 kb
Host smart-3bf00fb4-e422-4e65-ae95-dbc3c28ff441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915000940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1915000940
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1189027282
Short name T442
Test name
Test status
Simulation time 264615252 ps
CPU time 4.28 seconds
Started May 23 01:03:42 PM PDT 24
Finished May 23 01:03:49 PM PDT 24
Peak memory 200024 kb
Host smart-bd55fa9f-97ab-4428-8e10-5f9e3b0f2039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189027282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1189027282
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.2161837854
Short name T415
Test name
Test status
Simulation time 107116482 ps
CPU time 0.93 seconds
Started May 23 01:03:25 PM PDT 24
Finished May 23 01:03:28 PM PDT 24
Peak memory 199404 kb
Host smart-47532875-d672-4360-988e-4cbe3c4c539a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161837854 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.2161837854
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.2201212683
Short name T233
Test name
Test status
Simulation time 216918346031 ps
CPU time 501.01 seconds
Started May 23 01:03:26 PM PDT 24
Finished May 23 01:11:50 PM PDT 24
Peak memory 200068 kb
Host smart-745c010f-b9d2-4798-bd02-19b71220942d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201212683 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.2201212683
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.1143640875
Short name T479
Test name
Test status
Simulation time 2183620267 ps
CPU time 34.61 seconds
Started May 23 01:03:24 PM PDT 24
Finished May 23 01:04:00 PM PDT 24
Peak memory 200008 kb
Host smart-b130df9e-cc26-46bd-a61c-18780256d0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143640875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1143640875
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2012857737
Short name T385
Test name
Test status
Simulation time 17126408 ps
CPU time 0.64 seconds
Started May 23 01:03:29 PM PDT 24
Finished May 23 01:03:32 PM PDT 24
Peak memory 195616 kb
Host smart-82e350a1-5578-4834-aa60-34099181e8e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012857737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2012857737
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1235903167
Short name T420
Test name
Test status
Simulation time 598178447 ps
CPU time 8.7 seconds
Started May 23 01:03:23 PM PDT 24
Finished May 23 01:03:34 PM PDT 24
Peak memory 200048 kb
Host smart-029dfac1-9624-4bf1-89ee-3b06261ee86c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1235903167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1235903167
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1604765238
Short name T347
Test name
Test status
Simulation time 985861704 ps
CPU time 26.62 seconds
Started May 23 01:03:25 PM PDT 24
Finished May 23 01:03:55 PM PDT 24
Peak memory 199928 kb
Host smart-13f32f98-026c-4d24-911b-f8e73241b917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604765238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1604765238
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.224290676
Short name T398
Test name
Test status
Simulation time 1173025735 ps
CPU time 135.25 seconds
Started May 23 01:03:19 PM PDT 24
Finished May 23 01:05:36 PM PDT 24
Peak memory 600452 kb
Host smart-84329a1d-9c7f-475c-a319-98ada13734a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=224290676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.224290676
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_long_msg.4275619832
Short name T523
Test name
Test status
Simulation time 1896175431 ps
CPU time 110 seconds
Started May 23 01:03:26 PM PDT 24
Finished May 23 01:05:19 PM PDT 24
Peak memory 199936 kb
Host smart-d6868b6f-8c9a-40a3-9229-6bf4f6a3f1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275619832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.4275619832
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2969424642
Short name T350
Test name
Test status
Simulation time 2417488419 ps
CPU time 6.18 seconds
Started May 23 01:03:43 PM PDT 24
Finished May 23 01:03:52 PM PDT 24
Peak memory 200084 kb
Host smart-e2c21a11-42a8-47b5-b0fa-cea0c1c86428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969424642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2969424642
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.3793280733
Short name T256
Test name
Test status
Simulation time 52921741 ps
CPU time 1.2 seconds
Started May 23 01:03:29 PM PDT 24
Finished May 23 01:03:33 PM PDT 24
Peak memory 199852 kb
Host smart-dafbd2d5-a795-42f0-bafb-4bf4b8887ed1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793280733 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.3793280733
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.813770739
Short name T386
Test name
Test status
Simulation time 33845495268 ps
CPU time 465.67 seconds
Started May 23 01:03:21 PM PDT 24
Finished May 23 01:11:09 PM PDT 24
Peak memory 199944 kb
Host smart-57174c6c-fa88-4097-9118-a09a74ca8121
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813770739 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.813770739
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2681248683
Short name T202
Test name
Test status
Simulation time 1596121813 ps
CPU time 30.03 seconds
Started May 23 01:03:25 PM PDT 24
Finished May 23 01:03:58 PM PDT 24
Peak memory 199904 kb
Host smart-1731b320-82f3-4ae0-b117-5c68897d2af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681248683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2681248683
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3215340139
Short name T485
Test name
Test status
Simulation time 22844022 ps
CPU time 0.61 seconds
Started May 23 01:03:24 PM PDT 24
Finished May 23 01:03:27 PM PDT 24
Peak memory 195716 kb
Host smart-bd2343ad-f633-493f-a8a5-bd9e25f8c642
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215340139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3215340139
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.112255683
Short name T320
Test name
Test status
Simulation time 537314791 ps
CPU time 14.29 seconds
Started May 23 01:03:40 PM PDT 24
Finished May 23 01:03:56 PM PDT 24
Peak memory 219472 kb
Host smart-f2560fec-5080-49eb-85fa-477ffb53bb86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=112255683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.112255683
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1756333175
Short name T36
Test name
Test status
Simulation time 155002109 ps
CPU time 7.98 seconds
Started May 23 01:03:34 PM PDT 24
Finished May 23 01:03:44 PM PDT 24
Peak memory 199960 kb
Host smart-c3418b88-5730-46dd-9a42-c3965ffea592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756333175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1756333175
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.371175508
Short name T465
Test name
Test status
Simulation time 1191207337 ps
CPU time 290.71 seconds
Started May 23 01:03:26 PM PDT 24
Finished May 23 01:08:20 PM PDT 24
Peak memory 589056 kb
Host smart-4ca24de8-856a-46a1-9be2-090291fc79ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=371175508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.371175508
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_long_msg.755980346
Short name T295
Test name
Test status
Simulation time 7650013657 ps
CPU time 112.64 seconds
Started May 23 01:03:26 PM PDT 24
Finished May 23 01:05:22 PM PDT 24
Peak memory 200084 kb
Host smart-0117d766-aa5c-426e-ae4e-c5cdd421540a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755980346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.755980346
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1731317286
Short name T155
Test name
Test status
Simulation time 459270475 ps
CPU time 5.42 seconds
Started May 23 01:03:17 PM PDT 24
Finished May 23 01:03:24 PM PDT 24
Peak memory 199944 kb
Host smart-8494bc2f-8122-4a9f-8a93-821c8e255fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731317286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1731317286
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all_with_rand_reset.3310190106
Short name T73
Test name
Test status
Simulation time 49957577620 ps
CPU time 2161.58 seconds
Started May 23 01:03:23 PM PDT 24
Finished May 23 01:39:27 PM PDT 24
Peak memory 212452 kb
Host smart-90881d63-a1ca-496b-b349-c7e8005958a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3310190106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all_with_rand_reset.3310190106
Directory /workspace/22.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.2387579860
Short name T381
Test name
Test status
Simulation time 33008380 ps
CPU time 1.16 seconds
Started May 23 01:03:21 PM PDT 24
Finished May 23 01:03:24 PM PDT 24
Peak memory 199956 kb
Host smart-d55f29ae-e845-47e6-bf87-cd9e6f8fbd0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387579860 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.2387579860
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.2247920491
Short name T7
Test name
Test status
Simulation time 10933108899 ps
CPU time 460.86 seconds
Started May 23 01:03:25 PM PDT 24
Finished May 23 01:11:09 PM PDT 24
Peak memory 199988 kb
Host smart-ac8bea66-fc1d-4e37-bb2f-83f7af35d308
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247920491 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.2247920491
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2986884074
Short name T315
Test name
Test status
Simulation time 2222583194 ps
CPU time 41.7 seconds
Started May 23 01:03:26 PM PDT 24
Finished May 23 01:04:11 PM PDT 24
Peak memory 199928 kb
Host smart-2a797f07-7f06-4c0f-a39a-bfee24dfc2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986884074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2986884074
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.1905582303
Short name T429
Test name
Test status
Simulation time 18637870 ps
CPU time 0.59 seconds
Started May 23 01:03:35 PM PDT 24
Finished May 23 01:03:38 PM PDT 24
Peak memory 194596 kb
Host smart-dc981bc4-228e-4970-a051-47901b190ea4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905582303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1905582303
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1011794738
Short name T458
Test name
Test status
Simulation time 4047949300 ps
CPU time 57.72 seconds
Started May 23 01:03:19 PM PDT 24
Finished May 23 01:04:18 PM PDT 24
Peak memory 231960 kb
Host smart-b040a9af-0c03-4572-92c8-0e5c26fef87a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1011794738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1011794738
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.490901511
Short name T213
Test name
Test status
Simulation time 203905231 ps
CPU time 9.88 seconds
Started May 23 01:03:27 PM PDT 24
Finished May 23 01:03:40 PM PDT 24
Peak memory 199908 kb
Host smart-d8c08925-50fe-41b3-9e55-7dc9a76a09d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490901511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.490901511
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2587595277
Short name T358
Test name
Test status
Simulation time 2854204234 ps
CPU time 729.63 seconds
Started May 23 01:03:29 PM PDT 24
Finished May 23 01:15:41 PM PDT 24
Peak memory 748884 kb
Host smart-a3a67e7a-b2ba-4904-a3f8-e3b3ee8d5499
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2587595277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2587595277
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_long_msg.190817385
Short name T205
Test name
Test status
Simulation time 7021525479 ps
CPU time 53.52 seconds
Started May 23 01:03:24 PM PDT 24
Finished May 23 01:04:19 PM PDT 24
Peak memory 200080 kb
Host smart-0baec757-552a-4368-8158-3422240a2ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190817385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.190817385
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2482606930
Short name T99
Test name
Test status
Simulation time 145809492 ps
CPU time 2.53 seconds
Started May 23 01:03:26 PM PDT 24
Finished May 23 01:03:32 PM PDT 24
Peak memory 200024 kb
Host smart-e6b8337c-20c4-40f6-9081-09052abde33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482606930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2482606930
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.1785214298
Short name T372
Test name
Test status
Simulation time 354739388 ps
CPU time 0.96 seconds
Started May 23 01:03:38 PM PDT 24
Finished May 23 01:03:41 PM PDT 24
Peak memory 198508 kb
Host smart-ab142b74-83e9-4e2c-bffd-f28f067417ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785214298 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.1785214298
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.3215321218
Short name T291
Test name
Test status
Simulation time 7928076716 ps
CPU time 422.4 seconds
Started May 23 01:03:33 PM PDT 24
Finished May 23 01:10:38 PM PDT 24
Peak memory 200128 kb
Host smart-972dcba5-d6bc-4e1f-b38e-2b494d7c1a01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215321218 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.3215321218
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.930458270
Short name T503
Test name
Test status
Simulation time 2030068523 ps
CPU time 32.44 seconds
Started May 23 01:03:21 PM PDT 24
Finished May 23 01:03:55 PM PDT 24
Peak memory 199968 kb
Host smart-7ec5b2cd-4e26-4363-b691-cfb5b712ffd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930458270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.930458270
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3249847529
Short name T191
Test name
Test status
Simulation time 14124267 ps
CPU time 0.57 seconds
Started May 23 01:03:38 PM PDT 24
Finished May 23 01:03:40 PM PDT 24
Peak memory 194600 kb
Host smart-02a8b283-68e2-4456-bdc2-f91f417a47b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249847529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3249847529
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.4275699391
Short name T264
Test name
Test status
Simulation time 319368325 ps
CPU time 18.63 seconds
Started May 23 01:03:26 PM PDT 24
Finished May 23 01:03:48 PM PDT 24
Peak memory 232712 kb
Host smart-59e563fc-9057-458e-82d3-b9d1b975b374
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4275699391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.4275699391
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.839302261
Short name T84
Test name
Test status
Simulation time 1931676710 ps
CPU time 26.32 seconds
Started May 23 01:03:20 PM PDT 24
Finished May 23 01:03:48 PM PDT 24
Peak memory 200044 kb
Host smart-a7638877-778b-4773-b32e-ce6f24c391c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839302261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.839302261
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.2555833036
Short name T161
Test name
Test status
Simulation time 2507944832 ps
CPU time 668.92 seconds
Started May 23 01:03:25 PM PDT 24
Finished May 23 01:14:38 PM PDT 24
Peak memory 744152 kb
Host smart-99cbfb4b-fed3-4fa1-a13e-b9c27edf056e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2555833036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.2555833036
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3946563004
Short name T23
Test name
Test status
Simulation time 6285626830 ps
CPU time 118.33 seconds
Started May 23 01:03:19 PM PDT 24
Finished May 23 01:05:19 PM PDT 24
Peak memory 200076 kb
Host smart-0588715a-6650-4ae7-9069-a36d15f20e8c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946563004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3946563004
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.4061489498
Short name T453
Test name
Test status
Simulation time 46565765196 ps
CPU time 59.29 seconds
Started May 23 01:03:36 PM PDT 24
Finished May 23 01:04:37 PM PDT 24
Peak memory 199972 kb
Host smart-68e38c6f-2038-40c1-9248-c360d1f426d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061489498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.4061489498
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.296582811
Short name T377
Test name
Test status
Simulation time 104877194 ps
CPU time 3.64 seconds
Started May 23 01:03:24 PM PDT 24
Finished May 23 01:03:30 PM PDT 24
Peak memory 199908 kb
Host smart-e8464f38-75b6-479a-acf7-04e2077e1e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296582811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.296582811
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.689218037
Short name T235
Test name
Test status
Simulation time 67620251 ps
CPU time 1.25 seconds
Started May 23 01:03:25 PM PDT 24
Finished May 23 01:03:30 PM PDT 24
Peak memory 199904 kb
Host smart-643cfb45-a003-4405-b4de-9119ee699bcb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689218037 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.hmac_test_hmac_vectors.689218037
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.631318181
Short name T46
Test name
Test status
Simulation time 38851327368 ps
CPU time 541.31 seconds
Started May 23 01:03:25 PM PDT 24
Finished May 23 01:12:30 PM PDT 24
Peak memory 199980 kb
Host smart-a84cfbcd-daff-4b91-8fb3-2113eb599f15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631318181 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.631318181
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2788596006
Short name T168
Test name
Test status
Simulation time 5268144895 ps
CPU time 20.52 seconds
Started May 23 01:03:23 PM PDT 24
Finished May 23 01:03:46 PM PDT 24
Peak memory 200068 kb
Host smart-56c3e6dc-bd4b-4f02-ba70-cd392d61d988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788596006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2788596006
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.373364607
Short name T416
Test name
Test status
Simulation time 86356435 ps
CPU time 0.58 seconds
Started May 23 01:03:35 PM PDT 24
Finished May 23 01:03:38 PM PDT 24
Peak memory 195748 kb
Host smart-6a65b4bb-98c0-41ce-9039-09c3f71a8db9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373364607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.373364607
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.880025906
Short name T450
Test name
Test status
Simulation time 706937378 ps
CPU time 16.02 seconds
Started May 23 01:03:36 PM PDT 24
Finished May 23 01:03:54 PM PDT 24
Peak memory 208140 kb
Host smart-7b88203a-8819-4e96-b10b-05c335add312
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=880025906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.880025906
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.108737089
Short name T214
Test name
Test status
Simulation time 1314424513 ps
CPU time 71.05 seconds
Started May 23 01:03:45 PM PDT 24
Finished May 23 01:05:00 PM PDT 24
Peak memory 199944 kb
Host smart-88e4394d-a926-4ab1-a0a1-2d45b7015037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108737089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.108737089
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.2713258854
Short name T341
Test name
Test status
Simulation time 573147240 ps
CPU time 26.88 seconds
Started May 23 01:03:54 PM PDT 24
Finished May 23 01:04:29 PM PDT 24
Peak memory 246316 kb
Host smart-7bba9ecb-364c-4c6d-9b59-9d696e32efcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2713258854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2713258854
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3355523806
Short name T145
Test name
Test status
Simulation time 573908974 ps
CPU time 31.82 seconds
Started May 23 01:03:25 PM PDT 24
Finished May 23 01:04:00 PM PDT 24
Peak memory 199876 kb
Host smart-28ea472f-1e9f-4c95-afbb-bc264dd49fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355523806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3355523806
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.665045066
Short name T472
Test name
Test status
Simulation time 274030094 ps
CPU time 2.48 seconds
Started May 23 01:03:25 PM PDT 24
Finished May 23 01:03:31 PM PDT 24
Peak memory 199896 kb
Host smart-b2dfe8b9-0a80-4287-ad9f-8fc022995176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665045066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.665045066
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.2544390774
Short name T509
Test name
Test status
Simulation time 103837066 ps
CPU time 1.24 seconds
Started May 23 01:03:44 PM PDT 24
Finished May 23 01:03:49 PM PDT 24
Peak memory 200000 kb
Host smart-d7df2114-ecde-44ab-b69c-f511bad2e50a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544390774 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.2544390774
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.2689833382
Short name T432
Test name
Test status
Simulation time 16022609899 ps
CPU time 465.95 seconds
Started May 23 01:03:38 PM PDT 24
Finished May 23 01:11:26 PM PDT 24
Peak memory 200176 kb
Host smart-8fdae26f-896f-44ff-b1ad-0e03d78e574c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689833382 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.2689833382
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2500400618
Short name T475
Test name
Test status
Simulation time 67193389067 ps
CPU time 88.3 seconds
Started May 23 01:03:36 PM PDT 24
Finished May 23 01:05:06 PM PDT 24
Peak memory 200016 kb
Host smart-b746e922-6b49-4509-bd37-9625e6c959e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500400618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2500400618
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2204908617
Short name T260
Test name
Test status
Simulation time 11342928 ps
CPU time 0.58 seconds
Started May 23 01:03:36 PM PDT 24
Finished May 23 01:03:38 PM PDT 24
Peak memory 195536 kb
Host smart-aeeecc0b-be56-4616-8cad-c7286330bbab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204908617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2204908617
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.4032882131
Short name T58
Test name
Test status
Simulation time 1648903533 ps
CPU time 34.64 seconds
Started May 23 01:03:46 PM PDT 24
Finished May 23 01:04:25 PM PDT 24
Peak memory 224692 kb
Host smart-63c9d69b-098a-4395-8c5e-2a1747c05367
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4032882131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.4032882131
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.4118884192
Short name T274
Test name
Test status
Simulation time 1487368932 ps
CPU time 26.85 seconds
Started May 23 01:03:51 PM PDT 24
Finished May 23 01:04:23 PM PDT 24
Peak memory 199844 kb
Host smart-a2f88588-bb48-4768-8d30-18040ceb9299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118884192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.4118884192
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.22745278
Short name T380
Test name
Test status
Simulation time 5241994080 ps
CPU time 654.79 seconds
Started May 23 01:03:54 PM PDT 24
Finished May 23 01:14:56 PM PDT 24
Peak memory 703388 kb
Host smart-c0e0f6c0-0de3-43c4-9f12-92502f56ebfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=22745278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.22745278
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.327899675
Short name T53
Test name
Test status
Simulation time 832681052 ps
CPU time 7.88 seconds
Started May 23 01:03:38 PM PDT 24
Finished May 23 01:03:47 PM PDT 24
Peak memory 199824 kb
Host smart-5d71b9cb-ba4e-4971-aff0-20e32a5538a1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327899675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.327899675
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2084337829
Short name T196
Test name
Test status
Simulation time 27690234490 ps
CPU time 82.66 seconds
Started May 23 01:03:37 PM PDT 24
Finished May 23 01:05:02 PM PDT 24
Peak memory 200148 kb
Host smart-8e62f8c0-3a5c-42d8-9ee2-59c9bf7a226b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084337829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2084337829
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.390703021
Short name T279
Test name
Test status
Simulation time 133213489 ps
CPU time 1.07 seconds
Started May 23 01:03:50 PM PDT 24
Finished May 23 01:03:56 PM PDT 24
Peak memory 199800 kb
Host smart-641e493c-f2d9-450c-b4a7-4f0196a0affe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390703021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.390703021
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.3591393183
Short name T263
Test name
Test status
Simulation time 199092551 ps
CPU time 1.06 seconds
Started May 23 01:03:47 PM PDT 24
Finished May 23 01:03:53 PM PDT 24
Peak memory 199868 kb
Host smart-1de47df5-0d2e-432f-944b-4bd90c30a3b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591393183 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.3591393183
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.2588228495
Short name T129
Test name
Test status
Simulation time 15104938424 ps
CPU time 386.36 seconds
Started May 23 01:03:50 PM PDT 24
Finished May 23 01:10:22 PM PDT 24
Peak memory 200100 kb
Host smart-f0fc4374-3f89-4892-826e-f1e9f5192631
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588228495 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.2588228495
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3616671645
Short name T355
Test name
Test status
Simulation time 4490355350 ps
CPU time 43.44 seconds
Started May 23 01:03:51 PM PDT 24
Finished May 23 01:04:40 PM PDT 24
Peak memory 199984 kb
Host smart-3b711615-ae45-4a1d-9950-6498998eb356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616671645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3616671645
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1610173045
Short name T284
Test name
Test status
Simulation time 95465802 ps
CPU time 0.6 seconds
Started May 23 01:03:46 PM PDT 24
Finished May 23 01:03:52 PM PDT 24
Peak memory 196468 kb
Host smart-a3cafc6e-f9a3-46d0-86ea-484c033ae2c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610173045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1610173045
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.4104083022
Short name T455
Test name
Test status
Simulation time 9222984693 ps
CPU time 38.55 seconds
Started May 23 01:03:34 PM PDT 24
Finished May 23 01:04:15 PM PDT 24
Peak memory 221048 kb
Host smart-3e787a01-619e-4c07-b5cf-6f762e5f0dc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4104083022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.4104083022
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3318680888
Short name T120
Test name
Test status
Simulation time 2004055436 ps
CPU time 37.32 seconds
Started May 23 01:03:43 PM PDT 24
Finished May 23 01:04:23 PM PDT 24
Peak memory 199944 kb
Host smart-e74f2658-026a-4e54-bb59-b2dcafab63bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318680888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3318680888
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.22661435
Short name T63
Test name
Test status
Simulation time 784413136 ps
CPU time 62.46 seconds
Started May 23 01:03:37 PM PDT 24
Finished May 23 01:04:41 PM PDT 24
Peak memory 326896 kb
Host smart-b417d732-3c56-4ee7-a4d9-64c378345852
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=22661435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.22661435
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2488965089
Short name T244
Test name
Test status
Simulation time 2075231769 ps
CPU time 15.74 seconds
Started May 23 01:03:41 PM PDT 24
Finished May 23 01:03:58 PM PDT 24
Peak memory 199948 kb
Host smart-65033542-548d-47a3-812d-1c969c60ecd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488965089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2488965089
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.922395145
Short name T514
Test name
Test status
Simulation time 483066001 ps
CPU time 2.7 seconds
Started May 23 01:03:37 PM PDT 24
Finished May 23 01:03:41 PM PDT 24
Peak memory 199976 kb
Host smart-2cf58890-9eef-421f-9885-5b17c4c18665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922395145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.922395145
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2447887521
Short name T267
Test name
Test status
Simulation time 15403866865 ps
CPU time 421.82 seconds
Started May 23 01:03:49 PM PDT 24
Finished May 23 01:10:56 PM PDT 24
Peak memory 199972 kb
Host smart-1550f12f-cb2a-43b0-b581-8e18f2da8951
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447887521 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2447887521
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.2091220611
Short name T404
Test name
Test status
Simulation time 77853936 ps
CPU time 1.02 seconds
Started May 23 01:03:52 PM PDT 24
Finished May 23 01:03:59 PM PDT 24
Peak memory 198516 kb
Host smart-274c3264-e50e-4077-86c0-bd33b0003c22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091220611 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.2091220611
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.3093792122
Short name T261
Test name
Test status
Simulation time 173721557216 ps
CPU time 568.26 seconds
Started May 23 01:03:35 PM PDT 24
Finished May 23 01:13:05 PM PDT 24
Peak memory 199960 kb
Host smart-60646112-f49c-48b6-b79b-6ac13d08b615
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093792122 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.3093792122
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_alert_test.3790850409
Short name T193
Test name
Test status
Simulation time 14846020 ps
CPU time 0.59 seconds
Started May 23 01:03:44 PM PDT 24
Finished May 23 01:03:48 PM PDT 24
Peak memory 195608 kb
Host smart-34d82ec6-0a2d-4f2d-85b4-bf7fa61d15c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790850409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.3790850409
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.4182372934
Short name T440
Test name
Test status
Simulation time 580003041 ps
CPU time 9.82 seconds
Started May 23 01:03:52 PM PDT 24
Finished May 23 01:04:08 PM PDT 24
Peak memory 199972 kb
Host smart-be851b0e-a07c-4070-a9b8-3847e9caf96e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4182372934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.4182372934
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.584802687
Short name T100
Test name
Test status
Simulation time 3771881385 ps
CPU time 34.33 seconds
Started May 23 01:03:42 PM PDT 24
Finished May 23 01:04:19 PM PDT 24
Peak memory 199992 kb
Host smart-3c9bf4ea-626a-47f2-bc8f-c44130feae74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584802687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.584802687
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3010096238
Short name T433
Test name
Test status
Simulation time 2313828358 ps
CPU time 348.55 seconds
Started May 23 01:03:37 PM PDT 24
Finished May 23 01:09:27 PM PDT 24
Peak memory 705544 kb
Host smart-6b9856d1-e85a-4517-a0e0-07f1eb38e5bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3010096238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3010096238
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1856538406
Short name T6
Test name
Test status
Simulation time 1440538160 ps
CPU time 86.69 seconds
Started May 23 01:03:41 PM PDT 24
Finished May 23 01:05:10 PM PDT 24
Peak memory 200000 kb
Host smart-eca34e14-5f77-4f99-a87e-c6b2641bca69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856538406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1856538406
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3084838289
Short name T52
Test name
Test status
Simulation time 1190796610 ps
CPU time 2.61 seconds
Started May 23 01:03:38 PM PDT 24
Finished May 23 01:03:42 PM PDT 24
Peak memory 199880 kb
Host smart-a6f1755e-610e-402c-8968-263347d00218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084838289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3084838289
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.1398117956
Short name T293
Test name
Test status
Simulation time 42120067 ps
CPU time 1.02 seconds
Started May 23 01:03:50 PM PDT 24
Finished May 23 01:03:56 PM PDT 24
Peak memory 199584 kb
Host smart-473eda21-559d-4f08-abc4-f50069a6846c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398117956 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.1398117956
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.1933670855
Short name T270
Test name
Test status
Simulation time 164714440489 ps
CPU time 453.17 seconds
Started May 23 01:03:48 PM PDT 24
Finished May 23 01:11:26 PM PDT 24
Peak memory 200004 kb
Host smart-2f827f29-1e0e-49d3-8b67-c9cf0fc622f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933670855 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.1933670855
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.1730802662
Short name T497
Test name
Test status
Simulation time 675446155 ps
CPU time 9.3 seconds
Started May 23 01:03:48 PM PDT 24
Finished May 23 01:04:03 PM PDT 24
Peak memory 200008 kb
Host smart-770bb95b-a88a-4fb4-b405-0c7ffd0e405d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730802662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.1730802662
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.2561389726
Short name T407
Test name
Test status
Simulation time 33086113 ps
CPU time 0.61 seconds
Started May 23 01:03:40 PM PDT 24
Finished May 23 01:03:42 PM PDT 24
Peak memory 195744 kb
Host smart-3f0fb1a9-4efc-4adc-b4c1-44600912e28c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561389726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2561389726
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.1614724406
Short name T457
Test name
Test status
Simulation time 783987582 ps
CPU time 6.09 seconds
Started May 23 01:03:50 PM PDT 24
Finished May 23 01:04:02 PM PDT 24
Peak memory 200004 kb
Host smart-780f98e8-ce56-4c2f-aea8-fe767767f863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614724406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1614724406
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1853649455
Short name T126
Test name
Test status
Simulation time 11623148243 ps
CPU time 665.56 seconds
Started May 23 01:03:35 PM PDT 24
Finished May 23 01:14:43 PM PDT 24
Peak memory 713060 kb
Host smart-7fc775de-eac7-47c2-8997-21f00c0dbb50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1853649455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1853649455
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_long_msg.3913522564
Short name T170
Test name
Test status
Simulation time 51005524 ps
CPU time 3.05 seconds
Started May 23 01:03:42 PM PDT 24
Finished May 23 01:03:48 PM PDT 24
Peak memory 199936 kb
Host smart-d39e7320-2c45-4eaf-8998-2d4dc7ea61e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913522564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3913522564
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.4164593697
Short name T188
Test name
Test status
Simulation time 180179531 ps
CPU time 1.33 seconds
Started May 23 01:03:50 PM PDT 24
Finished May 23 01:03:57 PM PDT 24
Peak memory 200092 kb
Host smart-d3bb0193-6546-4740-a35a-4350fc4e81e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164593697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.4164593697
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.108350318
Short name T421
Test name
Test status
Simulation time 8310651722 ps
CPU time 1303.88 seconds
Started May 23 01:03:54 PM PDT 24
Finished May 23 01:25:45 PM PDT 24
Peak memory 758272 kb
Host smart-a0e5d1d7-fb42-40e3-bcc0-94204a1d9523
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108350318 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.108350318
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.2538323634
Short name T175
Test name
Test status
Simulation time 54719266 ps
CPU time 1.01 seconds
Started May 23 01:03:48 PM PDT 24
Finished May 23 01:03:55 PM PDT 24
Peak memory 199540 kb
Host smart-180ff95b-2517-43b5-ad1c-95f99a526c61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538323634 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.2538323634
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.1710169084
Short name T489
Test name
Test status
Simulation time 11404528774 ps
CPU time 401.03 seconds
Started May 23 01:03:34 PM PDT 24
Finished May 23 01:10:17 PM PDT 24
Peak memory 200104 kb
Host smart-54c156b1-2f68-4826-bdf1-087c4a3dc3d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710169084 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.1710169084
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1593656867
Short name T195
Test name
Test status
Simulation time 4412858593 ps
CPU time 45.57 seconds
Started May 23 01:03:53 PM PDT 24
Finished May 23 01:04:44 PM PDT 24
Peak memory 200024 kb
Host smart-a4cdc619-cda1-44f2-8853-7436c8558713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593656867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1593656867
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.827857339
Short name T169
Test name
Test status
Simulation time 37688941 ps
CPU time 0.63 seconds
Started May 23 01:03:07 PM PDT 24
Finished May 23 01:03:10 PM PDT 24
Peak memory 195504 kb
Host smart-0ecb5659-3562-4b1b-b213-93b49fa55593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827857339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.827857339
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3328167028
Short name T81
Test name
Test status
Simulation time 780636728 ps
CPU time 21.49 seconds
Started May 23 01:03:07 PM PDT 24
Finished May 23 01:03:31 PM PDT 24
Peak memory 208112 kb
Host smart-1ee441ad-659b-414d-b770-72f1186cf0ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3328167028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3328167028
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.2471009129
Short name T353
Test name
Test status
Simulation time 1012884235 ps
CPU time 52.87 seconds
Started May 23 01:02:55 PM PDT 24
Finished May 23 01:03:49 PM PDT 24
Peak memory 199992 kb
Host smart-838bcb28-7db6-43ae-a578-e12fe9a73fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471009129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.2471009129
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3531046037
Short name T390
Test name
Test status
Simulation time 2737713008 ps
CPU time 672.17 seconds
Started May 23 01:02:58 PM PDT 24
Finished May 23 01:14:11 PM PDT 24
Peak memory 699912 kb
Host smart-e1f39d89-ce55-4785-8a80-c4b89037e8ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3531046037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3531046037
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_long_msg.840304983
Short name T194
Test name
Test status
Simulation time 22467394763 ps
CPU time 70.95 seconds
Started May 23 01:02:55 PM PDT 24
Finished May 23 01:04:08 PM PDT 24
Peak memory 199988 kb
Host smart-71a3e6a2-0205-4570-be45-6d6de9462c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840304983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.840304983
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2819139933
Short name T43
Test name
Test status
Simulation time 90262004 ps
CPU time 1.01 seconds
Started May 23 01:03:01 PM PDT 24
Finished May 23 01:03:03 PM PDT 24
Peak memory 218896 kb
Host smart-db293efa-21f5-41e7-beae-f43578e3872c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819139933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2819139933
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3052820146
Short name T298
Test name
Test status
Simulation time 321877755 ps
CPU time 5.24 seconds
Started May 23 01:02:56 PM PDT 24
Finished May 23 01:03:02 PM PDT 24
Peak memory 199908 kb
Host smart-884da601-91c0-4513-9bb1-ecae0b7c0ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052820146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3052820146
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.3085605964
Short name T316
Test name
Test status
Simulation time 59307515 ps
CPU time 1.25 seconds
Started May 23 01:03:01 PM PDT 24
Finished May 23 01:03:04 PM PDT 24
Peak memory 199940 kb
Host smart-9e2abf0b-0700-46c4-9238-a8741764c6c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085605964 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.3085605964
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.2806305083
Short name T340
Test name
Test status
Simulation time 250758019379 ps
CPU time 529.67 seconds
Started May 23 01:03:00 PM PDT 24
Finished May 23 01:11:51 PM PDT 24
Peak memory 200056 kb
Host smart-34520729-1c05-4fa0-bbf5-9a90f82ef236
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806305083 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.2806305083
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3690634811
Short name T359
Test name
Test status
Simulation time 4827259305 ps
CPU time 91.25 seconds
Started May 23 01:03:03 PM PDT 24
Finished May 23 01:04:36 PM PDT 24
Peak memory 200080 kb
Host smart-27d8024f-77f8-45e6-ac2e-48ce7264b8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690634811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3690634811
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1916623355
Short name T417
Test name
Test status
Simulation time 92487576 ps
CPU time 0.61 seconds
Started May 23 01:03:55 PM PDT 24
Finished May 23 01:04:03 PM PDT 24
Peak memory 196328 kb
Host smart-1fda20ca-d4cc-4ba3-911d-404d41ea42c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916623355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1916623355
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.763234355
Short name T55
Test name
Test status
Simulation time 937277546 ps
CPU time 23.01 seconds
Started May 23 01:03:40 PM PDT 24
Finished May 23 01:04:05 PM PDT 24
Peak memory 216124 kb
Host smart-2444d396-583b-4642-90ae-860abdf3477f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=763234355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.763234355
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.641918429
Short name T414
Test name
Test status
Simulation time 2275558570 ps
CPU time 41.49 seconds
Started May 23 01:03:54 PM PDT 24
Finished May 23 01:04:42 PM PDT 24
Peak memory 200012 kb
Host smart-2c0d638b-c25d-4072-acbd-e1313cdc35f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641918429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.641918429
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.36455692
Short name T219
Test name
Test status
Simulation time 6578404852 ps
CPU time 370.82 seconds
Started May 23 01:03:42 PM PDT 24
Finished May 23 01:09:56 PM PDT 24
Peak memory 639668 kb
Host smart-8d9ded41-121f-4874-bbf9-ed0d5e51d334
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=36455692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.36455692
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3560823984
Short name T463
Test name
Test status
Simulation time 109058426 ps
CPU time 6.25 seconds
Started May 23 01:03:46 PM PDT 24
Finished May 23 01:03:58 PM PDT 24
Peak memory 199844 kb
Host smart-886f4628-5d79-4aae-93bc-ba1056985416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560823984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3560823984
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3783115621
Short name T229
Test name
Test status
Simulation time 2583532441 ps
CPU time 7.22 seconds
Started May 23 01:03:45 PM PDT 24
Finished May 23 01:03:56 PM PDT 24
Peak memory 200008 kb
Host smart-21f57b76-e469-4ae3-8c03-834b673a048c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783115621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3783115621
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.3214969169
Short name T228
Test name
Test status
Simulation time 1413107991 ps
CPU time 9.41 seconds
Started May 23 01:03:55 PM PDT 24
Finished May 23 01:04:12 PM PDT 24
Peak memory 200120 kb
Host smart-ca4bf194-a8c4-478f-bf6b-8acf8fe67232
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214969169 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.3214969169
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.4314524
Short name T491
Test name
Test status
Simulation time 75119307 ps
CPU time 1.32 seconds
Started May 23 01:03:52 PM PDT 24
Finished May 23 01:04:00 PM PDT 24
Peak memory 200016 kb
Host smart-e769b58d-3450-44ad-b460-e1e557a10e7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4314524 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.hmac_test_hmac_vectors.4314524
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.3441014578
Short name T254
Test name
Test status
Simulation time 117824390575 ps
CPU time 457.34 seconds
Started May 23 01:03:56 PM PDT 24
Finished May 23 01:11:40 PM PDT 24
Peak memory 199960 kb
Host smart-7e6e5017-efa5-4897-a132-629c7ea67d87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441014578 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.3441014578
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.490843913
Short name T371
Test name
Test status
Simulation time 587651141 ps
CPU time 24.97 seconds
Started May 23 01:03:54 PM PDT 24
Finished May 23 01:04:26 PM PDT 24
Peak memory 199900 kb
Host smart-f8b4147d-92ee-4f12-a607-1df2177d7870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490843913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.490843913
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.820274321
Short name T207
Test name
Test status
Simulation time 13969868 ps
CPU time 0.58 seconds
Started May 23 01:03:53 PM PDT 24
Finished May 23 01:03:59 PM PDT 24
Peak memory 195624 kb
Host smart-0664d7f1-598a-4ba0-bcec-a4d4676c5bc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820274321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.820274321
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2560292466
Short name T241
Test name
Test status
Simulation time 680565566 ps
CPU time 14.59 seconds
Started May 23 01:03:54 PM PDT 24
Finished May 23 01:04:16 PM PDT 24
Peak memory 199900 kb
Host smart-cdce46bd-7419-48f8-b66c-fe8a1e56cb0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2560292466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2560292466
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3070775819
Short name T239
Test name
Test status
Simulation time 2787596054 ps
CPU time 492.06 seconds
Started May 23 01:03:54 PM PDT 24
Finished May 23 01:12:12 PM PDT 24
Peak memory 733448 kb
Host smart-36ccba4a-e706-44a9-9cfa-7320ee06a203
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3070775819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3070775819
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1400543591
Short name T379
Test name
Test status
Simulation time 2425444325 ps
CPU time 36.98 seconds
Started May 23 01:03:53 PM PDT 24
Finished May 23 01:04:36 PM PDT 24
Peak memory 199984 kb
Host smart-c753439c-1fa9-46f0-b1ea-9cb2d2eddc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400543591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1400543591
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3892239675
Short name T83
Test name
Test status
Simulation time 375830966 ps
CPU time 3.49 seconds
Started May 23 01:03:55 PM PDT 24
Finished May 23 01:04:06 PM PDT 24
Peak memory 200068 kb
Host smart-ae6c75db-1984-4d7e-8ebd-f96891eb6cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892239675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3892239675
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.287167792
Short name T95
Test name
Test status
Simulation time 126057535976 ps
CPU time 501.18 seconds
Started May 23 01:03:54 PM PDT 24
Finished May 23 01:12:23 PM PDT 24
Peak memory 200168 kb
Host smart-f660018b-ff10-4452-a9cd-605d7e7c3251
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287167792 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.287167792
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.3248176808
Short name T452
Test name
Test status
Simulation time 94128851 ps
CPU time 1.16 seconds
Started May 23 01:03:54 PM PDT 24
Finished May 23 01:04:01 PM PDT 24
Peak memory 200020 kb
Host smart-76c1b5de-f036-4aa9-aa0c-f28827079f27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248176808 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.3248176808
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.1753545435
Short name T401
Test name
Test status
Simulation time 27053084515 ps
CPU time 395.43 seconds
Started May 23 01:03:54 PM PDT 24
Finished May 23 01:10:37 PM PDT 24
Peak memory 199908 kb
Host smart-8cb3f181-00f6-4187-a162-127f33818589
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753545435 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.1753545435
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2329768286
Short name T486
Test name
Test status
Simulation time 785268444 ps
CPU time 11.28 seconds
Started May 23 01:03:51 PM PDT 24
Finished May 23 01:04:08 PM PDT 24
Peak memory 200056 kb
Host smart-d39a9c79-b543-4ee5-81d9-2ae1fd508814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329768286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2329768286
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1304921902
Short name T522
Test name
Test status
Simulation time 71711210 ps
CPU time 0.61 seconds
Started May 23 01:03:54 PM PDT 24
Finished May 23 01:04:01 PM PDT 24
Peak memory 195600 kb
Host smart-582d2962-fb73-464b-9dcb-5458d209cc77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304921902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1304921902
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.4186403602
Short name T54
Test name
Test status
Simulation time 575864997 ps
CPU time 28.72 seconds
Started May 23 01:03:48 PM PDT 24
Finished May 23 01:04:22 PM PDT 24
Peak memory 208204 kb
Host smart-b2189d00-5bb3-4435-836f-c857ccfac00a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4186403602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.4186403602
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.429680978
Short name T480
Test name
Test status
Simulation time 78583595 ps
CPU time 4.25 seconds
Started May 23 01:03:55 PM PDT 24
Finished May 23 01:04:06 PM PDT 24
Peak memory 199892 kb
Host smart-b38bde71-a885-4a5f-918a-5c4e43d4358c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429680978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.429680978
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.1437428776
Short name T460
Test name
Test status
Simulation time 2128203876 ps
CPU time 501.7 seconds
Started May 23 01:03:53 PM PDT 24
Finished May 23 01:12:22 PM PDT 24
Peak memory 608720 kb
Host smart-0410fe70-b7fd-46c3-bcc6-0d99368e2eed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1437428776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1437428776
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2610529981
Short name T62
Test name
Test status
Simulation time 10844445115 ps
CPU time 84.89 seconds
Started May 23 01:03:54 PM PDT 24
Finished May 23 01:05:26 PM PDT 24
Peak memory 200008 kb
Host smart-91012757-3945-44bb-adef-0d96a30fd4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610529981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2610529981
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2810057096
Short name T441
Test name
Test status
Simulation time 445763859 ps
CPU time 2.41 seconds
Started May 23 01:03:51 PM PDT 24
Finished May 23 01:03:59 PM PDT 24
Peak memory 200104 kb
Host smart-5d83f1fd-e56b-425e-8627-e24e21b0ca67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810057096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2810057096
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.2194107656
Short name T344
Test name
Test status
Simulation time 147199153 ps
CPU time 1.32 seconds
Started May 23 01:03:55 PM PDT 24
Finished May 23 01:04:04 PM PDT 24
Peak memory 200012 kb
Host smart-3239acc9-82d0-424f-a678-0be71e98f57a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194107656 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.2194107656
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.1179495750
Short name T157
Test name
Test status
Simulation time 58076397377 ps
CPU time 531.43 seconds
Started May 23 01:03:55 PM PDT 24
Finished May 23 01:12:54 PM PDT 24
Peak memory 200100 kb
Host smart-8f8cd7a7-7a49-4211-ae2c-b67de4f9d8ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179495750 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.1179495750
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1316139609
Short name T269
Test name
Test status
Simulation time 1863506853 ps
CPU time 17.37 seconds
Started May 23 01:03:55 PM PDT 24
Finished May 23 01:04:20 PM PDT 24
Peak memory 200100 kb
Host smart-2ca996d2-4a7e-4000-849c-6b7f3eca854a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316139609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1316139609
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.396088498
Short name T467
Test name
Test status
Simulation time 92077900 ps
CPU time 0.57 seconds
Started May 23 01:03:52 PM PDT 24
Finished May 23 01:03:58 PM PDT 24
Peak memory 194724 kb
Host smart-d99369be-1e13-494f-9ca8-1f0b1f6db855
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396088498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.396088498
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.23680696
Short name T19
Test name
Test status
Simulation time 329269164 ps
CPU time 18.35 seconds
Started May 23 01:03:56 PM PDT 24
Finished May 23 01:04:22 PM PDT 24
Peak memory 208200 kb
Host smart-bdb6c228-7adf-4438-9846-1f46b94ab3f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=23680696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.23680696
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.444388435
Short name T3
Test name
Test status
Simulation time 957052307 ps
CPU time 18.29 seconds
Started May 23 01:03:54 PM PDT 24
Finished May 23 01:04:20 PM PDT 24
Peak memory 199932 kb
Host smart-1c85b0d8-4c3f-4176-b28a-17ba8812a87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444388435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.444388435
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2767632111
Short name T48
Test name
Test status
Simulation time 6292562587 ps
CPU time 261.54 seconds
Started May 23 01:03:52 PM PDT 24
Finished May 23 01:08:19 PM PDT 24
Peak memory 616076 kb
Host smart-dd04fa5c-2987-4dbf-be9f-f1b1944f8bc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2767632111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2767632111
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3152818821
Short name T482
Test name
Test status
Simulation time 9651653314 ps
CPU time 91.29 seconds
Started May 23 01:03:54 PM PDT 24
Finished May 23 01:05:31 PM PDT 24
Peak memory 199956 kb
Host smart-62e250d7-2212-4eff-9810-85703c4c8c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152818821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3152818821
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1056335035
Short name T411
Test name
Test status
Simulation time 56751102 ps
CPU time 0.71 seconds
Started May 23 01:03:47 PM PDT 24
Finished May 23 01:03:53 PM PDT 24
Peak memory 197480 kb
Host smart-f564e957-2454-4a3b-b058-9bb61525a725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056335035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1056335035
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.1195798287
Short name T342
Test name
Test status
Simulation time 4019014148 ps
CPU time 62.23 seconds
Started May 23 01:03:55 PM PDT 24
Finished May 23 01:05:04 PM PDT 24
Peak memory 199988 kb
Host smart-079612ed-38a5-417a-94ee-095f753f3527
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195798287 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.1195798287
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.2318936363
Short name T403
Test name
Test status
Simulation time 55613425 ps
CPU time 1.21 seconds
Started May 23 01:03:56 PM PDT 24
Finished May 23 01:04:05 PM PDT 24
Peak memory 199704 kb
Host smart-2e924b74-f140-4634-baad-177580c5a2de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318936363 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.2318936363
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.3972758828
Short name T318
Test name
Test status
Simulation time 224621905988 ps
CPU time 493.27 seconds
Started May 23 01:03:54 PM PDT 24
Finished May 23 01:12:13 PM PDT 24
Peak memory 199956 kb
Host smart-eb299f36-d6f7-4555-ab92-26ad198d80a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972758828 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.3972758828
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.1745656173
Short name T38
Test name
Test status
Simulation time 1044924426 ps
CPU time 14.4 seconds
Started May 23 01:03:50 PM PDT 24
Finished May 23 01:04:09 PM PDT 24
Peak memory 200052 kb
Host smart-91291843-2460-4df7-9942-253158413b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745656173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1745656173
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.1504844360
Short name T22
Test name
Test status
Simulation time 11148358 ps
CPU time 0.59 seconds
Started May 23 01:03:52 PM PDT 24
Finished May 23 01:03:58 PM PDT 24
Peak memory 195540 kb
Host smart-8acc82c2-98e4-4dc7-93d7-0a6410806cc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504844360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1504844360
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.4212746084
Short name T51
Test name
Test status
Simulation time 1223236516 ps
CPU time 53.38 seconds
Started May 23 01:03:50 PM PDT 24
Finished May 23 01:04:49 PM PDT 24
Peak memory 225528 kb
Host smart-6d06ad09-67d9-40ae-8813-4846a15ead9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4212746084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.4212746084
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2149156284
Short name T474
Test name
Test status
Simulation time 6294569953 ps
CPU time 62.14 seconds
Started May 23 01:03:53 PM PDT 24
Finished May 23 01:05:01 PM PDT 24
Peak memory 200020 kb
Host smart-41b82599-cf32-4e60-a8e7-f17862cf42f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149156284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2149156284
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3761394524
Short name T294
Test name
Test status
Simulation time 5502900150 ps
CPU time 974.4 seconds
Started May 23 01:03:55 PM PDT 24
Finished May 23 01:20:17 PM PDT 24
Peak memory 720796 kb
Host smart-f3d9086b-1c7d-4774-989d-cb5df8300d3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3761394524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3761394524
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_long_msg.537989855
Short name T200
Test name
Test status
Simulation time 12305536166 ps
CPU time 59.5 seconds
Started May 23 01:03:54 PM PDT 24
Finished May 23 01:05:00 PM PDT 24
Peak memory 199968 kb
Host smart-f2f0e5e0-1f74-4484-89fd-d3889f176e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537989855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.537989855
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1375050402
Short name T164
Test name
Test status
Simulation time 268509278 ps
CPU time 3.99 seconds
Started May 23 01:03:52 PM PDT 24
Finished May 23 01:04:02 PM PDT 24
Peak memory 199968 kb
Host smart-d93de8cf-12d8-4e5c-a97f-e51813f740eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375050402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1375050402
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.1029405045
Short name T132
Test name
Test status
Simulation time 19370725194 ps
CPU time 982.24 seconds
Started May 23 01:03:56 PM PDT 24
Finished May 23 01:20:26 PM PDT 24
Peak memory 729116 kb
Host smart-651f385a-3d2a-488b-bcbb-dd3d09b3561b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029405045 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1029405045
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.3715452915
Short name T302
Test name
Test status
Simulation time 189391833 ps
CPU time 1.1 seconds
Started May 23 01:03:57 PM PDT 24
Finished May 23 01:04:06 PM PDT 24
Peak memory 199460 kb
Host smart-35b736a0-234c-45ee-afeb-530952f83ec7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715452915 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.3715452915
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.4130252561
Short name T520
Test name
Test status
Simulation time 15673546804 ps
CPU time 463.32 seconds
Started May 23 01:03:53 PM PDT 24
Finished May 23 01:11:43 PM PDT 24
Peak memory 200116 kb
Host smart-a7952da6-5dbb-4695-a34a-f38fbb58efa6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130252561 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.4130252561
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.3646950068
Short name T121
Test name
Test status
Simulation time 5755714090 ps
CPU time 54.01 seconds
Started May 23 01:03:57 PM PDT 24
Finished May 23 01:04:58 PM PDT 24
Peak memory 199960 kb
Host smart-7e0d476c-b9a5-481b-aa00-c8f7485fd9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646950068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3646950068
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.331923114
Short name T499
Test name
Test status
Simulation time 13977864 ps
CPU time 0.59 seconds
Started May 23 01:03:50 PM PDT 24
Finished May 23 01:03:55 PM PDT 24
Peak memory 194784 kb
Host smart-86bc67fa-bedd-474b-97d1-d930eaefcd0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331923114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.331923114
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.179755898
Short name T515
Test name
Test status
Simulation time 901606218 ps
CPU time 52.17 seconds
Started May 23 01:03:52 PM PDT 24
Finished May 23 01:04:50 PM PDT 24
Peak memory 223524 kb
Host smart-48cac5fe-429f-4fdd-a0e9-9171f9da0693
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=179755898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.179755898
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.571922516
Short name T248
Test name
Test status
Simulation time 3664536019 ps
CPU time 1142.04 seconds
Started May 23 01:04:04 PM PDT 24
Finished May 23 01:23:12 PM PDT 24
Peak memory 704556 kb
Host smart-8fef06f4-b314-4f10-94ed-d60a0c022d79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=571922516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.571922516
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1203175833
Short name T400
Test name
Test status
Simulation time 947886771 ps
CPU time 58.27 seconds
Started May 23 01:03:55 PM PDT 24
Finished May 23 01:05:00 PM PDT 24
Peak memory 200084 kb
Host smart-29625786-bcef-49b4-8980-65f05672c5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203175833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1203175833
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.382623544
Short name T149
Test name
Test status
Simulation time 49570279 ps
CPU time 1.15 seconds
Started May 23 01:03:52 PM PDT 24
Finished May 23 01:04:00 PM PDT 24
Peak memory 199960 kb
Host smart-ab4ba32a-e67f-42bb-a6a3-04365e6bfcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382623544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.382623544
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.1714000355
Short name T408
Test name
Test status
Simulation time 47731233 ps
CPU time 0.98 seconds
Started May 23 01:03:54 PM PDT 24
Finished May 23 01:04:01 PM PDT 24
Peak memory 198344 kb
Host smart-43136f4b-1c77-4fae-a264-85cc3a0a8b85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714000355 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.1714000355
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.343233029
Short name T28
Test name
Test status
Simulation time 112607528041 ps
CPU time 499.52 seconds
Started May 23 01:03:53 PM PDT 24
Finished May 23 01:12:19 PM PDT 24
Peak memory 200004 kb
Host smart-15ceb6b4-d69c-43f9-a254-37debabf8322
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343233029 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.343233029
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2679858153
Short name T494
Test name
Test status
Simulation time 121753461 ps
CPU time 2.95 seconds
Started May 23 01:03:55 PM PDT 24
Finished May 23 01:04:05 PM PDT 24
Peak memory 199852 kb
Host smart-b61be75f-8480-4a30-81da-2ccd607a3690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679858153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2679858153
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.231316795
Short name T326
Test name
Test status
Simulation time 39012922 ps
CPU time 0.61 seconds
Started May 23 01:04:10 PM PDT 24
Finished May 23 01:04:16 PM PDT 24
Peak memory 194580 kb
Host smart-77a34f48-1ad9-4b1f-ae21-73b6d9369684
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231316795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.231316795
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.2181059748
Short name T101
Test name
Test status
Simulation time 607515737 ps
CPU time 6.23 seconds
Started May 23 01:04:11 PM PDT 24
Finished May 23 01:04:23 PM PDT 24
Peak memory 216000 kb
Host smart-8e55ce49-d4f1-473c-bc1d-36d6429e08c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2181059748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2181059748
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2978204550
Short name T481
Test name
Test status
Simulation time 1458223090 ps
CPU time 17.43 seconds
Started May 23 01:03:59 PM PDT 24
Finished May 23 01:04:24 PM PDT 24
Peak memory 200032 kb
Host smart-6f0cfa02-5fa9-4f0f-ab24-42523b6c61c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978204550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2978204550
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3818392961
Short name T80
Test name
Test status
Simulation time 3237567575 ps
CPU time 170.15 seconds
Started May 23 01:04:08 PM PDT 24
Finished May 23 01:07:04 PM PDT 24
Peak memory 443480 kb
Host smart-e4553a75-0e3d-498f-addf-67cc61790e27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3818392961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3818392961
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3155840554
Short name T492
Test name
Test status
Simulation time 3605773992 ps
CPU time 35.1 seconds
Started May 23 01:04:06 PM PDT 24
Finished May 23 01:04:47 PM PDT 24
Peak memory 200096 kb
Host smart-800d915b-78c7-4700-9f58-35794cb81938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155840554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3155840554
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2046217521
Short name T50
Test name
Test status
Simulation time 122667909 ps
CPU time 3.83 seconds
Started May 23 01:04:01 PM PDT 24
Finished May 23 01:04:12 PM PDT 24
Peak memory 200036 kb
Host smart-32d8ce44-ee2f-4d87-b7c4-51db7da6ae2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046217521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2046217521
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.2504863249
Short name T268
Test name
Test status
Simulation time 60014601 ps
CPU time 1.37 seconds
Started May 23 01:03:58 PM PDT 24
Finished May 23 01:04:06 PM PDT 24
Peak memory 199932 kb
Host smart-0cdd7144-9830-429a-b01e-fc05e8cd22f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504863249 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.2504863249
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.2978036011
Short name T311
Test name
Test status
Simulation time 78934561198 ps
CPU time 509.89 seconds
Started May 23 01:04:06 PM PDT 24
Finished May 23 01:12:42 PM PDT 24
Peak memory 200096 kb
Host smart-482922b6-a96a-4faf-8ba0-3971570928d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978036011 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.2978036011
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.4034766973
Short name T336
Test name
Test status
Simulation time 436475043 ps
CPU time 7.01 seconds
Started May 23 01:04:07 PM PDT 24
Finished May 23 01:04:20 PM PDT 24
Peak memory 199964 kb
Host smart-342c09e1-8bd6-43ce-9213-3f8f25b047c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034766973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.4034766973
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.549154681
Short name T459
Test name
Test status
Simulation time 43950249 ps
CPU time 0.6 seconds
Started May 23 01:04:03 PM PDT 24
Finished May 23 01:04:10 PM PDT 24
Peak memory 196368 kb
Host smart-b3b7ce1d-35c0-459d-8342-65ded48def56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549154681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.549154681
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.742974130
Short name T247
Test name
Test status
Simulation time 494375544 ps
CPU time 21.25 seconds
Started May 23 01:04:01 PM PDT 24
Finished May 23 01:04:29 PM PDT 24
Peak memory 208276 kb
Host smart-ff1ebb07-4c21-457b-8a36-8fe6236ca58b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=742974130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.742974130
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.2096002945
Short name T103
Test name
Test status
Simulation time 47654426 ps
CPU time 2.52 seconds
Started May 23 01:04:02 PM PDT 24
Finished May 23 01:04:11 PM PDT 24
Peak memory 199904 kb
Host smart-6b68880b-f5fc-440a-b444-1554e0aa7a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096002945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2096002945
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1895720756
Short name T211
Test name
Test status
Simulation time 2891861697 ps
CPU time 668.56 seconds
Started May 23 01:03:58 PM PDT 24
Finished May 23 01:15:14 PM PDT 24
Peak memory 632744 kb
Host smart-ce5f3813-eaea-4f9a-988e-55fba3a882e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1895720756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1895720756
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1393675497
Short name T61
Test name
Test status
Simulation time 35312926326 ps
CPU time 126.95 seconds
Started May 23 01:04:10 PM PDT 24
Finished May 23 01:06:22 PM PDT 24
Peak memory 200152 kb
Host smart-9be75764-6c5e-4b16-ba7a-dae24446be43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393675497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1393675497
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3762988383
Short name T44
Test name
Test status
Simulation time 34181113 ps
CPU time 1.3 seconds
Started May 23 01:04:11 PM PDT 24
Finished May 23 01:04:18 PM PDT 24
Peak memory 199908 kb
Host smart-943936bf-4199-4fef-91ee-8a3bd58f5830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762988383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3762988383
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.3341731745
Short name T189
Test name
Test status
Simulation time 29558041 ps
CPU time 1.03 seconds
Started May 23 01:04:06 PM PDT 24
Finished May 23 01:04:13 PM PDT 24
Peak memory 199608 kb
Host smart-45ddb74b-3e93-476c-9b39-975df0cadfe1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341731745 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.3341731745
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.1507427821
Short name T251
Test name
Test status
Simulation time 49614007162 ps
CPU time 450.88 seconds
Started May 23 01:04:00 PM PDT 24
Finished May 23 01:11:38 PM PDT 24
Peak memory 200008 kb
Host smart-223a46ad-5027-4716-88e8-2d957909abe8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507427821 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.1507427821
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3709034346
Short name T346
Test name
Test status
Simulation time 18294043 ps
CPU time 0.62 seconds
Started May 23 01:04:05 PM PDT 24
Finished May 23 01:04:12 PM PDT 24
Peak memory 195616 kb
Host smart-e6c152e7-9dfe-41e3-813e-699e0b007e48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709034346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3709034346
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2031048065
Short name T321
Test name
Test status
Simulation time 727416751 ps
CPU time 36.3 seconds
Started May 23 01:04:03 PM PDT 24
Finished May 23 01:04:46 PM PDT 24
Peak memory 208212 kb
Host smart-3c4e7f59-ff73-4335-a787-b8526b053132
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2031048065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2031048065
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3252011564
Short name T409
Test name
Test status
Simulation time 866493494 ps
CPU time 4.89 seconds
Started May 23 01:04:08 PM PDT 24
Finished May 23 01:04:19 PM PDT 24
Peak memory 199916 kb
Host smart-25572aff-a822-47e2-a4c9-9b5301dbdc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252011564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3252011564
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.95927893
Short name T226
Test name
Test status
Simulation time 1197176026 ps
CPU time 48.81 seconds
Started May 23 01:04:02 PM PDT 24
Finished May 23 01:04:57 PM PDT 24
Peak memory 316220 kb
Host smart-a719b32a-947f-4c70-a7e8-03899ec78eb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=95927893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.95927893
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_long_msg.79685323
Short name T296
Test name
Test status
Simulation time 4008258364 ps
CPU time 26.3 seconds
Started May 23 01:04:10 PM PDT 24
Finished May 23 01:04:42 PM PDT 24
Peak memory 200128 kb
Host smart-322e2d31-1897-4da1-826e-b12a267950cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79685323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.79685323
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2506151181
Short name T352
Test name
Test status
Simulation time 599687411 ps
CPU time 7.05 seconds
Started May 23 01:03:59 PM PDT 24
Finished May 23 01:04:13 PM PDT 24
Peak memory 199976 kb
Host smart-92281a1b-4fab-40ad-9a01-fec15a99946a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506151181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2506151181
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.94719698
Short name T406
Test name
Test status
Simulation time 148965296 ps
CPU time 1.45 seconds
Started May 23 01:04:02 PM PDT 24
Finished May 23 01:04:10 PM PDT 24
Peak memory 199960 kb
Host smart-f8bfee7c-0477-41d3-953e-141d4d6d6f2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94719698 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.hmac_test_hmac_vectors.94719698
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.3182230564
Short name T159
Test name
Test status
Simulation time 30294458011 ps
CPU time 388.39 seconds
Started May 23 01:04:07 PM PDT 24
Finished May 23 01:10:42 PM PDT 24
Peak memory 200052 kb
Host smart-1bafed3a-7346-47cf-bcf0-9fcd1ad11924
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182230564 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.3182230564
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.784811903
Short name T230
Test name
Test status
Simulation time 771074827 ps
CPU time 43.48 seconds
Started May 23 01:04:01 PM PDT 24
Finished May 23 01:04:51 PM PDT 24
Peak memory 199916 kb
Host smart-780a503b-fe24-44d2-8087-62853ab735d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784811903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.784811903
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.3722687555
Short name T179
Test name
Test status
Simulation time 40829249 ps
CPU time 0.58 seconds
Started May 23 01:04:02 PM PDT 24
Finished May 23 01:04:09 PM PDT 24
Peak memory 195376 kb
Host smart-c5fd3065-ec25-479d-8605-4b9feea6e0d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722687555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3722687555
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1369784044
Short name T56
Test name
Test status
Simulation time 82906376 ps
CPU time 4.96 seconds
Started May 23 01:04:01 PM PDT 24
Finished May 23 01:04:12 PM PDT 24
Peak memory 208272 kb
Host smart-c31ba848-88d7-4dde-9054-d3c7ca6aab8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1369784044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1369784044
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.2354209106
Short name T285
Test name
Test status
Simulation time 3913889006 ps
CPU time 47.23 seconds
Started May 23 01:03:57 PM PDT 24
Finished May 23 01:04:51 PM PDT 24
Peak memory 200100 kb
Host smart-1b5e9175-2308-481c-9331-a0b0eb14dad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354209106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2354209106
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3561574787
Short name T236
Test name
Test status
Simulation time 4400813065 ps
CPU time 271.92 seconds
Started May 23 01:03:58 PM PDT 24
Finished May 23 01:08:37 PM PDT 24
Peak memory 667680 kb
Host smart-f4997eaa-9c77-4672-8aeb-29fb43f38caa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3561574787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3561574787
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1276964319
Short name T443
Test name
Test status
Simulation time 1634691770 ps
CPU time 32.83 seconds
Started May 23 01:04:11 PM PDT 24
Finished May 23 01:04:50 PM PDT 24
Peak memory 199936 kb
Host smart-786d4111-bb12-4851-af15-e75df37e11ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276964319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1276964319
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2005697465
Short name T348
Test name
Test status
Simulation time 680975052 ps
CPU time 5.08 seconds
Started May 23 01:04:01 PM PDT 24
Finished May 23 01:04:13 PM PDT 24
Peak memory 200096 kb
Host smart-3bac63b3-c851-4511-b028-c2c1c4819222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005697465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2005697465
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.548393370
Short name T505
Test name
Test status
Simulation time 225455645 ps
CPU time 1.36 seconds
Started May 23 01:04:02 PM PDT 24
Finished May 23 01:04:10 PM PDT 24
Peak memory 199948 kb
Host smart-dd0d5043-a545-4ebb-8a15-3e397c5787d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548393370 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.hmac_test_hmac_vectors.548393370
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.3088785995
Short name T461
Test name
Test status
Simulation time 21805355273 ps
CPU time 517.99 seconds
Started May 23 01:04:00 PM PDT 24
Finished May 23 01:12:45 PM PDT 24
Peak memory 200092 kb
Host smart-bac4cfea-5afa-4509-9536-b29cace5f72b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088785995 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.3088785995
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.279058800
Short name T309
Test name
Test status
Simulation time 3030835225 ps
CPU time 29.16 seconds
Started May 23 01:04:03 PM PDT 24
Finished May 23 01:04:38 PM PDT 24
Peak memory 200020 kb
Host smart-5ebc5e09-5b18-4e09-99cc-edbacee6983c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279058800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.279058800
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.444121651
Short name T297
Test name
Test status
Simulation time 20394142 ps
CPU time 0.59 seconds
Started May 23 01:03:11 PM PDT 24
Finished May 23 01:03:13 PM PDT 24
Peak memory 195708 kb
Host smart-333a1e9d-5821-4968-a13b-bc02eef57ea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444121651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.444121651
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.662929404
Short name T18
Test name
Test status
Simulation time 2619102221 ps
CPU time 46.22 seconds
Started May 23 01:03:02 PM PDT 24
Finished May 23 01:03:50 PM PDT 24
Peak memory 234924 kb
Host smart-eb0818ab-f282-4078-96e0-64aabf82f4e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=662929404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.662929404
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.328238336
Short name T232
Test name
Test status
Simulation time 1251430999 ps
CPU time 22.22 seconds
Started May 23 01:03:00 PM PDT 24
Finished May 23 01:03:23 PM PDT 24
Peak memory 199940 kb
Host smart-72e80bad-83e0-498d-b99c-dca0663d51b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328238336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.328238336
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2492761113
Short name T150
Test name
Test status
Simulation time 5281525770 ps
CPU time 1557.81 seconds
Started May 23 01:03:00 PM PDT 24
Finished May 23 01:29:00 PM PDT 24
Peak memory 763888 kb
Host smart-0f61d6fe-0722-43d3-b544-d42559b17152
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2492761113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2492761113
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3292209496
Short name T493
Test name
Test status
Simulation time 163906983 ps
CPU time 9.58 seconds
Started May 23 01:02:55 PM PDT 24
Finished May 23 01:03:06 PM PDT 24
Peak memory 199944 kb
Host smart-2564a7dc-40f4-4b41-97a4-a32260e90892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292209496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3292209496
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.4182570065
Short name T42
Test name
Test status
Simulation time 55182369 ps
CPU time 0.88 seconds
Started May 23 01:02:56 PM PDT 24
Finished May 23 01:02:58 PM PDT 24
Peak memory 217856 kb
Host smart-4114e0c9-354e-4a04-9be4-5563ccadf03e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182570065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.4182570065
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1378335330
Short name T262
Test name
Test status
Simulation time 592482110 ps
CPU time 3.48 seconds
Started May 23 01:03:01 PM PDT 24
Finished May 23 01:03:06 PM PDT 24
Peak memory 200036 kb
Host smart-56a24c7f-f65b-4be8-bc81-b81e72684bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378335330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1378335330
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.4265766421
Short name T308
Test name
Test status
Simulation time 28402523 ps
CPU time 0.97 seconds
Started May 23 01:03:01 PM PDT 24
Finished May 23 01:03:04 PM PDT 24
Peak memory 199148 kb
Host smart-b8ec2d11-19db-4ba7-b214-75f663af9812
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265766421 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.4265766421
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.3613899320
Short name T328
Test name
Test status
Simulation time 59985512412 ps
CPU time 550.09 seconds
Started May 23 01:03:00 PM PDT 24
Finished May 23 01:12:12 PM PDT 24
Peak memory 200128 kb
Host smart-19d561a7-73dd-42e8-a9de-ba6965407ded
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613899320 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.3613899320
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1682814429
Short name T470
Test name
Test status
Simulation time 1793750197 ps
CPU time 22.57 seconds
Started May 23 01:03:02 PM PDT 24
Finished May 23 01:03:26 PM PDT 24
Peak memory 200028 kb
Host smart-7dc7f8bb-7cb9-4b70-806b-a2a185f2d615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682814429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1682814429
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.712592383
Short name T507
Test name
Test status
Simulation time 17698817 ps
CPU time 0.58 seconds
Started May 23 01:03:58 PM PDT 24
Finished May 23 01:04:06 PM PDT 24
Peak memory 194608 kb
Host smart-1efb29f0-6437-4be2-9ae1-ab01366ea2a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712592383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.712592383
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.2236976999
Short name T57
Test name
Test status
Simulation time 6751627419 ps
CPU time 44.66 seconds
Started May 23 01:04:08 PM PDT 24
Finished May 23 01:04:59 PM PDT 24
Peak memory 225480 kb
Host smart-e4d06fb2-8b98-46a4-b818-445bb1ec997c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2236976999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2236976999
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1204430672
Short name T388
Test name
Test status
Simulation time 5189589907 ps
CPU time 37.85 seconds
Started May 23 01:04:05 PM PDT 24
Finished May 23 01:04:49 PM PDT 24
Peak memory 200036 kb
Host smart-ec99887b-596a-41d2-8885-6235e4026ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204430672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1204430672
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1937886434
Short name T422
Test name
Test status
Simulation time 12620736818 ps
CPU time 633.47 seconds
Started May 23 01:04:03 PM PDT 24
Finished May 23 01:14:43 PM PDT 24
Peak memory 658332 kb
Host smart-3f152694-612d-4d77-aa8d-b5e1b2a9cfdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1937886434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1937886434
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_long_msg.1767805074
Short name T210
Test name
Test status
Simulation time 2758010144 ps
CPU time 77.75 seconds
Started May 23 01:03:59 PM PDT 24
Finished May 23 01:05:24 PM PDT 24
Peak memory 199932 kb
Host smart-600b3cf6-021c-4e35-bb33-167072f8ba1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767805074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1767805074
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.3380165487
Short name T464
Test name
Test status
Simulation time 668764423 ps
CPU time 2.68 seconds
Started May 23 01:04:08 PM PDT 24
Finished May 23 01:04:17 PM PDT 24
Peak memory 199900 kb
Host smart-1694e671-ba7b-49e4-ae3e-bb7a7756e82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380165487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.3380165487
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.1840558697
Short name T317
Test name
Test status
Simulation time 56251267 ps
CPU time 1.06 seconds
Started May 23 01:04:07 PM PDT 24
Finished May 23 01:04:14 PM PDT 24
Peak memory 199472 kb
Host smart-fcfe5425-ea0d-4720-acd2-7d1af1ce6497
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840558697 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.1840558697
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.3948655961
Short name T250
Test name
Test status
Simulation time 166906565657 ps
CPU time 521.62 seconds
Started May 23 01:04:11 PM PDT 24
Finished May 23 01:12:59 PM PDT 24
Peak memory 199956 kb
Host smart-a97fe251-011b-414e-a014-fb9c62ff5f6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948655961 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.3948655961
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.847647086
Short name T496
Test name
Test status
Simulation time 1293176845 ps
CPU time 53.45 seconds
Started May 23 01:03:57 PM PDT 24
Finished May 23 01:04:58 PM PDT 24
Peak memory 199964 kb
Host smart-2dc501e6-5c4e-430c-878b-65fb5ca61a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847647086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.847647086
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1826879984
Short name T427
Test name
Test status
Simulation time 15704607 ps
CPU time 0.59 seconds
Started May 23 01:04:03 PM PDT 24
Finished May 23 01:04:10 PM PDT 24
Peak memory 195624 kb
Host smart-d2b12b3f-62d2-4a25-950c-b4290f557837
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826879984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1826879984
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1317452182
Short name T410
Test name
Test status
Simulation time 1459898371 ps
CPU time 37.55 seconds
Started May 23 01:04:05 PM PDT 24
Finished May 23 01:04:49 PM PDT 24
Peak memory 222756 kb
Host smart-aabebfc7-a83b-41db-bcf1-4b960f854fad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1317452182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1317452182
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2251864231
Short name T30
Test name
Test status
Simulation time 116318690 ps
CPU time 6.44 seconds
Started May 23 01:04:07 PM PDT 24
Finished May 23 01:04:19 PM PDT 24
Peak memory 199984 kb
Host smart-edfa2006-a7e3-498c-9aa9-13ee2961d60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251864231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2251864231
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2810613014
Short name T192
Test name
Test status
Simulation time 5257308939 ps
CPU time 192.56 seconds
Started May 23 01:04:03 PM PDT 24
Finished May 23 01:07:22 PM PDT 24
Peak memory 488336 kb
Host smart-60acab54-1dea-4a22-835c-35f71f974fb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2810613014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2810613014
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_long_msg.428853289
Short name T9
Test name
Test status
Simulation time 13078336998 ps
CPU time 89.56 seconds
Started May 23 01:04:07 PM PDT 24
Finished May 23 01:05:42 PM PDT 24
Peak memory 200052 kb
Host smart-54524a9d-c5c2-407e-9620-49b00baaf95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428853289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.428853289
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.3280745909
Short name T98
Test name
Test status
Simulation time 1440892433 ps
CPU time 2.52 seconds
Started May 23 01:04:04 PM PDT 24
Finished May 23 01:04:13 PM PDT 24
Peak memory 199956 kb
Host smart-90754d60-5268-4c7e-8dc8-c4e19dbc7bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280745909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3280745909
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.3433868787
Short name T488
Test name
Test status
Simulation time 201277391 ps
CPU time 1.28 seconds
Started May 23 01:04:05 PM PDT 24
Finished May 23 01:04:12 PM PDT 24
Peak memory 199928 kb
Host smart-7ea7be18-513a-448b-bc82-2f6d7b8a24b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433868787 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.3433868787
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.3669420292
Short name T206
Test name
Test status
Simulation time 178816683810 ps
CPU time 553.77 seconds
Started May 23 01:04:05 PM PDT 24
Finished May 23 01:13:25 PM PDT 24
Peak memory 199968 kb
Host smart-4de39d19-dada-4638-9a1d-04294335eb8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669420292 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.3669420292
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.1529728902
Short name T222
Test name
Test status
Simulation time 3527150816 ps
CPU time 61.7 seconds
Started May 23 01:04:11 PM PDT 24
Finished May 23 01:05:18 PM PDT 24
Peak memory 199912 kb
Host smart-8ab99982-2b2c-4142-9631-7c643455ce24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529728902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1529728902
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1715612098
Short name T182
Test name
Test status
Simulation time 23183776 ps
CPU time 0.63 seconds
Started May 23 01:04:13 PM PDT 24
Finished May 23 01:04:20 PM PDT 24
Peak memory 195580 kb
Host smart-26cd08ed-bd45-451a-93a3-a8523315d6bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715612098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1715612098
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.3619142073
Short name T118
Test name
Test status
Simulation time 3643742161 ps
CPU time 50.98 seconds
Started May 23 01:04:10 PM PDT 24
Finished May 23 01:05:07 PM PDT 24
Peak memory 232740 kb
Host smart-df05fe73-93d8-493e-9af2-c57b33ad3cae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3619142073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3619142073
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2627096907
Short name T323
Test name
Test status
Simulation time 109184696 ps
CPU time 2.54 seconds
Started May 23 01:04:14 PM PDT 24
Finished May 23 01:04:23 PM PDT 24
Peak memory 199808 kb
Host smart-767fd2c6-4dfa-4cdb-ae10-e1e7834a2980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627096907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2627096907
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.3238843531
Short name T125
Test name
Test status
Simulation time 4636986483 ps
CPU time 548.6 seconds
Started May 23 01:04:15 PM PDT 24
Finished May 23 01:13:29 PM PDT 24
Peak memory 693256 kb
Host smart-73d681d1-07df-4a8e-baea-a54a3de88998
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3238843531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3238843531
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1905405396
Short name T60
Test name
Test status
Simulation time 1976067290 ps
CPU time 30.29 seconds
Started May 23 01:04:12 PM PDT 24
Finished May 23 01:04:48 PM PDT 24
Peak memory 199944 kb
Host smart-6ae32ddd-6270-444e-bd13-79ca9a9a487e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905405396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1905405396
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.182078281
Short name T305
Test name
Test status
Simulation time 1068551961 ps
CPU time 5.98 seconds
Started May 23 01:04:02 PM PDT 24
Finished May 23 01:04:14 PM PDT 24
Peak memory 199920 kb
Host smart-ae56e8fd-e1c3-47a7-b8fe-40ae3670ac18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182078281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.182078281
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.3846761036
Short name T454
Test name
Test status
Simulation time 71920148 ps
CPU time 1.03 seconds
Started May 23 01:04:11 PM PDT 24
Finished May 23 01:04:18 PM PDT 24
Peak memory 199556 kb
Host smart-e7287aca-fa45-42c6-846d-f38a2fe8aef6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846761036 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.3846761036
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.3230509305
Short name T231
Test name
Test status
Simulation time 28338994371 ps
CPU time 500.8 seconds
Started May 23 01:04:15 PM PDT 24
Finished May 23 01:12:41 PM PDT 24
Peak memory 200000 kb
Host smart-69abaf34-5015-40b9-b80c-818791279ca5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230509305 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.3230509305
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.2703400673
Short name T306
Test name
Test status
Simulation time 3840009138 ps
CPU time 9.52 seconds
Started May 23 01:04:14 PM PDT 24
Finished May 23 01:04:30 PM PDT 24
Peak memory 200016 kb
Host smart-a3b95213-21c4-4325-984e-20a025d5a272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703400673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2703400673
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3714467521
Short name T431
Test name
Test status
Simulation time 23159185 ps
CPU time 0.6 seconds
Started May 23 01:04:14 PM PDT 24
Finished May 23 01:04:21 PM PDT 24
Peak memory 195428 kb
Host smart-7d5a54b6-9a23-4f61-8214-c4aa56f2f1a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714467521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3714467521
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.2612231224
Short name T345
Test name
Test status
Simulation time 1518234759 ps
CPU time 17.77 seconds
Started May 23 01:04:14 PM PDT 24
Finished May 23 01:04:37 PM PDT 24
Peak memory 199932 kb
Host smart-1d49a0f4-235c-4dd6-b081-130f4f8f20d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2612231224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2612231224
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3984530492
Short name T203
Test name
Test status
Simulation time 1301992688 ps
CPU time 23.05 seconds
Started May 23 01:04:10 PM PDT 24
Finished May 23 01:04:39 PM PDT 24
Peak memory 200044 kb
Host smart-bcbcc48c-8372-417d-b1d8-65bfd7e351b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984530492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3984530492
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2398168235
Short name T508
Test name
Test status
Simulation time 4482032713 ps
CPU time 1116.06 seconds
Started May 23 01:04:12 PM PDT 24
Finished May 23 01:22:54 PM PDT 24
Peak memory 727088 kb
Host smart-4280d45d-6a65-4228-b918-82fb79947e5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2398168235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2398168235
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3513761084
Short name T322
Test name
Test status
Simulation time 2857855500 ps
CPU time 54.82 seconds
Started May 23 01:04:11 PM PDT 24
Finished May 23 01:05:11 PM PDT 24
Peak memory 200148 kb
Host smart-12d5b15c-909f-42a3-bae0-edf07330a5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513761084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3513761084
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.1601201436
Short name T384
Test name
Test status
Simulation time 595549560 ps
CPU time 2.51 seconds
Started May 23 01:04:11 PM PDT 24
Finished May 23 01:04:20 PM PDT 24
Peak memory 200016 kb
Host smart-64d9d53c-ac6f-4702-a76e-9d847655d68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601201436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1601201436
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.3986556783
Short name T468
Test name
Test status
Simulation time 2363788710 ps
CPU time 3.73 seconds
Started May 23 01:04:12 PM PDT 24
Finished May 23 01:04:22 PM PDT 24
Peak memory 200168 kb
Host smart-888b273a-bbae-40f8-a386-6aec848951a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986556783 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3986556783
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.2083906926
Short name T299
Test name
Test status
Simulation time 59181371 ps
CPU time 1.3 seconds
Started May 23 01:04:12 PM PDT 24
Finished May 23 01:04:19 PM PDT 24
Peak memory 200024 kb
Host smart-47663c64-568e-4a5c-a10b-0fb0fca69705
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083906926 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.2083906926
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.3040214244
Short name T368
Test name
Test status
Simulation time 33857144355 ps
CPU time 424.14 seconds
Started May 23 01:04:12 PM PDT 24
Finished May 23 01:11:22 PM PDT 24
Peak memory 199996 kb
Host smart-6530a78f-3340-45d1-9662-f01373f6a257
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040214244 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.3040214244
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.3181875376
Short name T152
Test name
Test status
Simulation time 20552017573 ps
CPU time 105.52 seconds
Started May 23 01:04:14 PM PDT 24
Finished May 23 01:06:06 PM PDT 24
Peak memory 199952 kb
Host smart-341ba442-56e7-48d4-a594-19509238acb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181875376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3181875376
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3578860335
Short name T484
Test name
Test status
Simulation time 74770505 ps
CPU time 0.6 seconds
Started May 23 01:04:14 PM PDT 24
Finished May 23 01:04:21 PM PDT 24
Peak memory 196368 kb
Host smart-d9a7c3c4-5ca0-4af9-9ade-b085d9496457
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578860335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3578860335
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.95134003
Short name T393
Test name
Test status
Simulation time 859328382 ps
CPU time 41.19 seconds
Started May 23 01:04:12 PM PDT 24
Finished May 23 01:04:59 PM PDT 24
Peak memory 208196 kb
Host smart-1451d206-1395-4b7b-b3a3-2f46ea755f98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=95134003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.95134003
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.4244315755
Short name T94
Test name
Test status
Simulation time 6994709864 ps
CPU time 48.72 seconds
Started May 23 01:04:11 PM PDT 24
Finished May 23 01:05:05 PM PDT 24
Peak memory 200204 kb
Host smart-334ce16f-e7a4-4c50-bf8f-4a7c608fa316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244315755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.4244315755
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.3872993741
Short name T524
Test name
Test status
Simulation time 2838482788 ps
CPU time 782 seconds
Started May 23 01:04:12 PM PDT 24
Finished May 23 01:17:20 PM PDT 24
Peak memory 688972 kb
Host smart-df3d695e-7a44-4bd5-b3ae-3b900f312576
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3872993741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3872993741
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2823243139
Short name T162
Test name
Test status
Simulation time 27997843457 ps
CPU time 96.77 seconds
Started May 23 01:04:11 PM PDT 24
Finished May 23 01:05:53 PM PDT 24
Peak memory 200072 kb
Host smart-aa75b140-c8b2-4d06-8ad9-108eaef71552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823243139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2823243139
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3431133326
Short name T190
Test name
Test status
Simulation time 318164789 ps
CPU time 2.73 seconds
Started May 23 01:04:11 PM PDT 24
Finished May 23 01:04:20 PM PDT 24
Peak memory 200012 kb
Host smart-7b2d11a8-9830-4579-a4cd-785782a47cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431133326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3431133326
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3743709031
Short name T128
Test name
Test status
Simulation time 896552416674 ps
CPU time 1947.48 seconds
Started May 23 01:04:12 PM PDT 24
Finished May 23 01:36:46 PM PDT 24
Peak memory 769604 kb
Host smart-de3c7ae4-9f88-4707-917d-9076c95a23ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743709031 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3743709031
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.1507478742
Short name T181
Test name
Test status
Simulation time 115336091 ps
CPU time 1.31 seconds
Started May 23 01:04:13 PM PDT 24
Finished May 23 01:04:20 PM PDT 24
Peak memory 199856 kb
Host smart-96acefe2-5c9f-4cca-a400-8ef1979c4aca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507478742 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.1507478742
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.844457596
Short name T276
Test name
Test status
Simulation time 31376388293 ps
CPU time 479.27 seconds
Started May 23 01:04:10 PM PDT 24
Finished May 23 01:12:16 PM PDT 24
Peak memory 200080 kb
Host smart-4af82e1c-ceca-44a4-a34d-e0b793438820
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844457596 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.844457596
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2475346579
Short name T221
Test name
Test status
Simulation time 8190490774 ps
CPU time 119.08 seconds
Started May 23 01:04:14 PM PDT 24
Finished May 23 01:06:18 PM PDT 24
Peak memory 199984 kb
Host smart-29f5b7a5-b6d8-42ef-8d09-d4275d7548f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475346579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2475346579
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.1744774789
Short name T227
Test name
Test status
Simulation time 15425451 ps
CPU time 0.62 seconds
Started May 23 01:04:14 PM PDT 24
Finished May 23 01:04:20 PM PDT 24
Peak memory 196344 kb
Host smart-a886d123-3412-43f0-89a5-bb000bd3ca52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744774789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1744774789
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.2084627801
Short name T419
Test name
Test status
Simulation time 695929825 ps
CPU time 43.71 seconds
Started May 23 01:04:10 PM PDT 24
Finished May 23 01:04:59 PM PDT 24
Peak memory 232552 kb
Host smart-5cf4386b-194c-40fb-87e1-7c8c31a80b6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2084627801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.2084627801
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.240425953
Short name T47
Test name
Test status
Simulation time 532832830 ps
CPU time 7.48 seconds
Started May 23 01:04:16 PM PDT 24
Finished May 23 01:04:29 PM PDT 24
Peak memory 199860 kb
Host smart-08f688bd-a874-4b44-9b92-9fdc8fe87867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240425953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.240425953
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2244357152
Short name T521
Test name
Test status
Simulation time 3254948483 ps
CPU time 922.38 seconds
Started May 23 01:04:14 PM PDT 24
Finished May 23 01:19:42 PM PDT 24
Peak memory 781072 kb
Host smart-3e98f37e-6cbb-4e98-b30c-20521158602c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2244357152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2244357152
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_long_msg.89612076
Short name T412
Test name
Test status
Simulation time 15815992799 ps
CPU time 52.46 seconds
Started May 23 01:04:10 PM PDT 24
Finished May 23 01:05:08 PM PDT 24
Peak memory 200044 kb
Host smart-150443e4-f271-499c-8d7e-f5a99487fb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89612076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.89612076
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.151196327
Short name T506
Test name
Test status
Simulation time 740904604 ps
CPU time 5.59 seconds
Started May 23 01:04:14 PM PDT 24
Finished May 23 01:04:25 PM PDT 24
Peak memory 199964 kb
Host smart-d982dba2-255b-4085-858c-4093c5603a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151196327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.151196327
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.1000390703
Short name T456
Test name
Test status
Simulation time 563493214 ps
CPU time 13.98 seconds
Started May 23 01:04:13 PM PDT 24
Finished May 23 01:04:32 PM PDT 24
Peak memory 208236 kb
Host smart-ad3f3539-6c2e-4564-8d76-1accbe8dd025
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000390703 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1000390703
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.100318385
Short name T331
Test name
Test status
Simulation time 29573947 ps
CPU time 1.02 seconds
Started May 23 01:04:11 PM PDT 24
Finished May 23 01:04:18 PM PDT 24
Peak memory 199724 kb
Host smart-99c6a40e-ff21-46d2-885d-901aaa09639a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100318385 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_hmac_vectors.100318385
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.1689302904
Short name T286
Test name
Test status
Simulation time 49169910283 ps
CPU time 440.85 seconds
Started May 23 01:04:12 PM PDT 24
Finished May 23 01:11:39 PM PDT 24
Peak memory 200104 kb
Host smart-1727cfd6-5118-4a50-a1dd-e709f0060115
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689302904 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.1689302904
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.2648708511
Short name T303
Test name
Test status
Simulation time 1709114394 ps
CPU time 77.8 seconds
Started May 23 01:04:11 PM PDT 24
Finished May 23 01:05:34 PM PDT 24
Peak memory 199908 kb
Host smart-4efd0b01-6c2d-44c4-bec7-dec1056489a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648708511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2648708511
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.1903840725
Short name T266
Test name
Test status
Simulation time 11821965 ps
CPU time 0.57 seconds
Started May 23 01:04:27 PM PDT 24
Finished May 23 01:04:31 PM PDT 24
Peak memory 194704 kb
Host smart-38cf13b0-1238-4e75-97a1-74aac4032360
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903840725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.1903840725
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.2708044096
Short name T338
Test name
Test status
Simulation time 780063947 ps
CPU time 15.55 seconds
Started May 23 01:04:15 PM PDT 24
Finished May 23 01:04:37 PM PDT 24
Peak memory 208172 kb
Host smart-6bb1e753-c9b9-4974-b2cf-ebbc9025423b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2708044096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2708044096
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.3396693230
Short name T130
Test name
Test status
Simulation time 4031412372 ps
CPU time 52.36 seconds
Started May 23 01:04:11 PM PDT 24
Finished May 23 01:05:09 PM PDT 24
Peak memory 199992 kb
Host smart-1d5c02db-cd19-4806-b064-2a703679b51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396693230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.3396693230
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2135678210
Short name T395
Test name
Test status
Simulation time 495346727 ps
CPU time 134.68 seconds
Started May 23 01:04:13 PM PDT 24
Finished May 23 01:06:34 PM PDT 24
Peak memory 621688 kb
Host smart-c7b6547f-8b19-4ef3-a820-c4571af509a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2135678210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2135678210
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_long_msg.788310519
Short name T367
Test name
Test status
Simulation time 1773105254 ps
CPU time 105.57 seconds
Started May 23 01:04:13 PM PDT 24
Finished May 23 01:06:04 PM PDT 24
Peak memory 199904 kb
Host smart-3aca413f-3a85-4db9-b497-f39cf8e95a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788310519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.788310519
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3335267025
Short name T224
Test name
Test status
Simulation time 164314554 ps
CPU time 2.13 seconds
Started May 23 01:04:12 PM PDT 24
Finished May 23 01:04:20 PM PDT 24
Peak memory 200084 kb
Host smart-ec9dad49-a81c-42f9-94ae-5e1ef012fef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335267025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3335267025
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1061124608
Short name T87
Test name
Test status
Simulation time 200737217229 ps
CPU time 2356.6 seconds
Started May 23 01:04:27 PM PDT 24
Finished May 23 01:43:47 PM PDT 24
Peak memory 807516 kb
Host smart-1341b721-6e8f-4e7f-ab1f-69b66844e34a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061124608 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1061124608
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.1057202451
Short name T32
Test name
Test status
Simulation time 135319495 ps
CPU time 1.33 seconds
Started May 23 01:04:28 PM PDT 24
Finished May 23 01:04:34 PM PDT 24
Peak memory 200020 kb
Host smart-f4d25dfb-7835-4117-9fb7-57ebda93e0be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057202451 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.1057202451
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.1422364156
Short name T45
Test name
Test status
Simulation time 315425676730 ps
CPU time 484.87 seconds
Started May 23 01:04:30 PM PDT 24
Finished May 23 01:12:39 PM PDT 24
Peak memory 200092 kb
Host smart-718f0044-3e62-4fc7-bdd0-ddbb311f2b1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422364156 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.1422364156
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.4108152556
Short name T153
Test name
Test status
Simulation time 188088828 ps
CPU time 7.84 seconds
Started May 23 01:04:28 PM PDT 24
Finished May 23 01:04:40 PM PDT 24
Peak memory 199920 kb
Host smart-91a7ecda-27a3-4ca3-9d20-591d274a6053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108152556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.4108152556
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1008128343
Short name T234
Test name
Test status
Simulation time 14388019 ps
CPU time 0.56 seconds
Started May 23 01:04:27 PM PDT 24
Finished May 23 01:04:30 PM PDT 24
Peak memory 194672 kb
Host smart-f26d8164-487e-4b90-970b-dda1ceaa186d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008128343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1008128343
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1392309929
Short name T439
Test name
Test status
Simulation time 2488992441 ps
CPU time 45.24 seconds
Started May 23 01:04:29 PM PDT 24
Finished May 23 01:05:18 PM PDT 24
Peak memory 208372 kb
Host smart-4b4bd3d0-5575-49db-bc76-24631d465ae1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1392309929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1392309929
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1768648870
Short name T434
Test name
Test status
Simulation time 12518737542 ps
CPU time 41.98 seconds
Started May 23 01:04:28 PM PDT 24
Finished May 23 01:05:14 PM PDT 24
Peak memory 200132 kb
Host smart-50d67060-d01d-4961-934d-351227a0e0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768648870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1768648870
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.3528387767
Short name T187
Test name
Test status
Simulation time 6666262951 ps
CPU time 931.16 seconds
Started May 23 01:04:31 PM PDT 24
Finished May 23 01:20:07 PM PDT 24
Peak memory 745760 kb
Host smart-24156463-4b3e-4462-83f8-cd58a2d9e803
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3528387767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3528387767
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.3287263014
Short name T25
Test name
Test status
Simulation time 31382091465 ps
CPU time 99.19 seconds
Started May 23 01:04:28 PM PDT 24
Finished May 23 01:06:11 PM PDT 24
Peak memory 199988 kb
Host smart-6f950a23-0d3a-4b10-8a19-9d9e6b50c647
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287263014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3287263014
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.454415091
Short name T501
Test name
Test status
Simulation time 9674017623 ps
CPU time 95.73 seconds
Started May 23 01:04:29 PM PDT 24
Finished May 23 01:06:09 PM PDT 24
Peak memory 200068 kb
Host smart-9ea7bbe4-7bf2-45b4-a3ca-ce965d3195e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454415091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.454415091
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1077481863
Short name T314
Test name
Test status
Simulation time 510029109 ps
CPU time 5.79 seconds
Started May 23 01:04:28 PM PDT 24
Finished May 23 01:04:37 PM PDT 24
Peak memory 199900 kb
Host smart-aba90015-d9b3-4d4e-9a8d-6da7fa9755e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077481863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1077481863
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.2854792320
Short name T144
Test name
Test status
Simulation time 117161240194 ps
CPU time 618.68 seconds
Started May 23 01:04:28 PM PDT 24
Finished May 23 01:14:51 PM PDT 24
Peak memory 228828 kb
Host smart-ac2d9717-74d8-4ef7-80e7-333a9078197b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854792320 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2854792320
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.3837083662
Short name T356
Test name
Test status
Simulation time 1280562574 ps
CPU time 1.37 seconds
Started May 23 01:04:30 PM PDT 24
Finished May 23 01:04:35 PM PDT 24
Peak memory 200004 kb
Host smart-4da8789a-5cdb-493c-8375-9436a5027b5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837083662 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.3837083662
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.2066135361
Short name T151
Test name
Test status
Simulation time 80070538434 ps
CPU time 447.64 seconds
Started May 23 01:04:27 PM PDT 24
Finished May 23 01:11:57 PM PDT 24
Peak memory 200132 kb
Host smart-2f4ff9aa-3480-4a81-914e-c4a73148593e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066135361 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.2066135361
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.714369870
Short name T451
Test name
Test status
Simulation time 5794867899 ps
CPU time 64 seconds
Started May 23 01:04:34 PM PDT 24
Finished May 23 01:05:42 PM PDT 24
Peak memory 200080 kb
Host smart-3a5b9153-4177-490e-bfaf-b790ae4fb4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714369870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.714369870
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3442607512
Short name T304
Test name
Test status
Simulation time 13404598 ps
CPU time 0.61 seconds
Started May 23 01:04:30 PM PDT 24
Finished May 23 01:04:35 PM PDT 24
Peak memory 194608 kb
Host smart-b1ffadc5-eb09-4399-a1d6-0141bf2eadc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442607512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3442607512
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.3467064840
Short name T373
Test name
Test status
Simulation time 863955260 ps
CPU time 51.91 seconds
Started May 23 01:04:28 PM PDT 24
Finished May 23 01:05:23 PM PDT 24
Peak memory 232856 kb
Host smart-b126ea3e-60b3-43f2-a473-bbb7b31f9d70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3467064840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3467064840
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.210949677
Short name T405
Test name
Test status
Simulation time 4600216036 ps
CPU time 13.27 seconds
Started May 23 01:04:28 PM PDT 24
Finished May 23 01:04:46 PM PDT 24
Peak memory 200148 kb
Host smart-254b9f12-e0fc-4b41-b59d-39e85327140c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210949677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.210949677
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.484580610
Short name T512
Test name
Test status
Simulation time 3398571986 ps
CPU time 690.66 seconds
Started May 23 01:04:30 PM PDT 24
Finished May 23 01:16:05 PM PDT 24
Peak memory 640056 kb
Host smart-ac20643e-b30a-4e8f-bffd-bb4dcf5da0fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=484580610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.484580610
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1319962249
Short name T418
Test name
Test status
Simulation time 71983841 ps
CPU time 4.11 seconds
Started May 23 01:04:27 PM PDT 24
Finished May 23 01:04:34 PM PDT 24
Peak memory 200004 kb
Host smart-b6c51bc8-1573-4a58-92ef-1a2efd8b2785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319962249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1319962249
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.710372530
Short name T265
Test name
Test status
Simulation time 82248328 ps
CPU time 3.04 seconds
Started May 23 01:04:28 PM PDT 24
Finished May 23 01:04:34 PM PDT 24
Peak memory 199956 kb
Host smart-c4a703f2-44df-42e3-90da-a1ab15b9f263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710372530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.710372530
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.546330273
Short name T35
Test name
Test status
Simulation time 146653456508 ps
CPU time 2263.67 seconds
Started May 23 01:04:30 PM PDT 24
Finished May 23 01:42:18 PM PDT 24
Peak memory 775828 kb
Host smart-4193c78d-3a1b-42dc-8743-ab2358d9e63f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546330273 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.546330273
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.499404082
Short name T215
Test name
Test status
Simulation time 305060455 ps
CPU time 1.33 seconds
Started May 23 01:04:27 PM PDT 24
Finished May 23 01:04:32 PM PDT 24
Peak memory 200056 kb
Host smart-914007ef-5128-4f0d-b3df-38beae3b4df4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499404082 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_hmac_vectors.499404082
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.3547091254
Short name T198
Test name
Test status
Simulation time 252109399738 ps
CPU time 507.6 seconds
Started May 23 01:04:34 PM PDT 24
Finished May 23 01:13:06 PM PDT 24
Peak memory 200128 kb
Host smart-7830ea9a-fc38-4ed5-b560-7591eb23c378
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547091254 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.3547091254
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2121762966
Short name T277
Test name
Test status
Simulation time 10673063913 ps
CPU time 75.64 seconds
Started May 23 01:04:34 PM PDT 24
Finished May 23 01:05:54 PM PDT 24
Peak memory 200112 kb
Host smart-45d3c813-5ae4-4b0d-9c1e-a9ef758e8456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121762966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2121762966
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.61112412
Short name T437
Test name
Test status
Simulation time 16989075 ps
CPU time 0.6 seconds
Started May 23 01:04:34 PM PDT 24
Finished May 23 01:04:39 PM PDT 24
Peak memory 195404 kb
Host smart-2511efde-95f0-46e6-bc20-cfeef8fc441d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61112412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.61112412
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2045496894
Short name T354
Test name
Test status
Simulation time 1244258282 ps
CPU time 28.58 seconds
Started May 23 01:04:29 PM PDT 24
Finished May 23 01:05:02 PM PDT 24
Peak memory 200084 kb
Host smart-d676cf87-e1b1-4e2e-943d-6dfd1b42bfcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2045496894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2045496894
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1359041640
Short name T333
Test name
Test status
Simulation time 1062768794 ps
CPU time 43.16 seconds
Started May 23 01:04:34 PM PDT 24
Finished May 23 01:05:22 PM PDT 24
Peak memory 199912 kb
Host smart-b66833e9-2e24-4031-9cf8-f59104857363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359041640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1359041640
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.748765016
Short name T180
Test name
Test status
Simulation time 4270206960 ps
CPU time 1177.44 seconds
Started May 23 01:04:29 PM PDT 24
Finished May 23 01:24:10 PM PDT 24
Peak memory 713760 kb
Host smart-2c0fce9c-5efd-455b-862e-95ed601cbe8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=748765016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.748765016
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2795935897
Short name T165
Test name
Test status
Simulation time 13733009667 ps
CPU time 132.54 seconds
Started May 23 01:04:28 PM PDT 24
Finished May 23 01:06:44 PM PDT 24
Peak memory 200100 kb
Host smart-e8cf7aac-aedb-4ae4-b5f1-838ffa5d9aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795935897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2795935897
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3809209062
Short name T389
Test name
Test status
Simulation time 56734870 ps
CPU time 1.28 seconds
Started May 23 01:04:30 PM PDT 24
Finished May 23 01:04:36 PM PDT 24
Peak memory 199852 kb
Host smart-dd3fb19b-cfde-4719-b185-dd4c7b5275aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809209062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3809209062
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1892385571
Short name T445
Test name
Test status
Simulation time 31559610129 ps
CPU time 1473.25 seconds
Started May 23 01:04:28 PM PDT 24
Finished May 23 01:29:05 PM PDT 24
Peak memory 783196 kb
Host smart-156cb96c-9462-488d-ab45-76d05ac577e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892385571 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1892385571
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.4141698237
Short name T428
Test name
Test status
Simulation time 346893096 ps
CPU time 1.24 seconds
Started May 23 01:04:35 PM PDT 24
Finished May 23 01:04:40 PM PDT 24
Peak memory 199932 kb
Host smart-1c037ae7-ce71-420c-85aa-843726868aff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141698237 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.4141698237
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.744223571
Short name T186
Test name
Test status
Simulation time 59134170646 ps
CPU time 551.42 seconds
Started May 23 01:04:27 PM PDT 24
Finished May 23 01:13:42 PM PDT 24
Peak memory 200104 kb
Host smart-c24b9614-d0e6-4614-859b-616198bb4ce7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744223571 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.744223571
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.2104393496
Short name T249
Test name
Test status
Simulation time 1835233167 ps
CPU time 31.59 seconds
Started May 23 01:04:29 PM PDT 24
Finished May 23 01:05:05 PM PDT 24
Peak memory 199916 kb
Host smart-b635dee1-ca6d-4a11-963d-94ddab61d0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104393496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.2104393496
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.745324980
Short name T447
Test name
Test status
Simulation time 31286849 ps
CPU time 0.62 seconds
Started May 23 01:03:07 PM PDT 24
Finished May 23 01:03:10 PM PDT 24
Peak memory 195360 kb
Host smart-621c336a-5516-4233-ba37-be04daf9910d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745324980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.745324980
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.3067083678
Short name T366
Test name
Test status
Simulation time 2619097130 ps
CPU time 37.27 seconds
Started May 23 01:03:01 PM PDT 24
Finished May 23 01:03:40 PM PDT 24
Peak memory 229884 kb
Host smart-79be6fdd-956e-4c52-a131-b680b3b72a37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3067083678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3067083678
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.2385174508
Short name T242
Test name
Test status
Simulation time 160465824 ps
CPU time 2.87 seconds
Started May 23 01:03:03 PM PDT 24
Finished May 23 01:03:08 PM PDT 24
Peak memory 199928 kb
Host smart-dc8bfb43-a294-4e95-a5f3-e50d3e74853e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385174508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.2385174508
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.792559513
Short name T197
Test name
Test status
Simulation time 6718128572 ps
CPU time 835.91 seconds
Started May 23 01:03:07 PM PDT 24
Finished May 23 01:17:05 PM PDT 24
Peak memory 736120 kb
Host smart-26296b6f-97be-49f7-ac1a-5462086b5999
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=792559513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.792559513
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_long_msg.47490844
Short name T343
Test name
Test status
Simulation time 2804161423 ps
CPU time 27.11 seconds
Started May 23 01:03:06 PM PDT 24
Finished May 23 01:03:36 PM PDT 24
Peak memory 199952 kb
Host smart-42bea7db-1469-48d2-abb5-002028ba1b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47490844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.47490844
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.798692885
Short name T158
Test name
Test status
Simulation time 167487399 ps
CPU time 1.11 seconds
Started May 23 01:03:06 PM PDT 24
Finished May 23 01:03:09 PM PDT 24
Peak memory 199916 kb
Host smart-1976ca65-3406-4b29-9948-496c62d91be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798692885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.798692885
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.2649372577
Short name T160
Test name
Test status
Simulation time 65935827 ps
CPU time 1.26 seconds
Started May 23 01:03:01 PM PDT 24
Finished May 23 01:03:03 PM PDT 24
Peak memory 199944 kb
Host smart-a55ab336-b211-46d8-b280-c1cc29eade5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649372577 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.2649372577
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.3765062155
Short name T283
Test name
Test status
Simulation time 148956016530 ps
CPU time 531.6 seconds
Started May 23 01:02:53 PM PDT 24
Finished May 23 01:11:46 PM PDT 24
Peak memory 200064 kb
Host smart-f2e1a67f-d5dc-4d1e-be95-9f9832558c58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765062155 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.3765062155
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.2636209572
Short name T258
Test name
Test status
Simulation time 939518873 ps
CPU time 31.78 seconds
Started May 23 01:03:06 PM PDT 24
Finished May 23 01:03:39 PM PDT 24
Peak memory 199984 kb
Host smart-1efe8e7e-c4d1-476e-891c-08475ef6d399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636209572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.2636209572
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2651810664
Short name T96
Test name
Test status
Simulation time 12198718 ps
CPU time 0.58 seconds
Started May 23 01:03:16 PM PDT 24
Finished May 23 01:03:23 PM PDT 24
Peak memory 195608 kb
Host smart-e432ef72-2d38-4433-b606-52ab1e1a3829
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651810664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2651810664
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.423631990
Short name T156
Test name
Test status
Simulation time 38641926 ps
CPU time 2.35 seconds
Started May 23 01:03:08 PM PDT 24
Finished May 23 01:03:13 PM PDT 24
Peak memory 200056 kb
Host smart-6d5bf805-f290-4346-8c6d-f2aa9ab71bb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=423631990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.423631990
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.313706454
Short name T362
Test name
Test status
Simulation time 103561544 ps
CPU time 2.69 seconds
Started May 23 01:03:06 PM PDT 24
Finished May 23 01:03:10 PM PDT 24
Peak memory 200056 kb
Host smart-82319fa7-535e-4811-99fb-ed76f9a42994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313706454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.313706454
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3707903647
Short name T363
Test name
Test status
Simulation time 14390703666 ps
CPU time 48.14 seconds
Started May 23 01:03:05 PM PDT 24
Finished May 23 01:03:55 PM PDT 24
Peak memory 200036 kb
Host smart-8fef8bd6-44f1-4911-bc5f-cd9eee4fa125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707903647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3707903647
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.386768237
Short name T399
Test name
Test status
Simulation time 1139871207 ps
CPU time 4.32 seconds
Started May 23 01:03:12 PM PDT 24
Finished May 23 01:03:23 PM PDT 24
Peak memory 200012 kb
Host smart-d88bd265-6fef-4467-b5b4-f0ebe919ca8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386768237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.386768237
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.2066905871
Short name T2
Test name
Test status
Simulation time 64579645 ps
CPU time 1.35 seconds
Started May 23 01:03:15 PM PDT 24
Finished May 23 01:03:18 PM PDT 24
Peak memory 199840 kb
Host smart-b50ce6cc-d3e8-47ec-b490-17b37c1be049
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066905871 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.2066905871
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.3880330746
Short name T387
Test name
Test status
Simulation time 7726074047 ps
CPU time 424.7 seconds
Started May 23 01:03:05 PM PDT 24
Finished May 23 01:10:12 PM PDT 24
Peak memory 199996 kb
Host smart-594d6dcb-38ca-4435-a097-dd66f8f4577c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880330746 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.3880330746
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2179820230
Short name T97
Test name
Test status
Simulation time 962368837 ps
CPU time 51.55 seconds
Started May 23 01:03:11 PM PDT 24
Finished May 23 01:04:04 PM PDT 24
Peak memory 200004 kb
Host smart-24aeeece-44da-4f0f-b0ca-3aae11f6cb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179820230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2179820230
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2065862116
Short name T466
Test name
Test status
Simulation time 53157069 ps
CPU time 0.58 seconds
Started May 23 01:03:14 PM PDT 24
Finished May 23 01:03:15 PM PDT 24
Peak memory 196368 kb
Host smart-34d7e96c-ad8a-4d23-90bc-293d5cd3c732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065862116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2065862116
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.3521010168
Short name T375
Test name
Test status
Simulation time 3585733738 ps
CPU time 48.66 seconds
Started May 23 01:03:08 PM PDT 24
Finished May 23 01:03:59 PM PDT 24
Peak memory 232860 kb
Host smart-51abc617-02c5-42a2-9d73-1a45ede72673
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3521010168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3521010168
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3461660682
Short name T273
Test name
Test status
Simulation time 1581159726 ps
CPU time 29.78 seconds
Started May 23 01:03:16 PM PDT 24
Finished May 23 01:03:47 PM PDT 24
Peak memory 199940 kb
Host smart-9434c16b-836c-42f6-9e4a-531027ee764e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461660682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3461660682
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.337112139
Short name T402
Test name
Test status
Simulation time 51422061068 ps
CPU time 1475.27 seconds
Started May 23 01:03:16 PM PDT 24
Finished May 23 01:27:53 PM PDT 24
Peak memory 745220 kb
Host smart-a925439f-a6f4-4aa7-8067-0583e049412c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=337112139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.337112139
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2384756711
Short name T473
Test name
Test status
Simulation time 99688229 ps
CPU time 2.96 seconds
Started May 23 01:03:09 PM PDT 24
Finished May 23 01:03:14 PM PDT 24
Peak memory 199824 kb
Host smart-0994f537-a2b6-4ef2-9aef-3540851b9816
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384756711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2384756711
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3974953395
Short name T312
Test name
Test status
Simulation time 15013763184 ps
CPU time 53.09 seconds
Started May 23 01:03:06 PM PDT 24
Finished May 23 01:04:01 PM PDT 24
Peak memory 200084 kb
Host smart-7d4478e9-243d-4450-a63f-dc107f30ce41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974953395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3974953395
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2184833109
Short name T513
Test name
Test status
Simulation time 540568225 ps
CPU time 3.06 seconds
Started May 23 01:03:13 PM PDT 24
Finished May 23 01:03:17 PM PDT 24
Peak memory 199972 kb
Host smart-0e6686d6-7eaf-4ea3-93c6-6ab36c2f873b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184833109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2184833109
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.116215979
Short name T68
Test name
Test status
Simulation time 14931823609 ps
CPU time 770.17 seconds
Started May 23 01:03:16 PM PDT 24
Finished May 23 01:16:07 PM PDT 24
Peak memory 208276 kb
Host smart-58e334f9-f049-4069-94e0-4a3c9c7879a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116215979 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.116215979
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.4145442015
Short name T240
Test name
Test status
Simulation time 286608069 ps
CPU time 1.32 seconds
Started May 23 01:03:10 PM PDT 24
Finished May 23 01:03:14 PM PDT 24
Peak memory 199856 kb
Host smart-8d220368-822f-40f1-8f2c-188252b7eec0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145442015 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.4145442015
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.837021971
Short name T218
Test name
Test status
Simulation time 101916056907 ps
CPU time 469.08 seconds
Started May 23 01:03:08 PM PDT 24
Finished May 23 01:11:00 PM PDT 24
Peak memory 199996 kb
Host smart-1acd1a7c-d839-4840-850a-43d23653a13c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837021971 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.837021971
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.3077283709
Short name T199
Test name
Test status
Simulation time 2011083707 ps
CPU time 26.93 seconds
Started May 23 01:03:06 PM PDT 24
Finished May 23 01:03:36 PM PDT 24
Peak memory 200020 kb
Host smart-7c32187d-8205-485d-9ca4-e41342fdd980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077283709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3077283709
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1678602820
Short name T255
Test name
Test status
Simulation time 15139266 ps
CPU time 0.57 seconds
Started May 23 01:03:16 PM PDT 24
Finished May 23 01:03:19 PM PDT 24
Peak memory 194620 kb
Host smart-6428b103-aae1-40b4-9085-6a83cece1b78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678602820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1678602820
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3687043101
Short name T49
Test name
Test status
Simulation time 504405618 ps
CPU time 12.33 seconds
Started May 23 01:03:21 PM PDT 24
Finished May 23 01:03:35 PM PDT 24
Peak memory 208212 kb
Host smart-d34443af-0547-463b-9c90-5ac01dcf048b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3687043101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3687043101
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2035187485
Short name T424
Test name
Test status
Simulation time 569695443 ps
CPU time 29.01 seconds
Started May 23 01:03:16 PM PDT 24
Finished May 23 01:03:46 PM PDT 24
Peak memory 199928 kb
Host smart-1620fd8f-fdad-4639-995a-f4d2c996287c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035187485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2035187485
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.4030057906
Short name T476
Test name
Test status
Simulation time 2506955746 ps
CPU time 802.04 seconds
Started May 23 01:03:15 PM PDT 24
Finished May 23 01:16:38 PM PDT 24
Peak memory 729912 kb
Host smart-736ad8c3-ce03-4a54-b2ae-f747d3c16ce6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4030057906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.4030057906
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_long_msg.2878707698
Short name T392
Test name
Test status
Simulation time 1836583700 ps
CPU time 22.03 seconds
Started May 23 01:03:07 PM PDT 24
Finished May 23 01:03:32 PM PDT 24
Peak memory 200068 kb
Host smart-c5b303be-cd9f-424c-992a-633b74b8b8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878707698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.2878707698
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.2021504943
Short name T327
Test name
Test status
Simulation time 386998823 ps
CPU time 5.6 seconds
Started May 23 01:03:10 PM PDT 24
Finished May 23 01:03:18 PM PDT 24
Peak memory 199932 kb
Host smart-52dd28d7-2eeb-45fa-b650-018ec55b7811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021504943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.2021504943
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.2859281376
Short name T253
Test name
Test status
Simulation time 181393448 ps
CPU time 0.97 seconds
Started May 23 01:03:06 PM PDT 24
Finished May 23 01:03:09 PM PDT 24
Peak memory 198448 kb
Host smart-32270d7f-747d-4360-bd31-1972251deded
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859281376 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.2859281376
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.3094021415
Short name T185
Test name
Test status
Simulation time 11509941953 ps
CPU time 396.25 seconds
Started May 23 01:03:07 PM PDT 24
Finished May 23 01:09:45 PM PDT 24
Peak memory 200060 kb
Host smart-7707937e-d3f8-4446-b4c3-1f5f50977529
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094021415 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.3094021415
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1510572403
Short name T183
Test name
Test status
Simulation time 12634252172 ps
CPU time 36.05 seconds
Started May 23 01:03:16 PM PDT 24
Finished May 23 01:03:53 PM PDT 24
Peak memory 200108 kb
Host smart-0dae5822-4df9-46c2-863b-84717255d90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510572403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1510572403
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2747964902
Short name T290
Test name
Test status
Simulation time 35343386 ps
CPU time 0.65 seconds
Started May 23 01:03:09 PM PDT 24
Finished May 23 01:03:12 PM PDT 24
Peak memory 195424 kb
Host smart-91893ebe-d11e-4c46-9230-6a9d1ddb8e32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747964902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2747964902
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2587518402
Short name T82
Test name
Test status
Simulation time 3123490742 ps
CPU time 30.66 seconds
Started May 23 01:03:10 PM PDT 24
Finished May 23 01:03:43 PM PDT 24
Peak memory 225696 kb
Host smart-3ef1499e-8859-441b-b688-d6faab34df30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2587518402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2587518402
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.121743797
Short name T143
Test name
Test status
Simulation time 4072216377 ps
CPU time 51.59 seconds
Started May 23 01:03:06 PM PDT 24
Finished May 23 01:03:59 PM PDT 24
Peak memory 200072 kb
Host smart-161b1824-cb59-470c-a03e-6753cfde7c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121743797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.121743797
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.311291671
Short name T519
Test name
Test status
Simulation time 1799156889 ps
CPU time 85.17 seconds
Started May 23 01:03:16 PM PDT 24
Finished May 23 01:04:43 PM PDT 24
Peak memory 355992 kb
Host smart-57cdaa2f-3e26-4e44-862f-2426fa527b24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=311291671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.311291671
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_long_msg.1812390426
Short name T394
Test name
Test status
Simulation time 987702117 ps
CPU time 14.13 seconds
Started May 23 01:03:09 PM PDT 24
Finished May 23 01:03:25 PM PDT 24
Peak memory 199944 kb
Host smart-9b7bd65c-7350-45cb-85cd-a937c3c0baa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812390426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1812390426
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.275490716
Short name T518
Test name
Test status
Simulation time 122478010 ps
CPU time 0.89 seconds
Started May 23 01:03:10 PM PDT 24
Finished May 23 01:03:13 PM PDT 24
Peak memory 198680 kb
Host smart-3241414c-3470-486b-8218-3e05d82ecf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275490716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.275490716
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1123732293
Short name T142
Test name
Test status
Simulation time 16575254507 ps
CPU time 945.01 seconds
Started May 23 01:03:08 PM PDT 24
Finished May 23 01:18:56 PM PDT 24
Peak memory 309628 kb
Host smart-190be305-961a-45cd-932a-ed464d1a879c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123732293 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1123732293
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.2580112638
Short name T495
Test name
Test status
Simulation time 238877822 ps
CPU time 0.97 seconds
Started May 23 01:03:09 PM PDT 24
Finished May 23 01:03:12 PM PDT 24
Peak memory 198292 kb
Host smart-a503f416-74c6-488c-9245-34c30e2cdd72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580112638 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.2580112638
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.3808610812
Short name T435
Test name
Test status
Simulation time 16436806020 ps
CPU time 472.78 seconds
Started May 23 01:03:11 PM PDT 24
Finished May 23 01:11:05 PM PDT 24
Peak memory 199984 kb
Host smart-e8201825-745d-4ed4-b2f6-abd4bb452ac2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808610812 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.3808610812
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.2186864940
Short name T397
Test name
Test status
Simulation time 4245551064 ps
CPU time 24.49 seconds
Started May 23 01:03:06 PM PDT 24
Finished May 23 01:03:32 PM PDT 24
Peak memory 199964 kb
Host smart-cbad2635-a16c-4068-bdc9-6112dc672f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186864940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2186864940
Directory /workspace/9.hmac_wipe_secret/latest
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