Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7463097	1			T1	1509		T2	226		T3	628
all_values[1]	7463097	1			T1	1509		T2	226		T3	628
all_values[2]	7463097	1			T1	1509		T2	226		T3	628

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84439

1

T1

977

T5

4

T8

11

auto[1]

22304852

1

T1

3550

T2

678

T3

1884

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18711605

1

T1

4524

T2

602

T3

1755

auto[1]

3677686

1

T1

3

T2

76

T3

129

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	24150	1			T1	975		T19	18		T84	327
all_values[0]	auto[0]	auto[1]	228	1			T1	2		T19	1		T55	2
all_values[0]	auto[1]	auto[0]	7419358	1			T1	531		T2	206		T3	601
all_values[0]	auto[1]	auto[1]	19361	1			T1	1		T2	20		T3	27
all_values[1]	auto[0]	auto[0]	36922	1			T5	2		T13	250		T7	1395
all_values[1]	auto[0]	auto[1]	90	1			T19	1		T26	1		T51	5
all_values[1]	auto[1]	auto[0]	7425983	1			T1	1509		T2	226		T3	628
all_values[1]	auto[1]	auto[1]	102	1			T19	2		T26	1		T51	4
all_values[2]	auto[0]	auto[0]	14594	1			T5	2		T8	1		T54	2
all_values[2]	auto[0]	auto[1]	8455	1			T8	10		T54	1		T19	4
all_values[2]	auto[1]	auto[0]	3790598	1			T1	1509		T2	170		T3	526
all_values[2]	auto[1]	auto[1]	3649450	1			T2	56		T3	102		T4	15730