Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3566742

1

T1

530

T2

139

T3

91

auto[1]

1345304

1

T1

932

T2

57

T3

133

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1299010

1

T1

932

T2

104

T3

140

auto[1]

3613036

1

T1

530

T2

92

T3

84

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2998633

1

T2

127

T3

126

T5

3

auto[1]

1913413

1

T1

1462

T2

69

T3

98

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	3926304	1			T1	664		T2	150		T3	199
fifo_depth[1]	166847	1			T1	87		T2	4		T3	1
fifo_depth[2]	139148	1			T1	90		T2	6		T3	1
fifo_depth[3]	111374	1			T1	95		T2	4		T3	4
fifo_depth[4]	92018	1			T1	89		T2	4		T3	3
fifo_depth[5]	78639	1			T1	81		T2	8		T4	760
fifo_depth[6]	75203	1			T1	76		T2	4		T3	4
fifo_depth[7]	62914	1			T1	85		T2	6		T3	5

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

985742

1

T1

798

T2

46

T3

25

auto[1]

3926304

1

T1

664

T2

150

T3

199

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4904573

1

T1

1462

T2

196

T3

224

auto[1]

7473

1

T21

2895

T47

1

T26

79

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

39572

1

T5

1

T8

12

T9

1

auto[0]

auto[0]

auto[0]

auto[1]

40648

1

T5

2

T8

10

T13

65

auto[0]

auto[0]

auto[1]

auto[0]

480958

1

T8

3

T13

223

T9

2

auto[0]

auto[0]

auto[1]

auto[1]

41716

1

T13

7

T21

3456

T30

44

auto[0]

auto[1]

auto[0]

auto[0]

101541

1

T2

7

T3

7

T4

3952

auto[0]

auto[1]

auto[0]

auto[1]

83067

1

T1

615

T3

16

T4

455

auto[0]

auto[1]

auto[1]

auto[0]

87738

1

T1

183

T2

37

T3

2

auto[0]

auto[1]

auto[1]

auto[1]

110502

1

T2

2

T4

2143

T6

2306

auto[1]

auto[0]

auto[0]

auto[0]

127238

1

T2

41

T3

19

T10

35

auto[1]

auto[0]

auto[0]

auto[1]

141700

1

T2

40

T3

42

T10

23

auto[1]

auto[0]

auto[1]

auto[0]

1965936

1

T2

38

T3

25

T10

20

auto[1]

auto[0]

auto[1]

auto[1]

160865

1

T2

8

T3

40

T10

6

auto[1]

auto[1]

auto[0]

auto[0]

364450

1

T2

10

T3

36

T4

9952

auto[1]

auto[1]

auto[0]

auto[1]

400794

1

T1

317

T2

6

T3

20

auto[1]

auto[1]

auto[1]

auto[0]

399309

1

T1

347

T2

6

T3

2

auto[1]

auto[1]

auto[1]

auto[1]

366012

1

T2

1

T3

15

T4

4669

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

166501

1

T2

41

T3

19

T5

1

auto[0]

auto[0]

auto[0]

auto[1]

182222

1

T2

40

T3

42

T5

2

auto[0]

auto[0]

auto[1]

auto[0]

2444909

1

T2

38

T3

25

T10

20

auto[0]

auto[0]

auto[1]

auto[1]

202397

1

T2

8

T3

40

T10

6

auto[0]

auto[1]

auto[0]

auto[0]

465691

1

T2

17

T3

43

T4

13904

auto[0]

auto[1]

auto[0]

auto[1]

483698

1

T1

932

T2

6

T3

36

auto[0]

auto[1]

auto[1]

auto[0]

484816

1

T1

530

T2

43

T3

4

auto[0]

auto[1]

auto[1]

auto[1]

474339

1

T2

3

T3

15

T4

6812

auto[1]

auto[0]

auto[0]

auto[0]

309

1

T47

1

T26

5

T51

107

auto[1]

auto[0]

auto[0]

auto[1]

126

1

T26

1

T45

1

T119

1

auto[1]

auto[0]

auto[1]

auto[0]

1985

1

T21

1209

T26

19

T49

2

auto[1]

auto[0]

auto[1]

auto[1]

184

1

T21

21

T26

8

T51

7

auto[1]

auto[1]

auto[0]

auto[0]

300

1

T26

1

T51

25

T45

1

auto[1]

auto[1]

auto[0]

auto[1]

163

1

T51

123

T45

1

T120

5

auto[1]

auto[1]

auto[1]

auto[0]

2231

1

T21

1665

T26

44

T51

71

auto[1]

auto[1]

auto[1]

auto[1]

2175

1

T26

1

T51

76

T40

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	127238	1			T2	41		T3	19		T10	35
fifo_depth[0]	auto[0]	auto[0]	auto[1]	141700	1			T2	40		T3	42		T10	23
fifo_depth[0]	auto[0]	auto[1]	auto[0]	1965936	1			T2	38		T3	25		T10	20
fifo_depth[0]	auto[0]	auto[1]	auto[1]	160865	1			T2	8		T3	40		T10	6
fifo_depth[0]	auto[1]	auto[0]	auto[0]	364450	1			T2	10		T3	36		T4	9952
fifo_depth[0]	auto[1]	auto[0]	auto[1]	400794	1			T1	317		T2	6		T3	20
fifo_depth[0]	auto[1]	auto[1]	auto[0]	399309	1			T1	347		T2	6		T3	2
fifo_depth[0]	auto[1]	auto[1]	auto[1]	366012	1			T2	1		T3	15		T4	4669
fifo_depth[1]	auto[0]	auto[0]	auto[0]	3310	1			T8	9		T30	9		T19	14
fifo_depth[1]	auto[0]	auto[0]	auto[1]	4140	1			T8	6		T13	32		T30	8
fifo_depth[1]	auto[0]	auto[1]	auto[0]	115646	1			T8	3		T13	102		T21	10
fifo_depth[1]	auto[0]	auto[1]	auto[1]	4091	1			T13	4		T21	55		T30	30
fifo_depth[1]	auto[1]	auto[0]	auto[0]	10371	1			T4	436		T6	102		T10	3
fifo_depth[1]	auto[1]	auto[0]	auto[1]	8951	1			T1	67		T3	1		T4	51
fifo_depth[1]	auto[1]	auto[1]	auto[0]	9061	1			T1	20		T2	3		T4	102
fifo_depth[1]	auto[1]	auto[1]	auto[1]	11277	1			T2	1		T4	239		T6	241
fifo_depth[2]	auto[0]	auto[0]	auto[0]	3206	1			T8	3		T30	6		T19	8
fifo_depth[2]	auto[0]	auto[0]	auto[1]	3802	1			T8	3		T13	15		T30	2
fifo_depth[2]	auto[0]	auto[1]	auto[0]	90127	1			T13	73		T21	8		T18	2417
fifo_depth[2]	auto[0]	auto[1]	auto[1]	3502	1			T13	2		T21	46		T30	12
fifo_depth[2]	auto[1]	auto[0]	auto[0]	10101	1			T2	1		T4	436		T6	93
fifo_depth[2]	auto[1]	auto[0]	auto[1]	8700	1			T1	67		T3	1		T4	38
fifo_depth[2]	auto[1]	auto[1]	auto[0]	8422	1			T1	23		T2	4		T4	100
fifo_depth[2]	auto[1]	auto[1]	auto[1]	11288	1			T2	1		T4	228		T6	267
fifo_depth[3]	auto[0]	auto[0]	auto[0]	2576	1			T30	1		T19	7		T84	25
fifo_depth[3]	auto[0]	auto[0]	auto[1]	3161	1			T13	13		T30	1		T84	22
fifo_depth[3]	auto[0]	auto[1]	auto[0]	67251	1			T13	34		T21	11		T18	1980
fifo_depth[3]	auto[0]	auto[1]	auto[1]	2912	1			T13	1		T21	49		T30	2
fifo_depth[3]	auto[1]	auto[0]	auto[0]	9251	1			T4	413		T6	88		T8	4
fifo_depth[3]	auto[1]	auto[0]	auto[1]	7884	1			T1	76		T3	2		T4	56
fifo_depth[3]	auto[1]	auto[1]	auto[0]	7653	1			T1	19		T2	4		T3	2
fifo_depth[3]	auto[1]	auto[1]	auto[1]	10686	1			T4	230		T6	260		T13	1
fifo_depth[4]	auto[0]	auto[0]	auto[0]	2756	1			T84	28		T121	2		T99	3
fifo_depth[4]	auto[0]	auto[0]	auto[1]	3236	1			T8	1		T13	5		T21	7
fifo_depth[4]	auto[0]	auto[1]	auto[0]	47752	1			T13	11		T21	15		T18	1388
fifo_depth[4]	auto[0]	auto[1]	auto[1]	2807	1			T21	40		T19	1		T122	2
fifo_depth[4]	auto[1]	auto[0]	auto[0]	9072	1			T2	2		T3	1		T4	412
fifo_depth[4]	auto[1]	auto[0]	auto[1]	7909	1			T1	70		T3	2		T4	56
fifo_depth[4]	auto[1]	auto[1]	auto[0]	7607	1			T1	19		T2	2		T4	100
fifo_depth[4]	auto[1]	auto[1]	auto[1]	10879	1			T4	227		T6	265		T7	222
fifo_depth[5]	auto[0]	auto[0]	auto[0]	2341	1			T84	25		T121	4		T99	2
fifo_depth[5]	auto[0]	auto[0]	auto[1]	2757	1			T21	6		T30	1		T84	15
fifo_depth[5]	auto[0]	auto[1]	auto[0]	37509	1			T13	3		T21	11		T18	1145
fifo_depth[5]	auto[0]	auto[1]	auto[1]	2566	1			T21	5		T121	35		T99	1
fifo_depth[5]	auto[1]	auto[0]	auto[0]	8862	1			T2	2		T4	412		T6	97
fifo_depth[5]	auto[1]	auto[0]	auto[1]	7428	1			T1	59		T4	47		T6	13
fifo_depth[5]	auto[1]	auto[1]	auto[0]	7247	1			T1	22		T2	6		T4	89
fifo_depth[5]	auto[1]	auto[1]	auto[1]	9929	1			T4	212		T6	231		T7	194
fifo_depth[6]	auto[0]	auto[0]	auto[0]	2620	1			T84	27		T121	3		T99	3
fifo_depth[6]	auto[0]	auto[0]	auto[1]	3042	1			T21	40		T84	11		T123	33
fifo_depth[6]	auto[0]	auto[1]	auto[0]	32248	1			T21	23		T18	906		T20	5
fifo_depth[6]	auto[0]	auto[1]	auto[1]	2698	1			T121	37		T26	38		T16	4
fifo_depth[6]	auto[1]	auto[0]	auto[0]	9235	1			T2	1		T3	1		T4	420
fifo_depth[6]	auto[1]	auto[0]	auto[1]	7711	1			T1	62		T3	3		T4	49
fifo_depth[6]	auto[1]	auto[1]	auto[0]	7300	1			T1	14		T2	3		T4	102
fifo_depth[6]	auto[1]	auto[1]	auto[1]	10349	1			T4	228		T6	239		T21	5
fifo_depth[7]	auto[0]	auto[0]	auto[0]	2180	1			T84	23		T121	4		T99	2
fifo_depth[7]	auto[0]	auto[0]	auto[1]	2468	1			T21	42		T84	10		T123	51
fifo_depth[7]	auto[0]	auto[1]	auto[0]	25281	1			T21	22		T18	719		T20	2
fifo_depth[7]	auto[0]	auto[1]	auto[1]	2288	1			T121	29		T26	42		T16	2
fifo_depth[7]	auto[1]	auto[0]	auto[0]	8246	1			T2	1		T3	4		T4	374
fifo_depth[7]	auto[1]	auto[0]	auto[1]	6878	1			T1	66		T3	1		T4	50
fifo_depth[7]	auto[1]	auto[1]	auto[0]	6604	1			T1	19		T2	5		T4	95
fifo_depth[7]	auto[1]	auto[1]	auto[1]	8969	1			T4	212		T6	232		T21	9