Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7463097	1			T1	1509		T2	226		T3	628
all_pins[1]	7463097	1			T1	1509		T2	226		T3	628
all_pins[2]	7463097	1			T1	1509		T2	226		T3	628

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	18720026	1			T1	4526		T2	602		T3	1754
values[0x1]	3669265	1			T1	1		T2	76		T3	130
transitions[0x0=>0x1]	3669181	1			T1	1		T2	76		T3	130
transitions[0x1=>0x0]	3669195	1			T1	1		T2	76		T3	130

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	7443390	1			T1	1508		T2	206		T3	600
all_pins[0]	values[0x1]	19707	1			T1	1		T2	20		T3	28
all_pins[0]	transitions[0x0=>0x1]	19658	1			T1	1		T2	20		T3	28
all_pins[0]	transitions[0x1=>0x0]	3649415	1			T2	56		T3	102		T4	15730
all_pins[1]	values[0x0]	7462989	1			T1	1509		T2	226		T3	628
all_pins[1]	values[0x1]	108	1			T19	2		T26	2		T51	4
all_pins[1]	transitions[0x0=>0x1]	88	1			T19	1		T26	2		T51	3
all_pins[1]	transitions[0x1=>0x0]	19687	1			T1	1		T2	20		T3	28
all_pins[2]	values[0x0]	3813647	1			T1	1509		T2	170		T3	526
all_pins[2]	values[0x1]	3649450	1			T2	56		T3	102		T4	15730
all_pins[2]	transitions[0x0=>0x1]	3649435	1			T2	56		T3	102		T4	15730
all_pins[2]	transitions[0x1=>0x0]	93	1			T19	2		T26	2		T51	4