Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 449 1 T19 11 T26 7 T51 21
all_values[1] 449 1 T19 11 T26 7 T51 21
all_values[2] 449 1 T19 11 T26 7 T51 21


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 706 1 T19 16 T26 11 T51 36
auto[1] 641 1 T19 17 T26 10 T51 27


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 508 1 T19 13 T26 10 T51 22
auto[1] 839 1 T19 20 T26 11 T51 41


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 797 1 T19 19 T26 17 T51 33
auto[1] 550 1 T19 14 T26 4 T51 30


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 92 1 T19 1 T26 2 T51 5
all_values[0] auto[0] auto[0] auto[1] 46 1 T26 2 T51 2 T45 1
all_values[0] auto[0] auto[1] auto[0] 74 1 T19 1 T26 1 T51 3
all_values[0] auto[0] auto[1] auto[1] 46 1 T19 3 T26 1 T51 1
all_values[0] auto[1] auto[0] auto[1] 96 1 T19 2 T51 7 T45 3
all_values[0] auto[1] auto[1] auto[1] 95 1 T19 4 T26 1 T51 3
all_values[1] auto[0] auto[0] auto[0] 83 1 T19 4 T26 2 T51 4
all_values[1] auto[0] auto[0] auto[1] 58 1 T19 1 T51 1 T45 1
all_values[1] auto[0] auto[1] auto[0] 72 1 T19 2 T26 3 T51 3
all_values[1] auto[0] auto[1] auto[1] 58 1 T19 1 T26 1 T51 4
all_values[1] auto[1] auto[0] auto[1] 95 1 T26 1 T51 5 T45 2
all_values[1] auto[1] auto[1] auto[1] 83 1 T19 3 T51 4 T45 2
all_values[2] auto[0] auto[0] auto[0] 90 1 T19 3 T26 1 T51 4
all_values[2] auto[0] auto[0] auto[1] 43 1 T19 1 T26 2 T51 1
all_values[2] auto[0] auto[1] auto[0] 97 1 T19 2 T26 1 T51 3
all_values[2] auto[0] auto[1] auto[1] 38 1 T26 1 T51 2 T111 3
all_values[2] auto[1] auto[0] auto[1] 103 1 T19 4 T26 1 T51 7
all_values[2] auto[1] auto[1] auto[1] 78 1 T19 1 T26 1 T51 4


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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