Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.48 95.51 92.26 100.00 63.16 90.61 99.49 71.33


Total test records in report: 645
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T534 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3222809323 May 26 01:02:52 PM PDT 24 May 26 01:02:54 PM PDT 24 12609150 ps
T57 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1729705944 May 26 01:02:43 PM PDT 24 May 26 01:02:46 PM PDT 24 40956350 ps
T535 /workspace/coverage/cover_reg_top/47.hmac_intr_test.3532413701 May 26 01:02:59 PM PDT 24 May 26 01:03:02 PM PDT 24 13116705 ps
T67 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3140194344 May 26 01:02:35 PM PDT 24 May 26 01:02:39 PM PDT 24 382469617 ps
T536 /workspace/coverage/cover_reg_top/49.hmac_intr_test.4113649346 May 26 01:02:58 PM PDT 24 May 26 01:03:00 PM PDT 24 47096220 ps
T59 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.691886878 May 26 01:02:45 PM PDT 24 May 26 01:02:51 PM PDT 24 610096601 ps
T537 /workspace/coverage/cover_reg_top/43.hmac_intr_test.681379554 May 26 01:02:54 PM PDT 24 May 26 01:02:57 PM PDT 24 32568043 ps
T60 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.4246603832 May 26 01:02:36 PM PDT 24 May 26 01:02:40 PM PDT 24 153656099 ps
T538 /workspace/coverage/cover_reg_top/26.hmac_intr_test.52126415 May 26 01:02:53 PM PDT 24 May 26 01:02:56 PM PDT 24 35573830 ps
T539 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2006830503 May 26 01:02:34 PM PDT 24 May 26 01:02:36 PM PDT 24 66079358 ps
T77 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3970062388 May 26 01:02:30 PM PDT 24 May 26 01:02:32 PM PDT 24 171666416 ps
T61 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1374587156 May 26 01:02:46 PM PDT 24 May 26 01:02:52 PM PDT 24 973825597 ps
T540 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2746871454 May 26 01:02:41 PM PDT 24 May 26 01:02:44 PM PDT 24 67883437 ps
T541 /workspace/coverage/cover_reg_top/30.hmac_intr_test.3896489963 May 26 01:02:52 PM PDT 24 May 26 01:02:55 PM PDT 24 12967004 ps
T78 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3702329212 May 26 01:02:45 PM PDT 24 May 26 01:02:49 PM PDT 24 61950558 ps
T79 /workspace/coverage/cover_reg_top/29.hmac_intr_test.3138445648 May 26 01:02:55 PM PDT 24 May 26 01:02:58 PM PDT 24 14376605 ps
T542 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3437797107 May 26 01:02:34 PM PDT 24 May 26 01:02:37 PM PDT 24 45411028 ps
T543 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2233052924 May 26 01:02:45 PM PDT 24 May 26 01:02:49 PM PDT 24 81954173 ps
T86 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.698217848 May 26 01:02:50 PM PDT 24 May 26 01:02:56 PM PDT 24 555119141 ps
T544 /workspace/coverage/cover_reg_top/22.hmac_intr_test.717845314 May 26 01:03:00 PM PDT 24 May 26 01:03:02 PM PDT 24 59509867 ps
T545 /workspace/coverage/cover_reg_top/31.hmac_intr_test.1984707879 May 26 01:02:56 PM PDT 24 May 26 01:02:58 PM PDT 24 12952760 ps
T546 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1910812642 May 26 01:02:44 PM PDT 24 May 26 01:02:47 PM PDT 24 27861856 ps
T88 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1674924634 May 26 01:02:31 PM PDT 24 May 26 01:02:37 PM PDT 24 204926731 ps
T547 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3651566628 May 26 01:02:56 PM PDT 24 May 26 01:02:58 PM PDT 24 37454969 ps
T548 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3720637174 May 26 01:02:44 PM PDT 24 May 26 01:02:47 PM PDT 24 62453316 ps
T549 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2810860131 May 26 01:02:33 PM PDT 24 May 26 01:02:35 PM PDT 24 30655051 ps
T550 /workspace/coverage/cover_reg_top/17.hmac_intr_test.1768763367 May 26 01:02:49 PM PDT 24 May 26 01:02:52 PM PDT 24 15893488 ps
T551 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2556465201 May 26 01:02:42 PM PDT 24 May 26 01:02:45 PM PDT 24 113031012 ps
T552 /workspace/coverage/cover_reg_top/1.hmac_intr_test.2390616376 May 26 01:02:34 PM PDT 24 May 26 01:02:36 PM PDT 24 59717461 ps
T62 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.4015295440 May 26 01:02:37 PM PDT 24 May 26 01:02:41 PM PDT 24 124150235 ps
T553 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3061437091 May 26 01:02:45 PM PDT 24 May 26 01:02:49 PM PDT 24 66195715 ps
T115 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2843272807 May 26 01:02:46 PM PDT 24 May 26 01:02:53 PM PDT 24 494399938 ps
T554 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.930534534 May 26 01:02:46 PM PDT 24 May 26 01:02:50 PM PDT 24 114568737 ps
T89 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1378568216 May 26 01:02:46 PM PDT 24 May 26 01:02:50 PM PDT 24 34052416 ps
T65 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2661446495 May 26 01:02:36 PM PDT 24 May 26 01:02:38 PM PDT 24 207163711 ps
T71 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2422909226 May 26 01:02:44 PM PDT 24 May 26 01:02:48 PM PDT 24 95543277 ps
T66 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2749823462 May 26 01:02:45 PM PDT 24 May 26 01:02:50 PM PDT 24 106484174 ps
T555 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1354512858 May 26 01:02:46 PM PDT 24 May 26 01:02:49 PM PDT 24 30291536 ps
T556 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2081782579 May 26 01:02:46 PM PDT 24 May 26 01:02:49 PM PDT 24 12530795 ps
T63 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1277945894 May 26 01:02:43 PM PDT 24 May 26 01:02:47 PM PDT 24 117512861 ps
T90 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1937274269 May 26 01:02:53 PM PDT 24 May 26 01:02:56 PM PDT 24 33192346 ps
T557 /workspace/coverage/cover_reg_top/16.hmac_intr_test.341953222 May 26 01:02:49 PM PDT 24 May 26 01:02:52 PM PDT 24 13887024 ps
T558 /workspace/coverage/cover_reg_top/34.hmac_intr_test.2713068191 May 26 01:03:00 PM PDT 24 May 26 01:03:02 PM PDT 24 16779124 ps
T64 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2984653739 May 26 01:02:44 PM PDT 24 May 26 01:02:48 PM PDT 24 91714524 ps
T116 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3019482360 May 26 01:02:47 PM PDT 24 May 26 01:02:54 PM PDT 24 226789924 ps
T559 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1766033956 May 26 01:02:52 PM PDT 24 May 26 01:02:54 PM PDT 24 26186352 ps
T68 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3675054269 May 26 01:02:45 PM PDT 24 May 26 01:02:49 PM PDT 24 85113037 ps
T560 /workspace/coverage/cover_reg_top/42.hmac_intr_test.51219445 May 26 01:02:59 PM PDT 24 May 26 01:03:01 PM PDT 24 29993215 ps
T561 /workspace/coverage/cover_reg_top/32.hmac_intr_test.789814919 May 26 01:02:58 PM PDT 24 May 26 01:03:00 PM PDT 24 18745009 ps
T562 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.896386492 May 26 01:02:45 PM PDT 24 May 26 01:02:49 PM PDT 24 81300550 ps
T112 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.929692738 May 26 01:02:44 PM PDT 24 May 26 01:02:48 PM PDT 24 99295990 ps
T563 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1092282153 May 26 01:02:55 PM PDT 24 May 26 01:02:58 PM PDT 24 18606079 ps
T564 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1074115514 May 26 01:02:43 PM PDT 24 May 26 01:02:44 PM PDT 24 117605951 ps
T565 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.960913543 May 26 01:02:43 PM PDT 24 May 26 01:02:47 PM PDT 24 445945023 ps
T566 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.761894741 May 26 01:02:44 PM PDT 24 May 26 01:02:49 PM PDT 24 52065497 ps
T567 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2975639142 May 26 01:02:36 PM PDT 24 May 26 01:02:40 PM PDT 24 102891362 ps
T568 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3364247727 May 26 01:02:47 PM PDT 24 May 26 01:02:51 PM PDT 24 175835523 ps
T569 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1755046143 May 26 01:02:33 PM PDT 24 May 26 01:02:35 PM PDT 24 21529120 ps
T570 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.4256178827 May 26 01:02:52 PM PDT 24 May 26 01:02:56 PM PDT 24 80038186 ps
T117 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1338290659 May 26 01:02:36 PM PDT 24 May 26 01:02:39 PM PDT 24 1735853227 ps
T571 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.267893100 May 26 01:02:34 PM PDT 24 May 26 01:02:38 PM PDT 24 88539141 ps
T572 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1001595647 May 26 01:02:44 PM PDT 24 May 26 01:02:48 PM PDT 24 467829182 ps
T573 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1888544384 May 26 01:02:46 PM PDT 24 May 26 01:02:51 PM PDT 24 136771887 ps
T118 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1732644298 May 26 01:02:47 PM PDT 24 May 26 01:02:53 PM PDT 24 1335290890 ps
T574 /workspace/coverage/cover_reg_top/27.hmac_intr_test.929545426 May 26 01:02:52 PM PDT 24 May 26 01:02:54 PM PDT 24 21530524 ps
T575 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1105230944 May 26 01:02:42 PM PDT 24 May 26 01:02:44 PM PDT 24 343512012 ps
T576 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3693132646 May 26 01:02:46 PM PDT 24 May 26 01:02:51 PM PDT 24 82372041 ps
T577 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1483561492 May 26 01:02:34 PM PDT 24 May 26 01:02:37 PM PDT 24 106021890 ps
T578 /workspace/coverage/cover_reg_top/18.hmac_intr_test.4102941374 May 26 01:02:46 PM PDT 24 May 26 01:02:50 PM PDT 24 13940857 ps
T579 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2324868494 May 26 01:02:46 PM PDT 24 May 26 01:02:51 PM PDT 24 113874491 ps
T580 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2298944644 May 26 01:02:42 PM PDT 24 May 26 01:02:45 PM PDT 24 34075212 ps
T581 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.554288026 May 26 01:02:47 PM PDT 24 May 26 01:02:51 PM PDT 24 83781238 ps
T582 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2381982570 May 26 01:02:53 PM PDT 24 May 26 01:02:57 PM PDT 24 87010852 ps
T583 /workspace/coverage/cover_reg_top/5.hmac_intr_test.1251219801 May 26 01:02:44 PM PDT 24 May 26 01:02:47 PM PDT 24 183739229 ps
T584 /workspace/coverage/cover_reg_top/38.hmac_intr_test.1537121955 May 26 01:03:00 PM PDT 24 May 26 01:03:04 PM PDT 24 18030541 ps
T585 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.291800012 May 26 01:02:43 PM PDT 24 May 26 01:02:57 PM PDT 24 707359653 ps
T586 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2584967904 May 26 01:02:46 PM PDT 24 May 26 01:02:52 PM PDT 24 110160804 ps
T587 /workspace/coverage/cover_reg_top/8.hmac_intr_test.121200845 May 26 01:02:43 PM PDT 24 May 26 01:02:46 PM PDT 24 62074230 ps
T588 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2132501997 May 26 01:02:44 PM PDT 24 May 26 01:02:48 PM PDT 24 87196433 ps
T589 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1627952077 May 26 01:02:34 PM PDT 24 May 26 01:02:40 PM PDT 24 1146721912 ps
T590 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2746894193 May 26 01:02:45 PM PDT 24 May 26 01:12:16 PM PDT 24 141643039163 ps
T591 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1808997984 May 26 01:02:54 PM PDT 24 May 26 01:02:56 PM PDT 24 13596181 ps
T592 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2412757777 May 26 01:02:43 PM PDT 24 May 26 01:02:47 PM PDT 24 74534173 ps
T91 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.617763503 May 26 01:02:32 PM PDT 24 May 26 01:02:41 PM PDT 24 810961787 ps
T593 /workspace/coverage/cover_reg_top/4.hmac_intr_test.3460624509 May 26 01:02:33 PM PDT 24 May 26 01:02:35 PM PDT 24 30715038 ps
T594 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3032462673 May 26 01:02:46 PM PDT 24 May 26 01:02:52 PM PDT 24 311613527 ps
T595 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4189916721 May 26 01:02:40 PM PDT 24 May 26 01:02:42 PM PDT 24 119486305 ps
T92 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2326550889 May 26 01:02:47 PM PDT 24 May 26 01:02:51 PM PDT 24 26196994 ps
T596 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1509054768 May 26 01:02:47 PM PDT 24 May 26 01:02:51 PM PDT 24 79187517 ps
T113 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.715494663 May 26 01:02:46 PM PDT 24 May 26 01:02:53 PM PDT 24 251409951 ps
T597 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3270022039 May 26 01:02:33 PM PDT 24 May 26 01:02:35 PM PDT 24 23590185 ps
T93 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3897769063 May 26 01:02:46 PM PDT 24 May 26 01:02:50 PM PDT 24 207745925 ps
T114 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2603462845 May 26 01:02:39 PM PDT 24 May 26 01:02:45 PM PDT 24 253651256 ps
T598 /workspace/coverage/cover_reg_top/19.hmac_intr_test.3042400020 May 26 01:02:55 PM PDT 24 May 26 01:02:58 PM PDT 24 19520756 ps
T599 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1862298911 May 26 01:02:34 PM PDT 24 May 26 01:02:36 PM PDT 24 23681057 ps
T600 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2920181671 May 26 01:02:43 PM PDT 24 May 26 01:02:44 PM PDT 24 47943375 ps
T94 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3415830473 May 26 01:02:44 PM PDT 24 May 26 01:02:47 PM PDT 24 53440838 ps
T601 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2359415182 May 26 01:02:51 PM PDT 24 May 26 01:02:56 PM PDT 24 58369746 ps
T602 /workspace/coverage/cover_reg_top/11.hmac_intr_test.2528310119 May 26 01:02:44 PM PDT 24 May 26 01:02:47 PM PDT 24 19681303 ps
T603 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3850177817 May 26 01:02:51 PM PDT 24 May 26 01:02:55 PM PDT 24 37043222 ps
T604 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1394157180 May 26 01:02:46 PM PDT 24 May 26 01:02:50 PM PDT 24 23265290 ps
T605 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1515564759 May 26 01:02:45 PM PDT 24 May 26 01:02:50 PM PDT 24 362729765 ps
T606 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2978695793 May 26 01:02:33 PM PDT 24 May 26 01:02:37 PM PDT 24 169638462 ps
T607 /workspace/coverage/cover_reg_top/48.hmac_intr_test.3617109162 May 26 01:02:58 PM PDT 24 May 26 01:03:00 PM PDT 24 37632567 ps
T608 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2852629301 May 26 01:02:34 PM PDT 24 May 26 01:02:36 PM PDT 24 65122892 ps
T609 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.601639113 May 26 01:02:54 PM PDT 24 May 26 01:03:01 PM PDT 24 357589470 ps
T95 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2921928395 May 26 01:02:34 PM PDT 24 May 26 01:02:40 PM PDT 24 442047219 ps
T96 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.4210285618 May 26 01:02:55 PM PDT 24 May 26 01:02:58 PM PDT 24 79002913 ps
T610 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2386332448 May 26 01:02:43 PM PDT 24 May 26 01:02:49 PM PDT 24 331278482 ps
T611 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.322858498 May 26 01:02:35 PM PDT 24 May 26 01:02:37 PM PDT 24 134100959 ps
T612 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3118163802 May 26 01:02:52 PM PDT 24 May 26 01:02:54 PM PDT 24 13260539 ps
T613 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.114645112 May 26 01:02:31 PM PDT 24 May 26 01:02:36 PM PDT 24 1110501929 ps
T614 /workspace/coverage/cover_reg_top/14.hmac_intr_test.48664127 May 26 01:02:46 PM PDT 24 May 26 01:02:50 PM PDT 24 10640962 ps
T97 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1891417155 May 26 01:02:34 PM PDT 24 May 26 01:02:50 PM PDT 24 315240074 ps
T615 /workspace/coverage/cover_reg_top/20.hmac_intr_test.17738275 May 26 01:02:54 PM PDT 24 May 26 01:02:56 PM PDT 24 79214665 ps
T616 /workspace/coverage/cover_reg_top/3.hmac_intr_test.3400967446 May 26 01:02:39 PM PDT 24 May 26 01:02:41 PM PDT 24 14475970 ps
T617 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2140663763 May 26 01:02:41 PM PDT 24 May 26 01:02:43 PM PDT 24 24803155 ps
T618 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3839419365 May 26 01:02:46 PM PDT 24 May 26 01:02:52 PM PDT 24 703786668 ps
T619 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.359411025 May 26 01:02:44 PM PDT 24 May 26 01:02:49 PM PDT 24 126628943 ps
T620 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1789584560 May 26 01:02:46 PM PDT 24 May 26 01:02:51 PM PDT 24 291626134 ps
T621 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.795757025 May 26 01:02:46 PM PDT 24 May 26 01:02:50 PM PDT 24 80270541 ps
T622 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3379686729 May 26 01:02:44 PM PDT 24 May 26 01:02:48 PM PDT 24 30781284 ps
T623 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.78667225 May 26 01:02:34 PM PDT 24 May 26 01:02:44 PM PDT 24 445678220 ps
T624 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1312645366 May 26 01:02:46 PM PDT 24 May 26 01:02:50 PM PDT 24 88251223 ps
T625 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2186601443 May 26 01:02:55 PM PDT 24 May 26 01:02:58 PM PDT 24 179235318 ps
T626 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1265785565 May 26 01:02:46 PM PDT 24 May 26 01:02:49 PM PDT 24 42561559 ps
T627 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3505056945 May 26 01:02:46 PM PDT 24 May 26 01:02:51 PM PDT 24 1484764000 ps
T628 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3358553484 May 26 01:02:44 PM PDT 24 May 26 01:02:51 PM PDT 24 807785306 ps
T629 /workspace/coverage/cover_reg_top/36.hmac_intr_test.4224162990 May 26 01:02:51 PM PDT 24 May 26 01:02:53 PM PDT 24 15614037 ps
T630 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2012045987 May 26 01:02:33 PM PDT 24 May 26 01:02:35 PM PDT 24 64721935 ps
T631 /workspace/coverage/cover_reg_top/28.hmac_intr_test.621440854 May 26 01:02:57 PM PDT 24 May 26 01:02:59 PM PDT 24 20065284 ps
T632 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.754077645 May 26 01:02:49 PM PDT 24 May 26 01:02:54 PM PDT 24 141494776 ps
T633 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3217668564 May 26 01:02:37 PM PDT 24 May 26 01:02:40 PM PDT 24 69669708 ps
T634 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.4005804882 May 26 01:02:32 PM PDT 24 May 26 01:02:35 PM PDT 24 489579821 ps
T635 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1673355381 May 26 01:02:45 PM PDT 24 May 26 01:02:49 PM PDT 24 33641921 ps
T636 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3512027440 May 26 01:02:47 PM PDT 24 May 26 01:02:52 PM PDT 24 396690619 ps
T637 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1125324174 May 26 01:02:36 PM PDT 24 May 26 01:02:37 PM PDT 24 20769207 ps
T638 /workspace/coverage/cover_reg_top/13.hmac_intr_test.1834533004 May 26 01:02:44 PM PDT 24 May 26 01:02:47 PM PDT 24 15226870 ps
T639 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2300479184 May 26 01:02:43 PM PDT 24 May 26 01:02:49 PM PDT 24 818791179 ps
T640 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.4136921790 May 26 01:02:51 PM PDT 24 May 26 01:02:56 PM PDT 24 418081505 ps
T641 /workspace/coverage/cover_reg_top/40.hmac_intr_test.2761393320 May 26 01:03:00 PM PDT 24 May 26 01:03:03 PM PDT 24 14992199 ps
T642 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.549412357 May 26 01:02:45 PM PDT 24 May 26 01:02:50 PM PDT 24 123026596 ps
T643 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1379652363 May 26 01:02:39 PM PDT 24 May 26 01:02:41 PM PDT 24 30867686 ps
T644 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.882549945 May 26 01:02:33 PM PDT 24 May 26 01:02:36 PM PDT 24 159102346 ps
T645 /workspace/coverage/cover_reg_top/7.hmac_intr_test.3498098960 May 26 01:02:44 PM PDT 24 May 26 01:02:47 PM PDT 24 14650982 ps

Test location /workspace/coverage/default/44.hmac_smoke.1298710910
Short name T2
Test name
Test status
Simulation time 497008145 ps
CPU time 4.7 seconds
Started May 26 02:22:43 PM PDT 24
Finished May 26 02:22:48 PM PDT 24
Peak memory 200132 kb
Host smart-0af6c51b-cc92-4fe7-bf51-c73a59331334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298710910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1298710910
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1448197903
Short name T19
Test name
Test status
Simulation time 26544850927 ps
CPU time 127.6 seconds
Started May 26 02:22:02 PM PDT 24
Finished May 26 02:24:11 PM PDT 24
Peak memory 232364 kb
Host smart-a64728d9-d2c7-4a5c-b851-902c8337447f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448197903 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1448197903
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.99185475
Short name T29
Test name
Test status
Simulation time 145247192 ps
CPU time 1.59 seconds
Started May 26 01:02:34 PM PDT 24
Finished May 26 01:02:37 PM PDT 24
Peak memory 199692 kb
Host smart-7331a43c-f3dc-4c7e-bfaf-d495a40bdbf4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99185475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.99185475
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/default/9.hmac_stress_all.2665963488
Short name T51
Test name
Test status
Simulation time 27013552359 ps
CPU time 1846.7 seconds
Started May 26 02:21:13 PM PDT 24
Finished May 26 02:52:02 PM PDT 24
Peak memory 685072 kb
Host smart-95c2de60-d40c-4b69-9a60-aeeaa2a44eaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665963488 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2665963488
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3730581981
Short name T33
Test name
Test status
Simulation time 317267535 ps
CPU time 0.98 seconds
Started May 26 02:21:07 PM PDT 24
Finished May 26 02:21:09 PM PDT 24
Peak memory 219296 kb
Host smart-331bf4b6-56ce-48c7-8d4c-4f1f199033dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730581981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3730581981
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.8172420
Short name T4
Test name
Test status
Simulation time 6987395286 ps
CPU time 879.6 seconds
Started May 26 02:22:58 PM PDT 24
Finished May 26 02:37:38 PM PDT 24
Peak memory 725676 kb
Host smart-4c760416-5339-48fd-8816-ada798b58003
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=8172420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.8172420
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1732644298
Short name T118
Test name
Test status
Simulation time 1335290890 ps
CPU time 3.86 seconds
Started May 26 01:02:47 PM PDT 24
Finished May 26 01:02:53 PM PDT 24
Peak memory 199636 kb
Host smart-3e238d4b-3d11-4cb8-8ffb-a85e4fbb4aa3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732644298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1732644298
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/36.hmac_stress_all.3701453124
Short name T26
Test name
Test status
Simulation time 93364617258 ps
CPU time 796.28 seconds
Started May 26 02:22:27 PM PDT 24
Finished May 26 02:35:44 PM PDT 24
Peak memory 721740 kb
Host smart-3b04dcdc-d4b7-47c7-b73c-9edd42856a4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701453124 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.3701453124
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.696112224
Short name T75
Test name
Test status
Simulation time 46040430 ps
CPU time 0.84 seconds
Started May 26 01:02:44 PM PDT 24
Finished May 26 01:02:47 PM PDT 24
Peak memory 198928 kb
Host smart-56428f2f-ca1a-4709-b29a-188485f215f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696112224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.696112224
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2746894193
Short name T590
Test name
Test status
Simulation time 141643039163 ps
CPU time 568.2 seconds
Started May 26 01:02:45 PM PDT 24
Finished May 26 01:12:16 PM PDT 24
Peak memory 216132 kb
Host smart-2ad622a6-b649-40e6-bb5f-059f4927b288
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746894193 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2746894193
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.3306601771
Short name T81
Test name
Test status
Simulation time 90977486514 ps
CPU time 574.1 seconds
Started May 26 02:20:52 PM PDT 24
Finished May 26 02:30:27 PM PDT 24
Peak memory 200116 kb
Host smart-b8e83f76-a6be-4762-8b20-d6d8148616be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306601771 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.3306601771
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_alert_test.311704695
Short name T22
Test name
Test status
Simulation time 42692590 ps
CPU time 0.6 seconds
Started May 26 02:23:00 PM PDT 24
Finished May 26 02:23:01 PM PDT 24
Peak memory 196016 kb
Host smart-4b425c59-a633-4432-b958-aae7346c0580
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311704695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.311704695
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2921928395
Short name T95
Test name
Test status
Simulation time 442047219 ps
CPU time 5.26 seconds
Started May 26 01:02:34 PM PDT 24
Finished May 26 01:02:40 PM PDT 24
Peak memory 199600 kb
Host smart-9df1a632-3592-411d-b894-3f729869675c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921928395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2921928395
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3358553484
Short name T628
Test name
Test status
Simulation time 807785306 ps
CPU time 4.45 seconds
Started May 26 01:02:44 PM PDT 24
Finished May 26 01:02:51 PM PDT 24
Peak memory 199760 kb
Host smart-b1b5d721-36e0-4c57-a1f2-d3c99feac1fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358553484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3358553484
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.74155593
Short name T104
Test name
Test status
Simulation time 496188799 ps
CPU time 27.9 seconds
Started May 26 02:20:53 PM PDT 24
Finished May 26 02:21:22 PM PDT 24
Peak memory 200092 kb
Host smart-afdc2fb8-4341-49b2-b7ef-284ab106813d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74155593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.74155593
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2954328422
Short name T100
Test name
Test status
Simulation time 19390695475 ps
CPU time 91.51 seconds
Started May 26 02:21:53 PM PDT 24
Finished May 26 02:23:26 PM PDT 24
Peak memory 200136 kb
Host smart-e4d948f2-3ecc-452f-91b0-eeafb6a76044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954328422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2954328422
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.3484624548
Short name T107
Test name
Test status
Simulation time 1695353972 ps
CPU time 396 seconds
Started May 26 02:22:33 PM PDT 24
Finished May 26 02:29:11 PM PDT 24
Peak memory 662764 kb
Host smart-1aef2c63-e208-4dc9-a38e-da194677c961
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3484624548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.3484624548
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2324868494
Short name T579
Test name
Test status
Simulation time 113874491 ps
CPU time 2.5 seconds
Started May 26 01:02:46 PM PDT 24
Finished May 26 01:02:51 PM PDT 24
Peak memory 199636 kb
Host smart-308b4691-3597-431b-a07f-73c97413bbe7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324868494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2324868494
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3019482360
Short name T116
Test name
Test status
Simulation time 226789924 ps
CPU time 4.23 seconds
Started May 26 01:02:47 PM PDT 24
Finished May 26 01:02:54 PM PDT 24
Peak memory 199648 kb
Host smart-aa09e6f9-c24b-4509-acba-943297e96993
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019482360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3019482360
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1416677803
Short name T110
Test name
Test status
Simulation time 1842529593 ps
CPU time 215.29 seconds
Started May 26 02:21:47 PM PDT 24
Finished May 26 02:25:23 PM PDT 24
Peak memory 605780 kb
Host smart-4c779d79-f6fb-4f91-8054-005660af6942
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1416677803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1416677803
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1245088233
Short name T103
Test name
Test status
Simulation time 1848648581 ps
CPU time 35.22 seconds
Started May 26 02:23:06 PM PDT 24
Finished May 26 02:23:42 PM PDT 24
Peak memory 200184 kb
Host smart-47f45c0e-9a99-460f-b9b6-f6abca107caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245088233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1245088233
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.78667225
Short name T623
Test name
Test status
Simulation time 445678220 ps
CPU time 9.05 seconds
Started May 26 01:02:34 PM PDT 24
Finished May 26 01:02:44 PM PDT 24
Peak memory 199620 kb
Host smart-7a5385b3-a17a-47d7-a470-7902c83ccb7b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78667225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.78667225
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3437797107
Short name T542
Test name
Test status
Simulation time 45411028 ps
CPU time 1.02 seconds
Started May 26 01:02:34 PM PDT 24
Finished May 26 01:02:37 PM PDT 24
Peak memory 199448 kb
Host smart-d7d1c255-0a99-4607-b0dd-6b3ce477832e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437797107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3437797107
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.267893100
Short name T571
Test name
Test status
Simulation time 88539141 ps
CPU time 1.82 seconds
Started May 26 01:02:34 PM PDT 24
Finished May 26 01:02:38 PM PDT 24
Peak memory 199752 kb
Host smart-376de55a-db6a-433e-82e1-a6f456425219
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267893100 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.267893100
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.322858498
Short name T611
Test name
Test status
Simulation time 134100959 ps
CPU time 0.94 seconds
Started May 26 01:02:35 PM PDT 24
Finished May 26 01:02:37 PM PDT 24
Peak memory 198956 kb
Host smart-88e1541b-025e-4f71-a9dd-8bb3aa8b07a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322858498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.322858498
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1755046143
Short name T569
Test name
Test status
Simulation time 21529120 ps
CPU time 0.59 seconds
Started May 26 01:02:33 PM PDT 24
Finished May 26 01:02:35 PM PDT 24
Peak memory 194632 kb
Host smart-7cf65a7a-e86c-4615-bd15-b408f6a1ba18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755046143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1755046143
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2978695793
Short name T606
Test name
Test status
Simulation time 169638462 ps
CPU time 2.26 seconds
Started May 26 01:02:33 PM PDT 24
Finished May 26 01:02:37 PM PDT 24
Peak memory 199712 kb
Host smart-aa25f004-2cfc-4791-a73e-e3d7e2d14fa1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978695793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2978695793
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1627952077
Short name T589
Test name
Test status
Simulation time 1146721912 ps
CPU time 4.49 seconds
Started May 26 01:02:34 PM PDT 24
Finished May 26 01:02:40 PM PDT 24
Peak memory 199728 kb
Host smart-f67e4fd5-cb8a-4193-8fc1-2c249242b317
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627952077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1627952077
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2629264524
Short name T87
Test name
Test status
Simulation time 165806025 ps
CPU time 8.1 seconds
Started May 26 01:02:39 PM PDT 24
Finished May 26 01:02:48 PM PDT 24
Peak memory 199660 kb
Host smart-f3d92fe4-f998-4e37-864a-aa3b878f7f4c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629264524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.2629264524
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3855844374
Short name T532
Test name
Test status
Simulation time 2705439093 ps
CPU time 10.92 seconds
Started May 26 01:02:33 PM PDT 24
Finished May 26 01:02:45 PM PDT 24
Peak memory 199144 kb
Host smart-d07f69e9-e8a9-4303-b4ef-1e406d8d12a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855844374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3855844374
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1125324174
Short name T637
Test name
Test status
Simulation time 20769207 ps
CPU time 0.75 seconds
Started May 26 01:02:36 PM PDT 24
Finished May 26 01:02:37 PM PDT 24
Peak memory 197416 kb
Host smart-078f7c2d-412e-41d3-8108-dadccf1856dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125324174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1125324174
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3140194344
Short name T67
Test name
Test status
Simulation time 382469617 ps
CPU time 3.35 seconds
Started May 26 01:02:35 PM PDT 24
Finished May 26 01:02:39 PM PDT 24
Peak memory 216100 kb
Host smart-d0dc55f3-f27b-4d73-afb1-b08cae7f7399
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140194344 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.3140194344
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2006830503
Short name T539
Test name
Test status
Simulation time 66079358 ps
CPU time 0.92 seconds
Started May 26 01:02:34 PM PDT 24
Finished May 26 01:02:36 PM PDT 24
Peak memory 199452 kb
Host smart-6d182ce0-0baa-464d-8642-eec243c38aeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006830503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2006830503
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2390616376
Short name T552
Test name
Test status
Simulation time 59717461 ps
CPU time 0.63 seconds
Started May 26 01:02:34 PM PDT 24
Finished May 26 01:02:36 PM PDT 24
Peak memory 194784 kb
Host smart-e4c43014-85ec-4866-8527-c91db1dbb73c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390616376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2390616376
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3217668564
Short name T633
Test name
Test status
Simulation time 69669708 ps
CPU time 1.72 seconds
Started May 26 01:02:37 PM PDT 24
Finished May 26 01:02:40 PM PDT 24
Peak memory 199488 kb
Host smart-f33f07ff-4fed-4076-9bdd-8285476fbf6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217668564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.3217668564
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.114645112
Short name T613
Test name
Test status
Simulation time 1110501929 ps
CPU time 3.4 seconds
Started May 26 01:02:31 PM PDT 24
Finished May 26 01:02:36 PM PDT 24
Peak memory 199676 kb
Host smart-8e6825f7-7da3-47f2-bbcc-cc3836b05c0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114645112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.114645112
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.882549945
Short name T644
Test name
Test status
Simulation time 159102346 ps
CPU time 3.18 seconds
Started May 26 01:02:33 PM PDT 24
Finished May 26 01:02:36 PM PDT 24
Peak memory 199600 kb
Host smart-5c78c612-db2b-441e-8651-4a1f6b978087
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882549945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.882549945
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.359411025
Short name T619
Test name
Test status
Simulation time 126628943 ps
CPU time 1.78 seconds
Started May 26 01:02:44 PM PDT 24
Finished May 26 01:02:49 PM PDT 24
Peak memory 199640 kb
Host smart-3bcb774b-615f-4cae-abf5-cdf09679b682
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359411025 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.359411025
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1394157180
Short name T604
Test name
Test status
Simulation time 23265290 ps
CPU time 0.85 seconds
Started May 26 01:02:46 PM PDT 24
Finished May 26 01:02:50 PM PDT 24
Peak memory 199256 kb
Host smart-d10772e9-c720-4dae-bab0-aefdbd76b7bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394157180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1394157180
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1074115514
Short name T564
Test name
Test status
Simulation time 117605951 ps
CPU time 0.6 seconds
Started May 26 01:02:43 PM PDT 24
Finished May 26 01:02:44 PM PDT 24
Peak memory 194616 kb
Host smart-39fe53ee-195c-439a-affd-06d887e99139
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074115514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1074115514
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1105230944
Short name T575
Test name
Test status
Simulation time 343512012 ps
CPU time 1.08 seconds
Started May 26 01:02:42 PM PDT 24
Finished May 26 01:02:44 PM PDT 24
Peak memory 197940 kb
Host smart-bfda03ee-733d-42c1-9eef-ba110fc518ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105230944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1105230944
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2300479184
Short name T639
Test name
Test status
Simulation time 818791179 ps
CPU time 4.16 seconds
Started May 26 01:02:43 PM PDT 24
Finished May 26 01:02:49 PM PDT 24
Peak memory 199648 kb
Host smart-b76d01c2-eb36-41a0-a8ca-3436696a32aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300479184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2300479184
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.591447101
Short name T58
Test name
Test status
Simulation time 160141792 ps
CPU time 2.14 seconds
Started May 26 01:02:46 PM PDT 24
Finished May 26 01:02:51 PM PDT 24
Peak memory 199736 kb
Host smart-8a053cca-10af-44b7-80d1-cab9a6287525
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591447101 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.591447101
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2140663763
Short name T617
Test name
Test status
Simulation time 24803155 ps
CPU time 0.85 seconds
Started May 26 01:02:41 PM PDT 24
Finished May 26 01:02:43 PM PDT 24
Peak memory 199480 kb
Host smart-ce875bc0-9225-4461-8320-965e4bd80c05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140663763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2140663763
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2528310119
Short name T602
Test name
Test status
Simulation time 19681303 ps
CPU time 0.64 seconds
Started May 26 01:02:44 PM PDT 24
Finished May 26 01:02:47 PM PDT 24
Peak memory 194392 kb
Host smart-81363e17-cbbc-406f-a88b-7d967c9dc9c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528310119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2528310119
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2746871454
Short name T540
Test name
Test status
Simulation time 67883437 ps
CPU time 1.62 seconds
Started May 26 01:02:41 PM PDT 24
Finished May 26 01:02:44 PM PDT 24
Peak memory 199928 kb
Host smart-ea0cf2cc-41c8-42e8-8e0b-0a3e7009e646
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746871454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2746871454
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1312645366
Short name T624
Test name
Test status
Simulation time 88251223 ps
CPU time 1.31 seconds
Started May 26 01:02:46 PM PDT 24
Finished May 26 01:02:50 PM PDT 24
Peak memory 199572 kb
Host smart-c6f88093-5aee-4e47-84ab-06105b8e73ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312645366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1312645366
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1374587156
Short name T61
Test name
Test status
Simulation time 973825597 ps
CPU time 3 seconds
Started May 26 01:02:46 PM PDT 24
Finished May 26 01:02:52 PM PDT 24
Peak memory 199684 kb
Host smart-9f6dae36-1024-47c5-9dbd-09d80996f3d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374587156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1374587156
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1888544384
Short name T573
Test name
Test status
Simulation time 136771887 ps
CPU time 1.22 seconds
Started May 26 01:02:46 PM PDT 24
Finished May 26 01:02:51 PM PDT 24
Peak memory 199536 kb
Host smart-e11affc3-2d78-473d-baf6-c9a43a226534
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888544384 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1888544384
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3061437091
Short name T553
Test name
Test status
Simulation time 66195715 ps
CPU time 0.7 seconds
Started May 26 01:02:45 PM PDT 24
Finished May 26 01:02:49 PM PDT 24
Peak memory 197672 kb
Host smart-8b744b2b-4fc3-45c2-9c28-a968eb0fc54c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061437091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3061437091
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1910812642
Short name T546
Test name
Test status
Simulation time 27861856 ps
CPU time 0.6 seconds
Started May 26 01:02:44 PM PDT 24
Finished May 26 01:02:47 PM PDT 24
Peak memory 194544 kb
Host smart-7596ea43-155f-4422-b301-d26b43f8ea86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910812642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1910812642
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1001595647
Short name T572
Test name
Test status
Simulation time 467829182 ps
CPU time 1.7 seconds
Started May 26 01:02:44 PM PDT 24
Finished May 26 01:02:48 PM PDT 24
Peak memory 199496 kb
Host smart-9a9835df-b866-49cd-b41b-404f994e3721
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001595647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1001595647
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.896386492
Short name T562
Test name
Test status
Simulation time 81300550 ps
CPU time 1.98 seconds
Started May 26 01:02:45 PM PDT 24
Finished May 26 01:02:49 PM PDT 24
Peak memory 199652 kb
Host smart-0eafd190-272b-4caa-a234-b360c567c277
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896386492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.896386492
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1673355381
Short name T635
Test name
Test status
Simulation time 33641921 ps
CPU time 1.98 seconds
Started May 26 01:02:45 PM PDT 24
Finished May 26 01:02:49 PM PDT 24
Peak memory 199816 kb
Host smart-fa632df7-001f-4f16-8d4f-e6aeb13db9b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673355381 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1673355381
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.1834533004
Short name T638
Test name
Test status
Simulation time 15226870 ps
CPU time 0.57 seconds
Started May 26 01:02:44 PM PDT 24
Finished May 26 01:02:47 PM PDT 24
Peak memory 194368 kb
Host smart-060a5428-c5c5-402a-8a7a-eed471e8f24a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834533004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1834533004
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2233052924
Short name T543
Test name
Test status
Simulation time 81954173 ps
CPU time 1.18 seconds
Started May 26 01:02:45 PM PDT 24
Finished May 26 01:02:49 PM PDT 24
Peak memory 197336 kb
Host smart-e2c33e06-8dc2-44d3-a6f5-89c727e5db73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233052924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2233052924
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1158874625
Short name T56
Test name
Test status
Simulation time 100073580 ps
CPU time 2.71 seconds
Started May 26 01:02:45 PM PDT 24
Finished May 26 01:02:50 PM PDT 24
Peak memory 198884 kb
Host smart-5d308273-aa47-42ca-a070-933321e2c23c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158874625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1158874625
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2132501997
Short name T588
Test name
Test status
Simulation time 87196433 ps
CPU time 1.86 seconds
Started May 26 01:02:44 PM PDT 24
Finished May 26 01:02:48 PM PDT 24
Peak memory 199684 kb
Host smart-e0350630-dc47-4248-bfb3-13608093bf96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132501997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2132501997
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2584967904
Short name T586
Test name
Test status
Simulation time 110160804 ps
CPU time 3.66 seconds
Started May 26 01:02:46 PM PDT 24
Finished May 26 01:02:52 PM PDT 24
Peak memory 215244 kb
Host smart-6e74e99a-d38a-43f3-be8d-ee12141a3d69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584967904 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2584967904
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2993808818
Short name T70
Test name
Test status
Simulation time 35175212 ps
CPU time 0.99 seconds
Started May 26 01:02:47 PM PDT 24
Finished May 26 01:02:51 PM PDT 24
Peak memory 199248 kb
Host smart-8ea62cd8-94f2-48be-bde5-7cb52b6fe048
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993808818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2993808818
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.48664127
Short name T614
Test name
Test status
Simulation time 10640962 ps
CPU time 0.6 seconds
Started May 26 01:02:46 PM PDT 24
Finished May 26 01:02:50 PM PDT 24
Peak memory 194524 kb
Host smart-02ea5af6-a899-4228-89c9-f9dd4c31b3fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48664127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.48664127
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1509054768
Short name T596
Test name
Test status
Simulation time 79187517 ps
CPU time 1.12 seconds
Started May 26 01:02:47 PM PDT 24
Finished May 26 01:02:51 PM PDT 24
Peak memory 199476 kb
Host smart-545323fb-ab30-4e7c-9de2-499dfdd1f74f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509054768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1509054768
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1729705944
Short name T57
Test name
Test status
Simulation time 40956350 ps
CPU time 1.95 seconds
Started May 26 01:02:43 PM PDT 24
Finished May 26 01:02:46 PM PDT 24
Peak memory 199608 kb
Host smart-f9494978-82c3-41a6-ab3a-ad2c010cd6c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729705944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1729705944
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.715494663
Short name T113
Test name
Test status
Simulation time 251409951 ps
CPU time 4.29 seconds
Started May 26 01:02:46 PM PDT 24
Finished May 26 01:02:53 PM PDT 24
Peak memory 199408 kb
Host smart-a6fd3696-fe2f-43e7-8ccb-ef2956d546e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715494663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.715494663
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.549412357
Short name T642
Test name
Test status
Simulation time 123026596 ps
CPU time 1.82 seconds
Started May 26 01:02:45 PM PDT 24
Finished May 26 01:02:50 PM PDT 24
Peak memory 199712 kb
Host smart-b945b40b-ecd0-49dd-a922-6d06bc79d925
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549412357 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.549412357
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1378568216
Short name T89
Test name
Test status
Simulation time 34052416 ps
CPU time 0.91 seconds
Started May 26 01:02:46 PM PDT 24
Finished May 26 01:02:50 PM PDT 24
Peak memory 199552 kb
Host smart-28e3b4bc-49f9-43d7-a0c0-1c3973334521
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378568216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1378568216
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2081782579
Short name T556
Test name
Test status
Simulation time 12530795 ps
CPU time 0.6 seconds
Started May 26 01:02:46 PM PDT 24
Finished May 26 01:02:49 PM PDT 24
Peak memory 194428 kb
Host smart-45182ecf-fef4-4335-96c2-cb7a06c989bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081782579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2081782579
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.618708419
Short name T69
Test name
Test status
Simulation time 56515705 ps
CPU time 1.61 seconds
Started May 26 01:02:46 PM PDT 24
Finished May 26 01:02:51 PM PDT 24
Peak memory 199784 kb
Host smart-719f8604-fae6-47c7-9e6f-4e3afb2e3418
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618708419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr
_outstanding.618708419
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1789584560
Short name T620
Test name
Test status
Simulation time 291626134 ps
CPU time 1.71 seconds
Started May 26 01:02:46 PM PDT 24
Finished May 26 01:02:51 PM PDT 24
Peak memory 199620 kb
Host smart-704bbd3f-1a9f-4465-83e0-baf664fbb61b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789584560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1789584560
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3505056945
Short name T627
Test name
Test status
Simulation time 1484764000 ps
CPU time 1.79 seconds
Started May 26 01:02:46 PM PDT 24
Finished May 26 01:02:51 PM PDT 24
Peak memory 199772 kb
Host smart-caf10154-4001-4bc9-afff-095aa26009de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505056945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3505056945
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3850177817
Short name T603
Test name
Test status
Simulation time 37043222 ps
CPU time 2.41 seconds
Started May 26 01:02:51 PM PDT 24
Finished May 26 01:02:55 PM PDT 24
Peak memory 199796 kb
Host smart-7f082dd2-e2bd-4cd9-a178-cec745ecdc68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850177817 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3850177817
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2326550889
Short name T92
Test name
Test status
Simulation time 26196994 ps
CPU time 0.86 seconds
Started May 26 01:02:47 PM PDT 24
Finished May 26 01:02:51 PM PDT 24
Peak memory 199140 kb
Host smart-43c5b686-c155-4ec6-a0d8-8446ce952001
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326550889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2326550889
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.341953222
Short name T557
Test name
Test status
Simulation time 13887024 ps
CPU time 0.63 seconds
Started May 26 01:02:49 PM PDT 24
Finished May 26 01:02:52 PM PDT 24
Peak memory 194456 kb
Host smart-026c6189-c1f2-4739-90b0-86da5dcafd03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341953222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.341953222
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3512027440
Short name T636
Test name
Test status
Simulation time 396690619 ps
CPU time 1.9 seconds
Started May 26 01:02:47 PM PDT 24
Finished May 26 01:02:52 PM PDT 24
Peak memory 198840 kb
Host smart-0e7810a1-c410-4b77-894c-5f7378fecc96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512027440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3512027440
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3897769063
Short name T93
Test name
Test status
Simulation time 207745925 ps
CPU time 0.86 seconds
Started May 26 01:02:46 PM PDT 24
Finished May 26 01:02:50 PM PDT 24
Peak memory 199312 kb
Host smart-b8779e1a-e081-485c-aee9-53aa9180db62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897769063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3897769063
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1768763367
Short name T550
Test name
Test status
Simulation time 15893488 ps
CPU time 0.63 seconds
Started May 26 01:02:49 PM PDT 24
Finished May 26 01:02:52 PM PDT 24
Peak memory 194508 kb
Host smart-1e49a439-ec4f-46ba-be14-f783b23a38d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768763367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1768763367
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.554288026
Short name T581
Test name
Test status
Simulation time 83781238 ps
CPU time 1.09 seconds
Started May 26 01:02:47 PM PDT 24
Finished May 26 01:02:51 PM PDT 24
Peak memory 198060 kb
Host smart-d08aa487-5632-47c3-a9a4-24dd36a7f83a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554288026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr
_outstanding.554288026
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.4136921790
Short name T640
Test name
Test status
Simulation time 418081505 ps
CPU time 3.82 seconds
Started May 26 01:02:51 PM PDT 24
Finished May 26 01:02:56 PM PDT 24
Peak memory 199752 kb
Host smart-9ad5befc-d1d8-4fa7-b1ea-b76780ed85d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136921790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.4136921790
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.698217848
Short name T86
Test name
Test status
Simulation time 555119141 ps
CPU time 4.36 seconds
Started May 26 01:02:50 PM PDT 24
Finished May 26 01:02:56 PM PDT 24
Peak memory 199824 kb
Host smart-fe80e449-9624-4f5b-9879-29452a8688eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698217848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.698217848
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2359415182
Short name T601
Test name
Test status
Simulation time 58369746 ps
CPU time 3.44 seconds
Started May 26 01:02:51 PM PDT 24
Finished May 26 01:02:56 PM PDT 24
Peak memory 207956 kb
Host smart-13d32af7-0671-4bd5-b230-da4ceda174b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359415182 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2359415182
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.4210285618
Short name T96
Test name
Test status
Simulation time 79002913 ps
CPU time 0.82 seconds
Started May 26 01:02:55 PM PDT 24
Finished May 26 01:02:58 PM PDT 24
Peak memory 199448 kb
Host smart-a5194934-9340-4f1d-b9e5-15fa3de1304f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210285618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.4210285618
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.4102941374
Short name T578
Test name
Test status
Simulation time 13940857 ps
CPU time 0.59 seconds
Started May 26 01:02:46 PM PDT 24
Finished May 26 01:02:50 PM PDT 24
Peak memory 194596 kb
Host smart-a368a46a-d82f-4b56-b449-ac53f11c7b3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102941374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.4102941374
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2021170011
Short name T531
Test name
Test status
Simulation time 110971895 ps
CPU time 1.51 seconds
Started May 26 01:02:53 PM PDT 24
Finished May 26 01:02:56 PM PDT 24
Peak memory 199764 kb
Host smart-950dbd97-54a7-434a-a405-0e3f7d5d0b80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021170011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.2021170011
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.754077645
Short name T632
Test name
Test status
Simulation time 141494776 ps
CPU time 2.68 seconds
Started May 26 01:02:49 PM PDT 24
Finished May 26 01:02:54 PM PDT 24
Peak memory 199720 kb
Host smart-364b5f27-38b0-47bf-90b1-8a333b2496eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754077645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.754077645
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3839419365
Short name T618
Test name
Test status
Simulation time 703786668 ps
CPU time 3.16 seconds
Started May 26 01:02:46 PM PDT 24
Finished May 26 01:02:52 PM PDT 24
Peak memory 199788 kb
Host smart-920b9b0c-f9bf-4814-9343-2f8148ce31c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839419365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3839419365
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.4256178827
Short name T570
Test name
Test status
Simulation time 80038186 ps
CPU time 1.98 seconds
Started May 26 01:02:52 PM PDT 24
Finished May 26 01:02:56 PM PDT 24
Peak memory 199720 kb
Host smart-8318dfb2-a2b1-437b-b95e-686c786b895c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256178827 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.4256178827
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1937274269
Short name T90
Test name
Test status
Simulation time 33192346 ps
CPU time 0.99 seconds
Started May 26 01:02:53 PM PDT 24
Finished May 26 01:02:56 PM PDT 24
Peak memory 199444 kb
Host smart-697c10bd-f4a0-4963-a7be-78084009a779
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937274269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1937274269
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.3042400020
Short name T598
Test name
Test status
Simulation time 19520756 ps
CPU time 0.63 seconds
Started May 26 01:02:55 PM PDT 24
Finished May 26 01:02:58 PM PDT 24
Peak memory 194540 kb
Host smart-4aa5d950-fde6-4cad-9fee-fe40e1cde9d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042400020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3042400020
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2443599168
Short name T526
Test name
Test status
Simulation time 43432251 ps
CPU time 2.06 seconds
Started May 26 01:02:52 PM PDT 24
Finished May 26 01:02:55 PM PDT 24
Peak memory 199676 kb
Host smart-359648f8-3f7b-405b-87d4-dc640f8ff150
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443599168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.2443599168
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2381982570
Short name T582
Test name
Test status
Simulation time 87010852 ps
CPU time 2.08 seconds
Started May 26 01:02:53 PM PDT 24
Finished May 26 01:02:57 PM PDT 24
Peak memory 199740 kb
Host smart-f6e859d0-82aa-44da-af06-49e178bae3a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381982570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2381982570
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.601639113
Short name T609
Test name
Test status
Simulation time 357589470 ps
CPU time 4.35 seconds
Started May 26 01:02:54 PM PDT 24
Finished May 26 01:03:01 PM PDT 24
Peak memory 199728 kb
Host smart-d18025b1-8b87-4d7f-b939-70bdcb26a36d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601639113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.601639113
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.617763503
Short name T91
Test name
Test status
Simulation time 810961787 ps
CPU time 8.21 seconds
Started May 26 01:02:32 PM PDT 24
Finished May 26 01:02:41 PM PDT 24
Peak memory 199688 kb
Host smart-8efc533e-d173-4b24-83b9-98740d9f3afc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617763503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.617763503
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1891417155
Short name T97
Test name
Test status
Simulation time 315240074 ps
CPU time 14.51 seconds
Started May 26 01:02:34 PM PDT 24
Finished May 26 01:02:50 PM PDT 24
Peak memory 198684 kb
Host smart-8734ae73-4df0-41ea-8525-62cd61b778c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891417155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.1891417155
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2852629301
Short name T608
Test name
Test status
Simulation time 65122892 ps
CPU time 0.75 seconds
Started May 26 01:02:34 PM PDT 24
Finished May 26 01:02:36 PM PDT 24
Peak memory 197752 kb
Host smart-d32560a6-ded8-43d9-ad6d-65a861098c5e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852629301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2852629301
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2975639142
Short name T567
Test name
Test status
Simulation time 102891362 ps
CPU time 2.51 seconds
Started May 26 01:02:36 PM PDT 24
Finished May 26 01:02:40 PM PDT 24
Peak memory 199740 kb
Host smart-3e161a57-7a7d-45f2-babd-69bc04e83c49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975639142 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2975639142
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3970062388
Short name T77
Test name
Test status
Simulation time 171666416 ps
CPU time 0.68 seconds
Started May 26 01:02:30 PM PDT 24
Finished May 26 01:02:32 PM PDT 24
Peak memory 197804 kb
Host smart-292537d9-d859-4faa-948d-7fbbfbe06379
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970062388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.3970062388
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2012045987
Short name T630
Test name
Test status
Simulation time 64721935 ps
CPU time 0.59 seconds
Started May 26 01:02:33 PM PDT 24
Finished May 26 01:02:35 PM PDT 24
Peak memory 194448 kb
Host smart-2256bc72-b7a5-4eed-95af-0a144f36b3d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012045987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2012045987
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1483561492
Short name T577
Test name
Test status
Simulation time 106021890 ps
CPU time 1.13 seconds
Started May 26 01:02:34 PM PDT 24
Finished May 26 01:02:37 PM PDT 24
Peak memory 199364 kb
Host smart-d957818b-a27d-44b4-9643-bf380a157172
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483561492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1483561492
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.4005804882
Short name T634
Test name
Test status
Simulation time 489579821 ps
CPU time 2.37 seconds
Started May 26 01:02:32 PM PDT 24
Finished May 26 01:02:35 PM PDT 24
Peak memory 199652 kb
Host smart-aa07fa4d-76dc-43ad-a8d5-f686cc3e4c49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005804882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.4005804882
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1338290659
Short name T117
Test name
Test status
Simulation time 1735853227 ps
CPU time 1.87 seconds
Started May 26 01:02:36 PM PDT 24
Finished May 26 01:02:39 PM PDT 24
Peak memory 199688 kb
Host smart-d7e5ba7d-371e-4f5e-a5eb-3010e71b125f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338290659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.1338290659
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.17738275
Short name T615
Test name
Test status
Simulation time 79214665 ps
CPU time 0.61 seconds
Started May 26 01:02:54 PM PDT 24
Finished May 26 01:02:56 PM PDT 24
Peak memory 194412 kb
Host smart-1fe38fee-6a43-452b-a291-94529f5f5cdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17738275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.17738275
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2796876820
Short name T530
Test name
Test status
Simulation time 37884702 ps
CPU time 0.63 seconds
Started May 26 01:02:53 PM PDT 24
Finished May 26 01:02:56 PM PDT 24
Peak memory 194616 kb
Host smart-ba9adc77-4c36-4ecd-9010-6037602d6b1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796876820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2796876820
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.717845314
Short name T544
Test name
Test status
Simulation time 59509867 ps
CPU time 0.61 seconds
Started May 26 01:03:00 PM PDT 24
Finished May 26 01:03:02 PM PDT 24
Peak memory 194452 kb
Host smart-a7eac1c4-e6fe-4bee-99f0-d2f86e04b941
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717845314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.717845314
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.3079620346
Short name T76
Test name
Test status
Simulation time 61861238 ps
CPU time 0.62 seconds
Started May 26 01:02:53 PM PDT 24
Finished May 26 01:02:55 PM PDT 24
Peak memory 194600 kb
Host smart-9f5372a3-367f-494f-aadd-255b33fe87fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079620346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.3079620346
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1808997984
Short name T591
Test name
Test status
Simulation time 13596181 ps
CPU time 0.63 seconds
Started May 26 01:02:54 PM PDT 24
Finished May 26 01:02:56 PM PDT 24
Peak memory 194500 kb
Host smart-0d07b51e-6125-431d-bd4c-15c403acc8ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808997984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1808997984
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3222809323
Short name T534
Test name
Test status
Simulation time 12609150 ps
CPU time 0.62 seconds
Started May 26 01:02:52 PM PDT 24
Finished May 26 01:02:54 PM PDT 24
Peak memory 194432 kb
Host smart-b298c8fe-f821-41fa-af35-4945b7e7aabd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222809323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3222809323
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.52126415
Short name T538
Test name
Test status
Simulation time 35573830 ps
CPU time 0.62 seconds
Started May 26 01:02:53 PM PDT 24
Finished May 26 01:02:56 PM PDT 24
Peak memory 194576 kb
Host smart-3b371924-9071-41f6-aee4-8d64cc874ab0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52126415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.52126415
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.929545426
Short name T574
Test name
Test status
Simulation time 21530524 ps
CPU time 0.61 seconds
Started May 26 01:02:52 PM PDT 24
Finished May 26 01:02:54 PM PDT 24
Peak memory 194540 kb
Host smart-85725ee7-d452-428f-95f9-2e09cebb6e60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929545426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.929545426
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.621440854
Short name T631
Test name
Test status
Simulation time 20065284 ps
CPU time 0.57 seconds
Started May 26 01:02:57 PM PDT 24
Finished May 26 01:02:59 PM PDT 24
Peak memory 194456 kb
Host smart-919d432d-dadc-4e4d-b4cb-cd02bdd322b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621440854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.621440854
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3138445648
Short name T79
Test name
Test status
Simulation time 14376605 ps
CPU time 0.6 seconds
Started May 26 01:02:55 PM PDT 24
Finished May 26 01:02:58 PM PDT 24
Peak memory 194420 kb
Host smart-2df61b6c-885d-4d10-9e14-031e7c35f77c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138445648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3138445648
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1674924634
Short name T88
Test name
Test status
Simulation time 204926731 ps
CPU time 5.44 seconds
Started May 26 01:02:31 PM PDT 24
Finished May 26 01:02:37 PM PDT 24
Peak memory 199628 kb
Host smart-67d72836-77a2-4e64-9b2d-fd76794e4508
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674924634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1674924634
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1126382484
Short name T528
Test name
Test status
Simulation time 118702257 ps
CPU time 5.29 seconds
Started May 26 01:02:36 PM PDT 24
Finished May 26 01:02:42 PM PDT 24
Peak memory 199608 kb
Host smart-4ed778e4-99ec-472b-9c88-e02a499a41b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126382484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1126382484
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3270022039
Short name T597
Test name
Test status
Simulation time 23590185 ps
CPU time 0.71 seconds
Started May 26 01:02:33 PM PDT 24
Finished May 26 01:02:35 PM PDT 24
Peak memory 197628 kb
Host smart-38134e95-d895-49c5-87e1-c840b0160c65
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270022039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3270022039
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2885558600
Short name T27
Test name
Test status
Simulation time 97359841 ps
CPU time 2.19 seconds
Started May 26 01:02:32 PM PDT 24
Finished May 26 01:02:35 PM PDT 24
Peak memory 199680 kb
Host smart-52c92b48-b39a-48b5-8322-11c868094a26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885558600 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2885558600
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1862298911
Short name T599
Test name
Test status
Simulation time 23681057 ps
CPU time 0.86 seconds
Started May 26 01:02:34 PM PDT 24
Finished May 26 01:02:36 PM PDT 24
Peak memory 198612 kb
Host smart-a71f74db-d936-4e9a-9809-7c1e591262b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862298911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1862298911
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3400967446
Short name T616
Test name
Test status
Simulation time 14475970 ps
CPU time 0.63 seconds
Started May 26 01:02:39 PM PDT 24
Finished May 26 01:02:41 PM PDT 24
Peak memory 194564 kb
Host smart-624fcf39-afa8-4027-a279-de07eb19e291
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400967446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3400967446
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4189916721
Short name T595
Test name
Test status
Simulation time 119486305 ps
CPU time 1.2 seconds
Started May 26 01:02:40 PM PDT 24
Finished May 26 01:02:42 PM PDT 24
Peak memory 198040 kb
Host smart-51e09338-bd82-4f5c-8db1-3fca1400a2ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189916721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.4189916721
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2661446495
Short name T65
Test name
Test status
Simulation time 207163711 ps
CPU time 1.64 seconds
Started May 26 01:02:36 PM PDT 24
Finished May 26 01:02:38 PM PDT 24
Peak memory 199696 kb
Host smart-dc51cee5-b556-4b09-85aa-d609ba410f44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661446495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2661446495
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.4246603832
Short name T60
Test name
Test status
Simulation time 153656099 ps
CPU time 3.2 seconds
Started May 26 01:02:36 PM PDT 24
Finished May 26 01:02:40 PM PDT 24
Peak memory 199692 kb
Host smart-77390a90-dfba-419a-bdf8-fd901f94fba9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246603832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.4246603832
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.3896489963
Short name T541
Test name
Test status
Simulation time 12967004 ps
CPU time 0.62 seconds
Started May 26 01:02:52 PM PDT 24
Finished May 26 01:02:55 PM PDT 24
Peak memory 194456 kb
Host smart-62ae4df1-db92-4013-8c6d-aa8f855b2ea5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896489963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.3896489963
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1984707879
Short name T545
Test name
Test status
Simulation time 12952760 ps
CPU time 0.59 seconds
Started May 26 01:02:56 PM PDT 24
Finished May 26 01:02:58 PM PDT 24
Peak memory 194364 kb
Host smart-dc4131a2-5566-4c94-b9d4-2330389577f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984707879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1984707879
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.789814919
Short name T561
Test name
Test status
Simulation time 18745009 ps
CPU time 0.64 seconds
Started May 26 01:02:58 PM PDT 24
Finished May 26 01:03:00 PM PDT 24
Peak memory 194468 kb
Host smart-dcd363d4-49ae-49ca-88c7-5c8898f204cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789814919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.789814919
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3651566628
Short name T547
Test name
Test status
Simulation time 37454969 ps
CPU time 0.61 seconds
Started May 26 01:02:56 PM PDT 24
Finished May 26 01:02:58 PM PDT 24
Peak memory 194404 kb
Host smart-dc4f9b13-7a1a-416e-9e1f-7d414fa1e5e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651566628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3651566628
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.2713068191
Short name T558
Test name
Test status
Simulation time 16779124 ps
CPU time 0.61 seconds
Started May 26 01:03:00 PM PDT 24
Finished May 26 01:03:02 PM PDT 24
Peak memory 194456 kb
Host smart-54d69e3d-ac1e-4c08-a227-6313276a0de4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713068191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2713068191
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2942991421
Short name T529
Test name
Test status
Simulation time 12499370 ps
CPU time 0.6 seconds
Started May 26 01:02:53 PM PDT 24
Finished May 26 01:02:55 PM PDT 24
Peak memory 194748 kb
Host smart-6d9822f7-a6e4-43e7-8a46-6b943fdaa6c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942991421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2942991421
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.4224162990
Short name T629
Test name
Test status
Simulation time 15614037 ps
CPU time 0.57 seconds
Started May 26 01:02:51 PM PDT 24
Finished May 26 01:02:53 PM PDT 24
Peak memory 194480 kb
Host smart-1693177d-e6ca-4cb9-a940-ac3cf29cf56a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224162990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.4224162990
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2186601443
Short name T625
Test name
Test status
Simulation time 179235318 ps
CPU time 0.59 seconds
Started May 26 01:02:55 PM PDT 24
Finished May 26 01:02:58 PM PDT 24
Peak memory 194484 kb
Host smart-37a7030d-da1a-4860-93f1-feaede78e09f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186601443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2186601443
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.1537121955
Short name T584
Test name
Test status
Simulation time 18030541 ps
CPU time 0.59 seconds
Started May 26 01:03:00 PM PDT 24
Finished May 26 01:03:04 PM PDT 24
Peak memory 194456 kb
Host smart-6cfd7be5-9b8a-4645-97a2-c10652f3fb3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537121955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1537121955
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1092282153
Short name T563
Test name
Test status
Simulation time 18606079 ps
CPU time 0.61 seconds
Started May 26 01:02:55 PM PDT 24
Finished May 26 01:02:58 PM PDT 24
Peak memory 194568 kb
Host smart-1c0435b3-f59a-471c-b722-e788fcee1861
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092282153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1092282153
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1099735401
Short name T533
Test name
Test status
Simulation time 63381097 ps
CPU time 3.12 seconds
Started May 26 01:02:44 PM PDT 24
Finished May 26 01:02:49 PM PDT 24
Peak memory 199628 kb
Host smart-dce5b4d6-6549-492b-874b-056ef410f978
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099735401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1099735401
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.291800012
Short name T585
Test name
Test status
Simulation time 707359653 ps
CPU time 11.06 seconds
Started May 26 01:02:43 PM PDT 24
Finished May 26 01:02:57 PM PDT 24
Peak memory 199692 kb
Host smart-b9cd7bec-cb6f-4ccd-8866-7caf892e6887
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291800012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.291800012
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1379652363
Short name T643
Test name
Test status
Simulation time 30867686 ps
CPU time 0.84 seconds
Started May 26 01:02:39 PM PDT 24
Finished May 26 01:02:41 PM PDT 24
Peak memory 198616 kb
Host smart-7c9f40a6-ec4b-4de9-b873-f9160cd62995
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379652363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1379652363
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3364247727
Short name T568
Test name
Test status
Simulation time 175835523 ps
CPU time 1.18 seconds
Started May 26 01:02:47 PM PDT 24
Finished May 26 01:02:51 PM PDT 24
Peak memory 199488 kb
Host smart-13173502-c9ac-4402-82dc-c1a0d6d9cd75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364247727 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3364247727
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2810860131
Short name T549
Test name
Test status
Simulation time 30655051 ps
CPU time 0.82 seconds
Started May 26 01:02:33 PM PDT 24
Finished May 26 01:02:35 PM PDT 24
Peak memory 198776 kb
Host smart-88bef6f1-170d-4843-9cdf-2581494ed2e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810860131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2810860131
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3460624509
Short name T593
Test name
Test status
Simulation time 30715038 ps
CPU time 0.66 seconds
Started May 26 01:02:33 PM PDT 24
Finished May 26 01:02:35 PM PDT 24
Peak memory 194520 kb
Host smart-4273b734-1dea-4055-bb28-3a0170c54316
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460624509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3460624509
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3693132646
Short name T576
Test name
Test status
Simulation time 82372041 ps
CPU time 1.11 seconds
Started May 26 01:02:46 PM PDT 24
Finished May 26 01:02:51 PM PDT 24
Peak memory 199628 kb
Host smart-caf8eeac-c99e-4a02-a1ed-5dc0ac9fc93c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693132646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3693132646
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.4015295440
Short name T62
Test name
Test status
Simulation time 124150235 ps
CPU time 3.21 seconds
Started May 26 01:02:37 PM PDT 24
Finished May 26 01:02:41 PM PDT 24
Peak memory 199676 kb
Host smart-9348b2a5-60f9-47f4-9b6d-3c5dc11ccea1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015295440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.4015295440
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2603462845
Short name T114
Test name
Test status
Simulation time 253651256 ps
CPU time 4.42 seconds
Started May 26 01:02:39 PM PDT 24
Finished May 26 01:02:45 PM PDT 24
Peak memory 199744 kb
Host smart-05299051-39bf-488d-bc10-4595ef33208f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603462845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2603462845
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.2761393320
Short name T641
Test name
Test status
Simulation time 14992199 ps
CPU time 0.62 seconds
Started May 26 01:03:00 PM PDT 24
Finished May 26 01:03:03 PM PDT 24
Peak memory 194524 kb
Host smart-3202acba-1032-4813-97d3-b4bbb119cedb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761393320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2761393320
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.110269582
Short name T525
Test name
Test status
Simulation time 29912744 ps
CPU time 0.6 seconds
Started May 26 01:02:53 PM PDT 24
Finished May 26 01:02:56 PM PDT 24
Peak memory 194540 kb
Host smart-70d35984-4091-43d2-b111-79a376a79e0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110269582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.110269582
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.51219445
Short name T560
Test name
Test status
Simulation time 29993215 ps
CPU time 0.59 seconds
Started May 26 01:02:59 PM PDT 24
Finished May 26 01:03:01 PM PDT 24
Peak memory 194520 kb
Host smart-b5553db2-e46d-4c11-a2e5-e685ccc9e095
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51219445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.51219445
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.681379554
Short name T537
Test name
Test status
Simulation time 32568043 ps
CPU time 0.6 seconds
Started May 26 01:02:54 PM PDT 24
Finished May 26 01:02:57 PM PDT 24
Peak memory 194452 kb
Host smart-41eb4021-e52e-44e0-a535-cd06fa3bf7e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681379554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.681379554
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3118163802
Short name T612
Test name
Test status
Simulation time 13260539 ps
CPU time 0.63 seconds
Started May 26 01:02:52 PM PDT 24
Finished May 26 01:02:54 PM PDT 24
Peak memory 194532 kb
Host smart-02956bb9-e643-4695-b15d-115f330c7bcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118163802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3118163802
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1766033956
Short name T559
Test name
Test status
Simulation time 26186352 ps
CPU time 0.57 seconds
Started May 26 01:02:52 PM PDT 24
Finished May 26 01:02:54 PM PDT 24
Peak memory 194520 kb
Host smart-b36a65c3-0719-45df-bf4f-986498343f86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766033956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1766033956
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1486522251
Short name T527
Test name
Test status
Simulation time 23585032 ps
CPU time 0.58 seconds
Started May 26 01:02:55 PM PDT 24
Finished May 26 01:02:58 PM PDT 24
Peak memory 194460 kb
Host smart-30dc9825-6f7a-4389-882a-f7d39047936c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486522251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1486522251
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3532413701
Short name T535
Test name
Test status
Simulation time 13116705 ps
CPU time 0.6 seconds
Started May 26 01:02:59 PM PDT 24
Finished May 26 01:03:02 PM PDT 24
Peak memory 194520 kb
Host smart-c3fb7d33-33da-4ffd-9bf1-8ae1b74a894c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532413701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3532413701
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.3617109162
Short name T607
Test name
Test status
Simulation time 37632567 ps
CPU time 0.61 seconds
Started May 26 01:02:58 PM PDT 24
Finished May 26 01:03:00 PM PDT 24
Peak memory 194448 kb
Host smart-8856bd6b-e32e-4b78-8a58-cd43a88bf2a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617109162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3617109162
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.4113649346
Short name T536
Test name
Test status
Simulation time 47096220 ps
CPU time 0.63 seconds
Started May 26 01:02:58 PM PDT 24
Finished May 26 01:03:00 PM PDT 24
Peak memory 194436 kb
Host smart-966a1278-333b-43f2-a699-dfe135eb7904
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113649346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.4113649346
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1718224047
Short name T72
Test name
Test status
Simulation time 41606598 ps
CPU time 2.78 seconds
Started May 26 01:02:54 PM PDT 24
Finished May 26 01:02:58 PM PDT 24
Peak memory 199752 kb
Host smart-bfc30212-3b90-4bdf-84bd-880e6c883bf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718224047 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.1718224047
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3379686729
Short name T622
Test name
Test status
Simulation time 30781284 ps
CPU time 0.7 seconds
Started May 26 01:02:44 PM PDT 24
Finished May 26 01:02:48 PM PDT 24
Peak memory 197544 kb
Host smart-cf544322-316e-4f82-8d02-43645f083522
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379686729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3379686729
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1251219801
Short name T583
Test name
Test status
Simulation time 183739229 ps
CPU time 0.58 seconds
Started May 26 01:02:44 PM PDT 24
Finished May 26 01:02:47 PM PDT 24
Peak memory 194440 kb
Host smart-6fc5ea43-7214-49aa-a761-0c8499cc84dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251219801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1251219801
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2298944644
Short name T580
Test name
Test status
Simulation time 34075212 ps
CPU time 1.54 seconds
Started May 26 01:02:42 PM PDT 24
Finished May 26 01:02:45 PM PDT 24
Peak memory 199640 kb
Host smart-a98e4ae3-e5c7-4a71-90bc-440b43bf9a49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298944644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.2298944644
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.761894741
Short name T566
Test name
Test status
Simulation time 52065497 ps
CPU time 2.81 seconds
Started May 26 01:02:44 PM PDT 24
Finished May 26 01:02:49 PM PDT 24
Peak memory 199548 kb
Host smart-3b379884-6bd9-4f7e-8a12-b859a007c51f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761894741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.761894741
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.691886878
Short name T59
Test name
Test status
Simulation time 610096601 ps
CPU time 3.12 seconds
Started May 26 01:02:45 PM PDT 24
Finished May 26 01:02:51 PM PDT 24
Peak memory 199728 kb
Host smart-0fa84cdc-3f5f-4bae-a794-22aab1b449ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691886878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.691886878
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2422909226
Short name T71
Test name
Test status
Simulation time 95543277 ps
CPU time 1.75 seconds
Started May 26 01:02:44 PM PDT 24
Finished May 26 01:02:48 PM PDT 24
Peak memory 199684 kb
Host smart-a7528d56-f31f-4425-a999-d1b2d9777aae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422909226 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.2422909226
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1265785565
Short name T626
Test name
Test status
Simulation time 42561559 ps
CPU time 0.83 seconds
Started May 26 01:02:46 PM PDT 24
Finished May 26 01:02:49 PM PDT 24
Peak memory 198844 kb
Host smart-80721da1-b761-4323-9f88-a98695bb3eaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265785565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1265785565
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3720637174
Short name T548
Test name
Test status
Simulation time 62453316 ps
CPU time 0.6 seconds
Started May 26 01:02:44 PM PDT 24
Finished May 26 01:02:47 PM PDT 24
Peak memory 194460 kb
Host smart-e00b52e8-4257-48f7-9da0-d8eb189bc8f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720637174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3720637174
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.960913543
Short name T565
Test name
Test status
Simulation time 445945023 ps
CPU time 1.96 seconds
Started May 26 01:02:43 PM PDT 24
Finished May 26 01:02:47 PM PDT 24
Peak memory 199644 kb
Host smart-da488cec-8814-46ee-aec4-dcf52bd6ed7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960913543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_
outstanding.960913543
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1277945894
Short name T63
Test name
Test status
Simulation time 117512861 ps
CPU time 1.82 seconds
Started May 26 01:02:43 PM PDT 24
Finished May 26 01:02:47 PM PDT 24
Peak memory 199652 kb
Host smart-512a88c3-adde-414f-a50d-131ff4631417
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277945894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1277945894
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1515564759
Short name T605
Test name
Test status
Simulation time 362729765 ps
CPU time 1.94 seconds
Started May 26 01:02:45 PM PDT 24
Finished May 26 01:02:50 PM PDT 24
Peak memory 199800 kb
Host smart-90525867-88c3-4654-b9f8-f3f492bb3488
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515564759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1515564759
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.930534534
Short name T554
Test name
Test status
Simulation time 114568737 ps
CPU time 1.68 seconds
Started May 26 01:02:46 PM PDT 24
Finished May 26 01:02:50 PM PDT 24
Peak memory 199804 kb
Host smart-fefeb502-3683-4cff-bf76-75230b3f8dad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930534534 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.930534534
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3702329212
Short name T78
Test name
Test status
Simulation time 61950558 ps
CPU time 0.69 seconds
Started May 26 01:02:45 PM PDT 24
Finished May 26 01:02:49 PM PDT 24
Peak memory 197400 kb
Host smart-e9989b62-f86f-46fb-aeca-afc7b8e88fa9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702329212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3702329212
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.3498098960
Short name T645
Test name
Test status
Simulation time 14650982 ps
CPU time 0.62 seconds
Started May 26 01:02:44 PM PDT 24
Finished May 26 01:02:47 PM PDT 24
Peak memory 194540 kb
Host smart-b7e8bfe5-7559-4d54-a3c9-b8c795901815
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498098960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3498098960
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2556465201
Short name T551
Test name
Test status
Simulation time 113031012 ps
CPU time 2.37 seconds
Started May 26 01:02:42 PM PDT 24
Finished May 26 01:02:45 PM PDT 24
Peak memory 199668 kb
Host smart-d8a97d48-e774-4bfe-8006-b4fa3a3c5a72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556465201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2556465201
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3675054269
Short name T68
Test name
Test status
Simulation time 85113037 ps
CPU time 1.33 seconds
Started May 26 01:02:45 PM PDT 24
Finished May 26 01:02:49 PM PDT 24
Peak memory 199720 kb
Host smart-d8ec5374-bec2-4c98-8f20-ee1d18c37128
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675054269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3675054269
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2843272807
Short name T115
Test name
Test status
Simulation time 494399938 ps
CPU time 3.93 seconds
Started May 26 01:02:46 PM PDT 24
Finished May 26 01:02:53 PM PDT 24
Peak memory 199632 kb
Host smart-48052fa5-41e8-4719-b6ba-9a085d88cf04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843272807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2843272807
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.798890623
Short name T28
Test name
Test status
Simulation time 37008185 ps
CPU time 1.29 seconds
Started May 26 01:02:46 PM PDT 24
Finished May 26 01:02:50 PM PDT 24
Peak memory 199276 kb
Host smart-b2d60259-b228-4d5c-b4f3-d0dd6b4ce577
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798890623 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.798890623
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3415830473
Short name T94
Test name
Test status
Simulation time 53440838 ps
CPU time 0.83 seconds
Started May 26 01:02:44 PM PDT 24
Finished May 26 01:02:47 PM PDT 24
Peak memory 198724 kb
Host smart-6a658a88-33db-4559-8319-fec27bac21cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415830473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3415830473
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.121200845
Short name T587
Test name
Test status
Simulation time 62074230 ps
CPU time 0.67 seconds
Started May 26 01:02:43 PM PDT 24
Finished May 26 01:02:46 PM PDT 24
Peak memory 194564 kb
Host smart-2d23b130-e755-447f-9874-7dd599755559
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121200845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.121200845
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3032462673
Short name T594
Test name
Test status
Simulation time 311613527 ps
CPU time 2.47 seconds
Started May 26 01:02:46 PM PDT 24
Finished May 26 01:02:52 PM PDT 24
Peak memory 199632 kb
Host smart-97a98848-97f5-4d65-a263-b50722eedc55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032462673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3032462673
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2749823462
Short name T66
Test name
Test status
Simulation time 106484174 ps
CPU time 2.17 seconds
Started May 26 01:02:45 PM PDT 24
Finished May 26 01:02:50 PM PDT 24
Peak memory 199676 kb
Host smart-20e9bf5d-5a99-4cae-bf79-fe30b42fedfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749823462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2749823462
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2386332448
Short name T610
Test name
Test status
Simulation time 331278482 ps
CPU time 3.06 seconds
Started May 26 01:02:43 PM PDT 24
Finished May 26 01:02:49 PM PDT 24
Peak memory 199736 kb
Host smart-93aac6d2-b2c5-466c-90da-afa1e9772867
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386332448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.2386332448
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2412757777
Short name T592
Test name
Test status
Simulation time 74534173 ps
CPU time 1.97 seconds
Started May 26 01:02:43 PM PDT 24
Finished May 26 01:02:47 PM PDT 24
Peak memory 199724 kb
Host smart-e8b709df-7844-4abb-98d6-f9c4272cc77d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412757777 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2412757777
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1354512858
Short name T555
Test name
Test status
Simulation time 30291536 ps
CPU time 0.84 seconds
Started May 26 01:02:46 PM PDT 24
Finished May 26 01:02:49 PM PDT 24
Peak memory 198628 kb
Host smart-dedbd6bf-6609-424d-ba6f-6dfd3b36f951
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354512858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1354512858
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2920181671
Short name T600
Test name
Test status
Simulation time 47943375 ps
CPU time 0.62 seconds
Started May 26 01:02:43 PM PDT 24
Finished May 26 01:02:44 PM PDT 24
Peak memory 194512 kb
Host smart-0d10c8bd-a585-4b1b-a20e-0db9f291290f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920181671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2920181671
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.795757025
Short name T621
Test name
Test status
Simulation time 80270541 ps
CPU time 1.12 seconds
Started May 26 01:02:46 PM PDT 24
Finished May 26 01:02:50 PM PDT 24
Peak memory 199684 kb
Host smart-6d00bae1-5cd4-4cc7-89ad-0202cadb3583
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795757025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.795757025
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2984653739
Short name T64
Test name
Test status
Simulation time 91714524 ps
CPU time 1.91 seconds
Started May 26 01:02:44 PM PDT 24
Finished May 26 01:02:48 PM PDT 24
Peak memory 199604 kb
Host smart-915348b9-1701-4176-a90f-2e9a443e6464
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984653739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2984653739
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.929692738
Short name T112
Test name
Test status
Simulation time 99295990 ps
CPU time 1.85 seconds
Started May 26 01:02:44 PM PDT 24
Finished May 26 01:02:48 PM PDT 24
Peak memory 199668 kb
Host smart-e2042cba-6d5a-4fba-92ca-012eaa24ea93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929692738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.929692738
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3765287172
Short name T455
Test name
Test status
Simulation time 47661985 ps
CPU time 0.64 seconds
Started May 26 02:20:52 PM PDT 24
Finished May 26 02:20:54 PM PDT 24
Peak memory 196724 kb
Host smart-1be0d757-4273-4da2-9b44-ff074e58d2e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765287172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3765287172
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.772208263
Short name T493
Test name
Test status
Simulation time 1001494322 ps
CPU time 11.17 seconds
Started May 26 02:20:53 PM PDT 24
Finished May 26 02:21:06 PM PDT 24
Peak memory 216224 kb
Host smart-f4479427-c2c3-4bca-adc9-e43a7394e288
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=772208263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.772208263
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.2831245867
Short name T273
Test name
Test status
Simulation time 9139629059 ps
CPU time 564.61 seconds
Started May 26 02:20:52 PM PDT 24
Finished May 26 02:30:18 PM PDT 24
Peak memory 674668 kb
Host smart-a7df265c-a10b-4f10-9078-c5cafac6852b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2831245867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2831245867
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2092677871
Short name T507
Test name
Test status
Simulation time 2274464071 ps
CPU time 125.96 seconds
Started May 26 02:20:52 PM PDT 24
Finished May 26 02:22:59 PM PDT 24
Peak memory 200132 kb
Host smart-efc3784d-4166-496b-aba2-8c1eefed27f1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092677871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2092677871
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1909313312
Short name T203
Test name
Test status
Simulation time 7169500052 ps
CPU time 143.28 seconds
Started May 26 02:20:54 PM PDT 24
Finished May 26 02:23:19 PM PDT 24
Peak memory 200156 kb
Host smart-a7d8a20e-a09c-41c5-8594-fba303c09208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909313312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1909313312
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1862573636
Short name T37
Test name
Test status
Simulation time 304477924 ps
CPU time 0.87 seconds
Started May 26 02:20:52 PM PDT 24
Finished May 26 02:20:54 PM PDT 24
Peak memory 218080 kb
Host smart-25769a98-f4cc-48a6-9bbd-38b79e858b3f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862573636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1862573636
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.253908602
Short name T170
Test name
Test status
Simulation time 288408960 ps
CPU time 5.21 seconds
Started May 26 02:20:52 PM PDT 24
Finished May 26 02:20:59 PM PDT 24
Peak memory 200120 kb
Host smart-d166d692-ab33-4aac-b90e-efcfaecc24c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253908602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.253908602
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2566870775
Short name T395
Test name
Test status
Simulation time 37711122135 ps
CPU time 527.74 seconds
Started May 26 02:20:53 PM PDT 24
Finished May 26 02:29:42 PM PDT 24
Peak memory 200044 kb
Host smart-01dd8cdb-4764-41fe-a6bc-8809659f0041
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566870775 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2566870775
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.1042883951
Short name T389
Test name
Test status
Simulation time 42676115 ps
CPU time 1.12 seconds
Started May 26 02:20:53 PM PDT 24
Finished May 26 02:20:56 PM PDT 24
Peak memory 198784 kb
Host smart-5a4a9db4-45db-4eb1-82da-e104e0ae7946
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042883951 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.1042883951
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.2400600199
Short name T158
Test name
Test status
Simulation time 164285009384 ps
CPU time 517.52 seconds
Started May 26 02:20:53 PM PDT 24
Finished May 26 02:29:33 PM PDT 24
Peak memory 200100 kb
Host smart-6c1b699b-91c7-49d8-a98d-a0a5fccbb14b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400600199 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.2400600199
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.2016321937
Short name T473
Test name
Test status
Simulation time 36288216637 ps
CPU time 90.96 seconds
Started May 26 02:20:50 PM PDT 24
Finished May 26 02:22:21 PM PDT 24
Peak memory 200216 kb
Host smart-657fd3f6-1506-4d8a-93c4-747277964e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016321937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.2016321937
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3050076728
Short name T396
Test name
Test status
Simulation time 19782274 ps
CPU time 0.6 seconds
Started May 26 02:20:53 PM PDT 24
Finished May 26 02:20:55 PM PDT 24
Peak memory 195980 kb
Host smart-30f6b104-eae0-4737-80b7-cbd41af548cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050076728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3050076728
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3232154545
Short name T442
Test name
Test status
Simulation time 134305986 ps
CPU time 5.9 seconds
Started May 26 02:20:50 PM PDT 24
Finished May 26 02:20:58 PM PDT 24
Peak memory 200108 kb
Host smart-d658a389-e296-41ee-974b-6a3609cf317e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3232154545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3232154545
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2238566632
Short name T382
Test name
Test status
Simulation time 25482536 ps
CPU time 0.76 seconds
Started May 26 02:20:53 PM PDT 24
Finished May 26 02:20:56 PM PDT 24
Peak memory 197916 kb
Host smart-c5fc63e0-1e4d-4a28-a374-26adadcd9e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238566632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2238566632
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1711204441
Short name T404
Test name
Test status
Simulation time 1073889876 ps
CPU time 310.74 seconds
Started May 26 02:20:53 PM PDT 24
Finished May 26 02:26:05 PM PDT 24
Peak memory 648852 kb
Host smart-fb6b1b9c-d6c0-42e8-9e4c-905e96d6be3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1711204441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1711204441
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_long_msg.1138777690
Short name T42
Test name
Test status
Simulation time 4849755046 ps
CPU time 68.49 seconds
Started May 26 02:20:53 PM PDT 24
Finished May 26 02:22:03 PM PDT 24
Peak memory 200180 kb
Host smart-634893b9-1b9e-4a31-ab53-9caf2949506e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138777690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.1138777690
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1428645473
Short name T34
Test name
Test status
Simulation time 126406856 ps
CPU time 0.93 seconds
Started May 26 02:20:51 PM PDT 24
Finished May 26 02:20:53 PM PDT 24
Peak memory 218288 kb
Host smart-ccbd2087-82fa-4579-a986-0901526e1cef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428645473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1428645473
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.2717847307
Short name T291
Test name
Test status
Simulation time 236006745 ps
CPU time 4.1 seconds
Started May 26 02:20:50 PM PDT 24
Finished May 26 02:20:55 PM PDT 24
Peak memory 200156 kb
Host smart-915c5d89-86e5-485d-8b79-622f01b90637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717847307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2717847307
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.936440399
Short name T211
Test name
Test status
Simulation time 1326333777 ps
CPU time 57.8 seconds
Started May 26 02:20:51 PM PDT 24
Finished May 26 02:21:50 PM PDT 24
Peak memory 200324 kb
Host smart-ac9b164f-8dc0-4779-bdbf-ed870b47a722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936440399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.936440399
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.951482046
Short name T487
Test name
Test status
Simulation time 39517254 ps
CPU time 0.58 seconds
Started May 26 02:21:12 PM PDT 24
Finished May 26 02:21:14 PM PDT 24
Peak memory 196000 kb
Host smart-1c0030b2-c3b2-45a8-9f2f-eac8ab105947
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951482046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.951482046
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.2229230902
Short name T49
Test name
Test status
Simulation time 869557793 ps
CPU time 40.73 seconds
Started May 26 02:21:13 PM PDT 24
Finished May 26 02:21:55 PM PDT 24
Peak memory 208276 kb
Host smart-517dba51-188a-44c4-93c2-c171a43903b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2229230902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2229230902
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.534283073
Short name T294
Test name
Test status
Simulation time 3681707498 ps
CPU time 15.48 seconds
Started May 26 02:21:19 PM PDT 24
Finished May 26 02:21:35 PM PDT 24
Peak memory 200192 kb
Host smart-0a7bfa99-0742-44ee-95bd-4cacf36e8ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534283073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.534283073
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.4282894179
Short name T307
Test name
Test status
Simulation time 3178383232 ps
CPU time 449.29 seconds
Started May 26 02:21:13 PM PDT 24
Finished May 26 02:28:44 PM PDT 24
Peak memory 676776 kb
Host smart-b2294bda-ecbe-4869-9cb3-bb11acda7728
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4282894179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.4282894179
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3820840811
Short name T162
Test name
Test status
Simulation time 7231615745 ps
CPU time 110.24 seconds
Started May 26 02:21:16 PM PDT 24
Finished May 26 02:23:07 PM PDT 24
Peak memory 199964 kb
Host smart-1e470862-5961-4761-a80f-349457802c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820840811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3820840811
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.227838216
Short name T491
Test name
Test status
Simulation time 1243375761 ps
CPU time 6.6 seconds
Started May 26 02:21:13 PM PDT 24
Finished May 26 02:21:21 PM PDT 24
Peak memory 200084 kb
Host smart-22a2ef01-e63f-4eb7-ba14-de5afd86a40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227838216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.227838216
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1613044748
Short name T249
Test name
Test status
Simulation time 14020687104 ps
CPU time 50.52 seconds
Started May 26 02:21:15 PM PDT 24
Finished May 26 02:22:06 PM PDT 24
Peak memory 200188 kb
Host smart-572bae02-7282-4470-89e4-c21e460c3648
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613044748 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1613044748
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.1216236200
Short name T414
Test name
Test status
Simulation time 279961676 ps
CPU time 1.38 seconds
Started May 26 02:21:28 PM PDT 24
Finished May 26 02:21:31 PM PDT 24
Peak memory 200076 kb
Host smart-30f9c0ae-30ba-401d-9c6d-09b52c10c453
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216236200 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.1216236200
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.810901440
Short name T141
Test name
Test status
Simulation time 169935685552 ps
CPU time 561.14 seconds
Started May 26 02:21:13 PM PDT 24
Finished May 26 02:30:36 PM PDT 24
Peak memory 200192 kb
Host smart-905542cb-fab5-4c16-9084-ae258472cf8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810901440 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.810901440
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2828271588
Short name T287
Test name
Test status
Simulation time 13738774874 ps
CPU time 66.3 seconds
Started May 26 02:21:27 PM PDT 24
Finished May 26 02:22:35 PM PDT 24
Peak memory 200176 kb
Host smart-3da5d18e-5610-47de-b9a8-8e7fd3301de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828271588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2828271588
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.612205297
Short name T128
Test name
Test status
Simulation time 25793121 ps
CPU time 0.6 seconds
Started May 26 02:21:20 PM PDT 24
Finished May 26 02:21:21 PM PDT 24
Peak memory 195160 kb
Host smart-300ea572-110e-44ad-b588-18f21a3a2e35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612205297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.612205297
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1082618740
Short name T323
Test name
Test status
Simulation time 1976188628 ps
CPU time 55.06 seconds
Started May 26 02:21:14 PM PDT 24
Finished May 26 02:22:10 PM PDT 24
Peak memory 232776 kb
Host smart-9aea2091-1b7b-4e7d-9d34-6b120f93638f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1082618740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1082618740
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.983839299
Short name T402
Test name
Test status
Simulation time 142151299 ps
CPU time 6.74 seconds
Started May 26 02:21:14 PM PDT 24
Finished May 26 02:21:22 PM PDT 24
Peak memory 200092 kb
Host smart-76de9159-c3dd-4116-ab52-6ee827ea486b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983839299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.983839299
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1367781670
Short name T7
Test name
Test status
Simulation time 5698760265 ps
CPU time 328.88 seconds
Started May 26 02:21:26 PM PDT 24
Finished May 26 02:26:56 PM PDT 24
Peak memory 645820 kb
Host smart-f9c6fc1b-f90e-417b-9129-8f6a652a76ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1367781670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1367781670
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3814664098
Short name T508
Test name
Test status
Simulation time 9792414754 ps
CPU time 139.66 seconds
Started May 26 02:21:18 PM PDT 24
Finished May 26 02:23:38 PM PDT 24
Peak memory 200332 kb
Host smart-f5f6a84e-df68-4937-ab49-581dff03b54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814664098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3814664098
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.3652685480
Short name T160
Test name
Test status
Simulation time 94004084 ps
CPU time 3.16 seconds
Started May 26 02:21:19 PM PDT 24
Finished May 26 02:21:23 PM PDT 24
Peak memory 199928 kb
Host smart-132e465d-d840-4725-b978-6e87487ae079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652685480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3652685480
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.2977865540
Short name T318
Test name
Test status
Simulation time 65035726 ps
CPU time 1.13 seconds
Started May 26 02:21:21 PM PDT 24
Finished May 26 02:21:23 PM PDT 24
Peak memory 199856 kb
Host smart-217156cc-ae29-4262-90dc-389b2c8efafd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977865540 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2977865540
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.3200891971
Short name T312
Test name
Test status
Simulation time 192645044 ps
CPU time 1.33 seconds
Started May 26 02:21:28 PM PDT 24
Finished May 26 02:21:30 PM PDT 24
Peak memory 200048 kb
Host smart-b1dc31e5-59de-4487-b973-4939f06e3305
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200891971 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.3200891971
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.1800909892
Short name T218
Test name
Test status
Simulation time 28177643633 ps
CPU time 501.28 seconds
Started May 26 02:21:22 PM PDT 24
Finished May 26 02:29:44 PM PDT 24
Peak memory 200100 kb
Host smart-9c365516-7420-452d-9a3a-c04e46f4d0bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800909892 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.1800909892
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2087747354
Short name T147
Test name
Test status
Simulation time 22719036309 ps
CPU time 89.75 seconds
Started May 26 02:21:26 PM PDT 24
Finished May 26 02:22:57 PM PDT 24
Peak memory 200228 kb
Host smart-d565b681-205c-4d78-91fa-431978ee2239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087747354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2087747354
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2954098393
Short name T495
Test name
Test status
Simulation time 33121597 ps
CPU time 0.61 seconds
Started May 26 02:21:14 PM PDT 24
Finished May 26 02:21:16 PM PDT 24
Peak memory 196032 kb
Host smart-5c1aac24-0e29-492a-8f8f-e7f009cdaf8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954098393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2954098393
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3784331714
Short name T439
Test name
Test status
Simulation time 3826865804 ps
CPU time 51.66 seconds
Started May 26 02:21:26 PM PDT 24
Finished May 26 02:22:19 PM PDT 24
Peak memory 224816 kb
Host smart-0e073356-9097-49b9-b00a-eeaed22771ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3784331714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3784331714
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.3176104600
Short name T313
Test name
Test status
Simulation time 2055689869 ps
CPU time 29.41 seconds
Started May 26 02:21:13 PM PDT 24
Finished May 26 02:21:44 PM PDT 24
Peak memory 200032 kb
Host smart-0fece0a5-3b95-47c2-bd04-e1915fb4eaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176104600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.3176104600
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.2588862832
Short name T131
Test name
Test status
Simulation time 3026798526 ps
CPU time 694.03 seconds
Started May 26 02:21:27 PM PDT 24
Finished May 26 02:33:02 PM PDT 24
Peak memory 728024 kb
Host smart-3fe938fc-39ad-4446-a7f9-93fe49f903f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2588862832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2588862832
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.982956890
Short name T167
Test name
Test status
Simulation time 6794961162 ps
CPU time 100.53 seconds
Started May 26 02:21:27 PM PDT 24
Finished May 26 02:23:08 PM PDT 24
Peak memory 200172 kb
Host smart-b6819cbf-5bc3-4cd3-988e-a994601755c2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982956890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.982956890
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.2046088179
Short name T296
Test name
Test status
Simulation time 6599263124 ps
CPU time 76.8 seconds
Started May 26 02:21:13 PM PDT 24
Finished May 26 02:22:31 PM PDT 24
Peak memory 200156 kb
Host smart-853638e8-b668-431a-b207-8d6113650038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046088179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2046088179
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1413557871
Short name T3
Test name
Test status
Simulation time 508513528 ps
CPU time 5.64 seconds
Started May 26 02:21:12 PM PDT 24
Finished May 26 02:21:19 PM PDT 24
Peak memory 200140 kb
Host smart-270e856e-84ed-4d6b-a17f-6922577628c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413557871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1413557871
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.2859981604
Short name T336
Test name
Test status
Simulation time 712368977 ps
CPU time 1.02 seconds
Started May 26 02:21:13 PM PDT 24
Finished May 26 02:21:16 PM PDT 24
Peak memory 198992 kb
Host smart-23938e54-d5b3-4d6e-b5bd-c5565d784635
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859981604 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.2859981604
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.2157251017
Short name T190
Test name
Test status
Simulation time 24724986430 ps
CPU time 464.64 seconds
Started May 26 02:21:22 PM PDT 24
Finished May 26 02:29:08 PM PDT 24
Peak memory 200100 kb
Host smart-bf8594cc-cc40-4f07-909a-95aa8bc9d85a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157251017 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.2157251017
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2288144502
Short name T371
Test name
Test status
Simulation time 36097531 ps
CPU time 0.59 seconds
Started May 26 02:21:23 PM PDT 24
Finished May 26 02:21:24 PM PDT 24
Peak memory 194872 kb
Host smart-9c45d84b-8a2c-4395-b65c-82888feb7860
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288144502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2288144502
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1065121511
Short name T513
Test name
Test status
Simulation time 548678137 ps
CPU time 25.43 seconds
Started May 26 02:21:13 PM PDT 24
Finished May 26 02:21:40 PM PDT 24
Peak memory 216452 kb
Host smart-dde1703e-15c4-4073-92ce-c3ada44780e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1065121511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1065121511
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1662835354
Short name T98
Test name
Test status
Simulation time 9200590515 ps
CPU time 46.23 seconds
Started May 26 02:21:29 PM PDT 24
Finished May 26 02:22:16 PM PDT 24
Peak memory 200184 kb
Host smart-5bfde5d5-4654-4ac9-b7c7-aecc78234724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662835354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1662835354
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2149190922
Short name T41
Test name
Test status
Simulation time 1649208351 ps
CPU time 298.26 seconds
Started May 26 02:21:28 PM PDT 24
Finished May 26 02:26:27 PM PDT 24
Peak memory 648920 kb
Host smart-d9f2c02b-a250-4730-a653-a9db528271d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2149190922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2149190922
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1337121998
Short name T437
Test name
Test status
Simulation time 1844310704 ps
CPU time 33.85 seconds
Started May 26 02:21:16 PM PDT 24
Finished May 26 02:21:50 PM PDT 24
Peak memory 200124 kb
Host smart-fec9dbf7-808b-449e-bd48-ccd28928134d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337121998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1337121998
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2772341288
Short name T150
Test name
Test status
Simulation time 654746225 ps
CPU time 5.42 seconds
Started May 26 02:21:13 PM PDT 24
Finished May 26 02:21:19 PM PDT 24
Peak memory 200108 kb
Host smart-1582d5d4-7bcf-43f6-891e-4ba0054c9638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772341288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2772341288
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.854467565
Short name T45
Test name
Test status
Simulation time 60586205004 ps
CPU time 2023.57 seconds
Started May 26 02:21:21 PM PDT 24
Finished May 26 02:55:06 PM PDT 24
Peak memory 669228 kb
Host smart-3d6d74c3-1280-40ea-b735-1c362567c710
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854467565 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.854467565
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.3353145038
Short name T469
Test name
Test status
Simulation time 56484662 ps
CPU time 1.29 seconds
Started May 26 02:21:24 PM PDT 24
Finished May 26 02:21:26 PM PDT 24
Peak memory 200144 kb
Host smart-7de5c61a-e6dd-40f4-b76b-388f6975734d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353145038 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.3353145038
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.675092639
Short name T410
Test name
Test status
Simulation time 8266170599 ps
CPU time 458.96 seconds
Started May 26 02:21:29 PM PDT 24
Finished May 26 02:29:09 PM PDT 24
Peak memory 200204 kb
Host smart-06df5246-333b-4b66-a2c4-1a3d3f43117e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675092639 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.675092639
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2889867963
Short name T217
Test name
Test status
Simulation time 1899173955 ps
CPU time 26.57 seconds
Started May 26 02:21:32 PM PDT 24
Finished May 26 02:21:59 PM PDT 24
Peak memory 200160 kb
Host smart-89f369db-bfea-4b00-a394-64c1e1e0feba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889867963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2889867963
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.897899832
Short name T163
Test name
Test status
Simulation time 14872575 ps
CPU time 0.58 seconds
Started May 26 02:21:21 PM PDT 24
Finished May 26 02:21:22 PM PDT 24
Peak memory 194996 kb
Host smart-072a435a-11ad-4cd0-a9dc-bf0eef392ef4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897899832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.897899832
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2068250471
Short name T196
Test name
Test status
Simulation time 2803881237 ps
CPU time 41.85 seconds
Started May 26 02:21:22 PM PDT 24
Finished May 26 02:22:04 PM PDT 24
Peak memory 208364 kb
Host smart-2d953373-3cf3-44ce-bb71-52238037d0e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2068250471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2068250471
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.1141283329
Short name T357
Test name
Test status
Simulation time 3979045793 ps
CPU time 54.46 seconds
Started May 26 02:21:24 PM PDT 24
Finished May 26 02:22:19 PM PDT 24
Peak memory 200080 kb
Host smart-038c1ac4-b553-4ffb-8a9b-afbd536a3a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141283329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.1141283329
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.1573289319
Short name T209
Test name
Test status
Simulation time 2110396157 ps
CPU time 560.87 seconds
Started May 26 02:21:25 PM PDT 24
Finished May 26 02:30:47 PM PDT 24
Peak memory 714588 kb
Host smart-7c4437c0-391e-4671-bfea-ee41bb8fb061
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1573289319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1573289319
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_long_msg.471744168
Short name T241
Test name
Test status
Simulation time 4704932554 ps
CPU time 62.32 seconds
Started May 26 02:21:29 PM PDT 24
Finished May 26 02:22:32 PM PDT 24
Peak memory 200232 kb
Host smart-38a9143e-9288-48b0-8b07-5623a9a2334d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471744168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.471744168
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.4068092146
Short name T397
Test name
Test status
Simulation time 2498942629 ps
CPU time 13.04 seconds
Started May 26 02:21:23 PM PDT 24
Finished May 26 02:21:36 PM PDT 24
Peak memory 200240 kb
Host smart-40d3fb48-6830-4d51-b4ff-1e1aaf858ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068092146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.4068092146
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.2726620269
Short name T205
Test name
Test status
Simulation time 146069941 ps
CPU time 1.49 seconds
Started May 26 02:21:21 PM PDT 24
Finished May 26 02:21:23 PM PDT 24
Peak memory 200068 kb
Host smart-0f961143-413b-4348-ae43-0ae9333e1b3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726620269 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.2726620269
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.2475849732
Short name T18
Test name
Test status
Simulation time 17536452743 ps
CPU time 481.37 seconds
Started May 26 02:21:27 PM PDT 24
Finished May 26 02:29:29 PM PDT 24
Peak memory 200116 kb
Host smart-cbef20c0-29b6-469a-889b-2327136f1013
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475849732 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.2475849732
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2505038054
Short name T451
Test name
Test status
Simulation time 10313725340 ps
CPU time 82.76 seconds
Started May 26 02:21:27 PM PDT 24
Finished May 26 02:22:51 PM PDT 24
Peak memory 200304 kb
Host smart-4f4019bb-30b1-433a-9e1d-9950c4dde91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505038054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2505038054
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.540851424
Short name T246
Test name
Test status
Simulation time 13957853 ps
CPU time 0.57 seconds
Started May 26 02:21:21 PM PDT 24
Finished May 26 02:21:22 PM PDT 24
Peak memory 194996 kb
Host smart-b33519e8-c4be-4774-994f-5b31d09d10fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540851424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.540851424
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.175403427
Short name T522
Test name
Test status
Simulation time 698268561 ps
CPU time 29.72 seconds
Started May 26 02:21:26 PM PDT 24
Finished May 26 02:21:56 PM PDT 24
Peak memory 208460 kb
Host smart-8cb498cc-0f08-420e-98ea-e8be6f9efdd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=175403427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.175403427
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3183604107
Short name T39
Test name
Test status
Simulation time 2282407720 ps
CPU time 35.4 seconds
Started May 26 02:21:25 PM PDT 24
Finished May 26 02:22:01 PM PDT 24
Peak memory 200252 kb
Host smart-76c88b78-cdef-4664-96eb-af857f36da57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183604107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3183604107
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.536470137
Short name T440
Test name
Test status
Simulation time 2681089084 ps
CPU time 571.48 seconds
Started May 26 02:21:21 PM PDT 24
Finished May 26 02:30:53 PM PDT 24
Peak memory 686996 kb
Host smart-55d45d35-4c2f-46d7-899b-7121bcf27b0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=536470137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.536470137
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2629466905
Short name T224
Test name
Test status
Simulation time 11048403563 ps
CPU time 34.6 seconds
Started May 26 02:21:25 PM PDT 24
Finished May 26 02:22:01 PM PDT 24
Peak memory 200088 kb
Host smart-4bbb0030-9dd3-4527-946d-c405104201f6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629466905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2629466905
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3887665098
Short name T315
Test name
Test status
Simulation time 23892237576 ps
CPU time 118.43 seconds
Started May 26 02:21:24 PM PDT 24
Finished May 26 02:23:23 PM PDT 24
Peak memory 200200 kb
Host smart-c67382d1-f71b-4d83-9c54-387e3e83d4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887665098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3887665098
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.3975850585
Short name T475
Test name
Test status
Simulation time 194054571 ps
CPU time 3.3 seconds
Started May 26 02:21:19 PM PDT 24
Finished May 26 02:21:23 PM PDT 24
Peak memory 200124 kb
Host smart-b82c9be9-c79c-420f-b31f-603747364b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975850585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3975850585
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1314415019
Short name T359
Test name
Test status
Simulation time 80297865236 ps
CPU time 2075.46 seconds
Started May 26 02:21:23 PM PDT 24
Finished May 26 02:56:00 PM PDT 24
Peak memory 779044 kb
Host smart-5ca77a4f-91cc-459f-9e74-1e47645f667a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314415019 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1314415019
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.1568211313
Short name T264
Test name
Test status
Simulation time 45288030 ps
CPU time 1.11 seconds
Started May 26 02:21:30 PM PDT 24
Finished May 26 02:21:32 PM PDT 24
Peak memory 199316 kb
Host smart-b8e79c7a-31b5-44c8-9c54-730c83596aa5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568211313 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.1568211313
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.556659994
Short name T520
Test name
Test status
Simulation time 182093757093 ps
CPU time 453.48 seconds
Started May 26 02:21:20 PM PDT 24
Finished May 26 02:28:54 PM PDT 24
Peak memory 200100 kb
Host smart-dbf38b02-fd1b-48a3-84f2-02f752bf789a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556659994 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.556659994
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.687878434
Short name T488
Test name
Test status
Simulation time 552442699 ps
CPU time 4.41 seconds
Started May 26 02:21:25 PM PDT 24
Finished May 26 02:21:30 PM PDT 24
Peak memory 200108 kb
Host smart-843f8e8c-988a-4cec-a506-a41de45e12b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687878434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.687878434
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.890043542
Short name T454
Test name
Test status
Simulation time 13409084 ps
CPU time 0.59 seconds
Started May 26 02:21:31 PM PDT 24
Finished May 26 02:21:32 PM PDT 24
Peak memory 196752 kb
Host smart-e114e32f-001b-4a13-a395-e9da42152c68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890043542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.890043542
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1249388997
Short name T376
Test name
Test status
Simulation time 7709439312 ps
CPU time 31.11 seconds
Started May 26 02:21:22 PM PDT 24
Finished May 26 02:21:54 PM PDT 24
Peak memory 215756 kb
Host smart-b04059d4-a528-4022-a80a-f095620b35b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1249388997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1249388997
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.69679505
Short name T267
Test name
Test status
Simulation time 76565423 ps
CPU time 2.25 seconds
Started May 26 02:21:31 PM PDT 24
Finished May 26 02:21:34 PM PDT 24
Peak memory 200076 kb
Host smart-a935b193-5b04-404a-aac2-4fbfc854c47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69679505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.69679505
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2715876448
Short name T169
Test name
Test status
Simulation time 772068369 ps
CPU time 18.82 seconds
Started May 26 02:21:25 PM PDT 24
Finished May 26 02:21:45 PM PDT 24
Peak memory 233052 kb
Host smart-46313f28-5fc9-4266-ad6f-7a4b06c2ad45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2715876448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2715876448
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1787474845
Short name T185
Test name
Test status
Simulation time 1655022142 ps
CPU time 100.11 seconds
Started May 26 02:21:31 PM PDT 24
Finished May 26 02:23:12 PM PDT 24
Peak memory 200188 kb
Host smart-69c44217-d221-454d-881a-7ca3777ac8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787474845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1787474845
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.3453131232
Short name T55
Test name
Test status
Simulation time 143309206 ps
CPU time 4.81 seconds
Started May 26 02:21:27 PM PDT 24
Finished May 26 02:21:32 PM PDT 24
Peak memory 200156 kb
Host smart-1dec4958-ff53-4fdc-aff3-81b1713e6b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453131232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.3453131232
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.4041805269
Short name T370
Test name
Test status
Simulation time 305817522 ps
CPU time 1.46 seconds
Started May 26 02:21:28 PM PDT 24
Finished May 26 02:21:31 PM PDT 24
Peak memory 200100 kb
Host smart-e0ffcc85-77a2-4835-9c8f-df8ac84f0249
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041805269 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.4041805269
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.2428588972
Short name T242
Test name
Test status
Simulation time 7967029606 ps
CPU time 467.41 seconds
Started May 26 02:21:28 PM PDT 24
Finished May 26 02:29:16 PM PDT 24
Peak memory 200104 kb
Host smart-21e37325-967d-4802-a1a4-923fd99f4d21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428588972 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.2428588972
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1425117234
Short name T453
Test name
Test status
Simulation time 1037618259 ps
CPU time 23.03 seconds
Started May 26 02:21:33 PM PDT 24
Finished May 26 02:21:57 PM PDT 24
Peak memory 200156 kb
Host smart-50cfc508-5994-4d2f-b18c-74dcadf0972d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425117234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1425117234
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.483689296
Short name T343
Test name
Test status
Simulation time 18723700 ps
CPU time 0.59 seconds
Started May 26 02:21:27 PM PDT 24
Finished May 26 02:21:28 PM PDT 24
Peak memory 195056 kb
Host smart-ea1dcc0e-9476-4b8b-b2f2-3a238a011c53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483689296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.483689296
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3493778124
Short name T512
Test name
Test status
Simulation time 4868082625 ps
CPU time 19.6 seconds
Started May 26 02:21:31 PM PDT 24
Finished May 26 02:21:52 PM PDT 24
Peak memory 223288 kb
Host smart-605faacd-4a19-46dd-b6fd-961cc85217e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3493778124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3493778124
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.4065315175
Short name T99
Test name
Test status
Simulation time 2317971425 ps
CPU time 45.13 seconds
Started May 26 02:21:22 PM PDT 24
Finished May 26 02:22:08 PM PDT 24
Peak memory 200192 kb
Host smart-4a0c775e-0795-4efd-aa16-3b134b03d451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065315175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.4065315175
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2272707257
Short name T101
Test name
Test status
Simulation time 3585267398 ps
CPU time 863.3 seconds
Started May 26 02:21:28 PM PDT 24
Finished May 26 02:35:52 PM PDT 24
Peak memory 758680 kb
Host smart-86497a57-b6fe-498d-99e4-afc3c5c4d3a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2272707257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2272707257
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.2106054389
Short name T335
Test name
Test status
Simulation time 545570196 ps
CPU time 31.82 seconds
Started May 26 02:21:29 PM PDT 24
Finished May 26 02:22:01 PM PDT 24
Peak memory 200104 kb
Host smart-30ce6148-8c1a-4c15-bc8a-2dbd333cbe2b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106054389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2106054389
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.1800603686
Short name T419
Test name
Test status
Simulation time 4449772383 ps
CPU time 82.33 seconds
Started May 26 02:21:24 PM PDT 24
Finished May 26 02:22:47 PM PDT 24
Peak memory 200116 kb
Host smart-73bbe7df-3238-479e-a317-05c9d5d92d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800603686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1800603686
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.396119299
Short name T394
Test name
Test status
Simulation time 546288965 ps
CPU time 5.74 seconds
Started May 26 02:21:25 PM PDT 24
Finished May 26 02:21:31 PM PDT 24
Peak memory 200128 kb
Host smart-a5bcfd05-fe9e-4a25-9a2c-91ce784cc986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396119299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.396119299
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.1952219638
Short name T74
Test name
Test status
Simulation time 33259091215 ps
CPU time 121.43 seconds
Started May 26 02:21:27 PM PDT 24
Finished May 26 02:23:29 PM PDT 24
Peak memory 208456 kb
Host smart-16059d66-a2ee-445f-9c71-8696cd48cb62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952219638 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.1952219638
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.1832567261
Short name T154
Test name
Test status
Simulation time 50961206 ps
CPU time 0.99 seconds
Started May 26 02:21:27 PM PDT 24
Finished May 26 02:21:29 PM PDT 24
Peak memory 199644 kb
Host smart-37d4068e-2478-4db1-a418-2190e5f70f47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832567261 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.1832567261
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.4118270802
Short name T44
Test name
Test status
Simulation time 150959930751 ps
CPU time 534.96 seconds
Started May 26 02:21:24 PM PDT 24
Finished May 26 02:30:20 PM PDT 24
Peak memory 200048 kb
Host smart-96e90931-1c44-47d7-aa16-c621fc2ccf9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118270802 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.4118270802
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1200234702
Short name T435
Test name
Test status
Simulation time 3871102168 ps
CPU time 28.43 seconds
Started May 26 02:21:28 PM PDT 24
Finished May 26 02:21:58 PM PDT 24
Peak memory 200176 kb
Host smart-3f2a4ab8-84c3-440a-bba7-5a5a09679058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200234702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1200234702
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1272799667
Short name T270
Test name
Test status
Simulation time 12914910 ps
CPU time 0.59 seconds
Started May 26 02:21:31 PM PDT 24
Finished May 26 02:21:33 PM PDT 24
Peak memory 195004 kb
Host smart-137d2212-c7d4-4f48-a683-7f56f967014b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272799667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1272799667
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.3483081740
Short name T509
Test name
Test status
Simulation time 1067437430 ps
CPU time 24.49 seconds
Started May 26 02:21:29 PM PDT 24
Finished May 26 02:21:54 PM PDT 24
Peak memory 200156 kb
Host smart-7f2f6585-5294-4dc5-803f-7f821545b8bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3483081740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.3483081740
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.596280681
Short name T164
Test name
Test status
Simulation time 1515348151 ps
CPU time 21.69 seconds
Started May 26 02:21:24 PM PDT 24
Finished May 26 02:21:46 PM PDT 24
Peak memory 200056 kb
Host smart-a1ef3982-7300-41c4-9e91-d1c0b0a4777c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596280681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.596280681
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3846552397
Short name T377
Test name
Test status
Simulation time 9212267220 ps
CPU time 530.65 seconds
Started May 26 02:21:23 PM PDT 24
Finished May 26 02:30:14 PM PDT 24
Peak memory 479584 kb
Host smart-d1eb95ec-0a85-407a-99d5-35072492a691
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3846552397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3846552397
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.798520107
Short name T363
Test name
Test status
Simulation time 2589574928 ps
CPU time 48.71 seconds
Started May 26 02:21:32 PM PDT 24
Finished May 26 02:22:21 PM PDT 24
Peak memory 200164 kb
Host smart-bd596b53-da69-4cdf-a839-27847587661b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798520107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.798520107
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.2341545747
Short name T334
Test name
Test status
Simulation time 5409943333 ps
CPU time 83.42 seconds
Started May 26 02:21:26 PM PDT 24
Finished May 26 02:22:50 PM PDT 24
Peak memory 200344 kb
Host smart-981990b9-7104-4d6b-920d-d4a963c6aeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341545747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2341545747
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.1983089713
Short name T38
Test name
Test status
Simulation time 1877554765 ps
CPU time 11.24 seconds
Started May 26 02:21:22 PM PDT 24
Finished May 26 02:21:34 PM PDT 24
Peak memory 200116 kb
Host smart-f265dda1-22f4-4ca1-bbe7-1de3e8ead1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983089713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1983089713
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.899690627
Short name T210
Test name
Test status
Simulation time 28104727558 ps
CPU time 531.6 seconds
Started May 26 02:21:33 PM PDT 24
Finished May 26 02:30:25 PM PDT 24
Peak memory 200156 kb
Host smart-7d7c15a7-b70f-4a55-ae02-ff3551d73503
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899690627 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.899690627
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.1003826332
Short name T140
Test name
Test status
Simulation time 2322587996 ps
CPU time 9.04 seconds
Started May 26 02:21:30 PM PDT 24
Finished May 26 02:21:40 PM PDT 24
Peak memory 200176 kb
Host smart-1a08b1af-68e6-433f-b2c3-6dd097c9114a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003826332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1003826332
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1302491760
Short name T523
Test name
Test status
Simulation time 12167655 ps
CPU time 0.6 seconds
Started May 26 02:21:42 PM PDT 24
Finished May 26 02:21:44 PM PDT 24
Peak memory 196072 kb
Host smart-10072689-2625-4d7a-bc97-40036e55f2af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302491760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1302491760
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.86229044
Short name T192
Test name
Test status
Simulation time 392665265 ps
CPU time 17.85 seconds
Started May 26 02:21:34 PM PDT 24
Finished May 26 02:21:53 PM PDT 24
Peak memory 208324 kb
Host smart-3dc9db71-67dc-4a2d-9f6c-aa9c2e17661f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=86229044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.86229044
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.3849457961
Short name T457
Test name
Test status
Simulation time 5074792388 ps
CPU time 55.25 seconds
Started May 26 02:21:35 PM PDT 24
Finished May 26 02:22:31 PM PDT 24
Peak memory 200204 kb
Host smart-584ae914-9f8c-4b4f-995a-5936d8165169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849457961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.3849457961
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.4259882295
Short name T416
Test name
Test status
Simulation time 13945221360 ps
CPU time 786.41 seconds
Started May 26 02:21:35 PM PDT 24
Finished May 26 02:34:42 PM PDT 24
Peak memory 684140 kb
Host smart-d0d36910-2278-4678-910b-292f5f784154
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4259882295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.4259882295
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.667133159
Short name T339
Test name
Test status
Simulation time 9692281075 ps
CPU time 125 seconds
Started May 26 02:21:31 PM PDT 24
Finished May 26 02:23:37 PM PDT 24
Peak memory 200200 kb
Host smart-33b9ec28-0822-4907-aceb-579c882b44cf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667133159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.667133159
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1860052591
Short name T252
Test name
Test status
Simulation time 2286099242 ps
CPU time 65.33 seconds
Started May 26 02:21:41 PM PDT 24
Finished May 26 02:22:48 PM PDT 24
Peak memory 200172 kb
Host smart-76cf8adf-84c9-4304-827c-bd7c51dc7f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860052591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1860052591
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1334846009
Short name T216
Test name
Test status
Simulation time 4286219453 ps
CPU time 23.68 seconds
Started May 26 02:21:30 PM PDT 24
Finished May 26 02:21:54 PM PDT 24
Peak memory 200192 kb
Host smart-632525c4-adf1-40e0-9a77-c00813e38f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334846009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1334846009
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.1617468196
Short name T308
Test name
Test status
Simulation time 31143388357 ps
CPU time 441.81 seconds
Started May 26 02:21:39 PM PDT 24
Finished May 26 02:29:01 PM PDT 24
Peak memory 200148 kb
Host smart-95d6755e-0cd3-4721-9a82-be17acfc2059
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617468196 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.1617468196
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.656594580
Short name T226
Test name
Test status
Simulation time 8682222573 ps
CPU time 30.39 seconds
Started May 26 02:21:31 PM PDT 24
Finished May 26 02:22:02 PM PDT 24
Peak memory 200152 kb
Host smart-2aca1938-ae76-4297-bd94-a75bfa567011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656594580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.656594580
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1299398581
Short name T375
Test name
Test status
Simulation time 42815412 ps
CPU time 0.65 seconds
Started May 26 02:21:00 PM PDT 24
Finished May 26 02:21:02 PM PDT 24
Peak memory 195632 kb
Host smart-c35038d2-5a8e-4ef8-aaf7-56995365b9bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299398581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1299398581
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1008148016
Short name T53
Test name
Test status
Simulation time 862799436 ps
CPU time 10.71 seconds
Started May 26 02:20:50 PM PDT 24
Finished May 26 02:21:02 PM PDT 24
Peak memory 215856 kb
Host smart-32016845-94ee-40f4-bed7-f6ccdf824b0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1008148016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1008148016
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.4059721550
Short name T524
Test name
Test status
Simulation time 1020591945 ps
CPU time 52.91 seconds
Started May 26 02:20:55 PM PDT 24
Finished May 26 02:21:49 PM PDT 24
Peak memory 200112 kb
Host smart-aa6becc1-9213-4768-ae50-82701c6e3d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059721550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.4059721550
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.663507689
Short name T145
Test name
Test status
Simulation time 8314333676 ps
CPU time 935.84 seconds
Started May 26 02:20:52 PM PDT 24
Finished May 26 02:36:29 PM PDT 24
Peak memory 745256 kb
Host smart-a3e25495-5c93-44d8-911a-9642e7713d51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=663507689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.663507689
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3199985821
Short name T514
Test name
Test status
Simulation time 1144823106 ps
CPU time 15.47 seconds
Started May 26 02:20:53 PM PDT 24
Finished May 26 02:21:10 PM PDT 24
Peak memory 200004 kb
Host smart-c1b965d1-5f3e-4db7-8144-be9761336c64
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199985821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3199985821
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3693043190
Short name T324
Test name
Test status
Simulation time 339316366 ps
CPU time 19.4 seconds
Started May 26 02:20:53 PM PDT 24
Finished May 26 02:21:13 PM PDT 24
Peak memory 200264 kb
Host smart-3dd03d33-5535-4a96-9694-74fb824e0a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693043190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3693043190
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.853057399
Short name T36
Test name
Test status
Simulation time 346483743 ps
CPU time 1.01 seconds
Started May 26 02:20:53 PM PDT 24
Finished May 26 02:20:56 PM PDT 24
Peak memory 219276 kb
Host smart-047bc33d-9308-4935-b5a9-ff73b04671a7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853057399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.853057399
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.530285338
Short name T197
Test name
Test status
Simulation time 261900839 ps
CPU time 2.7 seconds
Started May 26 02:20:54 PM PDT 24
Finished May 26 02:20:58 PM PDT 24
Peak memory 200180 kb
Host smart-d43a6a2a-5067-4379-9429-2a609105b18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530285338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.530285338
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.364497622
Short name T368
Test name
Test status
Simulation time 7389473773 ps
CPU time 28.07 seconds
Started May 26 02:20:51 PM PDT 24
Finished May 26 02:21:20 PM PDT 24
Peak memory 224816 kb
Host smart-7a75da48-2c2c-4ce1-9323-49c33a4487ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364497622 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.364497622
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.1076019888
Short name T443
Test name
Test status
Simulation time 200337741 ps
CPU time 0.92 seconds
Started May 26 02:20:51 PM PDT 24
Finished May 26 02:20:53 PM PDT 24
Peak memory 199140 kb
Host smart-d842d1a1-5ee9-4f8f-9c28-724e2d9df140
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076019888 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.1076019888
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.2834525915
Short name T215
Test name
Test status
Simulation time 125204478474 ps
CPU time 426.59 seconds
Started May 26 02:20:55 PM PDT 24
Finished May 26 02:28:03 PM PDT 24
Peak memory 200152 kb
Host smart-9f175799-0884-49c1-90b1-aedf37cc7749
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834525915 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.2834525915
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2797424787
Short name T406
Test name
Test status
Simulation time 14253157 ps
CPU time 0.65 seconds
Started May 26 02:21:34 PM PDT 24
Finished May 26 02:21:35 PM PDT 24
Peak memory 195476 kb
Host smart-c08cf0c8-32ea-49ba-be77-14aae6b9cfe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797424787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2797424787
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2209533894
Short name T257
Test name
Test status
Simulation time 414158700 ps
CPU time 20.64 seconds
Started May 26 02:21:32 PM PDT 24
Finished May 26 02:21:54 PM PDT 24
Peak memory 208356 kb
Host smart-1a0a64cd-6b00-4222-8f4f-cd605cc87700
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2209533894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2209533894
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2286829592
Short name T417
Test name
Test status
Simulation time 843902879 ps
CPU time 9.14 seconds
Started May 26 02:21:36 PM PDT 24
Finished May 26 02:21:45 PM PDT 24
Peak memory 200140 kb
Host smart-a5de5ba7-571f-4f2a-86c2-05c78ab132c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286829592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2286829592
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.2887557836
Short name T151
Test name
Test status
Simulation time 3179290547 ps
CPU time 737.5 seconds
Started May 26 02:21:36 PM PDT 24
Finished May 26 02:33:54 PM PDT 24
Peak memory 695996 kb
Host smart-26488e47-6e09-48fc-a871-facf86629946
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2887557836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2887557836
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2152093193
Short name T258
Test name
Test status
Simulation time 1714871267 ps
CPU time 102.52 seconds
Started May 26 02:21:31 PM PDT 24
Finished May 26 02:23:15 PM PDT 24
Peak memory 200100 kb
Host smart-0ec7864d-a765-429d-9c5a-279d27882811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152093193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2152093193
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.175453719
Short name T310
Test name
Test status
Simulation time 676828166 ps
CPU time 6.12 seconds
Started May 26 02:21:32 PM PDT 24
Finished May 26 02:21:39 PM PDT 24
Peak memory 199984 kb
Host smart-124e1190-6a52-4511-a544-97dd5b856b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175453719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.175453719
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.3829005931
Short name T365
Test name
Test status
Simulation time 254792398 ps
CPU time 1.24 seconds
Started May 26 02:21:35 PM PDT 24
Finished May 26 02:21:37 PM PDT 24
Peak memory 200092 kb
Host smart-8a945bdb-9b43-42be-9b05-8940bc03d7ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829005931 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.3829005931
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.2005977007
Short name T223
Test name
Test status
Simulation time 8635897026 ps
CPU time 491.99 seconds
Started May 26 02:21:30 PM PDT 24
Finished May 26 02:29:43 PM PDT 24
Peak memory 200124 kb
Host smart-46afe6d6-4446-4f08-9a9d-30f89874f829
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005977007 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.2005977007
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.416555043
Short name T345
Test name
Test status
Simulation time 23913428820 ps
CPU time 89.03 seconds
Started May 26 02:21:34 PM PDT 24
Finished May 26 02:23:03 PM PDT 24
Peak memory 200172 kb
Host smart-d2997cdc-77c4-4057-aead-3f9286acdf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416555043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.416555043
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3624373985
Short name T477
Test name
Test status
Simulation time 213171432 ps
CPU time 0.61 seconds
Started May 26 02:21:32 PM PDT 24
Finished May 26 02:21:34 PM PDT 24
Peak memory 196032 kb
Host smart-705f02ad-6333-4ee7-9e13-867988b24821
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624373985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3624373985
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.912120751
Short name T441
Test name
Test status
Simulation time 1199700929 ps
CPU time 63.31 seconds
Started May 26 02:21:32 PM PDT 24
Finished May 26 02:22:37 PM PDT 24
Peak memory 224684 kb
Host smart-fe11dc56-63a2-4f38-867e-1c92ea889516
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=912120751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.912120751
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.4180314968
Short name T289
Test name
Test status
Simulation time 2243803107 ps
CPU time 11.54 seconds
Started May 26 02:21:34 PM PDT 24
Finished May 26 02:21:46 PM PDT 24
Peak memory 200140 kb
Host smart-35ed8f4d-a1a7-44b3-818c-bb6f035a3fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180314968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.4180314968
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1618370263
Short name T265
Test name
Test status
Simulation time 6561552041 ps
CPU time 267.62 seconds
Started May 26 02:21:41 PM PDT 24
Finished May 26 02:26:10 PM PDT 24
Peak memory 633980 kb
Host smart-836df2c7-355a-4434-8727-d667bd882c61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1618370263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1618370263
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.75672029
Short name T519
Test name
Test status
Simulation time 9317665115 ps
CPU time 46.87 seconds
Started May 26 02:21:33 PM PDT 24
Finished May 26 02:22:21 PM PDT 24
Peak memory 200120 kb
Host smart-fd035c5c-90b2-428d-bc7e-52184ca2e21f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75672029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.75672029
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1780500916
Short name T351
Test name
Test status
Simulation time 5255998020 ps
CPU time 101.16 seconds
Started May 26 02:21:40 PM PDT 24
Finished May 26 02:23:23 PM PDT 24
Peak memory 200252 kb
Host smart-f5dbe73f-e8bb-49f8-a57e-7d6cb46b363b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780500916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1780500916
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.1986053236
Short name T391
Test name
Test status
Simulation time 1687690845 ps
CPU time 4.88 seconds
Started May 26 02:21:30 PM PDT 24
Finished May 26 02:21:35 PM PDT 24
Peak memory 200132 kb
Host smart-f6d27ceb-2e83-42c8-95da-03b54b7fb145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986053236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.1986053236
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.4288536393
Short name T280
Test name
Test status
Simulation time 53197179 ps
CPU time 1.24 seconds
Started May 26 02:21:38 PM PDT 24
Finished May 26 02:21:40 PM PDT 24
Peak memory 200128 kb
Host smart-27573892-ec27-4f6b-9302-b535925239c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288536393 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.4288536393
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.184560732
Short name T176
Test name
Test status
Simulation time 116091369981 ps
CPU time 505.93 seconds
Started May 26 02:21:34 PM PDT 24
Finished May 26 02:30:01 PM PDT 24
Peak memory 199976 kb
Host smart-c01fe0bc-796f-4020-b72f-9bb15ea05f3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184560732 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.184560732
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.4133289041
Short name T424
Test name
Test status
Simulation time 2581030648 ps
CPU time 94.87 seconds
Started May 26 02:21:30 PM PDT 24
Finished May 26 02:23:06 PM PDT 24
Peak memory 200124 kb
Host smart-259f4cb7-6475-45aa-9e99-73ddcdf9501a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133289041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.4133289041
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1513523921
Short name T235
Test name
Test status
Simulation time 11444420 ps
CPU time 0.58 seconds
Started May 26 02:21:41 PM PDT 24
Finished May 26 02:21:44 PM PDT 24
Peak memory 195004 kb
Host smart-e35ff851-e884-42a2-b4a4-56a2b458cf8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513523921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1513523921
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.1222252555
Short name T12
Test name
Test status
Simulation time 191262663 ps
CPU time 8.82 seconds
Started May 26 02:21:47 PM PDT 24
Finished May 26 02:21:57 PM PDT 24
Peak memory 208272 kb
Host smart-1193f13a-297c-46cf-b8a4-a4019be86325
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1222252555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.1222252555
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.680970391
Short name T431
Test name
Test status
Simulation time 1655277454 ps
CPU time 24.42 seconds
Started May 26 02:21:48 PM PDT 24
Finished May 26 02:22:13 PM PDT 24
Peak memory 200116 kb
Host smart-8eb1e3c5-6b22-4895-9c27-bc7fb7e74ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680970391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.680970391
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.2609051264
Short name T427
Test name
Test status
Simulation time 1401138554 ps
CPU time 162.45 seconds
Started May 26 02:21:43 PM PDT 24
Finished May 26 02:24:26 PM PDT 24
Peak memory 439052 kb
Host smart-3f918d37-1e0e-402c-a9c0-832cb501620c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2609051264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2609051264
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2164202387
Short name T148
Test name
Test status
Simulation time 1480701832 ps
CPU time 20.72 seconds
Started May 26 02:21:39 PM PDT 24
Finished May 26 02:22:01 PM PDT 24
Peak memory 200124 kb
Host smart-677b2039-7f42-4dc0-b89f-6d3db17dd2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164202387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2164202387
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2942257687
Short name T352
Test name
Test status
Simulation time 962226057 ps
CPU time 5.41 seconds
Started May 26 02:21:39 PM PDT 24
Finished May 26 02:21:45 PM PDT 24
Peak memory 200124 kb
Host smart-69099c20-e90d-4e5c-9dee-75477700725b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942257687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2942257687
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.2319303069
Short name T401
Test name
Test status
Simulation time 57893560981 ps
CPU time 520.06 seconds
Started May 26 02:21:38 PM PDT 24
Finished May 26 02:30:19 PM PDT 24
Peak memory 200148 kb
Host smart-f7a6af8f-ff22-4c7d-b32d-f3b20b6b176e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319303069 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.2319303069
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.5742594
Short name T302
Test name
Test status
Simulation time 677533848 ps
CPU time 23.6 seconds
Started May 26 02:21:41 PM PDT 24
Finished May 26 02:22:06 PM PDT 24
Peak memory 199988 kb
Host smart-9b53f9f0-7549-4697-b9e8-1c4c1a6f0af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5742594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.5742594
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.914083164
Short name T478
Test name
Test status
Simulation time 32765708 ps
CPU time 0.59 seconds
Started May 26 02:21:41 PM PDT 24
Finished May 26 02:21:44 PM PDT 24
Peak memory 195736 kb
Host smart-1dbc61c2-4b66-4be1-a302-e334c89a9023
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914083164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.914083164
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1989231708
Short name T429
Test name
Test status
Simulation time 4311335995 ps
CPU time 63.96 seconds
Started May 26 02:21:40 PM PDT 24
Finished May 26 02:22:45 PM PDT 24
Peak memory 226576 kb
Host smart-e551862f-88bf-425a-92e5-3819d76a6eaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1989231708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1989231708
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.2761726099
Short name T338
Test name
Test status
Simulation time 3605937105 ps
CPU time 25.34 seconds
Started May 26 02:21:40 PM PDT 24
Finished May 26 02:22:06 PM PDT 24
Peak memory 200192 kb
Host smart-47b64995-930c-480a-b2bd-4a3c62ee2ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761726099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2761726099
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.3507693822
Short name T425
Test name
Test status
Simulation time 1702899243 ps
CPU time 477.08 seconds
Started May 26 02:21:39 PM PDT 24
Finished May 26 02:29:37 PM PDT 24
Peak memory 650248 kb
Host smart-c7475798-90c9-4ccf-8538-f76a37c718c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3507693822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.3507693822
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2380885971
Short name T482
Test name
Test status
Simulation time 12143558716 ps
CPU time 103.4 seconds
Started May 26 02:21:41 PM PDT 24
Finished May 26 02:23:26 PM PDT 24
Peak memory 200152 kb
Host smart-7e345ce5-aac1-4c38-b965-4ab560f5b0b0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380885971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2380885971
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3067017678
Short name T84
Test name
Test status
Simulation time 1262708209 ps
CPU time 69.66 seconds
Started May 26 02:21:40 PM PDT 24
Finished May 26 02:22:51 PM PDT 24
Peak memory 200164 kb
Host smart-7670b6d3-a949-4fd3-af5d-5ffcf140a700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067017678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3067017678
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2049751496
Short name T54
Test name
Test status
Simulation time 13637867 ps
CPU time 0.62 seconds
Started May 26 02:21:40 PM PDT 24
Finished May 26 02:21:41 PM PDT 24
Peak memory 196352 kb
Host smart-1e21eedc-088e-4aca-88f0-fe86b271ecef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049751496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2049751496
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.2631726323
Short name T398
Test name
Test status
Simulation time 239734574 ps
CPU time 0.99 seconds
Started May 26 02:21:48 PM PDT 24
Finished May 26 02:21:50 PM PDT 24
Peak memory 199948 kb
Host smart-b431fd41-31ca-4151-82c6-3815308a8aed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631726323 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.2631726323
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.3875997650
Short name T467
Test name
Test status
Simulation time 74863101875 ps
CPU time 469.74 seconds
Started May 26 02:21:42 PM PDT 24
Finished May 26 02:29:33 PM PDT 24
Peak memory 200116 kb
Host smart-35e5db54-8ee3-4816-a4ed-129e4a65a947
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875997650 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.3875997650
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2833804423
Short name T511
Test name
Test status
Simulation time 4107112520 ps
CPU time 81.6 seconds
Started May 26 02:21:45 PM PDT 24
Finished May 26 02:23:08 PM PDT 24
Peak memory 200156 kb
Host smart-9c182264-9d8a-46c5-9f80-d107538b318c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833804423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2833804423
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2346227391
Short name T240
Test name
Test status
Simulation time 14609851 ps
CPU time 0.63 seconds
Started May 26 02:21:44 PM PDT 24
Finished May 26 02:21:46 PM PDT 24
Peak memory 196016 kb
Host smart-6ff2fb41-4ac1-46b0-8a2c-0e1949ad522c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346227391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2346227391
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.4196561463
Short name T438
Test name
Test status
Simulation time 951258306 ps
CPU time 40.01 seconds
Started May 26 02:21:41 PM PDT 24
Finished May 26 02:22:23 PM PDT 24
Peak memory 215848 kb
Host smart-c416dc88-c4f0-4e7a-8d8b-78dab2c24863
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4196561463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.4196561463
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2428044581
Short name T498
Test name
Test status
Simulation time 1083866571 ps
CPU time 29.16 seconds
Started May 26 02:21:42 PM PDT 24
Finished May 26 02:22:13 PM PDT 24
Peak memory 200096 kb
Host smart-e7fb6dc2-a915-4d07-b8b7-54e5c2d009fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428044581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2428044581
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.2764521847
Short name T316
Test name
Test status
Simulation time 2689186802 ps
CPU time 690.25 seconds
Started May 26 02:21:41 PM PDT 24
Finished May 26 02:33:13 PM PDT 24
Peak memory 700284 kb
Host smart-3ad3fdea-2c35-4c57-b7e0-c4d8a3d5cc9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2764521847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.2764521847
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.1256559880
Short name T14
Test name
Test status
Simulation time 929332698 ps
CPU time 27.91 seconds
Started May 26 02:21:41 PM PDT 24
Finished May 26 02:22:10 PM PDT 24
Peak memory 200176 kb
Host smart-1133dc07-0920-48b2-9c5b-30d7b60be610
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256559880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1256559880
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.3184332777
Short name T400
Test name
Test status
Simulation time 835167904 ps
CPU time 50.91 seconds
Started May 26 02:21:44 PM PDT 24
Finished May 26 02:22:36 PM PDT 24
Peak memory 200128 kb
Host smart-39c063b2-ac01-4375-88f9-c17c31b8fa4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184332777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3184332777
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2389025279
Short name T311
Test name
Test status
Simulation time 1191023538 ps
CPU time 7.8 seconds
Started May 26 02:21:44 PM PDT 24
Finished May 26 02:21:53 PM PDT 24
Peak memory 200128 kb
Host smart-305ec3a1-a072-4b1e-bd97-415925b466bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389025279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2389025279
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.4141679575
Short name T109
Test name
Test status
Simulation time 16294494479 ps
CPU time 439.34 seconds
Started May 26 02:21:41 PM PDT 24
Finished May 26 02:29:02 PM PDT 24
Peak memory 199896 kb
Host smart-5ac1bf28-5d4e-4b40-a8e6-48d7657c6b99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141679575 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.4141679575
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.839728540
Short name T321
Test name
Test status
Simulation time 2005662136 ps
CPU time 85.33 seconds
Started May 26 02:21:41 PM PDT 24
Finished May 26 02:23:08 PM PDT 24
Peak memory 200104 kb
Host smart-dd9fd700-55c5-41f7-94da-70124158c994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839728540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.839728540
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.858072418
Short name T383
Test name
Test status
Simulation time 16339677 ps
CPU time 0.66 seconds
Started May 26 02:21:45 PM PDT 24
Finished May 26 02:21:47 PM PDT 24
Peak memory 196736 kb
Host smart-817f2759-f9f9-4a35-88c5-f53896d7dac5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858072418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.858072418
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3541278704
Short name T5
Test name
Test status
Simulation time 643956865 ps
CPU time 7.12 seconds
Started May 26 02:21:39 PM PDT 24
Finished May 26 02:21:47 PM PDT 24
Peak memory 216560 kb
Host smart-0952eb99-9388-427b-b419-6dc440a53a15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3541278704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3541278704
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.4089089040
Short name T462
Test name
Test status
Simulation time 668409659 ps
CPU time 32.51 seconds
Started May 26 02:21:41 PM PDT 24
Finished May 26 02:22:15 PM PDT 24
Peak memory 200128 kb
Host smart-e4ecbbd5-8bbc-4fe0-a082-b4d821fff871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089089040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.4089089040
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.4181289083
Short name T332
Test name
Test status
Simulation time 7593853390 ps
CPU time 369.73 seconds
Started May 26 02:21:47 PM PDT 24
Finished May 26 02:27:58 PM PDT 24
Peak memory 635616 kb
Host smart-4ce78925-5924-4ecc-841d-b341e21239b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4181289083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.4181289083
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.409728510
Short name T213
Test name
Test status
Simulation time 8610032605 ps
CPU time 39.03 seconds
Started May 26 02:21:42 PM PDT 24
Finished May 26 02:22:22 PM PDT 24
Peak memory 200172 kb
Host smart-c1a00b21-3bdf-4645-aebf-d00f2ab911bd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409728510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.409728510
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2668006351
Short name T13
Test name
Test status
Simulation time 2810099810 ps
CPU time 53.19 seconds
Started May 26 02:21:41 PM PDT 24
Finished May 26 02:22:36 PM PDT 24
Peak memory 199992 kb
Host smart-63afce5d-78c1-4b63-b121-24522644c3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668006351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2668006351
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.962705944
Short name T423
Test name
Test status
Simulation time 130030399 ps
CPU time 4.56 seconds
Started May 26 02:21:42 PM PDT 24
Finished May 26 02:21:48 PM PDT 24
Peak memory 200032 kb
Host smart-50820374-71bd-4f80-95fe-be149e1b8380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962705944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.962705944
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.1039743051
Short name T329
Test name
Test status
Simulation time 55051684 ps
CPU time 1.12 seconds
Started May 26 02:21:47 PM PDT 24
Finished May 26 02:21:49 PM PDT 24
Peak memory 200104 kb
Host smart-7e17afb0-6c86-4c3b-adbd-6f2c3cb5f0c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039743051 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.1039743051
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.1909960303
Short name T281
Test name
Test status
Simulation time 41732361928 ps
CPU time 560.8 seconds
Started May 26 02:21:43 PM PDT 24
Finished May 26 02:31:05 PM PDT 24
Peak memory 200156 kb
Host smart-f1f5a5e1-cc37-4568-884f-fd726342a3cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909960303 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.1909960303
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.4213145828
Short name T31
Test name
Test status
Simulation time 1578065766 ps
CPU time 20.74 seconds
Started May 26 02:21:40 PM PDT 24
Finished May 26 02:22:03 PM PDT 24
Peak memory 200132 kb
Host smart-f68b15e2-159f-4860-8cae-0301152b677b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213145828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.4213145828
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.849174413
Short name T134
Test name
Test status
Simulation time 22487642 ps
CPU time 0.57 seconds
Started May 26 02:21:52 PM PDT 24
Finished May 26 02:21:53 PM PDT 24
Peak memory 194852 kb
Host smart-4a43fefa-f1ce-408d-88b0-7d268cad60c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849174413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.849174413
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.1800607418
Short name T198
Test name
Test status
Simulation time 75881547 ps
CPU time 3.73 seconds
Started May 26 02:21:52 PM PDT 24
Finished May 26 02:21:56 PM PDT 24
Peak memory 208124 kb
Host smart-1cbe25a2-0af9-4b3d-b1a5-52ff812664b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1800607418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1800607418
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.3716826280
Short name T207
Test name
Test status
Simulation time 8577491674 ps
CPU time 33.02 seconds
Started May 26 02:21:47 PM PDT 24
Finished May 26 02:22:21 PM PDT 24
Peak memory 200160 kb
Host smart-ca0d2ce1-8864-4ed6-8c05-192fbdf13915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716826280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.3716826280
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1217244973
Short name T244
Test name
Test status
Simulation time 18085580063 ps
CPU time 1214.52 seconds
Started May 26 02:21:47 PM PDT 24
Finished May 26 02:42:03 PM PDT 24
Peak memory 798276 kb
Host smart-de65d0a6-0a3a-48c0-a22d-d1ff57b0d6a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1217244973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1217244973
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.2750361537
Short name T387
Test name
Test status
Simulation time 9786512631 ps
CPU time 188.46 seconds
Started May 26 02:21:47 PM PDT 24
Finished May 26 02:24:57 PM PDT 24
Peak memory 200176 kb
Host smart-7910f631-b752-42a0-93a1-c801c600ddb0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750361537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2750361537
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1785697127
Short name T121
Test name
Test status
Simulation time 546570088 ps
CPU time 32.86 seconds
Started May 26 02:21:46 PM PDT 24
Finished May 26 02:22:20 PM PDT 24
Peak memory 200176 kb
Host smart-548fd4da-d072-4f25-9769-de4ceac07edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785697127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1785697127
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.1397981029
Short name T139
Test name
Test status
Simulation time 200885492 ps
CPU time 2.06 seconds
Started May 26 02:21:45 PM PDT 24
Finished May 26 02:21:48 PM PDT 24
Peak memory 200184 kb
Host smart-253998f5-7b65-455e-b427-6a3907d3c01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397981029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1397981029
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.2678641723
Short name T132
Test name
Test status
Simulation time 294115548 ps
CPU time 1.22 seconds
Started May 26 02:21:51 PM PDT 24
Finished May 26 02:21:53 PM PDT 24
Peak memory 200168 kb
Host smart-b974535a-d585-4b6a-ae84-1a1621f8653b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678641723 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.2678641723
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.3910779084
Short name T279
Test name
Test status
Simulation time 54602777949 ps
CPU time 535.14 seconds
Started May 26 02:21:52 PM PDT 24
Finished May 26 02:30:47 PM PDT 24
Peak memory 200132 kb
Host smart-97ae0a6c-2a67-47d9-8c9c-5ffa90382f8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910779084 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.3910779084
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.1082217484
Short name T481
Test name
Test status
Simulation time 3811442947 ps
CPU time 88.71 seconds
Started May 26 02:21:47 PM PDT 24
Finished May 26 02:23:16 PM PDT 24
Peak memory 200176 kb
Host smart-da3cc243-3d54-4806-a242-aaf441de4ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082217484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1082217484
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.557073706
Short name T225
Test name
Test status
Simulation time 14093064 ps
CPU time 0.59 seconds
Started May 26 02:21:45 PM PDT 24
Finished May 26 02:21:46 PM PDT 24
Peak memory 194996 kb
Host smart-eb3deab0-1753-4ed1-b008-eae768ef48c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557073706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.557073706
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.242638950
Short name T282
Test name
Test status
Simulation time 1434836617 ps
CPU time 36.31 seconds
Started May 26 02:21:47 PM PDT 24
Finished May 26 02:22:24 PM PDT 24
Peak memory 208268 kb
Host smart-85466bb0-64c6-40c9-94cb-471a3f0bb738
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=242638950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.242638950
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.4171264655
Short name T330
Test name
Test status
Simulation time 364516230 ps
CPU time 10.63 seconds
Started May 26 02:21:47 PM PDT 24
Finished May 26 02:21:58 PM PDT 24
Peak memory 200124 kb
Host smart-1091fe16-85db-4b93-8542-6338253e2f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171264655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.4171264655
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3791186508
Short name T8
Test name
Test status
Simulation time 22299804738 ps
CPU time 83.41 seconds
Started May 26 02:21:47 PM PDT 24
Finished May 26 02:23:12 PM PDT 24
Peak memory 200244 kb
Host smart-63cd0012-586d-4900-a443-98ee9b24ad9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791186508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3791186508
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.809895670
Short name T480
Test name
Test status
Simulation time 291240727 ps
CPU time 3.24 seconds
Started May 26 02:21:47 PM PDT 24
Finished May 26 02:21:51 PM PDT 24
Peak memory 200084 kb
Host smart-367b69e8-f0b3-42cd-9c5b-a02ef545d439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809895670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.809895670
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.3876950936
Short name T390
Test name
Test status
Simulation time 526678049 ps
CPU time 1.05 seconds
Started May 26 02:21:52 PM PDT 24
Finished May 26 02:21:53 PM PDT 24
Peak memory 198932 kb
Host smart-e748dd73-a8c0-43ca-93af-ffda6df70fda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876950936 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.3876950936
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.473514085
Short name T173
Test name
Test status
Simulation time 8003671081 ps
CPU time 457.31 seconds
Started May 26 02:21:48 PM PDT 24
Finished May 26 02:29:26 PM PDT 24
Peak memory 200048 kb
Host smart-526d5b9b-6475-4456-bc43-a35fd9f3f02e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473514085 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.473514085
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1533959781
Short name T186
Test name
Test status
Simulation time 5254612439 ps
CPU time 51.87 seconds
Started May 26 02:21:44 PM PDT 24
Finished May 26 02:22:37 PM PDT 24
Peak memory 200100 kb
Host smart-13501fdc-5c64-4c3a-807b-d16e9e7167c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533959781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1533959781
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2223475735
Short name T269
Test name
Test status
Simulation time 35391113 ps
CPU time 0.6 seconds
Started May 26 02:21:54 PM PDT 24
Finished May 26 02:21:55 PM PDT 24
Peak memory 194852 kb
Host smart-19ead51e-b242-461f-99de-fd5207f51de2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223475735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2223475735
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1046934548
Short name T253
Test name
Test status
Simulation time 194503825 ps
CPU time 2.78 seconds
Started May 26 02:21:54 PM PDT 24
Finished May 26 02:21:57 PM PDT 24
Peak memory 200204 kb
Host smart-88f0dafb-c740-444c-9fed-a1b35e2bae45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1046934548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1046934548
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1823615600
Short name T183
Test name
Test status
Simulation time 3257368706 ps
CPU time 49.29 seconds
Started May 26 02:21:55 PM PDT 24
Finished May 26 02:22:45 PM PDT 24
Peak memory 200128 kb
Host smart-db76ceb5-dfc8-43fa-bb3d-b539f3c3c4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823615600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1823615600
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.1308342781
Short name T515
Test name
Test status
Simulation time 2581694341 ps
CPU time 698.74 seconds
Started May 26 02:21:58 PM PDT 24
Finished May 26 02:33:37 PM PDT 24
Peak memory 758984 kb
Host smart-86cb3508-758b-43d0-8528-29a31a580f0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1308342781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1308342781
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.2652752153
Short name T268
Test name
Test status
Simulation time 3903084022 ps
CPU time 28.77 seconds
Started May 26 02:21:53 PM PDT 24
Finished May 26 02:22:22 PM PDT 24
Peak memory 200168 kb
Host smart-0719c00f-dda9-4884-a763-880ac96d54a4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652752153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.2652752153
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2817812934
Short name T200
Test name
Test status
Simulation time 1879993169 ps
CPU time 119.04 seconds
Started May 26 02:21:58 PM PDT 24
Finished May 26 02:23:57 PM PDT 24
Peak memory 200184 kb
Host smart-604f862b-6ef8-4eb9-a0ae-8d19cd6d5a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817812934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2817812934
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.2505909320
Short name T314
Test name
Test status
Simulation time 221927366 ps
CPU time 4.19 seconds
Started May 26 02:21:56 PM PDT 24
Finished May 26 02:22:01 PM PDT 24
Peak memory 200140 kb
Host smart-4a6c522f-13bb-45b1-b928-0536ac30069c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505909320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2505909320
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.1785982485
Short name T499
Test name
Test status
Simulation time 42239513995 ps
CPU time 474.16 seconds
Started May 26 02:21:57 PM PDT 24
Finished May 26 02:29:52 PM PDT 24
Peak memory 200188 kb
Host smart-addfac17-7a6e-42b9-bf20-401e6bf7daad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785982485 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.1785982485
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3430909315
Short name T187
Test name
Test status
Simulation time 1351161735 ps
CPU time 58.65 seconds
Started May 26 02:21:53 PM PDT 24
Finished May 26 02:22:53 PM PDT 24
Peak memory 200260 kb
Host smart-638fcc62-cdcc-42fc-944c-445d782a2ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430909315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3430909315
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1229173097
Short name T24
Test name
Test status
Simulation time 45659799 ps
CPU time 0.62 seconds
Started May 26 02:22:02 PM PDT 24
Finished May 26 02:22:04 PM PDT 24
Peak memory 196032 kb
Host smart-acc8e48e-3efc-4fd7-b364-95790065fc32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229173097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1229173097
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2791629870
Short name T179
Test name
Test status
Simulation time 2975950038 ps
CPU time 37.49 seconds
Started May 26 02:21:56 PM PDT 24
Finished May 26 02:22:34 PM PDT 24
Peak memory 224768 kb
Host smart-698d7099-1279-46bf-92f4-9c575d1edb28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2791629870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2791629870
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2385685031
Short name T263
Test name
Test status
Simulation time 179785613 ps
CPU time 4.3 seconds
Started May 26 02:21:53 PM PDT 24
Finished May 26 02:21:58 PM PDT 24
Peak memory 200008 kb
Host smart-c0746585-7366-42a6-ac9d-68033d73c7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385685031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2385685031
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.919839293
Short name T355
Test name
Test status
Simulation time 9012316654 ps
CPU time 450.92 seconds
Started May 26 02:21:57 PM PDT 24
Finished May 26 02:29:28 PM PDT 24
Peak memory 678456 kb
Host smart-4f78495b-934d-4efe-beaa-a43a425f8836
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=919839293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.919839293
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2672355154
Short name T434
Test name
Test status
Simulation time 2457114944 ps
CPU time 136.1 seconds
Started May 26 02:21:55 PM PDT 24
Finished May 26 02:24:11 PM PDT 24
Peak memory 200220 kb
Host smart-f39ce386-bbec-4ede-949b-b18ee2a0d109
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672355154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2672355154
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1486808407
Short name T388
Test name
Test status
Simulation time 3064028156 ps
CPU time 61.2 seconds
Started May 26 02:21:53 PM PDT 24
Finished May 26 02:22:55 PM PDT 24
Peak memory 200180 kb
Host smart-28325071-5735-487e-b60c-e50ea54d6600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486808407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1486808407
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.427036784
Short name T125
Test name
Test status
Simulation time 66505201 ps
CPU time 1.63 seconds
Started May 26 02:21:59 PM PDT 24
Finished May 26 02:22:01 PM PDT 24
Peak memory 200144 kb
Host smart-63bfa96a-824e-45bc-bbc0-647b414f1f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427036784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.427036784
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.2410458575
Short name T292
Test name
Test status
Simulation time 61867767 ps
CPU time 1.23 seconds
Started May 26 02:21:57 PM PDT 24
Finished May 26 02:21:59 PM PDT 24
Peak memory 200092 kb
Host smart-aa9411c9-3cc5-40db-b70d-e589945b94e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410458575 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.2410458575
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.1155347639
Short name T465
Test name
Test status
Simulation time 32404425482 ps
CPU time 588.89 seconds
Started May 26 02:21:53 PM PDT 24
Finished May 26 02:31:43 PM PDT 24
Peak memory 200144 kb
Host smart-7127146f-6db7-48de-bd3e-c5da45a9521c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155347639 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.1155347639
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3095292827
Short name T278
Test name
Test status
Simulation time 11834058 ps
CPU time 0.6 seconds
Started May 26 02:21:07 PM PDT 24
Finished May 26 02:21:09 PM PDT 24
Peak memory 195652 kb
Host smart-bde0d43e-6357-440d-af39-7769a813a2a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095292827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3095292827
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3373017969
Short name T208
Test name
Test status
Simulation time 805002385 ps
CPU time 18.84 seconds
Started May 26 02:21:08 PM PDT 24
Finished May 26 02:21:28 PM PDT 24
Peak memory 208284 kb
Host smart-633241f5-25ac-4e24-97ec-6f55c791420a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3373017969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3373017969
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3157462171
Short name T40
Test name
Test status
Simulation time 582848060 ps
CPU time 6.43 seconds
Started May 26 02:21:06 PM PDT 24
Finished May 26 02:21:13 PM PDT 24
Peak memory 200116 kb
Host smart-d81124f4-808e-43b7-8d7f-f4c9121b2f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157462171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3157462171
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.499299968
Short name T350
Test name
Test status
Simulation time 6360293540 ps
CPU time 838.87 seconds
Started May 26 02:21:09 PM PDT 24
Finished May 26 02:35:10 PM PDT 24
Peak memory 755012 kb
Host smart-b64a02f0-0e45-4d37-a59d-fa6a354792bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=499299968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.499299968
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3899511386
Short name T450
Test name
Test status
Simulation time 13622570270 ps
CPU time 105.33 seconds
Started May 26 02:21:10 PM PDT 24
Finished May 26 02:22:57 PM PDT 24
Peak memory 200200 kb
Host smart-9348fc24-27a7-4afd-8380-edf409974653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899511386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3899511386
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.765170204
Short name T35
Test name
Test status
Simulation time 320839375 ps
CPU time 0.97 seconds
Started May 26 02:21:00 PM PDT 24
Finished May 26 02:21:01 PM PDT 24
Peak memory 219148 kb
Host smart-e12d26ca-ee17-4899-99d8-5de9f155d9af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765170204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.765170204
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3176382288
Short name T285
Test name
Test status
Simulation time 1961064403 ps
CPU time 9.15 seconds
Started May 26 02:21:07 PM PDT 24
Finished May 26 02:21:18 PM PDT 24
Peak memory 200180 kb
Host smart-835e45f7-b38f-4fd1-ad4e-e2a560d27f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176382288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3176382288
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.120978285
Short name T124
Test name
Test status
Simulation time 43051330 ps
CPU time 1.09 seconds
Started May 26 02:21:07 PM PDT 24
Finished May 26 02:21:10 PM PDT 24
Peak memory 199772 kb
Host smart-0ccd20d2-2ff6-4565-8203-3f342a3aae7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120978285 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.hmac_test_hmac_vectors.120978285
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.1278635122
Short name T392
Test name
Test status
Simulation time 7600306562 ps
CPU time 430.15 seconds
Started May 26 02:21:08 PM PDT 24
Finished May 26 02:28:20 PM PDT 24
Peak memory 200200 kb
Host smart-8724c54b-417b-4597-aec9-c247e83a72f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278635122 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.1278635122
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3663071111
Short name T342
Test name
Test status
Simulation time 5356362205 ps
CPU time 27 seconds
Started May 26 02:21:10 PM PDT 24
Finished May 26 02:21:38 PM PDT 24
Peak memory 200208 kb
Host smart-6f5643b9-cdbe-4056-af05-45035ff7e224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663071111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3663071111
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.777390587
Short name T403
Test name
Test status
Simulation time 29597008 ps
CPU time 0.59 seconds
Started May 26 02:22:01 PM PDT 24
Finished May 26 02:22:02 PM PDT 24
Peak memory 196004 kb
Host smart-04900a91-212f-45b6-b3f4-2cd299ee3fc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777390587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.777390587
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1417332718
Short name T386
Test name
Test status
Simulation time 540788614 ps
CPU time 12.22 seconds
Started May 26 02:22:02 PM PDT 24
Finished May 26 02:22:15 PM PDT 24
Peak memory 208324 kb
Host smart-3bbcb1b8-f867-44b4-99ee-b622e303ef54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1417332718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1417332718
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.238330191
Short name T276
Test name
Test status
Simulation time 248793801 ps
CPU time 5.42 seconds
Started May 26 02:22:01 PM PDT 24
Finished May 26 02:22:08 PM PDT 24
Peak memory 200036 kb
Host smart-a825cd9f-196d-4881-ab86-c284e2a72818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238330191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.238330191
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.3497021806
Short name T234
Test name
Test status
Simulation time 24688878658 ps
CPU time 594.42 seconds
Started May 26 02:22:21 PM PDT 24
Finished May 26 02:32:16 PM PDT 24
Peak memory 687000 kb
Host smart-bdda33c0-976a-41cb-8bcc-24d4bcc9f675
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3497021806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3497021806
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3813215107
Short name T245
Test name
Test status
Simulation time 250348979 ps
CPU time 15.18 seconds
Started May 26 02:22:02 PM PDT 24
Finished May 26 02:22:19 PM PDT 24
Peak memory 200128 kb
Host smart-5ba44a48-34e2-4820-81df-e5c48e08c540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813215107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3813215107
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2200358539
Short name T80
Test name
Test status
Simulation time 237753992 ps
CPU time 2.68 seconds
Started May 26 02:22:02 PM PDT 24
Finished May 26 02:22:06 PM PDT 24
Peak memory 200188 kb
Host smart-43cf553c-1121-4c8d-a6fe-b7d324d67669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200358539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2200358539
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.3079678189
Short name T152
Test name
Test status
Simulation time 396476453660 ps
CPU time 379.72 seconds
Started May 26 02:22:00 PM PDT 24
Finished May 26 02:28:21 PM PDT 24
Peak memory 200188 kb
Host smart-4ab4e1e6-6eef-48ea-aa7c-b30404871109
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079678189 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.3079678189
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3958809081
Short name T468
Test name
Test status
Simulation time 70682462 ps
CPU time 0.61 seconds
Started May 26 02:22:09 PM PDT 24
Finished May 26 02:22:11 PM PDT 24
Peak memory 196028 kb
Host smart-9a06429b-d905-4665-bd78-8638bec332c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958809081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3958809081
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3255810455
Short name T422
Test name
Test status
Simulation time 1699817282 ps
CPU time 24.44 seconds
Started May 26 02:22:12 PM PDT 24
Finished May 26 02:22:37 PM PDT 24
Peak memory 225984 kb
Host smart-cb182429-397d-43ac-b6a0-026662a55c90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3255810455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3255810455
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2470464292
Short name T460
Test name
Test status
Simulation time 14661740292 ps
CPU time 59.82 seconds
Started May 26 02:22:02 PM PDT 24
Finished May 26 02:23:03 PM PDT 24
Peak memory 200128 kb
Host smart-b8883a61-7e4d-488d-9cdd-0f8cb4ee008a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470464292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2470464292
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1695892601
Short name T384
Test name
Test status
Simulation time 381214660 ps
CPU time 70.38 seconds
Started May 26 02:22:05 PM PDT 24
Finished May 26 02:23:15 PM PDT 24
Peak memory 349388 kb
Host smart-13b13939-8c29-468b-bcfa-d8324f52f29d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1695892601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1695892601
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1594563785
Short name T212
Test name
Test status
Simulation time 12346050342 ps
CPU time 74.91 seconds
Started May 26 02:22:02 PM PDT 24
Finished May 26 02:23:18 PM PDT 24
Peak memory 200176 kb
Host smart-aad2e856-25de-4f38-be8f-75beaea4fedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594563785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1594563785
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1878605872
Short name T325
Test name
Test status
Simulation time 267225919 ps
CPU time 5.14 seconds
Started May 26 02:22:02 PM PDT 24
Finished May 26 02:22:08 PM PDT 24
Peak memory 200216 kb
Host smart-0ca1daa6-06ba-4370-9d86-5e85b2876aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878605872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1878605872
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.1286268833
Short name T385
Test name
Test status
Simulation time 28217971642 ps
CPU time 518.37 seconds
Started May 26 02:22:06 PM PDT 24
Finished May 26 02:30:45 PM PDT 24
Peak memory 200128 kb
Host smart-2a442c37-f4a7-402b-b972-b9185151f982
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286268833 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.1286268833
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1949552994
Short name T521
Test name
Test status
Simulation time 880488620 ps
CPU time 45.93 seconds
Started May 26 02:22:02 PM PDT 24
Finished May 26 02:22:49 PM PDT 24
Peak memory 200152 kb
Host smart-3d6549b3-4818-49eb-904e-c01cbc9c79a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949552994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1949552994
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1342881818
Short name T358
Test name
Test status
Simulation time 37604080 ps
CPU time 0.61 seconds
Started May 26 02:22:11 PM PDT 24
Finished May 26 02:22:13 PM PDT 24
Peak memory 194988 kb
Host smart-68b1f64a-5221-4c0b-91ec-83580b16699e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342881818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1342881818
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3421436667
Short name T327
Test name
Test status
Simulation time 1527700215 ps
CPU time 20.73 seconds
Started May 26 02:22:11 PM PDT 24
Finished May 26 02:22:33 PM PDT 24
Peak memory 200188 kb
Host smart-1b8fc835-200a-448d-b5cb-53c77f8d00f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3421436667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3421436667
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.164252253
Short name T409
Test name
Test status
Simulation time 3364966310 ps
CPU time 48.32 seconds
Started May 26 02:22:10 PM PDT 24
Finished May 26 02:23:00 PM PDT 24
Peak memory 200196 kb
Host smart-a0c11945-04c0-4d92-a967-628b0e8b77eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164252253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.164252253
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3740418151
Short name T175
Test name
Test status
Simulation time 33019041641 ps
CPU time 778.06 seconds
Started May 26 02:22:11 PM PDT 24
Finished May 26 02:35:11 PM PDT 24
Peak memory 733208 kb
Host smart-b7c3641a-1efb-4c95-94a0-1e5eddf31c00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3740418151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3740418151
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.2927113631
Short name T256
Test name
Test status
Simulation time 11471124392 ps
CPU time 42.26 seconds
Started May 26 02:22:11 PM PDT 24
Finished May 26 02:22:55 PM PDT 24
Peak memory 200116 kb
Host smart-ade9a921-14c1-48bc-ae41-8537d9496e95
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927113631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2927113631
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.562413988
Short name T393
Test name
Test status
Simulation time 1548532398 ps
CPU time 23.66 seconds
Started May 26 02:22:13 PM PDT 24
Finished May 26 02:22:37 PM PDT 24
Peak memory 200184 kb
Host smart-9387cdba-1fbb-41c5-b3c9-a6deb74e983c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562413988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.562413988
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.3349263530
Short name T446
Test name
Test status
Simulation time 76682484 ps
CPU time 2.8 seconds
Started May 26 02:22:10 PM PDT 24
Finished May 26 02:22:13 PM PDT 24
Peak memory 200176 kb
Host smart-4c5b431e-bcf6-44a6-86cd-1ba0356c205a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349263530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.3349263530
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1265162088
Short name T518
Test name
Test status
Simulation time 159038787 ps
CPU time 1.98 seconds
Started May 26 02:22:12 PM PDT 24
Finished May 26 02:22:15 PM PDT 24
Peak memory 200148 kb
Host smart-e7410a76-4504-4238-a0f4-1ef561ac64a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265162088 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1265162088
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.1232428953
Short name T470
Test name
Test status
Simulation time 127743975 ps
CPU time 1.07 seconds
Started May 26 02:22:08 PM PDT 24
Finished May 26 02:22:10 PM PDT 24
Peak memory 199840 kb
Host smart-07231637-8842-4bb3-859c-4dd4b4fda08d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232428953 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.1232428953
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.1002610063
Short name T248
Test name
Test status
Simulation time 146407017349 ps
CPU time 489.27 seconds
Started May 26 02:22:11 PM PDT 24
Finished May 26 02:30:21 PM PDT 24
Peak memory 200196 kb
Host smart-176d1d93-e6b7-4c65-819d-57a4525999ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002610063 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.1002610063
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.4161086724
Short name T304
Test name
Test status
Simulation time 1249916533 ps
CPU time 22.76 seconds
Started May 26 02:22:09 PM PDT 24
Finished May 26 02:22:32 PM PDT 24
Peak memory 200116 kb
Host smart-94aaa2ae-b9c7-40df-970d-e63d802cbe86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161086724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.4161086724
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.3028273119
Short name T214
Test name
Test status
Simulation time 59860848 ps
CPU time 0.59 seconds
Started May 26 02:22:11 PM PDT 24
Finished May 26 02:22:13 PM PDT 24
Peak memory 194988 kb
Host smart-831191a3-00e8-404a-b5e9-511a80543350
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028273119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3028273119
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3601132333
Short name T47
Test name
Test status
Simulation time 1665556639 ps
CPU time 48.98 seconds
Started May 26 02:22:11 PM PDT 24
Finished May 26 02:23:01 PM PDT 24
Peak memory 230844 kb
Host smart-506f0f87-d106-429c-9d2a-6fa7653ec98c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3601132333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3601132333
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1325418097
Short name T333
Test name
Test status
Simulation time 401538089 ps
CPU time 6.45 seconds
Started May 26 02:22:09 PM PDT 24
Finished May 26 02:22:17 PM PDT 24
Peak memory 200176 kb
Host smart-999e59bd-2f7c-46a8-997e-e4d0cef4505e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325418097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1325418097
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.378389766
Short name T496
Test name
Test status
Simulation time 70675929 ps
CPU time 6.79 seconds
Started May 26 02:22:11 PM PDT 24
Finished May 26 02:22:19 PM PDT 24
Peak memory 200012 kb
Host smart-8588f05c-6767-44f7-8af4-1b776ae8d7bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=378389766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.378389766
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.996376513
Short name T15
Test name
Test status
Simulation time 475316892 ps
CPU time 26.23 seconds
Started May 26 02:22:08 PM PDT 24
Finished May 26 02:22:35 PM PDT 24
Peak memory 200004 kb
Host smart-1f02714c-d9b6-4c54-98db-e0e616f5829f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996376513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.996376513
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.812249581
Short name T1
Test name
Test status
Simulation time 167674212 ps
CPU time 10.36 seconds
Started May 26 02:22:12 PM PDT 24
Finished May 26 02:22:24 PM PDT 24
Peak memory 200180 kb
Host smart-fa229c0e-75b4-44ea-bcc0-bb81076673d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812249581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.812249581
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.4081088136
Short name T127
Test name
Test status
Simulation time 14174346 ps
CPU time 0.73 seconds
Started May 26 02:22:10 PM PDT 24
Finished May 26 02:22:12 PM PDT 24
Peak memory 197296 kb
Host smart-a32fa4c8-5c86-4b8e-a70a-33eac8f66ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081088136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.4081088136
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2297825164
Short name T239
Test name
Test status
Simulation time 30434871822 ps
CPU time 1131 seconds
Started May 26 02:22:10 PM PDT 24
Finished May 26 02:41:02 PM PDT 24
Peak memory 798800 kb
Host smart-7502f224-2bb5-497b-8e33-2c94bdb62265
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297825164 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2297825164
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.1121291
Short name T301
Test name
Test status
Simulation time 40307543310 ps
CPU time 546.02 seconds
Started May 26 02:22:10 PM PDT 24
Finished May 26 02:31:17 PM PDT 24
Peak memory 200176 kb
Host smart-4d388ea7-5bd0-4bfa-9a3e-aaf9abca54f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121291 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.1121291
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.290672658
Short name T502
Test name
Test status
Simulation time 868671722 ps
CPU time 42.8 seconds
Started May 26 02:22:12 PM PDT 24
Finished May 26 02:22:56 PM PDT 24
Peak memory 200160 kb
Host smart-11b0e4b2-9918-4023-9075-822838bf6c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290672658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.290672658
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3212086436
Short name T319
Test name
Test status
Simulation time 41504685 ps
CPU time 0.6 seconds
Started May 26 02:22:18 PM PDT 24
Finished May 26 02:22:19 PM PDT 24
Peak memory 196724 kb
Host smart-eecf0a3c-2c09-41e6-91ac-ec7fc4287407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212086436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3212086436
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.2375503102
Short name T52
Test name
Test status
Simulation time 741127105 ps
CPU time 22.74 seconds
Started May 26 02:22:10 PM PDT 24
Finished May 26 02:22:34 PM PDT 24
Peak memory 232060 kb
Host smart-6ad32db6-c96a-4fd9-8c64-9604348aab32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2375503102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2375503102
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2115313859
Short name T108
Test name
Test status
Simulation time 1227214413 ps
CPU time 24.25 seconds
Started May 26 02:22:10 PM PDT 24
Finished May 26 02:22:35 PM PDT 24
Peak memory 200124 kb
Host smart-b12b4747-ee58-479d-a10b-691e27ae3e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115313859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2115313859
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3752801283
Short name T306
Test name
Test status
Simulation time 1473292901 ps
CPU time 375.61 seconds
Started May 26 02:22:10 PM PDT 24
Finished May 26 02:28:27 PM PDT 24
Peak memory 682292 kb
Host smart-d61da7c7-2682-4ee0-83f2-4442ead59e8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3752801283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3752801283
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_long_msg.2842191187
Short name T447
Test name
Test status
Simulation time 2608264966 ps
CPU time 77.57 seconds
Started May 26 02:22:10 PM PDT 24
Finished May 26 02:23:28 PM PDT 24
Peak memory 200192 kb
Host smart-a0957b93-bce5-45ff-a342-dd7396d1cf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842191187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.2842191187
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.4245815345
Short name T202
Test name
Test status
Simulation time 451309496 ps
CPU time 5.22 seconds
Started May 26 02:22:10 PM PDT 24
Finished May 26 02:22:17 PM PDT 24
Peak memory 200088 kb
Host smart-08a9cc64-a796-4f65-a49b-f2115a6475d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245815345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.4245815345
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.947033021
Short name T138
Test name
Test status
Simulation time 53457529586 ps
CPU time 523.87 seconds
Started May 26 02:22:17 PM PDT 24
Finished May 26 02:31:02 PM PDT 24
Peak memory 200156 kb
Host smart-bf33effd-e37c-4e7c-a915-6832dfdcea25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947033021 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.947033021
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.754738132
Short name T243
Test name
Test status
Simulation time 9347375553 ps
CPU time 49.27 seconds
Started May 26 02:22:12 PM PDT 24
Finished May 26 02:23:02 PM PDT 24
Peak memory 200220 kb
Host smart-e9648a56-0065-4db7-9f7d-7eb31cd30129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754738132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.754738132
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.689013993
Short name T448
Test name
Test status
Simulation time 12516386 ps
CPU time 0.6 seconds
Started May 26 02:22:23 PM PDT 24
Finished May 26 02:22:24 PM PDT 24
Peak memory 195588 kb
Host smart-83147d07-5918-4b34-ba99-4648440fa14c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689013993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.689013993
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1936886551
Short name T271
Test name
Test status
Simulation time 804451922 ps
CPU time 20.83 seconds
Started May 26 02:22:17 PM PDT 24
Finished May 26 02:22:38 PM PDT 24
Peak memory 210364 kb
Host smart-4f08a48f-a907-4910-80da-d96b886b30f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1936886551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1936886551
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2006882474
Short name T479
Test name
Test status
Simulation time 577722229 ps
CPU time 31.41 seconds
Started May 26 02:22:15 PM PDT 24
Finished May 26 02:22:47 PM PDT 24
Peak memory 200132 kb
Host smart-b7d1b659-5449-4307-93f5-a87ac51abf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006882474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2006882474
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3500592466
Short name T178
Test name
Test status
Simulation time 8332963514 ps
CPU time 681.54 seconds
Started May 26 02:22:17 PM PDT 24
Finished May 26 02:33:40 PM PDT 24
Peak memory 702396 kb
Host smart-b19157d0-71b2-45a1-a3ad-0af352fe529c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3500592466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3500592466
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1765949468
Short name T399
Test name
Test status
Simulation time 17200865731 ps
CPU time 124.35 seconds
Started May 26 02:22:17 PM PDT 24
Finished May 26 02:24:22 PM PDT 24
Peak memory 200172 kb
Host smart-379bc690-ac90-4177-9ca6-ca2439d5ba5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765949468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1765949468
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2337104519
Short name T11
Test name
Test status
Simulation time 1052694591 ps
CPU time 2.21 seconds
Started May 26 02:22:17 PM PDT 24
Finished May 26 02:22:20 PM PDT 24
Peak memory 200140 kb
Host smart-05a73974-c1c5-4b38-bdc0-ff9a83afac0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337104519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2337104519
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.1742813939
Short name T340
Test name
Test status
Simulation time 73671405661 ps
CPU time 520.79 seconds
Started May 26 02:22:20 PM PDT 24
Finished May 26 02:31:01 PM PDT 24
Peak memory 200148 kb
Host smart-ccc0cf30-a5d3-4cc4-8f0a-5e8ce65b36ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742813939 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.1742813939
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.75246973
Short name T274
Test name
Test status
Simulation time 3466180673 ps
CPU time 74.14 seconds
Started May 26 02:22:17 PM PDT 24
Finished May 26 02:23:32 PM PDT 24
Peak memory 200248 kb
Host smart-3a2bc02c-6dc1-4330-90d3-385a5e30fe13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75246973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.75246973
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3549104628
Short name T238
Test name
Test status
Simulation time 21342908 ps
CPU time 0.59 seconds
Started May 26 02:22:24 PM PDT 24
Finished May 26 02:22:25 PM PDT 24
Peak memory 195000 kb
Host smart-d19b3e30-4bd9-4bcb-bf92-431b4e78676e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549104628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3549104628
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.2157638752
Short name T9
Test name
Test status
Simulation time 330135337 ps
CPU time 16.36 seconds
Started May 26 02:22:24 PM PDT 24
Finished May 26 02:22:41 PM PDT 24
Peak memory 208312 kb
Host smart-8cc99369-ccbf-416e-8359-408cd67bff86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2157638752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2157638752
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2372956679
Short name T413
Test name
Test status
Simulation time 6171286203 ps
CPU time 25 seconds
Started May 26 02:22:35 PM PDT 24
Finished May 26 02:23:02 PM PDT 24
Peak memory 200036 kb
Host smart-31bd7f11-dbff-4266-b922-315a37b82b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372956679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2372956679
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3061629115
Short name T492
Test name
Test status
Simulation time 279970043 ps
CPU time 72.8 seconds
Started May 26 02:22:35 PM PDT 24
Finished May 26 02:23:49 PM PDT 24
Peak memory 436808 kb
Host smart-5cd3fe51-3cd7-46ed-a476-245dd9325707
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3061629115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3061629115
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3299443359
Short name T489
Test name
Test status
Simulation time 1391039497 ps
CPU time 40.51 seconds
Started May 26 02:22:17 PM PDT 24
Finished May 26 02:22:58 PM PDT 24
Peak memory 199980 kb
Host smart-7e8ac701-cd57-44d9-838d-eb43b71fc255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299443359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3299443359
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.1832753824
Short name T380
Test name
Test status
Simulation time 135460372 ps
CPU time 4.49 seconds
Started May 26 02:22:19 PM PDT 24
Finished May 26 02:22:24 PM PDT 24
Peak memory 200276 kb
Host smart-3a9007a2-1893-4295-bd9d-d2f09697262b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832753824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1832753824
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.1814932954
Short name T161
Test name
Test status
Simulation time 27508569 ps
CPU time 1.04 seconds
Started May 26 02:22:23 PM PDT 24
Finished May 26 02:22:25 PM PDT 24
Peak memory 199636 kb
Host smart-803b18a6-8b74-4ad7-92c7-2b95bfcd980c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814932954 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.1814932954
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.1215011435
Short name T155
Test name
Test status
Simulation time 508780542117 ps
CPU time 481.19 seconds
Started May 26 02:22:35 PM PDT 24
Finished May 26 02:30:38 PM PDT 24
Peak memory 200088 kb
Host smart-2479d020-9cb3-4d8f-aed8-8c69ac3e0b74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215011435 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.1215011435
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1948852218
Short name T456
Test name
Test status
Simulation time 17257267059 ps
CPU time 79.63 seconds
Started May 26 02:22:24 PM PDT 24
Finished May 26 02:23:44 PM PDT 24
Peak memory 200176 kb
Host smart-1712ad91-68bf-4ea7-bfa2-4d703ab69c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948852218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1948852218
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3308223541
Short name T516
Test name
Test status
Simulation time 34873736 ps
CPU time 0.58 seconds
Started May 26 02:22:35 PM PDT 24
Finished May 26 02:22:37 PM PDT 24
Peak memory 195648 kb
Host smart-f535be02-3b8d-42ff-a5b6-d31869810d2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308223541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3308223541
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.4125304289
Short name T421
Test name
Test status
Simulation time 862611435 ps
CPU time 36.53 seconds
Started May 26 02:22:25 PM PDT 24
Finished May 26 02:23:02 PM PDT 24
Peak memory 226840 kb
Host smart-d03cb8a5-9007-4096-8c1d-9b434cb5ce13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4125304289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.4125304289
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3134088018
Short name T361
Test name
Test status
Simulation time 28568592 ps
CPU time 0.85 seconds
Started May 26 02:22:25 PM PDT 24
Finished May 26 02:22:26 PM PDT 24
Peak memory 197860 kb
Host smart-29e60c63-1ce5-4cc0-991a-52b5383fd38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134088018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3134088018
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1636796410
Short name T405
Test name
Test status
Simulation time 8262171783 ps
CPU time 924.35 seconds
Started May 26 02:22:25 PM PDT 24
Finished May 26 02:37:50 PM PDT 24
Peak memory 732444 kb
Host smart-9487ac77-f455-4ee2-944c-3883e7bea268
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1636796410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1636796410
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.2223631788
Short name T17
Test name
Test status
Simulation time 12348237476 ps
CPU time 57.12 seconds
Started May 26 02:22:25 PM PDT 24
Finished May 26 02:23:23 PM PDT 24
Peak memory 200032 kb
Host smart-bf4ff40a-dce9-46e0-9cb7-8a491bec3846
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223631788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2223631788
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3654725867
Short name T300
Test name
Test status
Simulation time 4226568734 ps
CPU time 28.36 seconds
Started May 26 02:22:28 PM PDT 24
Finished May 26 02:22:57 PM PDT 24
Peak memory 200100 kb
Host smart-d63f35b0-13bd-481b-a9f8-9785e9868463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654725867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3654725867
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.1269009417
Short name T500
Test name
Test status
Simulation time 113678996 ps
CPU time 1.38 seconds
Started May 26 02:22:30 PM PDT 24
Finished May 26 02:22:32 PM PDT 24
Peak memory 200104 kb
Host smart-019030e8-2bae-454c-b430-645983137765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269009417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1269009417
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2340482252
Short name T16
Test name
Test status
Simulation time 169883664236 ps
CPU time 2012.98 seconds
Started May 26 02:22:26 PM PDT 24
Finished May 26 02:56:00 PM PDT 24
Peak memory 791976 kb
Host smart-2a8b2879-b6b9-4d43-b170-fcfcc308c047
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340482252 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2340482252
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.3313836024
Short name T369
Test name
Test status
Simulation time 103386042 ps
CPU time 1.02 seconds
Started May 26 02:22:27 PM PDT 24
Finished May 26 02:22:29 PM PDT 24
Peak memory 199844 kb
Host smart-ad2abc4a-8ca5-421f-9fde-bb6504c5438c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313836024 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.3313836024
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.514254217
Short name T188
Test name
Test status
Simulation time 7976481804 ps
CPU time 429.87 seconds
Started May 26 02:22:27 PM PDT 24
Finished May 26 02:29:38 PM PDT 24
Peak memory 200276 kb
Host smart-10220b64-d069-45a7-a222-a475fd08ad46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514254217 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.514254217
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.879836243
Short name T347
Test name
Test status
Simulation time 2037161478 ps
CPU time 12.87 seconds
Started May 26 02:22:27 PM PDT 24
Finished May 26 02:22:41 PM PDT 24
Peak memory 200088 kb
Host smart-a6f9eb8f-15f2-4c2e-9d4e-6fedaf207523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879836243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.879836243
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3787541497
Short name T133
Test name
Test status
Simulation time 14635413 ps
CPU time 0.6 seconds
Started May 26 02:22:35 PM PDT 24
Finished May 26 02:22:37 PM PDT 24
Peak memory 195600 kb
Host smart-4fe83886-ede6-4e92-bc74-b9287ff3f88c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787541497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3787541497
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.1269236012
Short name T219
Test name
Test status
Simulation time 858318750 ps
CPU time 42.45 seconds
Started May 26 02:22:26 PM PDT 24
Finished May 26 02:23:09 PM PDT 24
Peak memory 215988 kb
Host smart-58c7ba87-f890-40bb-aab0-ca64c22ca628
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1269236012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1269236012
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.607164686
Short name T254
Test name
Test status
Simulation time 5972311475 ps
CPU time 17.13 seconds
Started May 26 02:22:28 PM PDT 24
Finished May 26 02:22:46 PM PDT 24
Peak memory 200176 kb
Host smart-8443f488-3d20-449d-9ab4-f8b350bf4d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607164686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.607164686
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2536067021
Short name T85
Test name
Test status
Simulation time 1287504018 ps
CPU time 333.7 seconds
Started May 26 02:22:29 PM PDT 24
Finished May 26 02:28:03 PM PDT 24
Peak memory 631520 kb
Host smart-8633491c-81b6-4409-ac40-eda1c992ad64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2536067021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2536067021
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.1841104951
Short name T181
Test name
Test status
Simulation time 147922316 ps
CPU time 8.11 seconds
Started May 26 02:22:29 PM PDT 24
Finished May 26 02:22:38 PM PDT 24
Peak memory 200024 kb
Host smart-fcccd52d-f1e1-45dc-b14c-75f8539c5af8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841104951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.1841104951
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1835088673
Short name T284
Test name
Test status
Simulation time 81626238090 ps
CPU time 111.61 seconds
Started May 26 02:22:24 PM PDT 24
Finished May 26 02:24:17 PM PDT 24
Peak memory 200172 kb
Host smart-86932b37-e2b6-4aaa-a64a-f0fa105c50f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835088673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1835088673
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3527062457
Short name T463
Test name
Test status
Simulation time 33246888 ps
CPU time 0.84 seconds
Started May 26 02:22:23 PM PDT 24
Finished May 26 02:22:25 PM PDT 24
Peak memory 197720 kb
Host smart-b888ce9e-8824-4c5a-88d3-e15d7ee8fcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527062457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3527062457
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3256757267
Short name T433
Test name
Test status
Simulation time 5282352319 ps
CPU time 104.72 seconds
Started May 26 02:22:28 PM PDT 24
Finished May 26 02:24:13 PM PDT 24
Peak memory 208440 kb
Host smart-fb23ae1d-f52c-4c47-84c3-eb2bf9ad40e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256757267 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3256757267
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.3546023186
Short name T146
Test name
Test status
Simulation time 80207740 ps
CPU time 1.47 seconds
Started May 26 02:22:26 PM PDT 24
Finished May 26 02:22:28 PM PDT 24
Peak memory 200104 kb
Host smart-90a9bf3b-57d7-49da-be63-7b58739f93e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546023186 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.3546023186
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.961266561
Short name T184
Test name
Test status
Simulation time 244496608006 ps
CPU time 513.22 seconds
Started May 26 02:22:24 PM PDT 24
Finished May 26 02:30:58 PM PDT 24
Peak memory 200132 kb
Host smart-633f1b03-4e24-4d9a-a941-6686acd9ca82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961266561 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.961266561
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.4018322756
Short name T30
Test name
Test status
Simulation time 2150331312 ps
CPU time 42.84 seconds
Started May 26 02:22:35 PM PDT 24
Finished May 26 02:23:19 PM PDT 24
Peak memory 200112 kb
Host smart-e6e77e8f-6fbc-4a08-8cf5-329852df9da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018322756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.4018322756
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.4001150237
Short name T204
Test name
Test status
Simulation time 13149582 ps
CPU time 0.58 seconds
Started May 26 02:22:33 PM PDT 24
Finished May 26 02:22:35 PM PDT 24
Peak memory 195152 kb
Host smart-19a5bd81-05ef-4d70-a2a5-d75ea91087dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001150237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.4001150237
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.2994198900
Short name T501
Test name
Test status
Simulation time 822725780 ps
CPU time 23.65 seconds
Started May 26 02:22:35 PM PDT 24
Finished May 26 02:23:01 PM PDT 24
Peak memory 216496 kb
Host smart-44c86a87-8b5d-4608-8785-21df238efa0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2994198900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.2994198900
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1092365650
Short name T445
Test name
Test status
Simulation time 299311956 ps
CPU time 1.74 seconds
Started May 26 02:22:35 PM PDT 24
Finished May 26 02:22:38 PM PDT 24
Peak memory 200116 kb
Host smart-5b82f535-e31d-4cbf-8c33-7925f53d474f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092365650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1092365650
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1741886176
Short name T378
Test name
Test status
Simulation time 5888767829 ps
CPU time 675.49 seconds
Started May 26 02:22:34 PM PDT 24
Finished May 26 02:33:51 PM PDT 24
Peak memory 702136 kb
Host smart-3b840b17-0b5d-48ea-966d-e1d0c96f3bd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1741886176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1741886176
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1568550677
Short name T153
Test name
Test status
Simulation time 3667127393 ps
CPU time 17.11 seconds
Started May 26 02:22:32 PM PDT 24
Finished May 26 02:22:51 PM PDT 24
Peak memory 200200 kb
Host smart-8cc6dde3-afd9-4ea0-b22c-86bbede52dd3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568550677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1568550677
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.784140935
Short name T295
Test name
Test status
Simulation time 18115948346 ps
CPU time 69.57 seconds
Started May 26 02:22:36 PM PDT 24
Finished May 26 02:23:47 PM PDT 24
Peak memory 200180 kb
Host smart-5dbd0444-6bdd-4859-8f3d-73053769d518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784140935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.784140935
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.4249198921
Short name T232
Test name
Test status
Simulation time 403759768 ps
CPU time 6.9 seconds
Started May 26 02:22:28 PM PDT 24
Finished May 26 02:22:35 PM PDT 24
Peak memory 200116 kb
Host smart-a16857b0-2d29-497a-b93b-f1840f6f9203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249198921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.4249198921
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.4124333259
Short name T428
Test name
Test status
Simulation time 11500547066 ps
CPU time 160.86 seconds
Started May 26 02:22:33 PM PDT 24
Finished May 26 02:25:15 PM PDT 24
Peak memory 200108 kb
Host smart-5faedcae-b2ce-4777-bae4-f25fafe58e96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124333259 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.4124333259
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.4103690069
Short name T20
Test name
Test status
Simulation time 60463104092 ps
CPU time 530.06 seconds
Started May 26 02:22:35 PM PDT 24
Finished May 26 02:31:27 PM PDT 24
Peak memory 200196 kb
Host smart-5c1e9f1e-f454-40f3-9d25-5d555d91ff9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103690069 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.4103690069
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3104629288
Short name T195
Test name
Test status
Simulation time 914238818 ps
CPU time 35.54 seconds
Started May 26 02:22:36 PM PDT 24
Finished May 26 02:23:13 PM PDT 24
Peak memory 200104 kb
Host smart-e03cd049-524a-4566-b4b3-89a7b71aa466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104629288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3104629288
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3083827016
Short name T201
Test name
Test status
Simulation time 24407465 ps
CPU time 0.62 seconds
Started May 26 02:21:00 PM PDT 24
Finished May 26 02:21:02 PM PDT 24
Peak memory 196184 kb
Host smart-40d8e8f5-d6e0-4a9c-859b-2d0e13b977ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083827016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3083827016
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3356037443
Short name T349
Test name
Test status
Simulation time 149234609 ps
CPU time 3.45 seconds
Started May 26 02:20:58 PM PDT 24
Finished May 26 02:21:03 PM PDT 24
Peak memory 200164 kb
Host smart-34418269-6ce0-440a-a9ec-5feb211b416b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3356037443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3356037443
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3835509220
Short name T506
Test name
Test status
Simulation time 929942167 ps
CPU time 4.92 seconds
Started May 26 02:21:00 PM PDT 24
Finished May 26 02:21:05 PM PDT 24
Peak memory 200116 kb
Host smart-ca7da167-9547-4934-a91a-2c86b729cd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835509220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3835509220
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.3010447445
Short name T517
Test name
Test status
Simulation time 7272844539 ps
CPU time 628.26 seconds
Started May 26 02:21:11 PM PDT 24
Finished May 26 02:31:41 PM PDT 24
Peak memory 700008 kb
Host smart-804140aa-bad6-49e6-8dd8-ccee7a9f4575
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3010447445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.3010447445
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1033651193
Short name T46
Test name
Test status
Simulation time 53497838 ps
CPU time 0.73 seconds
Started May 26 02:20:59 PM PDT 24
Finished May 26 02:21:01 PM PDT 24
Peak memory 196720 kb
Host smart-e609e9ec-ff32-4b93-abb9-ba9b05131d8e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033651193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1033651193
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.713791636
Short name T485
Test name
Test status
Simulation time 2032440559 ps
CPU time 30.27 seconds
Started May 26 02:21:10 PM PDT 24
Finished May 26 02:21:41 PM PDT 24
Peak memory 200280 kb
Host smart-0fce2180-eb00-488c-915a-39fffc543b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713791636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.713791636
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_smoke.2648329147
Short name T510
Test name
Test status
Simulation time 552150637 ps
CPU time 5.16 seconds
Started May 26 02:20:58 PM PDT 24
Finished May 26 02:21:04 PM PDT 24
Peak memory 200140 kb
Host smart-58b93a2d-8211-49dd-94aa-cfc86e9ba43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648329147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2648329147
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.2366051715
Short name T322
Test name
Test status
Simulation time 54013365 ps
CPU time 1.25 seconds
Started May 26 02:21:11 PM PDT 24
Finished May 26 02:21:14 PM PDT 24
Peak memory 200068 kb
Host smart-bbd66dd4-69ed-4a13-9e12-78152c4c5769
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366051715 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.2366051715
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.2156370046
Short name T346
Test name
Test status
Simulation time 173464796328 ps
CPU time 545.24 seconds
Started May 26 02:21:10 PM PDT 24
Finished May 26 02:30:16 PM PDT 24
Peak memory 200128 kb
Host smart-3ce072d7-d93e-42d1-a768-96f318f9c5d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156370046 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.2156370046
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.130320680
Short name T177
Test name
Test status
Simulation time 8704681335 ps
CPU time 81.25 seconds
Started May 26 02:20:59 PM PDT 24
Finished May 26 02:22:21 PM PDT 24
Peak memory 200168 kb
Host smart-748744c6-e1f9-4030-991f-fbedae7b908c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130320680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.130320680
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2671779014
Short name T331
Test name
Test status
Simulation time 23385008 ps
CPU time 0.63 seconds
Started May 26 02:22:32 PM PDT 24
Finished May 26 02:22:34 PM PDT 24
Peak memory 196004 kb
Host smart-2f5bbfe2-556b-40bd-803c-3820be10ee04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671779014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2671779014
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.3353576524
Short name T48
Test name
Test status
Simulation time 928382671 ps
CPU time 10.24 seconds
Started May 26 02:22:35 PM PDT 24
Finished May 26 02:22:47 PM PDT 24
Peak memory 208240 kb
Host smart-506bd71f-a926-4285-b73f-817009d6fc4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3353576524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3353576524
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2503960537
Short name T159
Test name
Test status
Simulation time 13464607942 ps
CPU time 51.71 seconds
Started May 26 02:22:33 PM PDT 24
Finished May 26 02:23:26 PM PDT 24
Peak memory 200204 kb
Host smart-d1cdfb97-4d9c-4e96-add8-4c408a5220e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503960537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2503960537
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1826659489
Short name T102
Test name
Test status
Simulation time 2115124760 ps
CPU time 501.69 seconds
Started May 26 02:22:36 PM PDT 24
Finished May 26 02:31:00 PM PDT 24
Peak memory 505516 kb
Host smart-604cde94-6d14-4991-9d85-4104ccaad30e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1826659489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1826659489
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3703375247
Short name T366
Test name
Test status
Simulation time 33213388944 ps
CPU time 115.14 seconds
Started May 26 02:22:36 PM PDT 24
Finished May 26 02:24:33 PM PDT 24
Peak memory 200240 kb
Host smart-da2c2e4d-4912-444e-a661-9f5414856831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703375247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3703375247
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1059362422
Short name T432
Test name
Test status
Simulation time 99526849 ps
CPU time 2.04 seconds
Started May 26 02:22:34 PM PDT 24
Finished May 26 02:22:37 PM PDT 24
Peak memory 200168 kb
Host smart-58a09054-f168-4a77-b480-fb2d5add1a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059362422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1059362422
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.1327885746
Short name T317
Test name
Test status
Simulation time 143604342 ps
CPU time 1.28 seconds
Started May 26 02:22:32 PM PDT 24
Finished May 26 02:22:34 PM PDT 24
Peak memory 200224 kb
Host smart-4b1f084e-f413-43c8-8f86-507345abd731
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327885746 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.1327885746
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.2162684166
Short name T174
Test name
Test status
Simulation time 71252214602 ps
CPU time 345.59 seconds
Started May 26 02:22:35 PM PDT 24
Finished May 26 02:28:23 PM PDT 24
Peak memory 200148 kb
Host smart-212d4868-c29a-4a27-a8c1-a8b7e2c711c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162684166 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.2162684166
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.867390629
Short name T504
Test name
Test status
Simulation time 1678147952 ps
CPU time 31.51 seconds
Started May 26 02:22:34 PM PDT 24
Finished May 26 02:23:07 PM PDT 24
Peak memory 200080 kb
Host smart-f2bb7325-e37a-4e08-9abf-263c01072603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867390629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.867390629
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2737806722
Short name T261
Test name
Test status
Simulation time 22765574 ps
CPU time 0.62 seconds
Started May 26 02:22:41 PM PDT 24
Finished May 26 02:22:42 PM PDT 24
Peak memory 196916 kb
Host smart-bad5b7d1-911f-47cf-9398-f1499da3f578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737806722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2737806722
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.3836120795
Short name T367
Test name
Test status
Simulation time 468626261 ps
CPU time 23.84 seconds
Started May 26 02:22:31 PM PDT 24
Finished May 26 02:22:56 PM PDT 24
Peak memory 216528 kb
Host smart-7247ad1c-1b1f-45ea-a17c-fc368f409abd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3836120795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.3836120795
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3996337789
Short name T299
Test name
Test status
Simulation time 5894657821 ps
CPU time 22.1 seconds
Started May 26 02:22:36 PM PDT 24
Finished May 26 02:23:00 PM PDT 24
Peak memory 200168 kb
Host smart-96b5b284-865f-4dce-a299-3b356f6a154b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996337789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3996337789
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_error.772981959
Short name T411
Test name
Test status
Simulation time 55155571579 ps
CPU time 68.65 seconds
Started May 26 02:22:34 PM PDT 24
Finished May 26 02:23:43 PM PDT 24
Peak memory 200080 kb
Host smart-f9d86a8e-666c-4f25-aa5e-64f4521593b8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772981959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.772981959
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.2524023014
Short name T123
Test name
Test status
Simulation time 142859788 ps
CPU time 9.33 seconds
Started May 26 02:22:31 PM PDT 24
Finished May 26 02:22:42 PM PDT 24
Peak memory 200112 kb
Host smart-b1ca6c48-f2a1-4687-828e-66163e8891f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524023014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.2524023014
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1660961564
Short name T472
Test name
Test status
Simulation time 40261751 ps
CPU time 0.95 seconds
Started May 26 02:22:31 PM PDT 24
Finished May 26 02:22:32 PM PDT 24
Peak memory 199452 kb
Host smart-29fd9cb9-9e65-4f17-ac18-34383196a4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660961564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1660961564
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.654394847
Short name T452
Test name
Test status
Simulation time 77311090 ps
CPU time 1.42 seconds
Started May 26 02:22:46 PM PDT 24
Finished May 26 02:22:48 PM PDT 24
Peak memory 200044 kb
Host smart-4d7319f6-7115-4781-8f87-a6834737c3b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654394847 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.hmac_test_hmac_vectors.654394847
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.950953155
Short name T182
Test name
Test status
Simulation time 7187814355 ps
CPU time 381.05 seconds
Started May 26 02:22:32 PM PDT 24
Finished May 26 02:28:54 PM PDT 24
Peak memory 200144 kb
Host smart-fcd41a9c-08d1-4ebd-aa8d-b640b6ddaee2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950953155 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.950953155
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3733839991
Short name T142
Test name
Test status
Simulation time 317727309 ps
CPU time 5.08 seconds
Started May 26 02:22:36 PM PDT 24
Finished May 26 02:22:43 PM PDT 24
Peak memory 200108 kb
Host smart-cff7b86d-96f4-4b08-9c75-6c0f45a10390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733839991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3733839991
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1877303013
Short name T275
Test name
Test status
Simulation time 24559976 ps
CPU time 0.6 seconds
Started May 26 02:22:41 PM PDT 24
Finished May 26 02:22:42 PM PDT 24
Peak memory 195680 kb
Host smart-ddccc088-55d0-4288-8e5b-9a1dd7beaee0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877303013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1877303013
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.243382107
Short name T222
Test name
Test status
Simulation time 1555673377 ps
CPU time 42.11 seconds
Started May 26 02:22:40 PM PDT 24
Finished May 26 02:23:23 PM PDT 24
Peak memory 208372 kb
Host smart-6a8de896-6f8c-4047-8430-c57858dc746e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=243382107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.243382107
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.481731590
Short name T180
Test name
Test status
Simulation time 109427112 ps
CPU time 2.83 seconds
Started May 26 02:22:40 PM PDT 24
Finished May 26 02:22:44 PM PDT 24
Peak memory 200096 kb
Host smart-407f5c35-daf9-4ca5-9f28-5ce02d6a00ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481731590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.481731590
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.3548509799
Short name T193
Test name
Test status
Simulation time 17054491549 ps
CPU time 759.28 seconds
Started May 26 02:22:43 PM PDT 24
Finished May 26 02:35:23 PM PDT 24
Peak memory 745712 kb
Host smart-5fe88867-ec8f-4de4-9f94-019199538a4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3548509799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3548509799
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.1521549613
Short name T364
Test name
Test status
Simulation time 1128338973 ps
CPU time 61.3 seconds
Started May 26 02:22:44 PM PDT 24
Finished May 26 02:23:46 PM PDT 24
Peak memory 200096 kb
Host smart-b4b4d163-5564-4cca-a5b6-6b65064a0d13
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521549613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.1521549613
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2905530056
Short name T293
Test name
Test status
Simulation time 18616951240 ps
CPU time 70.7 seconds
Started May 26 02:22:41 PM PDT 24
Finished May 26 02:23:52 PM PDT 24
Peak memory 200136 kb
Host smart-90cf625e-e5cb-4c5b-829a-4f50257b2ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905530056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2905530056
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1728657453
Short name T408
Test name
Test status
Simulation time 23266812 ps
CPU time 1.06 seconds
Started May 26 02:22:41 PM PDT 24
Finished May 26 02:22:43 PM PDT 24
Peak memory 199984 kb
Host smart-95f128fe-b71e-4531-ba1c-a4e707d3c20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728657453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1728657453
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.4277569134
Short name T105
Test name
Test status
Simulation time 33074926243 ps
CPU time 1235.85 seconds
Started May 26 02:22:40 PM PDT 24
Finished May 26 02:43:16 PM PDT 24
Peak memory 779052 kb
Host smart-242e2cec-d75b-406f-92fb-08bfab04ca1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277569134 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.4277569134
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.2186599964
Short name T43
Test name
Test status
Simulation time 52571275 ps
CPU time 1.25 seconds
Started May 26 02:22:44 PM PDT 24
Finished May 26 02:22:46 PM PDT 24
Peak memory 200116 kb
Host smart-639f1f28-6dae-46f0-80b5-a13af0a5eb37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186599964 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.2186599964
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.1923927513
Short name T320
Test name
Test status
Simulation time 13756538311 ps
CPU time 438.74 seconds
Started May 26 02:22:41 PM PDT 24
Finished May 26 02:30:01 PM PDT 24
Peak memory 200124 kb
Host smart-7cf8a803-de3b-4780-ad76-4b04a28e77f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923927513 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.1923927513
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.2620590473
Short name T259
Test name
Test status
Simulation time 1510840405 ps
CPU time 6.47 seconds
Started May 26 02:22:43 PM PDT 24
Finished May 26 02:22:50 PM PDT 24
Peak memory 200136 kb
Host smart-4ab1c15a-504e-403c-97d4-bb422edf17e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620590473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2620590473
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2706256898
Short name T231
Test name
Test status
Simulation time 29643422 ps
CPU time 0.6 seconds
Started May 26 02:22:42 PM PDT 24
Finished May 26 02:22:43 PM PDT 24
Peak memory 196020 kb
Host smart-490f3684-9376-4d5c-9aff-9f4f604d96c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706256898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2706256898
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.2991396947
Short name T415
Test name
Test status
Simulation time 520671391 ps
CPU time 2.83 seconds
Started May 26 02:22:44 PM PDT 24
Finished May 26 02:22:47 PM PDT 24
Peak memory 200088 kb
Host smart-488315eb-c67b-4343-9e0d-84d6e821d8d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2991396947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2991396947
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.790796154
Short name T156
Test name
Test status
Simulation time 2328884553 ps
CPU time 47.82 seconds
Started May 26 02:22:40 PM PDT 24
Finished May 26 02:23:28 PM PDT 24
Peak memory 200172 kb
Host smart-5897fb15-ebc1-4d70-a17f-8b3aec274c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790796154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.790796154
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.1539816239
Short name T247
Test name
Test status
Simulation time 1950896978 ps
CPU time 436.53 seconds
Started May 26 02:22:45 PM PDT 24
Finished May 26 02:30:03 PM PDT 24
Peak memory 623220 kb
Host smart-94c52e6f-e4a7-4392-84ee-20e2dd2482c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1539816239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.1539816239
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_long_msg.4121476027
Short name T172
Test name
Test status
Simulation time 824205844 ps
CPU time 25.12 seconds
Started May 26 02:22:41 PM PDT 24
Finished May 26 02:23:07 PM PDT 24
Peak memory 200032 kb
Host smart-5bc9b5e0-8d72-4e1e-a8f0-027b144d27ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121476027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.4121476027
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.1139087873
Short name T483
Test name
Test status
Simulation time 758921727 ps
CPU time 7.14 seconds
Started May 26 02:22:43 PM PDT 24
Finished May 26 02:22:51 PM PDT 24
Peak memory 200116 kb
Host smart-075b959a-0709-4a0a-b056-8c51d7cb6a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139087873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1139087873
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.640075220
Short name T466
Test name
Test status
Simulation time 8663113224 ps
CPU time 481.6 seconds
Started May 26 02:22:41 PM PDT 24
Finished May 26 02:30:43 PM PDT 24
Peak memory 200156 kb
Host smart-46567cd8-642e-4c3c-8853-24d66e054698
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640075220 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.640075220
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.4016308842
Short name T237
Test name
Test status
Simulation time 2043727937 ps
CPU time 41.65 seconds
Started May 26 02:22:42 PM PDT 24
Finished May 26 02:23:24 PM PDT 24
Peak memory 200016 kb
Host smart-9a3d25ea-e76d-470d-b1f7-510b41e09c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016308842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.4016308842
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2262355158
Short name T194
Test name
Test status
Simulation time 56764744 ps
CPU time 0.6 seconds
Started May 26 02:22:54 PM PDT 24
Finished May 26 02:22:55 PM PDT 24
Peak memory 195736 kb
Host smart-f3c653f5-b69a-415e-8e5a-8f27865a8922
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262355158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2262355158
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.4236681568
Short name T464
Test name
Test status
Simulation time 1738219021 ps
CPU time 14.23 seconds
Started May 26 02:22:48 PM PDT 24
Finished May 26 02:23:03 PM PDT 24
Peak memory 200088 kb
Host smart-6f89bd46-dd9a-4950-8ea5-6f79d76f6e0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4236681568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.4236681568
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3296743275
Short name T303
Test name
Test status
Simulation time 3640408232 ps
CPU time 27.86 seconds
Started May 26 02:22:47 PM PDT 24
Finished May 26 02:23:16 PM PDT 24
Peak memory 200212 kb
Host smart-1ca52cd9-2884-40c7-a98e-ff72dbd25f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296743275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3296743275
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.944310209
Short name T149
Test name
Test status
Simulation time 514220207 ps
CPU time 116.91 seconds
Started May 26 02:22:48 PM PDT 24
Finished May 26 02:24:46 PM PDT 24
Peak memory 435996 kb
Host smart-1c5df340-8383-4496-b400-019c9c496cac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=944310209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.944310209
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1183422452
Short name T420
Test name
Test status
Simulation time 3699802279 ps
CPU time 45.82 seconds
Started May 26 02:22:49 PM PDT 24
Finished May 26 02:23:36 PM PDT 24
Peak memory 200188 kb
Host smart-6ec5820e-1f29-4eba-b3a3-226a7b8b1871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183422452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1183422452
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2202752582
Short name T412
Test name
Test status
Simulation time 46088323205 ps
CPU time 865.16 seconds
Started May 26 02:22:47 PM PDT 24
Finished May 26 02:37:13 PM PDT 24
Peak memory 224824 kb
Host smart-c87c9142-ad6e-46af-9c3c-2b5e67caf6c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202752582 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2202752582
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.1247083397
Short name T191
Test name
Test status
Simulation time 41398534275 ps
CPU time 522.41 seconds
Started May 26 02:22:49 PM PDT 24
Finished May 26 02:31:32 PM PDT 24
Peak memory 200176 kb
Host smart-0d3f501d-27fa-4007-ae7a-166d6fc283c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247083397 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.1247083397
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1218389680
Short name T130
Test name
Test status
Simulation time 5150202579 ps
CPU time 68.84 seconds
Started May 26 02:22:47 PM PDT 24
Finished May 26 02:23:57 PM PDT 24
Peak memory 200164 kb
Host smart-1d730359-e058-4057-bfa0-f777190d2959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218389680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1218389680
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2479726218
Short name T135
Test name
Test status
Simulation time 27802084 ps
CPU time 0.57 seconds
Started May 26 02:22:50 PM PDT 24
Finished May 26 02:22:52 PM PDT 24
Peak memory 194996 kb
Host smart-86c0cad0-9c57-400f-abae-617307647eb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479726218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2479726218
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.399836876
Short name T251
Test name
Test status
Simulation time 1074055205 ps
CPU time 55.39 seconds
Started May 26 02:22:49 PM PDT 24
Finished May 26 02:23:45 PM PDT 24
Peak memory 217552 kb
Host smart-6d766ec1-5f2d-4708-84da-9ee4c9f2ed4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=399836876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.399836876
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.685577093
Short name T476
Test name
Test status
Simulation time 1806885734 ps
CPU time 34.49 seconds
Started May 26 02:22:47 PM PDT 24
Finished May 26 02:23:23 PM PDT 24
Peak memory 200188 kb
Host smart-10e76181-dbae-4d54-b858-75493ec50a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685577093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.685577093
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3397454816
Short name T143
Test name
Test status
Simulation time 11895581 ps
CPU time 0.72 seconds
Started May 26 02:22:48 PM PDT 24
Finished May 26 02:22:49 PM PDT 24
Peak memory 197228 kb
Host smart-6fad825d-078d-4053-83b6-aa2931f7491c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3397454816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3397454816
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.3683319010
Short name T505
Test name
Test status
Simulation time 1420945097 ps
CPU time 78.76 seconds
Started May 26 02:22:51 PM PDT 24
Finished May 26 02:24:11 PM PDT 24
Peak memory 200024 kb
Host smart-2d879de5-3d89-42c8-b44e-0a369dfe95f4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683319010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.3683319010
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3745802328
Short name T348
Test name
Test status
Simulation time 371451201 ps
CPU time 21.93 seconds
Started May 26 02:22:48 PM PDT 24
Finished May 26 02:23:10 PM PDT 24
Peak memory 200156 kb
Host smart-bff9677e-86f7-469b-be00-44c8bb135d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745802328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3745802328
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1253447859
Short name T474
Test name
Test status
Simulation time 251679986 ps
CPU time 3.62 seconds
Started May 26 02:22:50 PM PDT 24
Finished May 26 02:22:55 PM PDT 24
Peak memory 200168 kb
Host smart-5863f08e-0140-48af-8882-5ecce88841df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253447859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1253447859
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.3872618551
Short name T288
Test name
Test status
Simulation time 50727926373 ps
CPU time 467.03 seconds
Started May 26 02:22:51 PM PDT 24
Finished May 26 02:30:38 PM PDT 24
Peak memory 200140 kb
Host smart-02fa3ae1-55f0-42b8-bc42-5a2038559b8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872618551 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.3872618551
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.2612420245
Short name T266
Test name
Test status
Simulation time 25822268052 ps
CPU time 90 seconds
Started May 26 02:22:47 PM PDT 24
Finished May 26 02:24:18 PM PDT 24
Peak memory 200096 kb
Host smart-9f1dc87b-9eb4-4e91-a215-0db79c4ee9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612420245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2612420245
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3596472684
Short name T436
Test name
Test status
Simulation time 12486408 ps
CPU time 0.63 seconds
Started May 26 02:22:56 PM PDT 24
Finished May 26 02:22:57 PM PDT 24
Peak memory 196032 kb
Host smart-7d41fa5b-9ce2-425c-a6e1-7b7853513a17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596472684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3596472684
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3191235257
Short name T199
Test name
Test status
Simulation time 2179890540 ps
CPU time 50.08 seconds
Started May 26 02:22:56 PM PDT 24
Finished May 26 02:23:47 PM PDT 24
Peak memory 208432 kb
Host smart-5a0fa2d0-a858-4c43-92fe-6c897434ce21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3191235257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3191235257
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.251318532
Short name T120
Test name
Test status
Simulation time 9740387181 ps
CPU time 48.59 seconds
Started May 26 02:22:57 PM PDT 24
Finished May 26 02:23:47 PM PDT 24
Peak memory 200192 kb
Host smart-7e566327-937f-4c57-90b1-8f2f6e32b0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251318532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.251318532
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2593080784
Short name T106
Test name
Test status
Simulation time 5735040610 ps
CPU time 484.8 seconds
Started May 26 02:23:02 PM PDT 24
Finished May 26 02:31:08 PM PDT 24
Peak memory 626180 kb
Host smart-a627005d-3e46-411a-9e04-a942c24e538d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2593080784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2593080784
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2216445450
Short name T221
Test name
Test status
Simulation time 16107227543 ps
CPU time 104.12 seconds
Started May 26 02:22:56 PM PDT 24
Finished May 26 02:24:41 PM PDT 24
Peak memory 200112 kb
Host smart-28e32660-be36-466c-ba29-260c80ff45ff
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216445450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2216445450
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.2945200659
Short name T459
Test name
Test status
Simulation time 3374601739 ps
CPU time 47.79 seconds
Started May 26 02:22:56 PM PDT 24
Finished May 26 02:23:45 PM PDT 24
Peak memory 200200 kb
Host smart-dd3c3a03-d97e-4b81-a7dd-4594148d27a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945200659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2945200659
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.143804382
Short name T82
Test name
Test status
Simulation time 249738606 ps
CPU time 4.41 seconds
Started May 26 02:22:47 PM PDT 24
Finished May 26 02:22:52 PM PDT 24
Peak memory 200188 kb
Host smart-c420a8b4-570a-4f53-88a7-1eb5040ecc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143804382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.143804382
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.1142668719
Short name T165
Test name
Test status
Simulation time 93567824 ps
CPU time 0.95 seconds
Started May 26 02:22:56 PM PDT 24
Finished May 26 02:22:59 PM PDT 24
Peak memory 198928 kb
Host smart-9378c45e-2c54-48ab-b29b-041019e8d67d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142668719 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.1142668719
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.3104912525
Short name T444
Test name
Test status
Simulation time 108400935514 ps
CPU time 491.74 seconds
Started May 26 02:23:02 PM PDT 24
Finished May 26 02:31:15 PM PDT 24
Peak memory 200200 kb
Host smart-d3f72930-acc6-412b-aa5a-00cb5c26f6a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104912525 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.3104912525
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.4148140137
Short name T298
Test name
Test status
Simulation time 960715509 ps
CPU time 17.93 seconds
Started May 26 02:22:57 PM PDT 24
Finished May 26 02:23:16 PM PDT 24
Peak memory 200208 kb
Host smart-de9c051c-3610-4f36-80c4-1c14944305ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148140137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.4148140137
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.435246908
Short name T449
Test name
Test status
Simulation time 376820561 ps
CPU time 16.48 seconds
Started May 26 02:22:56 PM PDT 24
Finished May 26 02:23:14 PM PDT 24
Peak memory 200100 kb
Host smart-ebae460a-5b85-4942-8d05-493457ee0d46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=435246908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.435246908
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2852339041
Short name T272
Test name
Test status
Simulation time 6244177068 ps
CPU time 97.46 seconds
Started May 26 02:22:55 PM PDT 24
Finished May 26 02:24:33 PM PDT 24
Peak memory 200180 kb
Host smart-287c870c-285d-4a0b-a15c-e958bf226bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852339041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2852339041
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2515545338
Short name T373
Test name
Test status
Simulation time 4023002541 ps
CPU time 250.71 seconds
Started May 26 02:22:56 PM PDT 24
Finished May 26 02:27:08 PM PDT 24
Peak memory 686864 kb
Host smart-30e64cd7-aa3b-4207-9c45-d9190fa4ee76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2515545338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2515545338
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_long_msg.2829723208
Short name T297
Test name
Test status
Simulation time 224102933 ps
CPU time 5.77 seconds
Started May 26 02:22:56 PM PDT 24
Finished May 26 02:23:03 PM PDT 24
Peak memory 200188 kb
Host smart-c1298a0e-1d94-4af8-8239-294c00349f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829723208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2829723208
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3512774007
Short name T362
Test name
Test status
Simulation time 386781029 ps
CPU time 4.48 seconds
Started May 26 02:22:56 PM PDT 24
Finished May 26 02:23:02 PM PDT 24
Peak memory 200112 kb
Host smart-34b83913-e887-4121-8eff-e4403b9c383b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512774007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3512774007
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.648231777
Short name T111
Test name
Test status
Simulation time 4100079677 ps
CPU time 197.25 seconds
Started May 26 02:22:56 PM PDT 24
Finished May 26 02:26:15 PM PDT 24
Peak memory 200136 kb
Host smart-42ebde68-7d83-4f05-a74f-c4449deff5ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648231777 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.648231777
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.3427977475
Short name T255
Test name
Test status
Simulation time 141821940 ps
CPU time 1.2 seconds
Started May 26 02:22:55 PM PDT 24
Finished May 26 02:22:57 PM PDT 24
Peak memory 200136 kb
Host smart-839cc153-2ead-4acb-83e8-191e0c69d7e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427977475 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.3427977475
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.2917888952
Short name T250
Test name
Test status
Simulation time 26688964927 ps
CPU time 492.56 seconds
Started May 26 02:22:56 PM PDT 24
Finished May 26 02:31:09 PM PDT 24
Peak memory 200188 kb
Host smart-c003e0f4-4d0e-495f-ba0c-0f8258d1c57a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917888952 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.2917888952
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3219388101
Short name T122
Test name
Test status
Simulation time 3088128685 ps
CPU time 15.32 seconds
Started May 26 02:23:02 PM PDT 24
Finished May 26 02:23:18 PM PDT 24
Peak memory 200172 kb
Host smart-83928bd9-dfdb-4024-8ef1-3e3a11599050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219388101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3219388101
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.613491757
Short name T168
Test name
Test status
Simulation time 52465266 ps
CPU time 0.61 seconds
Started May 26 02:23:04 PM PDT 24
Finished May 26 02:23:06 PM PDT 24
Peak memory 196012 kb
Host smart-0c71738b-6e1b-4e44-a14a-6cad26d28299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613491757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.613491757
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.1423460913
Short name T260
Test name
Test status
Simulation time 2826673940 ps
CPU time 57.49 seconds
Started May 26 02:22:57 PM PDT 24
Finished May 26 02:23:56 PM PDT 24
Peak memory 224756 kb
Host smart-4e969420-f0d4-4af3-bd4b-422c76ecec2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1423460913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.1423460913
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.4287855256
Short name T328
Test name
Test status
Simulation time 3404217254 ps
CPU time 18.04 seconds
Started May 26 02:22:55 PM PDT 24
Finished May 26 02:23:14 PM PDT 24
Peak memory 200164 kb
Host smart-73ba86cf-5007-4df0-960f-c04d91f2cf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287855256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.4287855256
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2570394402
Short name T426
Test name
Test status
Simulation time 501412285 ps
CPU time 8.28 seconds
Started May 26 02:23:02 PM PDT 24
Finished May 26 02:23:11 PM PDT 24
Peak memory 200136 kb
Host smart-cff68e87-4832-4b53-a1b7-1dafa66e1e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570394402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2570394402
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.378413223
Short name T283
Test name
Test status
Simulation time 51830114 ps
CPU time 1.69 seconds
Started May 26 02:23:00 PM PDT 24
Finished May 26 02:23:02 PM PDT 24
Peak memory 200168 kb
Host smart-8be66b3f-cf5b-4238-9025-4725ef3ff93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378413223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.378413223
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.2835527153
Short name T486
Test name
Test status
Simulation time 9362696470 ps
CPU time 463.81 seconds
Started May 26 02:22:57 PM PDT 24
Finished May 26 02:30:42 PM PDT 24
Peak memory 200100 kb
Host smart-ebccc82b-67ea-4e81-a37a-480d6b71db30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835527153 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.2835527153
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.53836379
Short name T228
Test name
Test status
Simulation time 726203747 ps
CPU time 13.09 seconds
Started May 26 02:22:55 PM PDT 24
Finished May 26 02:23:09 PM PDT 24
Peak memory 200164 kb
Host smart-cf4c6570-a54f-46bd-bfdc-0f52f108af9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53836379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.53836379
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.800809439
Short name T326
Test name
Test status
Simulation time 47377707 ps
CPU time 0.61 seconds
Started May 26 02:23:04 PM PDT 24
Finished May 26 02:23:06 PM PDT 24
Peak memory 195964 kb
Host smart-3596bf5d-d410-450b-a764-fabd6a61d18b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800809439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.800809439
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2879150074
Short name T233
Test name
Test status
Simulation time 229932668 ps
CPU time 6.47 seconds
Started May 26 02:23:05 PM PDT 24
Finished May 26 02:23:13 PM PDT 24
Peak memory 200052 kb
Host smart-7634d239-87bb-4f94-b0f2-2fee0ae4194b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2879150074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2879150074
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.4039407464
Short name T407
Test name
Test status
Simulation time 11535336250 ps
CPU time 529.97 seconds
Started May 26 02:23:04 PM PDT 24
Finished May 26 02:31:55 PM PDT 24
Peak memory 708448 kb
Host smart-e42aaead-f7a4-4fe7-9313-be9a214f6fa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4039407464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.4039407464
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2064543359
Short name T126
Test name
Test status
Simulation time 7804096862 ps
CPU time 14.37 seconds
Started May 26 02:23:04 PM PDT 24
Finished May 26 02:23:19 PM PDT 24
Peak memory 199988 kb
Host smart-db9e3646-eeac-4806-b78a-7e1f9411f3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064543359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2064543359
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3686351285
Short name T354
Test name
Test status
Simulation time 620852425 ps
CPU time 6.89 seconds
Started May 26 02:23:03 PM PDT 24
Finished May 26 02:23:11 PM PDT 24
Peak memory 200140 kb
Host smart-ad1eabb7-3e6a-4a44-91aa-9e4236b0f4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686351285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3686351285
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.4096909397
Short name T144
Test name
Test status
Simulation time 16626323934 ps
CPU time 909.32 seconds
Started May 26 02:23:05 PM PDT 24
Finished May 26 02:38:16 PM PDT 24
Peak memory 200132 kb
Host smart-c19f4ab9-7d4f-4559-b6b9-1b213d2ef39d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096909397 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.4096909397
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.1134818808
Short name T25
Test name
Test status
Simulation time 281359078 ps
CPU time 1.28 seconds
Started May 26 02:23:05 PM PDT 24
Finished May 26 02:23:08 PM PDT 24
Peak memory 200068 kb
Host smart-853af664-fc55-4fbf-846b-4f934ce56c66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134818808 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.1134818808
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.2341060303
Short name T458
Test name
Test status
Simulation time 139090572769 ps
CPU time 528.46 seconds
Started May 26 02:23:02 PM PDT 24
Finished May 26 02:31:51 PM PDT 24
Peak memory 200276 kb
Host smart-3ccc1391-e88b-4641-ac43-86290185f822
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341060303 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.2341060303
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1362951920
Short name T236
Test name
Test status
Simulation time 28061394 ps
CPU time 0.75 seconds
Started May 26 02:20:58 PM PDT 24
Finished May 26 02:20:59 PM PDT 24
Peak memory 196780 kb
Host smart-778e6df4-3566-41bf-b2ff-301f52c763d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362951920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1362951920
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1252585357
Short name T129
Test name
Test status
Simulation time 61709459 ps
CPU time 4.2 seconds
Started May 26 02:20:59 PM PDT 24
Finished May 26 02:21:03 PM PDT 24
Peak memory 199932 kb
Host smart-cb13acfd-4531-4da7-a43b-980ac31c1874
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1252585357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1252585357
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.466608501
Short name T230
Test name
Test status
Simulation time 1877687349 ps
CPU time 26.61 seconds
Started May 26 02:21:07 PM PDT 24
Finished May 26 02:21:35 PM PDT 24
Peak memory 200040 kb
Host smart-f017a30d-5839-4601-bff4-1b7dd70e439d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466608501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.466608501
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.4264417382
Short name T137
Test name
Test status
Simulation time 2110127356 ps
CPU time 339.32 seconds
Started May 26 02:21:10 PM PDT 24
Finished May 26 02:26:51 PM PDT 24
Peak memory 453756 kb
Host smart-5c41c0eb-7574-4d95-9b42-efeccd45b2b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4264417382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.4264417382
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_long_msg.1786124990
Short name T374
Test name
Test status
Simulation time 1612916842 ps
CPU time 12.03 seconds
Started May 26 02:21:07 PM PDT 24
Finished May 26 02:21:20 PM PDT 24
Peak memory 200136 kb
Host smart-c650b466-4c94-4699-b112-afbd0a80cdf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786124990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1786124990
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1567605477
Short name T136
Test name
Test status
Simulation time 47874096 ps
CPU time 0.83 seconds
Started May 26 02:21:10 PM PDT 24
Finished May 26 02:21:13 PM PDT 24
Peak memory 196968 kb
Host smart-7b86ddfd-ab3c-4188-8de4-9848a8dc17d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567605477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1567605477
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.896819938
Short name T360
Test name
Test status
Simulation time 61848659 ps
CPU time 1.08 seconds
Started May 26 02:21:12 PM PDT 24
Finished May 26 02:21:14 PM PDT 24
Peak memory 200016 kb
Host smart-8396ccf8-e38a-4568-b9d4-928835ad61c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896819938 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_hmac_vectors.896819938
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.1530391081
Short name T171
Test name
Test status
Simulation time 52500875749 ps
CPU time 496.7 seconds
Started May 26 02:21:08 PM PDT 24
Finished May 26 02:29:26 PM PDT 24
Peak memory 200168 kb
Host smart-b4889d9e-8115-48f3-9656-313ae34cb4ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530391081 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.1530391081
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.4063137237
Short name T497
Test name
Test status
Simulation time 1304398941 ps
CPU time 64.7 seconds
Started May 26 02:21:06 PM PDT 24
Finished May 26 02:22:12 PM PDT 24
Peak memory 200100 kb
Host smart-fbda4f77-ff75-4138-9cad-47dbfe33072b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063137237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.4063137237
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1915078532
Short name T337
Test name
Test status
Simulation time 12020349 ps
CPU time 0.63 seconds
Started May 26 02:21:10 PM PDT 24
Finished May 26 02:21:12 PM PDT 24
Peak memory 194828 kb
Host smart-ccae235c-ac7c-4ecc-8bc3-e2822ba7c545
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915078532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1915078532
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.4082910250
Short name T309
Test name
Test status
Simulation time 201244466 ps
CPU time 6.26 seconds
Started May 26 02:21:00 PM PDT 24
Finished May 26 02:21:07 PM PDT 24
Peak memory 215544 kb
Host smart-71921e04-42c8-4d13-87e7-5f2116a93b3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4082910250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.4082910250
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.2846308705
Short name T277
Test name
Test status
Simulation time 2852134976 ps
CPU time 43.18 seconds
Started May 26 02:21:12 PM PDT 24
Finished May 26 02:21:57 PM PDT 24
Peak memory 200168 kb
Host smart-10a9a4ee-3f84-4979-ae51-885b7ca78060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846308705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2846308705
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2788160931
Short name T83
Test name
Test status
Simulation time 12177319865 ps
CPU time 642.5 seconds
Started May 26 02:21:13 PM PDT 24
Finished May 26 02:31:57 PM PDT 24
Peak memory 700692 kb
Host smart-394e3898-8cec-4292-816a-5c92ad54ce66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2788160931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2788160931
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.2476527069
Short name T344
Test name
Test status
Simulation time 1563511327 ps
CPU time 14.96 seconds
Started May 26 02:21:10 PM PDT 24
Finished May 26 02:21:26 PM PDT 24
Peak memory 199972 kb
Host smart-dd764f2b-8752-414d-9e17-6d7a5aa52397
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476527069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2476527069
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.416560748
Short name T379
Test name
Test status
Simulation time 552481565 ps
CPU time 2.74 seconds
Started May 26 02:21:06 PM PDT 24
Finished May 26 02:21:09 PM PDT 24
Peak memory 200136 kb
Host smart-6a37295b-fb35-4dea-9d5d-100bd6d78d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416560748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.416560748
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3092330123
Short name T189
Test name
Test status
Simulation time 183699228 ps
CPU time 6.09 seconds
Started May 26 02:20:58 PM PDT 24
Finished May 26 02:21:04 PM PDT 24
Peak memory 200160 kb
Host smart-c76983ae-c144-457b-b40a-3e6427553a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092330123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3092330123
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.3659980731
Short name T21
Test name
Test status
Simulation time 1054952029 ps
CPU time 55.72 seconds
Started May 26 02:21:07 PM PDT 24
Finished May 26 02:22:04 PM PDT 24
Peak memory 200064 kb
Host smart-bad5255b-b10b-467e-bf15-759b913ce283
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659980731 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3659980731
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.3243156015
Short name T372
Test name
Test status
Simulation time 70970254 ps
CPU time 1.36 seconds
Started May 26 02:21:09 PM PDT 24
Finished May 26 02:21:12 PM PDT 24
Peak memory 200092 kb
Host smart-196ef0db-564d-46e0-891d-b68bc4229c46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243156015 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.3243156015
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.3372013754
Short name T381
Test name
Test status
Simulation time 15602109408 ps
CPU time 468.23 seconds
Started May 26 02:21:06 PM PDT 24
Finished May 26 02:28:55 PM PDT 24
Peak memory 200192 kb
Host smart-a189e385-e746-45cc-bbbf-fed130f4ab0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372013754 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.3372013754
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2803046048
Short name T32
Test name
Test status
Simulation time 526369308 ps
CPU time 8.09 seconds
Started May 26 02:21:08 PM PDT 24
Finished May 26 02:21:17 PM PDT 24
Peak memory 200004 kb
Host smart-587c7200-e72f-45f2-a3de-70af5480f6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803046048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2803046048
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3989437864
Short name T494
Test name
Test status
Simulation time 14052310 ps
CPU time 0.57 seconds
Started May 26 02:21:09 PM PDT 24
Finished May 26 02:21:11 PM PDT 24
Peak memory 194980 kb
Host smart-c951481d-3341-4557-b6c7-1a0168e332ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989437864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3989437864
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2570062512
Short name T119
Test name
Test status
Simulation time 4715416674 ps
CPU time 44.27 seconds
Started May 26 02:21:13 PM PDT 24
Finished May 26 02:21:59 PM PDT 24
Peak memory 214216 kb
Host smart-aab27e2b-cee3-4bc2-bc0a-7cde8b9e3a07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2570062512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2570062512
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3347448514
Short name T206
Test name
Test status
Simulation time 795732258 ps
CPU time 11.93 seconds
Started May 26 02:21:09 PM PDT 24
Finished May 26 02:21:23 PM PDT 24
Peak memory 200032 kb
Host smart-36624069-dd98-419a-a861-9ac57e8b3f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347448514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3347448514
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.1089598425
Short name T490
Test name
Test status
Simulation time 17288773005 ps
CPU time 811.83 seconds
Started May 26 02:21:11 PM PDT 24
Finished May 26 02:34:45 PM PDT 24
Peak memory 669504 kb
Host smart-e9a690b1-88e4-4402-8148-e4bef2e83e13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1089598425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1089598425
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_long_msg.1643881065
Short name T461
Test name
Test status
Simulation time 1219757023 ps
CPU time 69.47 seconds
Started May 26 02:21:13 PM PDT 24
Finished May 26 02:22:24 PM PDT 24
Peak memory 200116 kb
Host smart-dd691405-eea9-4de3-8f72-ed9017980911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643881065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1643881065
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.4289803980
Short name T305
Test name
Test status
Simulation time 145212992 ps
CPU time 4.83 seconds
Started May 26 02:21:07 PM PDT 24
Finished May 26 02:21:13 PM PDT 24
Peak memory 200096 kb
Host smart-d201777f-6a1b-4a64-baa9-bcf26ca42579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289803980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.4289803980
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1266627064
Short name T73
Test name
Test status
Simulation time 167872543981 ps
CPU time 935.35 seconds
Started May 26 02:21:10 PM PDT 24
Finished May 26 02:36:47 PM PDT 24
Peak memory 702532 kb
Host smart-7f25713d-4a80-49f9-b555-0e241dfc0342
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266627064 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1266627064
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.2438156307
Short name T471
Test name
Test status
Simulation time 104468328 ps
CPU time 1.15 seconds
Started May 26 02:21:08 PM PDT 24
Finished May 26 02:21:10 PM PDT 24
Peak memory 200000 kb
Host smart-91a56d2c-1779-41be-906e-95a0be3098c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438156307 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.2438156307
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.409342439
Short name T290
Test name
Test status
Simulation time 8402752971 ps
CPU time 480.4 seconds
Started May 26 02:21:08 PM PDT 24
Finished May 26 02:29:10 PM PDT 24
Peak memory 200108 kb
Host smart-b23bfcce-7bf1-485e-9f97-13426b8e3243
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409342439 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.409342439
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1388430196
Short name T430
Test name
Test status
Simulation time 555984527 ps
CPU time 28.09 seconds
Started May 26 02:21:15 PM PDT 24
Finished May 26 02:21:44 PM PDT 24
Peak memory 200104 kb
Host smart-d9f532eb-5dcc-4b83-a5a5-633f1d39301f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388430196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1388430196
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3168513494
Short name T23
Test name
Test status
Simulation time 14204833 ps
CPU time 0.57 seconds
Started May 26 02:21:11 PM PDT 24
Finished May 26 02:21:13 PM PDT 24
Peak memory 195728 kb
Host smart-dc368453-8e03-4cb0-a1ec-1bc2be50084d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168513494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3168513494
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2999391654
Short name T50
Test name
Test status
Simulation time 834228098 ps
CPU time 11.69 seconds
Started May 26 02:21:08 PM PDT 24
Finished May 26 02:21:21 PM PDT 24
Peak memory 200096 kb
Host smart-81962ab8-99be-47c4-a737-7bbc5c35c8c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2999391654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2999391654
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1690921791
Short name T356
Test name
Test status
Simulation time 5309332682 ps
CPU time 79.42 seconds
Started May 26 02:21:06 PM PDT 24
Finished May 26 02:22:26 PM PDT 24
Peak memory 200200 kb
Host smart-926ae8be-d995-45e6-94dc-38f5b9ddfb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690921791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1690921791
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3708432281
Short name T6
Test name
Test status
Simulation time 6022812145 ps
CPU time 683.46 seconds
Started May 26 02:21:06 PM PDT 24
Finished May 26 02:32:31 PM PDT 24
Peak memory 642256 kb
Host smart-46411352-8e56-42ae-a117-e0d87d7b7467
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3708432281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3708432281
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_long_msg.2513892892
Short name T166
Test name
Test status
Simulation time 4079741992 ps
CPU time 82.26 seconds
Started May 26 02:21:07 PM PDT 24
Finished May 26 02:22:30 PM PDT 24
Peak memory 200160 kb
Host smart-542991ad-28a4-447a-bc2d-d9b33365be4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513892892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.2513892892
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1444161222
Short name T10
Test name
Test status
Simulation time 1203848252 ps
CPU time 6.14 seconds
Started May 26 02:21:09 PM PDT 24
Finished May 26 02:21:17 PM PDT 24
Peak memory 200184 kb
Host smart-228e4eb1-1538-465a-8674-b7e8decc9b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444161222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1444161222
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.2443227898
Short name T353
Test name
Test status
Simulation time 166149449783 ps
CPU time 421.37 seconds
Started May 26 02:21:09 PM PDT 24
Finished May 26 02:28:12 PM PDT 24
Peak memory 200120 kb
Host smart-e58022ff-1f11-4c89-addc-2a8dfce132e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443227898 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.2443227898
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1650251425
Short name T229
Test name
Test status
Simulation time 1791576266 ps
CPU time 89.59 seconds
Started May 26 02:21:13 PM PDT 24
Finished May 26 02:22:44 PM PDT 24
Peak memory 200112 kb
Host smart-36cfc6b1-d6fc-4f90-b8cd-8e8a3a4041a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650251425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1650251425
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.896201955
Short name T157
Test name
Test status
Simulation time 30886501 ps
CPU time 0.59 seconds
Started May 26 02:21:11 PM PDT 24
Finished May 26 02:21:13 PM PDT 24
Peak memory 196008 kb
Host smart-0d766ccf-6777-4aed-bb0c-081b79d8547c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896201955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.896201955
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2892305167
Short name T286
Test name
Test status
Simulation time 2940653145 ps
CPU time 21.96 seconds
Started May 26 02:21:08 PM PDT 24
Finished May 26 02:21:31 PM PDT 24
Peak memory 200188 kb
Host smart-53a16240-c011-4dbf-9d79-ba2ae9b32f79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2892305167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2892305167
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.706810835
Short name T341
Test name
Test status
Simulation time 4572961313 ps
CPU time 23.5 seconds
Started May 26 02:21:06 PM PDT 24
Finished May 26 02:21:30 PM PDT 24
Peak memory 200204 kb
Host smart-f86dcff6-0c18-40fb-8903-10e5560164dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706810835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.706810835
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3899580627
Short name T484
Test name
Test status
Simulation time 3489588789 ps
CPU time 154.73 seconds
Started May 26 02:21:21 PM PDT 24
Finished May 26 02:23:56 PM PDT 24
Peak memory 421220 kb
Host smart-1b48e374-4a7a-4577-bc6a-3d7a3fb8c451
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3899580627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3899580627
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_long_msg.1729499235
Short name T227
Test name
Test status
Simulation time 39573114225 ps
CPU time 143.21 seconds
Started May 26 02:21:14 PM PDT 24
Finished May 26 02:23:38 PM PDT 24
Peak memory 200180 kb
Host smart-3affadd9-817d-499d-80bd-cfe5e5db31e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729499235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1729499235
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2673143806
Short name T503
Test name
Test status
Simulation time 30395119 ps
CPU time 1.08 seconds
Started May 26 02:21:12 PM PDT 24
Finished May 26 02:21:14 PM PDT 24
Peak memory 199964 kb
Host smart-2edb7b1b-aed0-49ab-b092-40f45717cdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673143806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2673143806
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.1664241556
Short name T262
Test name
Test status
Simulation time 190738738 ps
CPU time 1.16 seconds
Started May 26 02:21:07 PM PDT 24
Finished May 26 02:21:09 PM PDT 24
Peak memory 200012 kb
Host smart-dda60e4d-65a5-45ce-a73c-f41d467e6d60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664241556 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.1664241556
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.1630834914
Short name T418
Test name
Test status
Simulation time 63685481437 ps
CPU time 434.04 seconds
Started May 26 02:21:14 PM PDT 24
Finished May 26 02:28:29 PM PDT 24
Peak memory 200156 kb
Host smart-421f0168-4cf9-44c5-b948-33e7798a064c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630834914 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.1630834914
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.1651163016
Short name T220
Test name
Test status
Simulation time 9896413378 ps
CPU time 69.1 seconds
Started May 26 02:21:13 PM PDT 24
Finished May 26 02:22:24 PM PDT 24
Peak memory 200176 kb
Host smart-b45632d4-dd73-408e-abaf-83f158156a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651163016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1651163016
Directory /workspace/9.hmac_wipe_secret/latest
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