Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14905940	1			T1	4429		T2	21346		T3	141757
all_values[1]	14905940	1			T1	4429		T2	21346		T3	141757
all_values[2]	14905940	1			T1	4429		T2	21346		T3	141757

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

141687

1

T3

316

T7

773

T4

282

auto[1]

44576133

1

T1

13287

T2

64038

T3

424955

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37257349

1

T1

11259

T2

49359

T3

373851

auto[1]

7460471

1

T1

2028

T2

14679

T3

51420

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	54677	1			T3	27		T4	282		T14	28
all_values[0]	auto[0]	auto[1]	370	1			T3	4		T14	2		T24	1
all_values[0]	auto[1]	auto[0]	14813076	1			T1	4420		T2	21333		T3	141272
all_values[0]	auto[1]	auto[1]	37817	1			T1	9		T2	13		T3	454
all_values[1]	auto[0]	auto[0]	42925	1			T3	237		T7	773		T26	467
all_values[1]	auto[0]	auto[1]	197	1			T24	2		T13	5		T25	3
all_values[1]	auto[1]	auto[0]	14862476	1			T1	4429		T2	21346		T3	141515
all_values[1]	auto[1]	auto[1]	342	1			T3	5		T24	9		T13	21
all_values[2]	auto[0]	auto[0]	20859	1			T3	40		T49	338		T26	467
all_values[2]	auto[0]	auto[1]	22659	1			T3	8		T27	334		T13	473
all_values[2]	auto[1]	auto[0]	7463336	1			T1	2410		T2	6680		T3	90760
all_values[2]	auto[1]	auto[1]	7399086	1			T1	2019		T2	14666		T3	50949