Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6912988

1

T1

1336

T2

3029

T3

64566

auto[1]

2671617

1

T1

3080

T2

3993

T3

44015

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2686478

1

T1

2129

T2

3186

T3

33351

auto[1]

6898127

1

T1

2287

T2

3836

T3

75230

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5771800

1

T1

681

T2

3129

T3

48308

auto[1]

3812805

1

T1

3735

T2

3893

T3

60273

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	7510732	1			T1	3008		T2	5625		T3	103112
fifo_depth[1]	329194	1			T1	174		T2	257		T3	2890
fifo_depth[2]	280788	1			T1	157		T2	226		T3	1536
fifo_depth[3]	227304	1			T1	148		T2	181		T3	637
fifo_depth[4]	189663	1			T1	164		T2	145		T3	239
fifo_depth[5]	162960	1			T1	148		T2	126		T3	77
fifo_depth[6]	153973	1			T1	139		T2	120		T3	57
fifo_depth[7]	127273	1			T1	147		T2	99		T3	10

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2073873

1

T1

1408

T2

1397

T3

5469

auto[1]

7510732

1

T1

3008

T2

5625

T3

103112

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9571174

1

T1

4416

T2

7022

T3

108581

auto[1]

13431

1

T17

2

T18

15

T24

152

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

102059

1

T3

98

T4

33

T14

1

auto[0]

auto[0]

auto[0]

auto[1]

98623

1

T1

299

T2

82

T3

256

auto[0]

auto[0]

auto[1]

auto[0]

1014667

1

T1

119

T2

307

T3

2768

auto[0]

auto[0]

auto[1]

auto[1]

105165

1

T2

209

T3

157

T7

1

auto[0]

auto[1]

auto[0]

auto[0]

190148

1

T1

742

T2

376

T3

255

auto[0]

auto[1]

auto[0]

auto[1]

193411

1

T1

166

T3

592

T4

20

auto[0]

auto[1]

auto[1]

auto[0]

174263

1

T3

547

T16

2

T4

139

auto[0]

auto[1]

auto[1]

auto[1]

195537

1

T1

82

T2

423

T3

796

auto[1]

auto[0]

auto[0]

auto[0]

275199

1

T2

370

T3

2445

T7

363

auto[1]

auto[0]

auto[0]

auto[1]

263306

1

T1

189

T2

656

T3

4508

auto[1]

auto[0]

auto[1]

auto[0]

3638693

1

T1

63

T2

627

T3

36052

auto[1]

auto[0]

auto[1]

auto[1]

274088

1

T1

11

T2

878

T3

2024

auto[1]

auto[1]

auto[0]

auto[0]

780643

1

T1

412

T2

1345

T3

10949

auto[1]

auto[1]

auto[0]

auto[1]

783089

1

T1

321

T2

357

T3

14248

auto[1]

auto[1]

auto[1]

auto[0]

737316

1

T2

4

T3

11452

T16

22

auto[1]

auto[1]

auto[1]

auto[1]

758398

1

T1

2012

T2

1388

T3

21434

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

374606

1

T2

370

T3

2543

T7

363

auto[0]

auto[0]

auto[0]

auto[1]

359016

1

T1

488

T2

738

T3

4764

auto[0]

auto[0]

auto[1]

auto[0]

4650899

1

T1

182

T2

934

T3

38820

auto[0]

auto[0]

auto[1]

auto[1]

377338

1

T1

11

T2

1087

T3

2181

auto[0]

auto[1]

auto[0]

auto[0]

969709

1

T1

1154

T2

1721

T3

11204

auto[0]

auto[1]

auto[0]

auto[1]

975707

1

T1

487

T2

357

T3

14840

auto[0]

auto[1]

auto[1]

auto[0]

910618

1

T2

4

T3

11999

T16

24

auto[0]

auto[1]

auto[1]

auto[1]

953281

1

T1

2094

T2

1811

T3

22230

auto[1]

auto[0]

auto[0]

auto[0]

2652

1

T24

1

T13

2

T45

1

auto[1]

auto[0]

auto[0]

auto[1]

2913

1

T24

22

T43

1

T13

24

auto[1]

auto[0]

auto[1]

auto[0]

2461

1

T18

15

T24

3

T19

2

auto[1]

auto[0]

auto[1]

auto[1]

1915

1

T17

1

T24

2

T13

5

auto[1]

auto[1]

auto[0]

auto[0]

1082

1

T17

1

T24

9

T19

1

auto[1]

auto[1]

auto[0]

auto[1]

793

1

T24

11

T13

24

T25

6

auto[1]

auto[1]

auto[1]

auto[0]

961

1

T24

2

T13

39

T45

1

auto[1]

auto[1]

auto[1]

auto[1]

654

1

T24

102

T13

134

T46

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	275199	1			T2	370		T3	2445		T7	363
fifo_depth[0]	auto[0]	auto[0]	auto[1]	263306	1			T1	189		T2	656		T3	4508
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3638693	1			T1	63		T2	627		T3	36052
fifo_depth[0]	auto[0]	auto[1]	auto[1]	274088	1			T1	11		T2	878		T3	2024
fifo_depth[0]	auto[1]	auto[0]	auto[0]	780643	1			T1	412		T2	1345		T3	10949
fifo_depth[0]	auto[1]	auto[0]	auto[1]	783089	1			T1	321		T2	357		T3	14248
fifo_depth[0]	auto[1]	auto[1]	auto[0]	737316	1			T2	4		T3	11452		T16	22
fifo_depth[0]	auto[1]	auto[1]	auto[1]	758398	1			T1	2012		T2	1388		T3	21434
fifo_depth[1]	auto[0]	auto[0]	auto[0]	7877	1			T3	40		T4	26		T15	31
fifo_depth[1]	auto[0]	auto[0]	auto[1]	7827	1			T1	39		T2	30		T3	123
fifo_depth[1]	auto[0]	auto[1]	auto[0]	227866	1			T1	11		T2	37		T3	1584
fifo_depth[1]	auto[0]	auto[1]	auto[1]	7827	1			T2	76		T3	82		T7	1
fifo_depth[1]	auto[1]	auto[0]	auto[0]	18948	1			T1	92		T2	62		T3	116
fifo_depth[1]	auto[1]	auto[0]	auto[1]	20465	1			T1	21		T3	271		T4	16
fifo_depth[1]	auto[1]	auto[1]	auto[0]	18315	1			T3	261		T16	2		T4	92
fifo_depth[1]	auto[1]	auto[1]	auto[1]	20069	1			T1	11		T2	52		T3	413
fifo_depth[2]	auto[0]	auto[0]	auto[0]	7242	1			T3	29		T4	7		T15	36
fifo_depth[2]	auto[0]	auto[0]	auto[1]	7486	1			T1	29		T2	28		T3	85
fifo_depth[2]	auto[0]	auto[1]	auto[0]	185183	1			T1	19		T2	36		T3	750
fifo_depth[2]	auto[0]	auto[1]	auto[1]	7443	1			T2	66		T3	38		T4	1
fifo_depth[2]	auto[1]	auto[0]	auto[0]	18258	1			T1	87		T2	50		T3	73
fifo_depth[2]	auto[1]	auto[0]	auto[1]	18973	1			T1	12		T3	177		T4	3
fifo_depth[2]	auto[1]	auto[1]	auto[0]	17603	1			T3	154		T4	30		T5	273
fifo_depth[2]	auto[1]	auto[1]	auto[1]	18600	1			T1	10		T2	46		T3	230
fifo_depth[3]	auto[0]	auto[0]	auto[0]	5878	1			T3	8		T15	30		T49	2
fifo_depth[3]	auto[0]	auto[0]	auto[1]	5719	1			T1	25		T2	18		T3	26
fifo_depth[3]	auto[0]	auto[1]	auto[0]	142541	1			T1	9		T2	27		T3	273
fifo_depth[3]	auto[0]	auto[1]	auto[1]	6009	1			T2	53		T3	22		T4	1
fifo_depth[3]	auto[1]	auto[0]	auto[0]	16733	1			T1	90		T2	35		T3	45
fifo_depth[3]	auto[1]	auto[0]	auto[1]	17146	1			T1	15		T3	77		T4	1
fifo_depth[3]	auto[1]	auto[1]	auto[0]	16134	1			T3	92		T4	15		T5	258
fifo_depth[3]	auto[1]	auto[1]	auto[1]	17144	1			T1	9		T2	48		T3	94
fifo_depth[4]	auto[0]	auto[0]	auto[0]	6382	1			T3	4		T15	23		T26	1
fifo_depth[4]	auto[0]	auto[0]	auto[1]	5884	1			T1	41		T2	6		T3	12
fifo_depth[4]	auto[0]	auto[1]	auto[0]	104739	1			T1	10		T2	35		T3	109
fifo_depth[4]	auto[0]	auto[1]	auto[1]	6201	1			T2	12		T3	7		T15	48
fifo_depth[4]	auto[1]	auto[0]	auto[0]	16584	1			T1	85		T2	45		T3	15
fifo_depth[4]	auto[1]	auto[0]	auto[1]	17251	1			T1	18		T3	34		T5	178
fifo_depth[4]	auto[1]	auto[1]	auto[0]	16181	1			T3	30		T4	2		T5	298
fifo_depth[4]	auto[1]	auto[1]	auto[1]	16441	1			T1	10		T2	47		T3	28
fifo_depth[5]	auto[0]	auto[0]	auto[0]	5399	1			T3	6		T15	31		T50	1
fifo_depth[5]	auto[0]	auto[0]	auto[1]	5013	1			T1	32		T3	1		T26	1
fifo_depth[5]	auto[0]	auto[1]	auto[0]	83952	1			T1	17		T2	41		T3	24
fifo_depth[5]	auto[0]	auto[1]	auto[1]	5413	1			T2	2		T3	5		T15	63
fifo_depth[5]	auto[1]	auto[0]	auto[0]	15852	1			T1	77		T2	34		T3	6
fifo_depth[5]	auto[1]	auto[0]	auto[1]	16217	1			T1	15		T3	16		T5	167
fifo_depth[5]	auto[1]	auto[1]	auto[0]	15114	1			T3	7		T5	267		T14	1
fifo_depth[5]	auto[1]	auto[1]	auto[1]	16000	1			T1	7		T2	49		T3	12
fifo_depth[6]	auto[0]	auto[0]	auto[0]	6074	1			T3	5		T15	37		T50	3
fifo_depth[6]	auto[0]	auto[0]	auto[1]	5634	1			T1	31		T3	7		T18	7
fifo_depth[6]	auto[0]	auto[1]	auto[0]	72201	1			T1	14		T2	35		T3	24
fifo_depth[6]	auto[0]	auto[1]	auto[1]	6061	1			T3	1		T15	52		T18	7
fifo_depth[6]	auto[1]	auto[0]	auto[0]	16160	1			T1	68		T2	27		T5	127
fifo_depth[6]	auto[1]	auto[0]	auto[1]	16590	1			T1	15		T3	8		T5	142
fifo_depth[6]	auto[1]	auto[1]	auto[0]	15366	1			T3	1		T5	263		T24	281
fifo_depth[6]	auto[1]	auto[1]	auto[1]	15887	1			T1	11		T2	58		T3	11
fifo_depth[7]	auto[0]	auto[0]	auto[0]	4956	1			T3	3		T15	25		T18	6
fifo_depth[7]	auto[0]	auto[0]	auto[1]	4459	1			T1	37		T18	5		T24	85
fifo_depth[7]	auto[0]	auto[1]	auto[0]	56026	1			T1	10		T2	30		T3	3
fifo_depth[7]	auto[0]	auto[1]	auto[1]	4917	1			T3	1		T15	40		T18	3
fifo_depth[7]	auto[1]	auto[0]	auto[0]	14334	1			T1	79		T2	36		T5	122
fifo_depth[7]	auto[1]	auto[0]	auto[1]	14433	1			T1	11		T5	162		T50	1
fifo_depth[7]	auto[1]	auto[1]	auto[0]	13798	1			T5	244		T24	194		T69	2
fifo_depth[7]	auto[1]	auto[1]	auto[1]	14350	1			T1	10		T2	33		T3	3