Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	14905940	1			T1	4429		T2	21346		T3	141757
all_pins[1]	14905940	1			T1	4429		T2	21346		T3	141757
all_pins[2]	14905940	1			T1	4429		T2	21346		T3	141757

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	37279867	1			T1	11259		T2	49359		T3	373858
values[0x1]	7437953	1			T1	2028		T2	14679		T3	51413
transitions[0x0=>0x1]	7437800	1			T1	2028		T2	14679		T3	51409
transitions[0x1=>0x0]	7437815	1			T1	2028		T2	14679		T3	51409

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	14867423	1			T1	4420		T2	21333		T3	141298
all_pins[0]	values[0x1]	38517	1			T1	9		T2	13		T3	459
all_pins[0]	transitions[0x0=>0x1]	38433	1			T1	9		T2	13		T3	458
all_pins[0]	transitions[0x1=>0x0]	7399017	1			T1	2019		T2	14666		T3	50948
all_pins[1]	values[0x0]	14905590	1			T1	4429		T2	21346		T3	141752
all_pins[1]	values[0x1]	350	1			T3	5		T24	9		T13	21
all_pins[1]	transitions[0x0=>0x1]	308	1			T3	4		T24	7		T13	20
all_pins[1]	transitions[0x1=>0x0]	38475	1			T1	9		T2	13		T3	458
all_pins[2]	values[0x0]	7506854	1			T1	2410		T2	6680		T3	90808
all_pins[2]	values[0x1]	7399086	1			T1	2019		T2	14666		T3	50949
all_pins[2]	transitions[0x0=>0x1]	7399059	1			T1	2019		T2	14666		T3	50947
all_pins[2]	transitions[0x1=>0x0]	323	1			T3	3		T24	9		T13	21