Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 821 1 T3 10 T24 8 T13 26
all_values[1] 821 1 T3 10 T24 8 T13 26
all_values[2] 821 1 T3 10 T24 8 T13 26



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1331 1 T3 11 T24 15 T13 47
auto[1] 1132 1 T3 19 T24 9 T13 31



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 882 1 T3 10 T24 9 T13 40
auto[1] 1581 1 T3 20 T24 15 T13 38



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1410 1 T3 17 T24 13 T13 54
auto[1] 1053 1 T3 13 T24 11 T13 24



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 158 1 T3 2 T24 1 T13 12
all_values[0] auto[0] auto[0] auto[1] 92 1 T3 2 T24 1 T13 2
all_values[0] auto[0] auto[1] auto[0] 149 1 T3 3 T24 2 T13 3
all_values[0] auto[0] auto[1] auto[1] 83 1 T3 1 T24 1 T13 1
all_values[0] auto[1] auto[0] auto[1] 185 1 T3 2 T24 1 T13 5
all_values[0] auto[1] auto[1] auto[1] 154 1 T24 2 T13 3 T25 3
all_values[1] auto[0] auto[0] auto[0] 130 1 T3 1 T24 1 T13 6
all_values[1] auto[0] auto[0] auto[1] 107 1 T24 1 T13 6 T25 2
all_values[1] auto[0] auto[1] auto[0] 118 1 T3 2 T13 5 T25 3
all_values[1] auto[0] auto[1] auto[1] 95 1 T3 2 T24 1 T13 1
all_values[1] auto[1] auto[0] auto[1] 213 1 T24 3 T13 5 T25 4
all_values[1] auto[1] auto[1] auto[1] 158 1 T3 5 T24 2 T13 3
all_values[2] auto[0] auto[0] auto[0] 170 1 T3 1 T24 4 T13 4
all_values[2] auto[0] auto[0] auto[1] 88 1 T3 1 T13 3 T25 1
all_values[2] auto[0] auto[1] auto[0] 157 1 T3 1 T24 1 T13 10
all_values[2] auto[0] auto[1] auto[1] 63 1 T3 1 T13 1 T40 1
all_values[2] auto[1] auto[0] auto[1] 188 1 T3 2 T24 3 T13 4
all_values[2] auto[1] auto[1] auto[1] 155 1 T3 4 T13 4 T25 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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