Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
60.78	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	4	16	80.00
Crosses	82	36	46	56.10

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	2	3	60.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	1	6	85.71	100	1	1	0
sha_en	2	1	1	50.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	8	0	8	100.00	100	1	1	0
hmac_dis_x_sha_en	4	2	2	50.00	100	1	1	0
key_x_digest_mismatch	35	17	18	51.43	100	1	1	0
key_length_x_digest_size	35	17	18	51.43	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	2	3	60.00

User Defined Bins for digest_size

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
sha2_invalid	0	1	1
sha2_none	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_512	4261	1			T2	3		T3	72		T4	7
sha2_384	4267	1			T1	1		T2	3		T3	73
sha2_256	26815	1			T1	6		T2	4		T3	262

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29239

1

T1

2

T2

4

T3

292

auto[1]

6104

1

T1

5

T2

6

T3

115

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6187

1

T1

4

T2

4

T3

101

auto[1]

29156

1

T1

3

T2

6

T3

306

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

6755

1

T1

3

T2

5

T3

112

disabled

28588

1

T1

4

T2

5

T3

295

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for key_length

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
key_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	982	1			T1	1		T3	15		T7	1
key_1024	1911	1			T2	2		T3	38		T4	3
key_512	2327	1			T1	1		T2	2		T3	42
key_384	2354	1			T2	1		T3	35		T4	4
key_256	25389	1			T1	2		T2	3		T3	240
key_128	2380	1			T1	3		T2	2		T3	37

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for sha_en

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
disabled	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

35343

1

T1

7

T2

10

T3

407

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
enabled	auto[0]	auto[0]	1640	1			T1	1		T2	2		T3	21
enabled	auto[0]	auto[1]	1558	1			T1	1		T3	25		T4	4
enabled	auto[1]	auto[0]	2016	1			T3	29		T16	4		T4	2
enabled	auto[1]	auto[1]	1541	1			T1	1		T2	3		T3	37
disabled	auto[0]	auto[0]	1490	1			T3	26		T4	1		T14	1
disabled	auto[0]	auto[1]	1499	1			T1	2		T2	2		T3	29
disabled	auto[1]	auto[0]	24093	1			T1	1		T2	2		T3	216
disabled	auto[1]	auto[1]	1506	1			T1	1		T2	1		T3	24

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	2	2	50.00	2
Automatically Generated Cross Bins	3	2	1	33.33	2
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Element holes

hmac_en	sha_en	COUNT	AT LEAST	NUMBER	STATUS
*	[disabled]	--	--	2

Covered bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

6755

1

T1

3

T2

5

T3

112

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

28588

1

T1

4

T2

5

T3

295

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	17	18	51.43	17
Automatically Generated Cross Bins	34	17	17	50.00	17
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid , sha2_none]	--	--	12

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_512	343	1			T3	7		T14	1		T48	1
key_none	sha2_384	328	1			T3	4		T7	1		T14	1
key_none	sha2_256	311	1			T1	1		T3	4		T42	1
key_1024	sha2_512	798	1			T2	2		T3	12		T4	2
key_1024	sha2_384	801	1			T3	20		T4	1		T5	1
key_512	sha2_512	770	1			T2	1		T3	19		T4	1
key_512	sha2_384	798	1			T2	1		T3	16		T4	1
key_512	sha2_256	759	1			T1	1		T3	7		T4	2
key_384	sha2_512	816	1			T3	9		T4	1		T5	2
key_384	sha2_384	741	1			T3	14		T4	1		T5	2
key_384	sha2_256	797	1			T2	1		T3	12		T4	2
key_256	sha2_512	742	1			T3	12		T4	2		T5	2
key_256	sha2_384	787	1			T3	8		T4	4		T5	2
key_256	sha2_256	23860	1			T1	2		T2	3		T3	220
key_128	sha2_512	792	1			T3	13		T4	1		T5	1
key_128	sha2_384	812	1			T1	1		T2	2		T3	11
key_128	sha2_256	776	1			T1	2		T3	13		T5	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

312

1

T3

6

T14

1

T49

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	17	18	51.43	17

Automatically Generated Cross Bins for key_length_x_digest_size

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid , sha2_none]	--	--	12

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_512	343	1			T3	7		T14	1		T48	1
key_none	sha2_384	328	1			T3	4		T7	1		T14	1
key_none	sha2_256	311	1			T1	1		T3	4		T42	1
key_1024	sha2_512	798	1			T2	2		T3	12		T4	2
key_1024	sha2_384	801	1			T3	20		T4	1		T5	1
key_1024	sha2_256	312	1			T3	6		T14	1		T49	1
key_512	sha2_512	770	1			T2	1		T3	19		T4	1
key_512	sha2_384	798	1			T2	1		T3	16		T4	1
key_512	sha2_256	759	1			T1	1		T3	7		T4	2
key_384	sha2_512	816	1			T3	9		T4	1		T5	2
key_384	sha2_384	741	1			T3	14		T4	1		T5	2
key_384	sha2_256	797	1			T2	1		T3	12		T4	2
key_256	sha2_512	742	1			T3	12		T4	2		T5	2
key_256	sha2_384	787	1			T3	8		T4	4		T5	2
key_256	sha2_256	23860	1			T1	2		T2	3		T3	220
key_128	sha2_512	792	1			T3	13		T4	1		T5	1
key_128	sha2_384	812	1			T1	1		T2	2		T3	11
key_128	sha2_256	776	1			T1	2		T3	13		T5	1