Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.16 95.60 93.58 100.00 78.95 91.06 99.49 72.47


Total test records in report: 731
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T535 /workspace/coverage/default/38.hmac_stress_all.617540286 May 28 01:17:44 PM PDT 24 May 28 01:51:17 PM PDT 24 112041189854 ps
T536 /workspace/coverage/default/4.hmac_smoke.147542052 May 28 01:15:32 PM PDT 24 May 28 01:15:40 PM PDT 24 197562150 ps
T537 /workspace/coverage/default/25.hmac_stress_all.3836627964 May 28 01:16:54 PM PDT 24 May 28 01:57:37 PM PDT 24 98468717810 ps
T538 /workspace/coverage/default/7.hmac_burst_wr.325480871 May 28 01:15:51 PM PDT 24 May 28 01:16:06 PM PDT 24 1482771361 ps
T539 /workspace/coverage/default/2.hmac_burst_wr.1442418768 May 28 01:15:18 PM PDT 24 May 28 01:16:11 PM PDT 24 3509696008 ps
T540 /workspace/coverage/default/22.hmac_back_pressure.2243564950 May 28 01:16:36 PM PDT 24 May 28 01:16:54 PM PDT 24 1569306603 ps
T541 /workspace/coverage/default/38.hmac_back_pressure.794669720 May 28 01:17:43 PM PDT 24 May 28 01:18:04 PM PDT 24 420999124 ps
T542 /workspace/coverage/default/25.hmac_error.2003944392 May 28 01:16:48 PM PDT 24 May 28 01:20:20 PM PDT 24 29404777716 ps
T543 /workspace/coverage/default/16.hmac_long_msg.1448968357 May 28 01:16:21 PM PDT 24 May 28 01:17:26 PM PDT 24 4223764164 ps
T544 /workspace/coverage/default/26.hmac_alert_test.3983842407 May 28 01:16:55 PM PDT 24 May 28 01:16:57 PM PDT 24 17926061 ps
T545 /workspace/coverage/default/47.hmac_datapath_stress.85978879 May 28 01:18:10 PM PDT 24 May 28 01:18:39 PM PDT 24 1068083527 ps
T546 /workspace/coverage/default/32.hmac_test_hmac_vectors.731318773 May 28 01:17:18 PM PDT 24 May 28 01:17:23 PM PDT 24 553764591 ps
T11 /workspace/coverage/default/138.hmac_stress_all_with_rand_reset.1048313372 May 28 01:18:57 PM PDT 24 May 28 02:36:24 PM PDT 24 69100409603 ps
T61 /workspace/coverage/default/158.hmac_stress_all_with_rand_reset.391899414 May 28 01:18:58 PM PDT 24 May 28 02:31:12 PM PDT 24 97150924125 ps
T547 /workspace/coverage/default/5.hmac_back_pressure.1705002578 May 28 01:15:35 PM PDT 24 May 28 01:16:06 PM PDT 24 627419501 ps
T548 /workspace/coverage/default/18.hmac_test_hmac_vectors.244163130 May 28 01:16:21 PM PDT 24 May 28 01:16:24 PM PDT 24 66221748 ps
T12 /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.164861417 May 28 01:15:19 PM PDT 24 May 28 01:48:42 PM PDT 24 29477421211 ps
T549 /workspace/coverage/default/44.hmac_alert_test.2851927285 May 28 01:18:07 PM PDT 24 May 28 01:18:10 PM PDT 24 34125242 ps
T550 /workspace/coverage/default/4.hmac_datapath_stress.748896992 May 28 01:15:36 PM PDT 24 May 28 01:15:39 PM PDT 24 55438703 ps
T551 /workspace/coverage/default/47.hmac_burst_wr.1795687453 May 28 01:18:08 PM PDT 24 May 28 01:19:15 PM PDT 24 21986479041 ps
T552 /workspace/coverage/default/48.hmac_smoke.3035217330 May 28 01:18:08 PM PDT 24 May 28 01:18:15 PM PDT 24 856436801 ps
T553 /workspace/coverage/default/16.hmac_stress_all.1746579929 May 28 01:16:23 PM PDT 24 May 28 01:43:51 PM PDT 24 238657897629 ps
T554 /workspace/coverage/default/48.hmac_datapath_stress.1849925559 May 28 01:18:07 PM PDT 24 May 28 01:23:37 PM PDT 24 8374373618 ps
T555 /workspace/coverage/default/44.hmac_test_hmac_vectors.477137658 May 28 01:18:08 PM PDT 24 May 28 01:18:11 PM PDT 24 217557866 ps
T556 /workspace/coverage/default/43.hmac_error.364479082 May 28 01:18:00 PM PDT 24 May 28 01:20:16 PM PDT 24 13909562943 ps
T557 /workspace/coverage/default/16.hmac_error.1725621279 May 28 01:16:24 PM PDT 24 May 28 01:19:54 PM PDT 24 16178759952 ps
T117 /workspace/coverage/default/24.hmac_stress_all.77217519 May 28 01:16:56 PM PDT 24 May 28 01:33:42 PM PDT 24 113833930560 ps
T558 /workspace/coverage/default/8.hmac_smoke.3855612087 May 28 01:15:50 PM PDT 24 May 28 01:16:00 PM PDT 24 1354084807 ps
T559 /workspace/coverage/default/31.hmac_long_msg.1780761267 May 28 01:17:05 PM PDT 24 May 28 01:17:29 PM PDT 24 400470084 ps
T560 /workspace/coverage/default/22.hmac_burst_wr.2052758726 May 28 01:16:38 PM PDT 24 May 28 01:17:06 PM PDT 24 2196374102 ps
T561 /workspace/coverage/default/44.hmac_burst_wr.2053236114 May 28 01:17:54 PM PDT 24 May 28 01:18:27 PM PDT 24 627956558 ps
T562 /workspace/coverage/default/26.hmac_long_msg.4079141689 May 28 01:16:51 PM PDT 24 May 28 01:17:05 PM PDT 24 363086506 ps
T111 /workspace/coverage/default/11.hmac_wipe_secret.1187736966 May 28 01:16:08 PM PDT 24 May 28 01:17:30 PM PDT 24 7776356101 ps
T563 /workspace/coverage/default/35.hmac_test_hmac_vectors.1363354707 May 28 01:17:29 PM PDT 24 May 28 01:17:33 PM PDT 24 180414601 ps
T564 /workspace/coverage/default/2.hmac_test_hmac_vectors.3399090245 May 28 01:15:21 PM PDT 24 May 28 01:15:25 PM PDT 24 64433945 ps
T565 /workspace/coverage/default/24.hmac_error.579686414 May 28 01:16:38 PM PDT 24 May 28 01:18:32 PM PDT 24 36422403064 ps
T566 /workspace/coverage/default/1.hmac_error.896242152 May 28 01:15:20 PM PDT 24 May 28 01:17:11 PM PDT 24 7900933052 ps
T567 /workspace/coverage/default/122.hmac_stress_all_with_rand_reset.189933546 May 28 01:18:57 PM PDT 24 May 28 02:01:42 PM PDT 24 53728621934 ps
T568 /workspace/coverage/default/18.hmac_alert_test.2835834264 May 28 01:16:29 PM PDT 24 May 28 01:16:32 PM PDT 24 45836095 ps
T569 /workspace/coverage/default/3.hmac_test_hmac_vectors.1481077379 May 28 01:15:35 PM PDT 24 May 28 01:15:38 PM PDT 24 100809033 ps
T570 /workspace/coverage/default/35.hmac_datapath_stress.3463235113 May 28 01:17:29 PM PDT 24 May 28 01:27:21 PM PDT 24 2152514026 ps
T571 /workspace/coverage/default/19.hmac_wipe_secret.3877623068 May 28 01:16:25 PM PDT 24 May 28 01:16:34 PM PDT 24 481238627 ps
T572 /workspace/coverage/default/49.hmac_error.1419719942 May 28 01:18:24 PM PDT 24 May 28 01:20:32 PM PDT 24 2294930634 ps
T573 /workspace/coverage/default/33.hmac_back_pressure.414236266 May 28 01:17:15 PM PDT 24 May 28 01:17:18 PM PDT 24 55750532 ps
T574 /workspace/coverage/default/47.hmac_smoke.3795611042 May 28 01:18:06 PM PDT 24 May 28 01:18:08 PM PDT 24 760171628 ps
T575 /workspace/coverage/default/43.hmac_test_sha_vectors.2888274224 May 28 01:17:55 PM PDT 24 May 28 01:25:57 PM PDT 24 138192447547 ps
T576 /workspace/coverage/default/14.hmac_error.1513073887 May 28 01:16:09 PM PDT 24 May 28 01:19:01 PM PDT 24 16786015244 ps
T577 /workspace/coverage/default/28.hmac_wipe_secret.4026862699 May 28 01:16:51 PM PDT 24 May 28 01:17:13 PM PDT 24 1154555758 ps
T578 /workspace/coverage/default/21.hmac_test_hmac_vectors.3220651792 May 28 01:16:41 PM PDT 24 May 28 01:16:44 PM PDT 24 95960136 ps
T579 /workspace/coverage/default/33.hmac_test_hmac_vectors.2414094376 May 28 01:17:16 PM PDT 24 May 28 01:17:19 PM PDT 24 274244515 ps
T580 /workspace/coverage/default/49.hmac_smoke.3243781871 May 28 01:18:26 PM PDT 24 May 28 01:18:32 PM PDT 24 335437816 ps
T581 /workspace/coverage/default/21.hmac_wipe_secret.2734095984 May 28 01:16:25 PM PDT 24 May 28 01:17:30 PM PDT 24 5757769809 ps
T582 /workspace/coverage/default/16.hmac_test_sha_vectors.2537173377 May 28 01:16:21 PM PDT 24 May 28 01:25:23 PM PDT 24 41439221988 ps
T116 /workspace/coverage/default/10.hmac_stress_all.3996506995 May 28 01:16:06 PM PDT 24 May 28 02:00:05 PM PDT 24 103603974148 ps
T583 /workspace/coverage/default/24.hmac_datapath_stress.3625882883 May 28 01:16:41 PM PDT 24 May 28 01:27:04 PM PDT 24 33072128969 ps
T584 /workspace/coverage/default/25.hmac_back_pressure.468806425 May 28 01:16:48 PM PDT 24 May 28 01:17:15 PM PDT 24 1807933468 ps
T585 /workspace/coverage/default/29.hmac_test_sha_vectors.2732155253 May 28 01:17:03 PM PDT 24 May 28 01:24:11 PM PDT 24 120706615223 ps
T586 /workspace/coverage/default/38.hmac_error.4048973593 May 28 01:17:37 PM PDT 24 May 28 01:19:40 PM PDT 24 33707599610 ps
T587 /workspace/coverage/default/13.hmac_alert_test.2450399081 May 28 01:16:05 PM PDT 24 May 28 01:16:07 PM PDT 24 10711538 ps
T588 /workspace/coverage/default/34.hmac_error.1778808311 May 28 01:17:17 PM PDT 24 May 28 01:18:22 PM PDT 24 17185278436 ps
T589 /workspace/coverage/default/15.hmac_test_sha_vectors.425105236 May 28 01:16:08 PM PDT 24 May 28 01:23:56 PM PDT 24 417653436511 ps
T590 /workspace/coverage/default/49.hmac_wipe_secret.945109312 May 28 01:18:24 PM PDT 24 May 28 01:19:23 PM PDT 24 1726477650 ps
T591 /workspace/coverage/default/27.hmac_test_sha_vectors.1635038502 May 28 01:16:50 PM PDT 24 May 28 01:25:28 PM PDT 24 162297353123 ps
T592 /workspace/coverage/default/46.hmac_alert_test.2059460082 May 28 01:18:06 PM PDT 24 May 28 01:18:08 PM PDT 24 25862973 ps
T593 /workspace/coverage/default/38.hmac_smoke.1598524701 May 28 01:17:30 PM PDT 24 May 28 01:17:39 PM PDT 24 347169474 ps
T594 /workspace/coverage/default/39.hmac_wipe_secret.2411745847 May 28 01:17:41 PM PDT 24 May 28 01:18:57 PM PDT 24 3729298864 ps
T56 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2053250102 May 28 01:03:56 PM PDT 24 May 28 01:03:59 PM PDT 24 24104656 ps
T595 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2629203430 May 28 01:03:54 PM PDT 24 May 28 01:03:57 PM PDT 24 40291642 ps
T57 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.554511877 May 28 01:03:41 PM PDT 24 May 28 01:03:48 PM PDT 24 116939648 ps
T58 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2827874430 May 28 01:03:50 PM PDT 24 May 28 01:03:55 PM PDT 24 21273805 ps
T53 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3874401505 May 28 01:03:42 PM PDT 24 May 28 01:03:49 PM PDT 24 322533567 ps
T76 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1906615148 May 28 01:03:38 PM PDT 24 May 28 01:03:46 PM PDT 24 40012584 ps
T596 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.228050915 May 28 01:03:48 PM PDT 24 May 28 01:03:55 PM PDT 24 91860699 ps
T54 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.498533514 May 28 01:03:43 PM PDT 24 May 28 01:03:52 PM PDT 24 1749165098 ps
T597 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1010094935 May 28 01:03:42 PM PDT 24 May 28 01:03:49 PM PDT 24 171349004 ps
T598 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.306003773 May 28 01:03:58 PM PDT 24 May 28 01:04:04 PM PDT 24 184428427 ps
T599 /workspace/coverage/cover_reg_top/17.hmac_intr_test.204475030 May 28 01:03:54 PM PDT 24 May 28 01:03:58 PM PDT 24 37065854 ps
T600 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.643603877 May 28 01:03:32 PM PDT 24 May 28 01:03:42 PM PDT 24 31911790 ps
T601 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3708274066 May 28 01:03:34 PM PDT 24 May 28 01:17:49 PM PDT 24 246797889106 ps
T602 /workspace/coverage/cover_reg_top/22.hmac_intr_test.1635776206 May 28 01:04:00 PM PDT 24 May 28 01:04:02 PM PDT 24 24872522 ps
T603 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.180471292 May 28 01:03:37 PM PDT 24 May 28 01:03:45 PM PDT 24 86053621 ps
T604 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3798296380 May 28 01:03:38 PM PDT 24 May 28 01:03:46 PM PDT 24 87990519 ps
T605 /workspace/coverage/cover_reg_top/36.hmac_intr_test.3755723720 May 28 01:04:04 PM PDT 24 May 28 01:04:07 PM PDT 24 49221989 ps
T606 /workspace/coverage/cover_reg_top/19.hmac_intr_test.3844082605 May 28 01:03:59 PM PDT 24 May 28 01:04:02 PM PDT 24 13966928 ps
T607 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3250313512 May 28 01:04:02 PM PDT 24 May 28 01:04:05 PM PDT 24 48775205 ps
T608 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1391301690 May 28 01:03:42 PM PDT 24 May 28 01:03:49 PM PDT 24 54672342 ps
T609 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1157160209 May 28 01:03:45 PM PDT 24 May 28 01:03:52 PM PDT 24 64857553 ps
T610 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3255634545 May 28 01:03:54 PM PDT 24 May 28 01:03:59 PM PDT 24 203849907 ps
T611 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1678902202 May 28 01:03:31 PM PDT 24 May 28 01:03:41 PM PDT 24 88736092 ps
T55 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3633324085 May 28 01:03:53 PM PDT 24 May 28 01:03:59 PM PDT 24 97975637 ps
T612 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2771717203 May 28 01:03:45 PM PDT 24 May 28 01:03:53 PM PDT 24 302298344 ps
T90 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1522182848 May 28 01:03:44 PM PDT 24 May 28 01:03:54 PM PDT 24 26894536 ps
T613 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1455437898 May 28 01:04:07 PM PDT 24 May 28 01:04:10 PM PDT 24 111576171 ps
T614 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.948282250 May 28 01:03:29 PM PDT 24 May 28 01:03:39 PM PDT 24 17959021 ps
T615 /workspace/coverage/cover_reg_top/10.hmac_intr_test.868482019 May 28 01:03:44 PM PDT 24 May 28 01:03:50 PM PDT 24 17236974 ps
T91 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1011026447 May 28 01:03:36 PM PDT 24 May 28 01:03:49 PM PDT 24 692112903 ps
T616 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.705299968 May 28 01:03:51 PM PDT 24 May 28 01:03:56 PM PDT 24 24788865 ps
T617 /workspace/coverage/cover_reg_top/3.hmac_intr_test.1297953331 May 28 01:03:42 PM PDT 24 May 28 01:03:48 PM PDT 24 84233892 ps
T618 /workspace/coverage/cover_reg_top/37.hmac_intr_test.392384210 May 28 01:03:54 PM PDT 24 May 28 01:03:57 PM PDT 24 27684579 ps
T619 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3578707877 May 28 01:03:42 PM PDT 24 May 28 01:03:50 PM PDT 24 576368105 ps
T620 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1493318907 May 28 01:03:54 PM PDT 24 May 28 01:04:00 PM PDT 24 148448969 ps
T121 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1462073072 May 28 01:03:44 PM PDT 24 May 28 01:03:54 PM PDT 24 1116494394 ps
T621 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.965437802 May 28 01:03:45 PM PDT 24 May 28 01:03:55 PM PDT 24 351006433 ps
T622 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3410390458 May 28 01:03:44 PM PDT 24 May 28 01:03:50 PM PDT 24 30818755 ps
T123 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3247525556 May 28 01:03:44 PM PDT 24 May 28 01:03:54 PM PDT 24 1088416389 ps
T623 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1769716614 May 28 01:03:45 PM PDT 24 May 28 01:03:52 PM PDT 24 264970721 ps
T624 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1618159218 May 28 01:03:59 PM PDT 24 May 28 01:04:02 PM PDT 24 14523727 ps
T625 /workspace/coverage/cover_reg_top/28.hmac_intr_test.3066209943 May 28 01:03:43 PM PDT 24 May 28 01:03:49 PM PDT 24 10449138 ps
T626 /workspace/coverage/cover_reg_top/20.hmac_intr_test.566643925 May 28 01:04:10 PM PDT 24 May 28 01:04:14 PM PDT 24 16014816 ps
T627 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.4182660314 May 28 01:04:01 PM PDT 24 May 28 01:04:06 PM PDT 24 70492584 ps
T628 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3889494309 May 28 01:03:55 PM PDT 24 May 28 01:04:00 PM PDT 24 121517277 ps
T629 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2972610891 May 28 01:03:42 PM PDT 24 May 28 01:03:49 PM PDT 24 117289210 ps
T630 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1289753198 May 28 01:03:52 PM PDT 24 May 28 01:03:57 PM PDT 24 26250999 ps
T631 /workspace/coverage/cover_reg_top/2.hmac_intr_test.3880470467 May 28 01:03:42 PM PDT 24 May 28 01:03:49 PM PDT 24 16625085 ps
T59 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.544217863 May 28 01:03:58 PM PDT 24 May 28 01:04:06 PM PDT 24 227170209 ps
T632 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2410557101 May 28 01:03:49 PM PDT 24 May 28 01:03:58 PM PDT 24 231703156 ps
T633 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.781668953 May 28 01:03:54 PM PDT 24 May 28 01:04:03 PM PDT 24 3108875017 ps
T92 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2398407478 May 28 01:03:43 PM PDT 24 May 28 01:03:49 PM PDT 24 37366289 ps
T634 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1683169231 May 28 01:03:52 PM PDT 24 May 28 01:03:56 PM PDT 24 45560198 ps
T635 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3848970998 May 28 01:03:36 PM PDT 24 May 28 01:03:45 PM PDT 24 104900674 ps
T93 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3381490330 May 28 01:03:52 PM PDT 24 May 28 01:04:13 PM PDT 24 3203472108 ps
T636 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3896015576 May 28 01:03:43 PM PDT 24 May 28 01:03:50 PM PDT 24 100220767 ps
T637 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2381876007 May 28 01:03:50 PM PDT 24 May 28 01:03:56 PM PDT 24 156163066 ps
T638 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2301927038 May 28 01:03:47 PM PDT 24 May 28 01:03:54 PM PDT 24 238443377 ps
T119 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.4078325412 May 28 01:03:42 PM PDT 24 May 28 01:03:50 PM PDT 24 326708693 ps
T94 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1436816034 May 28 01:03:44 PM PDT 24 May 28 01:03:50 PM PDT 24 58014981 ps
T639 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.892044146 May 28 01:03:46 PM PDT 24 May 28 01:03:53 PM PDT 24 119476701 ps
T640 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3250246179 May 28 01:03:54 PM PDT 24 May 28 01:03:57 PM PDT 24 80220002 ps
T124 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.37460519 May 28 01:03:46 PM PDT 24 May 28 01:03:56 PM PDT 24 226860707 ps
T641 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3443141660 May 28 01:03:56 PM PDT 24 May 28 01:04:01 PM PDT 24 96841271 ps
T642 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.491230219 May 28 01:03:43 PM PDT 24 May 28 01:03:52 PM PDT 24 123863646 ps
T643 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1452051830 May 28 01:03:44 PM PDT 24 May 28 01:03:52 PM PDT 24 97665249 ps
T644 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.4119902643 May 28 01:03:33 PM PDT 24 May 28 01:03:47 PM PDT 24 4444410602 ps
T645 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1724396772 May 28 01:03:53 PM PDT 24 May 28 01:03:58 PM PDT 24 225414038 ps
T646 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1744007849 May 28 01:03:43 PM PDT 24 May 28 01:03:49 PM PDT 24 43854180 ps
T122 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3822056547 May 28 01:03:43 PM PDT 24 May 28 01:03:53 PM PDT 24 131862793 ps
T647 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3205429065 May 28 01:04:01 PM PDT 24 May 28 01:04:04 PM PDT 24 65485997 ps
T120 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3105351610 May 28 01:03:53 PM PDT 24 May 28 01:03:59 PM PDT 24 318607701 ps
T648 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.924743108 May 28 01:03:40 PM PDT 24 May 28 01:03:47 PM PDT 24 64153411 ps
T649 /workspace/coverage/cover_reg_top/6.hmac_intr_test.2453157032 May 28 01:03:44 PM PDT 24 May 28 01:03:50 PM PDT 24 40396620 ps
T650 /workspace/coverage/cover_reg_top/9.hmac_intr_test.4279840018 May 28 01:03:49 PM PDT 24 May 28 01:03:54 PM PDT 24 42947674 ps
T651 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2155766157 May 28 01:03:42 PM PDT 24 May 28 01:03:49 PM PDT 24 36258228 ps
T652 /workspace/coverage/cover_reg_top/15.hmac_intr_test.3910621026 May 28 01:03:47 PM PDT 24 May 28 01:03:53 PM PDT 24 42821373 ps
T653 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1276517619 May 28 01:04:00 PM PDT 24 May 28 01:04:04 PM PDT 24 347030984 ps
T654 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2549336707 May 28 01:03:54 PM PDT 24 May 28 01:03:58 PM PDT 24 67010325 ps
T95 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.897082103 May 28 01:04:13 PM PDT 24 May 28 01:04:18 PM PDT 24 16720021 ps
T96 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3922080182 May 28 01:03:40 PM PDT 24 May 28 01:03:50 PM PDT 24 358074305 ps
T655 /workspace/coverage/cover_reg_top/7.hmac_intr_test.3488151886 May 28 01:03:43 PM PDT 24 May 28 01:03:49 PM PDT 24 15370363 ps
T656 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3483781081 May 28 01:03:47 PM PDT 24 May 28 01:03:53 PM PDT 24 24133983 ps
T657 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.720399720 May 28 01:03:52 PM PDT 24 May 28 01:03:59 PM PDT 24 133617104 ps
T97 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3028559175 May 28 01:03:25 PM PDT 24 May 28 01:03:36 PM PDT 24 15381948 ps
T658 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1545288372 May 28 01:03:56 PM PDT 24 May 28 01:04:01 PM PDT 24 99336733 ps
T659 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3589932316 May 28 01:03:49 PM PDT 24 May 28 01:03:56 PM PDT 24 73814264 ps
T660 /workspace/coverage/cover_reg_top/48.hmac_intr_test.1576736 May 28 01:04:01 PM PDT 24 May 28 01:04:03 PM PDT 24 30994728 ps
T661 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2147765635 May 28 01:04:03 PM PDT 24 May 28 01:04:06 PM PDT 24 76817562 ps
T662 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.978519559 May 28 01:03:44 PM PDT 24 May 28 01:03:51 PM PDT 24 22609911 ps
T663 /workspace/coverage/cover_reg_top/35.hmac_intr_test.1057160938 May 28 01:04:04 PM PDT 24 May 28 01:04:07 PM PDT 24 22635865 ps
T664 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.214829902 May 28 01:03:54 PM PDT 24 May 28 01:03:59 PM PDT 24 119607932 ps
T665 /workspace/coverage/cover_reg_top/27.hmac_intr_test.871448613 May 28 01:03:56 PM PDT 24 May 28 01:03:59 PM PDT 24 62302399 ps
T666 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.4173394263 May 28 01:03:51 PM PDT 24 May 28 01:03:55 PM PDT 24 13816361 ps
T667 /workspace/coverage/cover_reg_top/26.hmac_intr_test.953048246 May 28 01:04:07 PM PDT 24 May 28 01:04:10 PM PDT 24 11199183 ps
T668 /workspace/coverage/cover_reg_top/47.hmac_intr_test.45867249 May 28 01:03:58 PM PDT 24 May 28 01:04:02 PM PDT 24 30984229 ps
T669 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3594823683 May 28 01:03:40 PM PDT 24 May 28 01:03:48 PM PDT 24 702670704 ps
T670 /workspace/coverage/cover_reg_top/18.hmac_intr_test.306028528 May 28 01:03:48 PM PDT 24 May 28 01:03:54 PM PDT 24 21618059 ps
T671 /workspace/coverage/cover_reg_top/11.hmac_intr_test.2033035021 May 28 01:03:57 PM PDT 24 May 28 01:04:00 PM PDT 24 13768174 ps
T672 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3170317178 May 28 01:04:01 PM PDT 24 May 28 01:04:06 PM PDT 24 91756967 ps
T673 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3491914247 May 28 01:04:10 PM PDT 24 May 28 01:04:22 PM PDT 24 163540566 ps
T674 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.341346245 May 28 01:03:48 PM PDT 24 May 28 01:03:56 PM PDT 24 200150742 ps
T675 /workspace/coverage/cover_reg_top/29.hmac_intr_test.109401914 May 28 01:03:55 PM PDT 24 May 28 01:03:58 PM PDT 24 38160235 ps
T676 /workspace/coverage/cover_reg_top/39.hmac_intr_test.2726776138 May 28 01:04:01 PM PDT 24 May 28 01:04:03 PM PDT 24 12052527 ps
T677 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1775450001 May 28 01:04:04 PM PDT 24 May 28 01:04:07 PM PDT 24 107765087 ps
T678 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3944311461 May 28 01:03:35 PM PDT 24 May 28 01:03:43 PM PDT 24 40464628 ps
T679 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.369785529 May 28 01:04:04 PM PDT 24 May 28 01:04:11 PM PDT 24 119578901 ps
T680 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3612459739 May 28 01:03:56 PM PDT 24 May 28 01:04:03 PM PDT 24 68165227 ps
T681 /workspace/coverage/cover_reg_top/14.hmac_intr_test.748093945 May 28 01:03:49 PM PDT 24 May 28 01:03:54 PM PDT 24 22357281 ps
T682 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.353470925 May 28 01:03:45 PM PDT 24 May 28 01:03:52 PM PDT 24 88819668 ps
T683 /workspace/coverage/cover_reg_top/40.hmac_intr_test.557895330 May 28 01:03:56 PM PDT 24 May 28 01:04:00 PM PDT 24 18639943 ps
T684 /workspace/coverage/cover_reg_top/1.hmac_intr_test.2554661882 May 28 01:03:49 PM PDT 24 May 28 01:03:54 PM PDT 24 17669269 ps
T685 /workspace/coverage/cover_reg_top/30.hmac_intr_test.4280060318 May 28 01:03:47 PM PDT 24 May 28 01:03:53 PM PDT 24 45615570 ps
T686 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.869219648 May 28 01:03:39 PM PDT 24 May 28 01:03:47 PM PDT 24 424998280 ps
T687 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3870499624 May 28 01:03:50 PM PDT 24 May 28 01:03:58 PM PDT 24 351413029 ps
T688 /workspace/coverage/cover_reg_top/31.hmac_intr_test.791781589 May 28 01:03:57 PM PDT 24 May 28 01:04:01 PM PDT 24 33718390 ps
T689 /workspace/coverage/cover_reg_top/46.hmac_intr_test.2252899841 May 28 01:03:51 PM PDT 24 May 28 01:03:55 PM PDT 24 16599417 ps
T690 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1549777188 May 28 01:03:50 PM PDT 24 May 28 01:03:57 PM PDT 24 297099656 ps
T691 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1059784167 May 28 01:04:06 PM PDT 24 May 28 01:04:09 PM PDT 24 14354472 ps
T98 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2531082661 May 28 01:03:48 PM PDT 24 May 28 01:03:54 PM PDT 24 18828616 ps
T99 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3614644925 May 28 01:04:04 PM PDT 24 May 28 01:04:07 PM PDT 24 34229897 ps
T692 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.58378993 May 28 01:03:51 PM PDT 24 May 28 01:03:59 PM PDT 24 176740280 ps
T693 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3311798917 May 28 01:03:53 PM PDT 24 May 28 01:03:57 PM PDT 24 43002672 ps
T694 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3755884280 May 28 01:03:52 PM PDT 24 May 28 01:03:58 PM PDT 24 98632755 ps
T695 /workspace/coverage/cover_reg_top/33.hmac_intr_test.207356190 May 28 01:03:49 PM PDT 24 May 28 01:03:54 PM PDT 24 21963083 ps
T100 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2680603685 May 28 01:03:46 PM PDT 24 May 28 01:03:52 PM PDT 24 55718299 ps
T696 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2501789480 May 28 01:03:48 PM PDT 24 May 28 01:03:54 PM PDT 24 371352585 ps
T697 /workspace/coverage/cover_reg_top/32.hmac_intr_test.2318714141 May 28 01:03:56 PM PDT 24 May 28 01:03:59 PM PDT 24 10674515 ps
T698 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.51898546 May 28 01:03:59 PM PDT 24 May 28 01:04:03 PM PDT 24 115388767 ps
T699 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3029908015 May 28 01:03:54 PM PDT 24 May 28 01:04:01 PM PDT 24 236907305 ps
T700 /workspace/coverage/cover_reg_top/34.hmac_intr_test.2324638804 May 28 01:03:56 PM PDT 24 May 28 01:03:59 PM PDT 24 134242764 ps
T101 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2912476675 May 28 01:03:49 PM PDT 24 May 28 01:03:55 PM PDT 24 134415089 ps
T701 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.985769110 May 28 01:03:51 PM PDT 24 May 28 01:03:56 PM PDT 24 33066847 ps
T702 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3024052455 May 28 01:03:44 PM PDT 24 May 28 01:03:52 PM PDT 24 49662242 ps
T102 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1258283444 May 28 01:03:39 PM PDT 24 May 28 01:03:49 PM PDT 24 217887205 ps
T703 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1971334832 May 28 01:03:35 PM PDT 24 May 28 01:11:12 PM PDT 24 330888235125 ps
T704 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1763936035 May 28 01:03:39 PM PDT 24 May 28 01:03:47 PM PDT 24 259624112 ps
T705 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3900351367 May 28 01:03:45 PM PDT 24 May 28 01:03:55 PM PDT 24 328567130 ps
T706 /workspace/coverage/cover_reg_top/12.hmac_intr_test.3580337607 May 28 01:03:56 PM PDT 24 May 28 01:03:59 PM PDT 24 160020778 ps
T707 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1998000561 May 28 01:03:50 PM PDT 24 May 28 01:04:00 PM PDT 24 1910445199 ps
T708 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2489998597 May 28 01:03:45 PM PDT 24 May 28 01:03:54 PM PDT 24 806803462 ps
T709 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2253428824 May 28 01:03:31 PM PDT 24 May 28 01:03:41 PM PDT 24 44505098 ps
T710 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2393456647 May 28 01:03:57 PM PDT 24 May 28 01:04:00 PM PDT 24 12345484 ps
T711 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3648677641 May 28 01:04:00 PM PDT 24 May 28 01:04:03 PM PDT 24 26625410 ps
T712 /workspace/coverage/cover_reg_top/38.hmac_intr_test.1052245385 May 28 01:04:08 PM PDT 24 May 28 01:04:11 PM PDT 24 15210477 ps
T713 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2451086642 May 28 01:03:47 PM PDT 24 May 28 01:03:53 PM PDT 24 34158357 ps
T714 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2124619917 May 28 01:03:42 PM PDT 24 May 28 01:03:51 PM PDT 24 98055935 ps
T715 /workspace/coverage/cover_reg_top/5.hmac_intr_test.1340653707 May 28 01:03:26 PM PDT 24 May 28 01:03:36 PM PDT 24 35601077 ps
T716 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.19569269 May 28 01:03:30 PM PDT 24 May 28 01:03:47 PM PDT 24 603368471 ps
T717 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1585746424 May 28 01:03:56 PM PDT 24 May 28 01:03:59 PM PDT 24 34966525 ps
T718 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.336831506 May 28 01:03:41 PM PDT 24 May 28 01:03:49 PM PDT 24 114274770 ps
T719 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3498669929 May 28 01:03:45 PM PDT 24 May 28 01:03:53 PM PDT 24 279756350 ps
T125 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.999319464 May 28 01:04:00 PM PDT 24 May 28 01:04:06 PM PDT 24 132973004 ps
T720 /workspace/coverage/cover_reg_top/0.hmac_intr_test.3389863629 May 28 01:03:42 PM PDT 24 May 28 01:03:49 PM PDT 24 53805654 ps
T721 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.905969891 May 28 01:03:50 PM PDT 24 May 28 01:03:55 PM PDT 24 52501117 ps
T722 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1884616661 May 28 01:03:26 PM PDT 24 May 28 01:03:41 PM PDT 24 112187146 ps
T723 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3124205681 May 28 01:03:45 PM PDT 24 May 28 01:03:51 PM PDT 24 15863227 ps
T724 /workspace/coverage/cover_reg_top/25.hmac_intr_test.506969038 May 28 01:04:00 PM PDT 24 May 28 01:04:03 PM PDT 24 33340035 ps
T725 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1723153296 May 28 01:03:48 PM PDT 24 May 28 01:03:55 PM PDT 24 523072128 ps
T726 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1709114477 May 28 01:03:32 PM PDT 24 May 28 01:03:44 PM PDT 24 131551242 ps
T727 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3839320325 May 28 01:04:09 PM PDT 24 May 28 01:04:14 PM PDT 24 398920535 ps
T728 /workspace/coverage/cover_reg_top/44.hmac_intr_test.631701478 May 28 01:04:10 PM PDT 24 May 28 01:04:14 PM PDT 24 36552120 ps
T729 /workspace/coverage/cover_reg_top/8.hmac_intr_test.2767534609 May 28 01:03:41 PM PDT 24 May 28 01:03:47 PM PDT 24 25226125 ps
T730 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1646700260 May 28 01:03:42 PM PDT 24 May 28 01:03:49 PM PDT 24 41627143 ps
T731 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1922856599 May 28 01:03:56 PM PDT 24 May 28 01:04:00 PM PDT 24 619297599 ps

Test location /workspace/coverage/default/6.hmac_stress_all.2396422879
Short name T3
Test name
Test status
Simulation time 224113942035 ps
CPU time 2201.78 seconds
Started May 28 01:15:50 PM PDT 24
Finished May 28 01:52:33 PM PDT 24
Peak memory 782000 kb
Host smart-8b2437b8-9ca2-4ec1-911a-d1d8917d6a35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396422879 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2396422879
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/118.hmac_stress_all_with_rand_reset.2102886272
Short name T24
Test name
Test status
Simulation time 15473405811 ps
CPU time 1519 seconds
Started May 28 01:18:56 PM PDT 24
Finished May 28 01:44:16 PM PDT 24
Peak memory 737352 kb
Host smart-7c69bee2-f0a6-4151-be75-170086bf8f45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2102886272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.hmac_stress_all_with_rand_reset.2102886272
Directory /workspace/118.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.hmac_stress_all.3338742555
Short name T14
Test name
Test status
Simulation time 2640067366 ps
CPU time 35.08 seconds
Started May 28 01:18:08 PM PDT 24
Finished May 28 01:18:46 PM PDT 24
Peak memory 219552 kb
Host smart-93d42ff4-f561-44f8-bf34-3ee15de7ae28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338742555 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.3338742555
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/115.hmac_stress_all_with_rand_reset.1773006623
Short name T8
Test name
Test status
Simulation time 5200258534 ps
CPU time 146.95 seconds
Started May 28 01:18:59 PM PDT 24
Finished May 28 01:21:28 PM PDT 24
Peak memory 226144 kb
Host smart-ccdd1c42-89d5-4346-b886-9749704462fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1773006623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.hmac_stress_all_with_rand_reset.1773006623
Directory /workspace/115.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.16945444
Short name T32
Test name
Test status
Simulation time 251068326 ps
CPU time 1.08 seconds
Started May 28 01:15:18 PM PDT 24
Finished May 28 01:15:21 PM PDT 24
Peak memory 219300 kb
Host smart-3f903973-43f6-46ef-8600-1342a97bf9e6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16945444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.16945444
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/39.hmac_stress_all_with_rand_reset.1012397418
Short name T13
Test name
Test status
Simulation time 66885471705 ps
CPU time 3715.53 seconds
Started May 28 01:17:43 PM PDT 24
Finished May 28 02:19:42 PM PDT 24
Peak memory 827108 kb
Host smart-2e28d864-22ac-450a-99ff-a4d551406def
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1012397418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all_with_rand_reset.1012397418
Directory /workspace/39.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.498533514
Short name T54
Test name
Test status
Simulation time 1749165098 ps
CPU time 2.89 seconds
Started May 28 01:03:43 PM PDT 24
Finished May 28 01:03:52 PM PDT 24
Peak memory 199712 kb
Host smart-c69b0111-09f3-4ce7-a8d3-f959d4f628a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498533514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.498533514
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.164861417
Short name T12
Test name
Test status
Simulation time 29477421211 ps
CPU time 2000.29 seconds
Started May 28 01:15:19 PM PDT 24
Finished May 28 01:48:42 PM PDT 24
Peak memory 693264 kb
Host smart-cd2f0950-f33a-4905-8c60-db64affcf958
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=164861417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.164861417
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3700871649
Short name T21
Test name
Test status
Simulation time 47647863 ps
CPU time 0.61 seconds
Started May 28 01:15:19 PM PDT 24
Finished May 28 01:15:22 PM PDT 24
Peak memory 195888 kb
Host smart-2b527707-22bc-4e59-a953-8c64ae1faa24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700871649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3700871649
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.4078325412
Short name T119
Test name
Test status
Simulation time 326708693 ps
CPU time 2.85 seconds
Started May 28 01:03:42 PM PDT 24
Finished May 28 01:03:50 PM PDT 24
Peak memory 199664 kb
Host smart-a4383453-f57c-486a-812b-a85f02e7ea3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078325412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.4078325412
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3248698401
Short name T108
Test name
Test status
Simulation time 99364068500 ps
CPU time 2272 seconds
Started May 28 01:15:18 PM PDT 24
Finished May 28 01:53:11 PM PDT 24
Peak memory 670652 kb
Host smart-62e61127-0bbe-4c8d-954e-61fcd4b54374
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248698401 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3248698401
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2717466686
Short name T72
Test name
Test status
Simulation time 406302052727 ps
CPU time 3887.09 seconds
Started May 28 01:16:07 PM PDT 24
Finished May 28 02:20:58 PM PDT 24
Peak memory 765732 kb
Host smart-b500cd5b-2221-4fb8-9647-f92ee84ceca3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717466686 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2717466686
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1462073072
Short name T121
Test name
Test status
Simulation time 1116494394 ps
CPU time 4.62 seconds
Started May 28 01:03:44 PM PDT 24
Finished May 28 01:03:54 PM PDT 24
Peak memory 199656 kb
Host smart-0ce9887b-c600-4a80-8076-1a454357af70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462073072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1462073072
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3922080182
Short name T96
Test name
Test status
Simulation time 358074305 ps
CPU time 3.32 seconds
Started May 28 01:03:40 PM PDT 24
Finished May 28 01:03:50 PM PDT 24
Peak memory 199716 kb
Host smart-f6ccf65e-6e7c-4136-97b0-7609eb5dec96
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922080182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3922080182
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.1881623459
Short name T50
Test name
Test status
Simulation time 5881482932 ps
CPU time 44.93 seconds
Started May 28 01:15:19 PM PDT 24
Finished May 28 01:16:06 PM PDT 24
Peak memory 200008 kb
Host smart-5f29435a-f3a0-43c6-8910-f30ee07626fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881623459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1881623459
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3996506995
Short name T116
Test name
Test status
Simulation time 103603974148 ps
CPU time 2635.58 seconds
Started May 28 01:16:06 PM PDT 24
Finished May 28 02:00:05 PM PDT 24
Peak memory 733412 kb
Host smart-ee6482af-3c47-4769-8c4f-aa6a3f5f5ec2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996506995 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3996506995
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.1187736966
Short name T111
Test name
Test status
Simulation time 7776356101 ps
CPU time 78.22 seconds
Started May 28 01:16:08 PM PDT 24
Finished May 28 01:17:30 PM PDT 24
Peak memory 200020 kb
Host smart-592ae637-903b-4b26-a1ef-d79b59d0a21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187736966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1187736966
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/158.hmac_stress_all_with_rand_reset.391899414
Short name T61
Test name
Test status
Simulation time 97150924125 ps
CPU time 4331.91 seconds
Started May 28 01:18:58 PM PDT 24
Finished May 28 02:31:12 PM PDT 24
Peak memory 612876 kb
Host smart-a5e4f088-5360-40f9-9233-fa298c4049ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=391899414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.hmac_stress_all_with_rand_reset.391899414
Directory /workspace/158.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/175.hmac_stress_all_with_rand_reset.1600291988
Short name T9
Test name
Test status
Simulation time 91895864843 ps
CPU time 1731.48 seconds
Started May 28 01:19:13 PM PDT 24
Finished May 28 01:48:06 PM PDT 24
Peak memory 731772 kb
Host smart-62a78efd-62e7-4b42-b40b-e2af2da3ce80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1600291988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.hmac_stress_all_with_rand_reset.1600291988
Directory /workspace/175.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3789598648
Short name T106
Test name
Test status
Simulation time 15523452529 ps
CPU time 44.49 seconds
Started May 28 01:16:23 PM PDT 24
Finished May 28 01:17:09 PM PDT 24
Peak memory 199992 kb
Host smart-892f3956-af09-46d6-a24e-95518e39a7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789598648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3789598648
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.544217863
Short name T59
Test name
Test status
Simulation time 227170209 ps
CPU time 4.37 seconds
Started May 28 01:03:58 PM PDT 24
Finished May 28 01:04:06 PM PDT 24
Peak memory 199712 kb
Host smart-33be5cd1-7a08-424f-9e4a-5496b84f5a93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544217863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.544217863
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1884616661
Short name T722
Test name
Test status
Simulation time 112187146 ps
CPU time 5.09 seconds
Started May 28 01:03:26 PM PDT 24
Finished May 28 01:03:41 PM PDT 24
Peak memory 198580 kb
Host smart-89013551-cbd5-4622-bf08-d8bbae9c0351
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884616661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1884616661
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2827874430
Short name T58
Test name
Test status
Simulation time 21273805 ps
CPU time 0.8 seconds
Started May 28 01:03:50 PM PDT 24
Finished May 28 01:03:55 PM PDT 24
Peak memory 197680 kb
Host smart-b45cf7c7-7f4c-4510-a01d-59e960070448
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827874430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2827874430
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3589932316
Short name T659
Test name
Test status
Simulation time 73814264 ps
CPU time 1.9 seconds
Started May 28 01:03:49 PM PDT 24
Finished May 28 01:03:56 PM PDT 24
Peak memory 200104 kb
Host smart-d221aaab-d2dd-497c-a56a-540cc36330bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589932316 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.3589932316
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1436816034
Short name T94
Test name
Test status
Simulation time 58014981 ps
CPU time 0.69 seconds
Started May 28 01:03:44 PM PDT 24
Finished May 28 01:03:50 PM PDT 24
Peak memory 197360 kb
Host smart-f90bcbc2-7b7e-482d-973e-b15675fd0b26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436816034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1436816034
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.3389863629
Short name T720
Test name
Test status
Simulation time 53805654 ps
CPU time 0.65 seconds
Started May 28 01:03:42 PM PDT 24
Finished May 28 01:03:49 PM PDT 24
Peak memory 194568 kb
Host smart-fa6dfcc6-18ef-43db-800e-914dbe00a097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389863629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3389863629
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.180471292
Short name T603
Test name
Test status
Simulation time 86053621 ps
CPU time 1.15 seconds
Started May 28 01:03:37 PM PDT 24
Finished May 28 01:03:45 PM PDT 24
Peak memory 199468 kb
Host smart-d7211714-0ad5-439b-838d-88ff5ff23a82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180471292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_
outstanding.180471292
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1709114477
Short name T726
Test name
Test status
Simulation time 131551242 ps
CPU time 3.64 seconds
Started May 28 01:03:32 PM PDT 24
Finished May 28 01:03:44 PM PDT 24
Peak memory 199816 kb
Host smart-181bf405-8b33-411a-ad31-2a94ca0fd7fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709114477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1709114477
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3822056547
Short name T122
Test name
Test status
Simulation time 131862793 ps
CPU time 4.04 seconds
Started May 28 01:03:43 PM PDT 24
Finished May 28 01:03:53 PM PDT 24
Peak memory 199740 kb
Host smart-c5bff3c7-cbcc-44d2-bbee-7e051142a744
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822056547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3822056547
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1011026447
Short name T91
Test name
Test status
Simulation time 692112903 ps
CPU time 5.63 seconds
Started May 28 01:03:36 PM PDT 24
Finished May 28 01:03:49 PM PDT 24
Peak memory 199356 kb
Host smart-f045fc76-9a6f-4a9b-8180-eaa446abe37d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011026447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1011026447
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1998000561
Short name T707
Test name
Test status
Simulation time 1910445199 ps
CPU time 5.81 seconds
Started May 28 01:03:50 PM PDT 24
Finished May 28 01:04:00 PM PDT 24
Peak memory 199628 kb
Host smart-4f072549-e7d6-40ff-8ac3-70e4d945a511
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998000561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1998000561
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.924743108
Short name T648
Test name
Test status
Simulation time 64153411 ps
CPU time 0.91 seconds
Started May 28 01:03:40 PM PDT 24
Finished May 28 01:03:47 PM PDT 24
Peak memory 198548 kb
Host smart-12d78e19-9733-44f4-bfac-208f83bc3011
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924743108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.924743108
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3708274066
Short name T601
Test name
Test status
Simulation time 246797889106 ps
CPU time 847.33 seconds
Started May 28 01:03:34 PM PDT 24
Finished May 28 01:17:49 PM PDT 24
Peak memory 222592 kb
Host smart-0b297e37-79e8-4c92-9fd7-0fdea96b80be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708274066 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.3708274066
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2253428824
Short name T709
Test name
Test status
Simulation time 44505098 ps
CPU time 0.89 seconds
Started May 28 01:03:31 PM PDT 24
Finished May 28 01:03:41 PM PDT 24
Peak memory 199088 kb
Host smart-0d0e8738-d15f-4649-8d33-4b8f8f8aa8fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253428824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2253428824
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2554661882
Short name T684
Test name
Test status
Simulation time 17669269 ps
CPU time 0.63 seconds
Started May 28 01:03:49 PM PDT 24
Finished May 28 01:03:54 PM PDT 24
Peak memory 194520 kb
Host smart-8d63c102-be7a-493d-9738-621f6352f084
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554661882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2554661882
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2489998597
Short name T708
Test name
Test status
Simulation time 806803462 ps
CPU time 2.66 seconds
Started May 28 01:03:45 PM PDT 24
Finished May 28 01:03:54 PM PDT 24
Peak memory 200056 kb
Host smart-088545d1-7266-4dce-addc-8554fb3183dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489998597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2489998597
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1724396772
Short name T645
Test name
Test status
Simulation time 225414038 ps
CPU time 1.66 seconds
Started May 28 01:03:53 PM PDT 24
Finished May 28 01:03:58 PM PDT 24
Peak memory 199696 kb
Host smart-afbcaa69-10bb-412d-b998-0f7a9fcddd64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724396772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1724396772
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3870499624
Short name T687
Test name
Test status
Simulation time 351413029 ps
CPU time 3.22 seconds
Started May 28 01:03:50 PM PDT 24
Finished May 28 01:03:58 PM PDT 24
Peak memory 199776 kb
Host smart-ed855e39-789e-4289-b35d-82ed8ec7583c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870499624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3870499624
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.214829902
Short name T664
Test name
Test status
Simulation time 119607932 ps
CPU time 1.65 seconds
Started May 28 01:03:54 PM PDT 24
Finished May 28 01:03:59 PM PDT 24
Peak memory 199752 kb
Host smart-01b9b591-b542-4fe3-83d2-0dee5dc211f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214829902 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.214829902
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1391301690
Short name T608
Test name
Test status
Simulation time 54672342 ps
CPU time 0.78 seconds
Started May 28 01:03:42 PM PDT 24
Finished May 28 01:03:49 PM PDT 24
Peak memory 198488 kb
Host smart-13b269d4-f4ea-4314-af5e-60fff977af59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391301690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1391301690
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.868482019
Short name T615
Test name
Test status
Simulation time 17236974 ps
CPU time 0.61 seconds
Started May 28 01:03:44 PM PDT 24
Finished May 28 01:03:50 PM PDT 24
Peak memory 194480 kb
Host smart-c5c81ac2-63a6-423f-9e93-7932a0a73304
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868482019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.868482019
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3578707877
Short name T619
Test name
Test status
Simulation time 576368105 ps
CPU time 1.91 seconds
Started May 28 01:03:42 PM PDT 24
Finished May 28 01:03:50 PM PDT 24
Peak memory 199716 kb
Host smart-ca072f7b-b36f-4fb8-bdca-c5d6dfd38191
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578707877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.3578707877
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.491230219
Short name T642
Test name
Test status
Simulation time 123863646 ps
CPU time 3.01 seconds
Started May 28 01:03:43 PM PDT 24
Finished May 28 01:03:52 PM PDT 24
Peak memory 199760 kb
Host smart-92373455-4dc3-43dd-abab-8d68be382ff5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491230219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.491230219
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2410557101
Short name T632
Test name
Test status
Simulation time 231703156 ps
CPU time 4.35 seconds
Started May 28 01:03:49 PM PDT 24
Finished May 28 01:03:58 PM PDT 24
Peak memory 199712 kb
Host smart-ec001196-ac25-4375-b2f7-1783c891f158
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410557101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2410557101
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.869219648
Short name T686
Test name
Test status
Simulation time 424998280 ps
CPU time 1.21 seconds
Started May 28 01:03:39 PM PDT 24
Finished May 28 01:03:47 PM PDT 24
Peak memory 199456 kb
Host smart-f70e785f-5ee5-4b86-9d89-03bc0bb6008b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869219648 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.869219648
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3124205681
Short name T723
Test name
Test status
Simulation time 15863227 ps
CPU time 0.68 seconds
Started May 28 01:03:45 PM PDT 24
Finished May 28 01:03:51 PM PDT 24
Peak memory 197356 kb
Host smart-0454779c-df98-458a-ae16-f4db1af9ec30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124205681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3124205681
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2033035021
Short name T671
Test name
Test status
Simulation time 13768174 ps
CPU time 0.6 seconds
Started May 28 01:03:57 PM PDT 24
Finished May 28 01:04:00 PM PDT 24
Peak memory 194456 kb
Host smart-ad9eeba9-33df-434f-9bc4-c411ae646064
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033035021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2033035021
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.978519559
Short name T662
Test name
Test status
Simulation time 22609911 ps
CPU time 1.13 seconds
Started May 28 01:03:44 PM PDT 24
Finished May 28 01:03:51 PM PDT 24
Peak memory 199408 kb
Host smart-7ea2f38f-ff09-4c91-aa1d-6f6d85a019f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978519559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.978519559
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1289753198
Short name T630
Test name
Test status
Simulation time 26250999 ps
CPU time 1.32 seconds
Started May 28 01:03:52 PM PDT 24
Finished May 28 01:03:57 PM PDT 24
Peak memory 199728 kb
Host smart-6c1da341-cabc-4aa6-891c-8ca3af2c5a5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289753198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1289753198
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1922856599
Short name T731
Test name
Test status
Simulation time 619297599 ps
CPU time 1.28 seconds
Started May 28 01:03:56 PM PDT 24
Finished May 28 01:04:00 PM PDT 24
Peak memory 199560 kb
Host smart-3ad7acb7-28a6-42a3-aced-c2cae37a82a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922856599 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1922856599
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2053250102
Short name T56
Test name
Test status
Simulation time 24104656 ps
CPU time 0.82 seconds
Started May 28 01:03:56 PM PDT 24
Finished May 28 01:03:59 PM PDT 24
Peak memory 198528 kb
Host smart-5380ec81-760d-4e19-942d-223708500f21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053250102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2053250102
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.3580337607
Short name T706
Test name
Test status
Simulation time 160020778 ps
CPU time 0.63 seconds
Started May 28 01:03:56 PM PDT 24
Finished May 28 01:03:59 PM PDT 24
Peak memory 194536 kb
Host smart-aece8358-ad11-476e-9811-5bfa31e1ee47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580337607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3580337607
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2771717203
Short name T612
Test name
Test status
Simulation time 302298344 ps
CPU time 1.69 seconds
Started May 28 01:03:45 PM PDT 24
Finished May 28 01:03:53 PM PDT 24
Peak memory 199676 kb
Host smart-6e953d31-0ab4-4bc3-98ff-d054dc1d2dba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771717203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2771717203
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1769716614
Short name T623
Test name
Test status
Simulation time 264970721 ps
CPU time 1.35 seconds
Started May 28 01:03:45 PM PDT 24
Finished May 28 01:03:52 PM PDT 24
Peak memory 199808 kb
Host smart-ecfb51d0-b5c2-4dd7-b593-fe83ac41ba8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769716614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1769716614
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3029908015
Short name T699
Test name
Test status
Simulation time 236907305 ps
CPU time 3.85 seconds
Started May 28 01:03:54 PM PDT 24
Finished May 28 01:04:01 PM PDT 24
Peak memory 215268 kb
Host smart-6cba5319-5532-40d3-8dac-3d5232a89632
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029908015 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3029908015
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2912476675
Short name T101
Test name
Test status
Simulation time 134415089 ps
CPU time 0.96 seconds
Started May 28 01:03:49 PM PDT 24
Finished May 28 01:03:55 PM PDT 24
Peak memory 199320 kb
Host smart-d9a2b796-ccd2-4785-b6dc-43d1ac49b96b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912476675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2912476675
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3250246179
Short name T640
Test name
Test status
Simulation time 80220002 ps
CPU time 0.63 seconds
Started May 28 01:03:54 PM PDT 24
Finished May 28 01:03:57 PM PDT 24
Peak memory 194536 kb
Host smart-d0993bd9-928b-4a5d-91ae-26098f914339
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250246179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3250246179
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.228050915
Short name T596
Test name
Test status
Simulation time 91860699 ps
CPU time 2.14 seconds
Started May 28 01:03:48 PM PDT 24
Finished May 28 01:03:55 PM PDT 24
Peak memory 199704 kb
Host smart-121a452d-c975-459c-a88b-79848a34618b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228050915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr
_outstanding.228050915
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.965437802
Short name T621
Test name
Test status
Simulation time 351006433 ps
CPU time 4.01 seconds
Started May 28 01:03:45 PM PDT 24
Finished May 28 01:03:55 PM PDT 24
Peak memory 199792 kb
Host smart-616cc9c4-c469-44fa-a0ab-9fa095dc0baa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965437802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.965437802
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3443141660
Short name T641
Test name
Test status
Simulation time 96841271 ps
CPU time 1.91 seconds
Started May 28 01:03:56 PM PDT 24
Finished May 28 01:04:01 PM PDT 24
Peak memory 199764 kb
Host smart-23e78936-4567-4a5d-8085-99d57394614d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443141660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3443141660
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1646700260
Short name T730
Test name
Test status
Simulation time 41627143 ps
CPU time 1.21 seconds
Started May 28 01:03:42 PM PDT 24
Finished May 28 01:03:49 PM PDT 24
Peak memory 199560 kb
Host smart-80465227-55c5-41b7-aca1-2b9dede2d257
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646700260 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1646700260
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.985769110
Short name T701
Test name
Test status
Simulation time 33066847 ps
CPU time 0.91 seconds
Started May 28 01:03:51 PM PDT 24
Finished May 28 01:03:56 PM PDT 24
Peak memory 198952 kb
Host smart-dd957222-0354-492d-9397-f3dc5fc3e04e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985769110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.985769110
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.748093945
Short name T681
Test name
Test status
Simulation time 22357281 ps
CPU time 0.58 seconds
Started May 28 01:03:49 PM PDT 24
Finished May 28 01:03:54 PM PDT 24
Peak memory 194480 kb
Host smart-951760ba-8759-450f-b007-ada8c7c5972c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748093945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.748093945
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2301927038
Short name T638
Test name
Test status
Simulation time 238443377 ps
CPU time 2.03 seconds
Started May 28 01:03:47 PM PDT 24
Finished May 28 01:03:54 PM PDT 24
Peak memory 199676 kb
Host smart-b3045c3f-4250-459f-b9fe-bb0d4a4d1a80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301927038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2301927038
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3498669929
Short name T719
Test name
Test status
Simulation time 279756350 ps
CPU time 2.15 seconds
Started May 28 01:03:45 PM PDT 24
Finished May 28 01:03:53 PM PDT 24
Peak memory 199808 kb
Host smart-e822b315-ca42-4140-85f7-7c6e44be35ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498669929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3498669929
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3024052455
Short name T702
Test name
Test status
Simulation time 49662242 ps
CPU time 1.73 seconds
Started May 28 01:03:44 PM PDT 24
Finished May 28 01:03:52 PM PDT 24
Peak memory 199656 kb
Host smart-26916c74-7f2e-45c9-ad5f-a1d64a8c5a5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024052455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3024052455
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.948282250
Short name T614
Test name
Test status
Simulation time 17959021 ps
CPU time 1.06 seconds
Started May 28 01:03:29 PM PDT 24
Finished May 28 01:03:39 PM PDT 24
Peak memory 199576 kb
Host smart-27e5c37b-c640-4b6e-be97-b1ea87f924e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948282250 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.948282250
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.905969891
Short name T721
Test name
Test status
Simulation time 52501117 ps
CPU time 0.94 seconds
Started May 28 01:03:50 PM PDT 24
Finished May 28 01:03:55 PM PDT 24
Peak memory 199060 kb
Host smart-296533c5-51b6-462f-9fee-9856ca5c07da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905969891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.905969891
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.3910621026
Short name T652
Test name
Test status
Simulation time 42821373 ps
CPU time 0.63 seconds
Started May 28 01:03:47 PM PDT 24
Finished May 28 01:03:53 PM PDT 24
Peak memory 194580 kb
Host smart-6e0c8446-4997-406a-8bd9-8b6d8236c129
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910621026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.3910621026
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.336831506
Short name T718
Test name
Test status
Simulation time 114274770 ps
CPU time 2.31 seconds
Started May 28 01:03:41 PM PDT 24
Finished May 28 01:03:49 PM PDT 24
Peak memory 199664 kb
Host smart-2a0ad4e1-6e11-4526-a02f-5f4a09b16f60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336831506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr
_outstanding.336831506
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3594823683
Short name T669
Test name
Test status
Simulation time 702670704 ps
CPU time 2.51 seconds
Started May 28 01:03:40 PM PDT 24
Finished May 28 01:03:48 PM PDT 24
Peak memory 199696 kb
Host smart-a1427b4e-c4d0-4260-953d-0999f5402093
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594823683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3594823683
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3247525556
Short name T123
Test name
Test status
Simulation time 1088416389 ps
CPU time 4.52 seconds
Started May 28 01:03:44 PM PDT 24
Finished May 28 01:03:54 PM PDT 24
Peak memory 199764 kb
Host smart-013c5127-96d1-4488-8b0b-9cd9308e5c62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247525556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3247525556
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1971334832
Short name T703
Test name
Test status
Simulation time 330888235125 ps
CPU time 449.65 seconds
Started May 28 01:03:35 PM PDT 24
Finished May 28 01:11:12 PM PDT 24
Peak memory 215256 kb
Host smart-6c7c6e56-33fb-4336-9c30-0f5ca845bcfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971334832 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.1971334832
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2531082661
Short name T98
Test name
Test status
Simulation time 18828616 ps
CPU time 0.73 seconds
Started May 28 01:03:48 PM PDT 24
Finished May 28 01:03:54 PM PDT 24
Peak memory 197436 kb
Host smart-d136874c-1377-47cd-a608-fa9a54202bdb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531082661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2531082661
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.1683169231
Short name T634
Test name
Test status
Simulation time 45560198 ps
CPU time 0.65 seconds
Started May 28 01:03:52 PM PDT 24
Finished May 28 01:03:56 PM PDT 24
Peak memory 194580 kb
Host smart-ee156f05-cf10-4631-b221-2a33de17f843
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683169231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1683169231
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2155766157
Short name T651
Test name
Test status
Simulation time 36258228 ps
CPU time 1.55 seconds
Started May 28 01:03:42 PM PDT 24
Finished May 28 01:03:49 PM PDT 24
Peak memory 199680 kb
Host smart-ca221d61-3267-43eb-afd6-aa97c142f2da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155766157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.2155766157
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1545288372
Short name T658
Test name
Test status
Simulation time 99336733 ps
CPU time 2.01 seconds
Started May 28 01:03:56 PM PDT 24
Finished May 28 01:04:01 PM PDT 24
Peak memory 199792 kb
Host smart-34c925c4-b55e-44ca-851f-8ca5a9fb163d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545288372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1545288372
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3896015576
Short name T636
Test name
Test status
Simulation time 100220767 ps
CPU time 1.87 seconds
Started May 28 01:03:43 PM PDT 24
Finished May 28 01:03:50 PM PDT 24
Peak memory 199764 kb
Host smart-c9900f44-fd29-4dac-88ee-b73514dbb0b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896015576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3896015576
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3839320325
Short name T727
Test name
Test status
Simulation time 398920535 ps
CPU time 2.43 seconds
Started May 28 01:04:09 PM PDT 24
Finished May 28 01:04:14 PM PDT 24
Peak memory 199868 kb
Host smart-eff9a145-f928-474c-8e79-0ddf88146316
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839320325 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.3839320325
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1585746424
Short name T717
Test name
Test status
Simulation time 34966525 ps
CPU time 0.7 seconds
Started May 28 01:03:56 PM PDT 24
Finished May 28 01:03:59 PM PDT 24
Peak memory 197408 kb
Host smart-64cd5ab5-7f30-4e24-b27c-f59294df1381
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585746424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1585746424
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.204475030
Short name T599
Test name
Test status
Simulation time 37065854 ps
CPU time 0.59 seconds
Started May 28 01:03:54 PM PDT 24
Finished May 28 01:03:58 PM PDT 24
Peak memory 194548 kb
Host smart-fbe63f10-ed41-466b-819e-974f8e6ecdbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204475030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.204475030
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1549777188
Short name T690
Test name
Test status
Simulation time 297099656 ps
CPU time 2.47 seconds
Started May 28 01:03:50 PM PDT 24
Finished May 28 01:03:57 PM PDT 24
Peak memory 199764 kb
Host smart-372ded69-7d2d-4ed1-98e3-7d00e96ba38a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549777188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.1549777188
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2381876007
Short name T637
Test name
Test status
Simulation time 156163066 ps
CPU time 1.74 seconds
Started May 28 01:03:50 PM PDT 24
Finished May 28 01:03:56 PM PDT 24
Peak memory 199728 kb
Host smart-2dfc0c2b-8805-4308-9771-7bda86c01ac7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381876007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2381876007
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.37460519
Short name T124
Test name
Test status
Simulation time 226860707 ps
CPU time 4.59 seconds
Started May 28 01:03:46 PM PDT 24
Finished May 28 01:03:56 PM PDT 24
Peak memory 199712 kb
Host smart-d5f5fa2e-610e-4bc6-aea7-a9fa98442599
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37460519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.37460519
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.4182660314
Short name T627
Test name
Test status
Simulation time 70492584 ps
CPU time 2.07 seconds
Started May 28 01:04:01 PM PDT 24
Finished May 28 01:04:06 PM PDT 24
Peak memory 199728 kb
Host smart-c57301d7-dc1f-462d-b8bb-36098112b047
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182660314 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.4182660314
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3311798917
Short name T693
Test name
Test status
Simulation time 43002672 ps
CPU time 0.7 seconds
Started May 28 01:03:53 PM PDT 24
Finished May 28 01:03:57 PM PDT 24
Peak memory 197924 kb
Host smart-c0d3ae92-c878-489c-b64d-bd0c6e315a25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311798917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3311798917
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.306028528
Short name T670
Test name
Test status
Simulation time 21618059 ps
CPU time 0.59 seconds
Started May 28 01:03:48 PM PDT 24
Finished May 28 01:03:54 PM PDT 24
Peak memory 194544 kb
Host smart-79935780-5c42-41dd-8689-7965cf3840cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306028528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.306028528
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1493318907
Short name T620
Test name
Test status
Simulation time 148448969 ps
CPU time 2.55 seconds
Started May 28 01:03:54 PM PDT 24
Finished May 28 01:04:00 PM PDT 24
Peak memory 199760 kb
Host smart-8576d909-07c8-475f-99ed-8929389db884
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493318907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.1493318907
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3889494309
Short name T628
Test name
Test status
Simulation time 121517277 ps
CPU time 2.49 seconds
Started May 28 01:03:55 PM PDT 24
Finished May 28 01:04:00 PM PDT 24
Peak memory 199740 kb
Host smart-268180d5-9ec3-4e21-b93e-ed55d71a259e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889494309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3889494309
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.999319464
Short name T125
Test name
Test status
Simulation time 132973004 ps
CPU time 4.01 seconds
Started May 28 01:04:00 PM PDT 24
Finished May 28 01:04:06 PM PDT 24
Peak memory 199764 kb
Host smart-5442160a-39cc-463b-97fd-0e2506609e7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999319464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.999319464
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3205429065
Short name T647
Test name
Test status
Simulation time 65485997 ps
CPU time 1.38 seconds
Started May 28 01:04:01 PM PDT 24
Finished May 28 01:04:04 PM PDT 24
Peak memory 199772 kb
Host smart-c8b97966-b5d7-4f7e-afc7-d2895333acd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205429065 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3205429065
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.897082103
Short name T95
Test name
Test status
Simulation time 16720021 ps
CPU time 0.82 seconds
Started May 28 01:04:13 PM PDT 24
Finished May 28 01:04:18 PM PDT 24
Peak memory 199216 kb
Host smart-89a94b6d-4f35-4eb4-b006-bf630801072f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897082103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.897082103
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.3844082605
Short name T606
Test name
Test status
Simulation time 13966928 ps
CPU time 0.7 seconds
Started May 28 01:03:59 PM PDT 24
Finished May 28 01:04:02 PM PDT 24
Peak memory 194584 kb
Host smart-942f63bd-c1b0-46b0-bc83-82de10927214
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844082605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3844082605
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2549336707
Short name T654
Test name
Test status
Simulation time 67010325 ps
CPU time 1.05 seconds
Started May 28 01:03:54 PM PDT 24
Finished May 28 01:03:58 PM PDT 24
Peak memory 199536 kb
Host smart-1f633677-b24d-404e-bb08-5dc6f7c6deed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549336707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.2549336707
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.369785529
Short name T679
Test name
Test status
Simulation time 119578901 ps
CPU time 3.29 seconds
Started May 28 01:04:04 PM PDT 24
Finished May 28 01:04:11 PM PDT 24
Peak memory 199760 kb
Host smart-3f168344-0f80-4e72-b1c8-49b9ea11ef8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369785529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.369785529
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1775450001
Short name T677
Test name
Test status
Simulation time 107765087 ps
CPU time 1.76 seconds
Started May 28 01:04:04 PM PDT 24
Finished May 28 01:04:07 PM PDT 24
Peak memory 199700 kb
Host smart-cf56ab3e-d9a4-4de5-9ca5-b393f6f35937
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775450001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1775450001
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.19569269
Short name T716
Test name
Test status
Simulation time 603368471 ps
CPU time 8.1 seconds
Started May 28 01:03:30 PM PDT 24
Finished May 28 01:03:47 PM PDT 24
Peak memory 199736 kb
Host smart-39c26cff-b7b8-49db-84c2-d001a60280f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19569269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.19569269
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.781668953
Short name T633
Test name
Test status
Simulation time 3108875017 ps
CPU time 6.02 seconds
Started May 28 01:03:54 PM PDT 24
Finished May 28 01:04:03 PM PDT 24
Peak memory 199196 kb
Host smart-43cb15c8-79ce-469d-994f-6f2caa85f180
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781668953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.781668953
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1906615148
Short name T76
Test name
Test status
Simulation time 40012584 ps
CPU time 0.78 seconds
Started May 28 01:03:38 PM PDT 24
Finished May 28 01:03:46 PM PDT 24
Peak memory 197924 kb
Host smart-43664fe1-f265-40a4-ac38-4f12bd243ecb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906615148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1906615148
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2451086642
Short name T713
Test name
Test status
Simulation time 34158357 ps
CPU time 1.14 seconds
Started May 28 01:03:47 PM PDT 24
Finished May 28 01:03:53 PM PDT 24
Peak memory 199516 kb
Host smart-eed2e7fa-110a-4ca7-86c1-e26a39349694
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451086642 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2451086642
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.643603877
Short name T600
Test name
Test status
Simulation time 31911790 ps
CPU time 0.92 seconds
Started May 28 01:03:32 PM PDT 24
Finished May 28 01:03:42 PM PDT 24
Peak memory 199400 kb
Host smart-6cd3d961-27de-4601-993b-797adbf0c3aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643603877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.643603877
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.3880470467
Short name T631
Test name
Test status
Simulation time 16625085 ps
CPU time 0.63 seconds
Started May 28 01:03:42 PM PDT 24
Finished May 28 01:03:49 PM PDT 24
Peak memory 194572 kb
Host smart-63201be1-7cce-4206-b5ca-dca6b0039cd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880470467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3880470467
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2972610891
Short name T629
Test name
Test status
Simulation time 117289210 ps
CPU time 1.32 seconds
Started May 28 01:03:42 PM PDT 24
Finished May 28 01:03:49 PM PDT 24
Peak memory 198164 kb
Host smart-18c2f9bd-bd7c-42ef-a59b-25d91c8d127f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972610891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2972610891
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1763936035
Short name T704
Test name
Test status
Simulation time 259624112 ps
CPU time 2.35 seconds
Started May 28 01:03:39 PM PDT 24
Finished May 28 01:03:47 PM PDT 24
Peak memory 199820 kb
Host smart-54be109e-cd42-4b78-b209-0fb588317b80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763936035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1763936035
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3874401505
Short name T53
Test name
Test status
Simulation time 322533567 ps
CPU time 1.9 seconds
Started May 28 01:03:42 PM PDT 24
Finished May 28 01:03:49 PM PDT 24
Peak memory 199712 kb
Host smart-5375d78f-a69e-4ff1-aa54-c7e17909d814
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874401505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3874401505
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.566643925
Short name T626
Test name
Test status
Simulation time 16014816 ps
CPU time 0.59 seconds
Started May 28 01:04:10 PM PDT 24
Finished May 28 01:04:14 PM PDT 24
Peak memory 194372 kb
Host smart-dc79b280-07c0-486a-801c-805fbb34dc9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566643925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.566643925
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1618159218
Short name T624
Test name
Test status
Simulation time 14523727 ps
CPU time 0.62 seconds
Started May 28 01:03:59 PM PDT 24
Finished May 28 01:04:02 PM PDT 24
Peak memory 194540 kb
Host smart-c817745f-0fa8-48b4-8087-c78dd303d4f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618159218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1618159218
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1635776206
Short name T602
Test name
Test status
Simulation time 24872522 ps
CPU time 0.57 seconds
Started May 28 01:04:00 PM PDT 24
Finished May 28 01:04:02 PM PDT 24
Peak memory 194556 kb
Host smart-1c106367-3a17-4568-a2cd-b0c2cf018942
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635776206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1635776206
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2629203430
Short name T595
Test name
Test status
Simulation time 40291642 ps
CPU time 0.63 seconds
Started May 28 01:03:54 PM PDT 24
Finished May 28 01:03:57 PM PDT 24
Peak memory 194436 kb
Host smart-c84818b1-4193-4e2f-82bd-42a2328334aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629203430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2629203430
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1059784167
Short name T691
Test name
Test status
Simulation time 14354472 ps
CPU time 0.62 seconds
Started May 28 01:04:06 PM PDT 24
Finished May 28 01:04:09 PM PDT 24
Peak memory 194456 kb
Host smart-c6967f88-b780-4645-884a-dca819a0de1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059784167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1059784167
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.506969038
Short name T724
Test name
Test status
Simulation time 33340035 ps
CPU time 0.56 seconds
Started May 28 01:04:00 PM PDT 24
Finished May 28 01:04:03 PM PDT 24
Peak memory 194480 kb
Host smart-9562d856-dd6f-43c2-9c9f-347201070383
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506969038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.506969038
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.953048246
Short name T667
Test name
Test status
Simulation time 11199183 ps
CPU time 0.59 seconds
Started May 28 01:04:07 PM PDT 24
Finished May 28 01:04:10 PM PDT 24
Peak memory 194540 kb
Host smart-4194a9a7-6e3a-4b0c-b70e-2203602208a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953048246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.953048246
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.871448613
Short name T665
Test name
Test status
Simulation time 62302399 ps
CPU time 0.65 seconds
Started May 28 01:03:56 PM PDT 24
Finished May 28 01:03:59 PM PDT 24
Peak memory 194496 kb
Host smart-ab778f19-33ef-42ea-8a23-45c19520ad7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871448613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.871448613
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.3066209943
Short name T625
Test name
Test status
Simulation time 10449138 ps
CPU time 0.61 seconds
Started May 28 01:03:43 PM PDT 24
Finished May 28 01:03:49 PM PDT 24
Peak memory 194476 kb
Host smart-1459e50c-75e4-4225-9398-ee91f5dba439
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066209943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3066209943
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.109401914
Short name T675
Test name
Test status
Simulation time 38160235 ps
CPU time 0.55 seconds
Started May 28 01:03:55 PM PDT 24
Finished May 28 01:03:58 PM PDT 24
Peak memory 194480 kb
Host smart-1205e166-f5ee-4d5a-862a-9e9ec698141f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109401914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.109401914
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.306003773
Short name T598
Test name
Test status
Simulation time 184428427 ps
CPU time 3.37 seconds
Started May 28 01:03:58 PM PDT 24
Finished May 28 01:04:04 PM PDT 24
Peak memory 199464 kb
Host smart-775f4a6e-f1be-4367-9602-43cde6a45048
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306003773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.306003773
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3381490330
Short name T93
Test name
Test status
Simulation time 3203472108 ps
CPU time 16.7 seconds
Started May 28 01:03:52 PM PDT 24
Finished May 28 01:04:13 PM PDT 24
Peak memory 199748 kb
Host smart-e2a1e01c-097e-4d6d-b703-fffc0668b9f4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381490330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3381490330
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2398407478
Short name T92
Test name
Test status
Simulation time 37366289 ps
CPU time 0.95 seconds
Started May 28 01:03:43 PM PDT 24
Finished May 28 01:03:49 PM PDT 24
Peak memory 199460 kb
Host smart-7050ad00-48fe-4894-8615-5f9bb06c33d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398407478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2398407478
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3798296380
Short name T604
Test name
Test status
Simulation time 87990519 ps
CPU time 1.43 seconds
Started May 28 01:03:38 PM PDT 24
Finished May 28 01:03:46 PM PDT 24
Peak memory 199808 kb
Host smart-be6a94df-fbb8-40cf-9db0-6e8aa9ebf79f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798296380 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.3798296380
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3614644925
Short name T99
Test name
Test status
Simulation time 34229897 ps
CPU time 0.93 seconds
Started May 28 01:04:04 PM PDT 24
Finished May 28 01:04:07 PM PDT 24
Peak memory 199104 kb
Host smart-99277ba0-4631-4702-8a42-2cbf46df5eae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614644925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3614644925
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.1297953331
Short name T617
Test name
Test status
Simulation time 84233892 ps
CPU time 0.61 seconds
Started May 28 01:03:42 PM PDT 24
Finished May 28 01:03:48 PM PDT 24
Peak memory 194496 kb
Host smart-b44a0479-095f-4e8d-89cd-67695d8b138f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297953331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.1297953331
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.554511877
Short name T57
Test name
Test status
Simulation time 116939648 ps
CPU time 1.2 seconds
Started May 28 01:03:41 PM PDT 24
Finished May 28 01:03:48 PM PDT 24
Peak memory 199688 kb
Host smart-7f0ae00b-69ef-41fe-a852-d31fe676e3fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554511877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.554511877
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3755884280
Short name T694
Test name
Test status
Simulation time 98632755 ps
CPU time 2.56 seconds
Started May 28 01:03:52 PM PDT 24
Finished May 28 01:03:58 PM PDT 24
Peak memory 199816 kb
Host smart-a1f402af-93cf-4f74-b971-7b5d863efce8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755884280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.3755884280
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.4280060318
Short name T685
Test name
Test status
Simulation time 45615570 ps
CPU time 0.59 seconds
Started May 28 01:03:47 PM PDT 24
Finished May 28 01:03:53 PM PDT 24
Peak memory 194472 kb
Host smart-663450da-6526-40fa-821c-eaa5c9233422
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280060318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.4280060318
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.791781589
Short name T688
Test name
Test status
Simulation time 33718390 ps
CPU time 0.6 seconds
Started May 28 01:03:57 PM PDT 24
Finished May 28 01:04:01 PM PDT 24
Peak memory 194552 kb
Host smart-b37c8003-0340-499d-a680-027f58af34a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791781589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.791781589
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.2318714141
Short name T697
Test name
Test status
Simulation time 10674515 ps
CPU time 0.63 seconds
Started May 28 01:03:56 PM PDT 24
Finished May 28 01:03:59 PM PDT 24
Peak memory 194476 kb
Host smart-346d08c1-6d1c-4d73-acc1-e51bfb3aa3a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318714141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.2318714141
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.207356190
Short name T695
Test name
Test status
Simulation time 21963083 ps
CPU time 0.58 seconds
Started May 28 01:03:49 PM PDT 24
Finished May 28 01:03:54 PM PDT 24
Peak memory 194528 kb
Host smart-0fa76cb0-3be5-453d-b33b-5b10eb0ccdb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207356190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.207356190
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.2324638804
Short name T700
Test name
Test status
Simulation time 134242764 ps
CPU time 0.61 seconds
Started May 28 01:03:56 PM PDT 24
Finished May 28 01:03:59 PM PDT 24
Peak memory 194548 kb
Host smart-9394f20e-aa13-4775-adb8-cffb4c799714
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324638804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2324638804
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1057160938
Short name T663
Test name
Test status
Simulation time 22635865 ps
CPU time 0.58 seconds
Started May 28 01:04:04 PM PDT 24
Finished May 28 01:04:07 PM PDT 24
Peak memory 194468 kb
Host smart-7fd35b81-0594-4de8-b6a9-bed70dfcf785
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057160938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1057160938
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3755723720
Short name T605
Test name
Test status
Simulation time 49221989 ps
CPU time 0.59 seconds
Started May 28 01:04:04 PM PDT 24
Finished May 28 01:04:07 PM PDT 24
Peak memory 194536 kb
Host smart-eba7c8aa-031f-4734-814b-4d6a6b16efe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755723720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3755723720
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.392384210
Short name T618
Test name
Test status
Simulation time 27684579 ps
CPU time 0.64 seconds
Started May 28 01:03:54 PM PDT 24
Finished May 28 01:03:57 PM PDT 24
Peak memory 194456 kb
Host smart-4423836f-7300-41e5-a6ad-a853e9d9b4db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392384210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.392384210
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.1052245385
Short name T712
Test name
Test status
Simulation time 15210477 ps
CPU time 0.63 seconds
Started May 28 01:04:08 PM PDT 24
Finished May 28 01:04:11 PM PDT 24
Peak memory 194476 kb
Host smart-0fd1a7d7-0aac-457a-b345-4f056bdd0a94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052245385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1052245385
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.2726776138
Short name T676
Test name
Test status
Simulation time 12052527 ps
CPU time 0.63 seconds
Started May 28 01:04:01 PM PDT 24
Finished May 28 01:04:03 PM PDT 24
Peak memory 194564 kb
Host smart-1e780c3a-3875-4b49-b88e-7bfafae4d915
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726776138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.2726776138
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1258283444
Short name T102
Test name
Test status
Simulation time 217887205 ps
CPU time 3.12 seconds
Started May 28 01:03:39 PM PDT 24
Finished May 28 01:03:49 PM PDT 24
Peak memory 198876 kb
Host smart-af58c8ad-f396-4328-b8d1-0595e4cbec99
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258283444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1258283444
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.4119902643
Short name T644
Test name
Test status
Simulation time 4444410602 ps
CPU time 5.79 seconds
Started May 28 01:03:33 PM PDT 24
Finished May 28 01:03:47 PM PDT 24
Peak memory 199724 kb
Host smart-fc4d4bc4-8157-4dc8-8315-5e36c6c56256
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119902643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.4119902643
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.4173394263
Short name T666
Test name
Test status
Simulation time 13816361 ps
CPU time 0.72 seconds
Started May 28 01:03:51 PM PDT 24
Finished May 28 01:03:55 PM PDT 24
Peak memory 197220 kb
Host smart-5e705255-a211-4fc1-a8eb-87a31484f8bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173394263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.4173394263
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.705299968
Short name T616
Test name
Test status
Simulation time 24788865 ps
CPU time 1.54 seconds
Started May 28 01:03:51 PM PDT 24
Finished May 28 01:03:56 PM PDT 24
Peak memory 199720 kb
Host smart-fdf4dcfa-45eb-4a6d-a1dd-5d1c41d09e87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705299968 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.705299968
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3028559175
Short name T97
Test name
Test status
Simulation time 15381948 ps
CPU time 0.79 seconds
Started May 28 01:03:25 PM PDT 24
Finished May 28 01:03:36 PM PDT 24
Peak memory 199520 kb
Host smart-8f197cfb-8348-4751-8a69-d08f0bc45d84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028559175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3028559175
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2393456647
Short name T710
Test name
Test status
Simulation time 12345484 ps
CPU time 0.59 seconds
Started May 28 01:03:57 PM PDT 24
Finished May 28 01:04:00 PM PDT 24
Peak memory 194484 kb
Host smart-bb6b4a70-16eb-48f4-8b31-48194f532040
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393456647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2393456647
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3255634545
Short name T610
Test name
Test status
Simulation time 203849907 ps
CPU time 1.15 seconds
Started May 28 01:03:54 PM PDT 24
Finished May 28 01:03:59 PM PDT 24
Peak memory 199452 kb
Host smart-eef23ed5-587e-4a01-bbc4-3a12d8637436
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255634545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3255634545
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.58378993
Short name T692
Test name
Test status
Simulation time 176740280 ps
CPU time 3.76 seconds
Started May 28 01:03:51 PM PDT 24
Finished May 28 01:03:59 PM PDT 24
Peak memory 199820 kb
Host smart-cb18bf6e-667d-46f5-bc90-5e4edc517a6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58378993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.58378993
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3170317178
Short name T672
Test name
Test status
Simulation time 91756967 ps
CPU time 2.75 seconds
Started May 28 01:04:01 PM PDT 24
Finished May 28 01:04:06 PM PDT 24
Peak memory 199768 kb
Host smart-420eb3c6-45f9-48b1-9cb4-63a361772561
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170317178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3170317178
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.557895330
Short name T683
Test name
Test status
Simulation time 18639943 ps
CPU time 0.6 seconds
Started May 28 01:03:56 PM PDT 24
Finished May 28 01:04:00 PM PDT 24
Peak memory 194528 kb
Host smart-534779d9-0fb9-404b-9a18-50a83ccd383d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557895330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.557895330
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1744007849
Short name T646
Test name
Test status
Simulation time 43854180 ps
CPU time 0.57 seconds
Started May 28 01:03:43 PM PDT 24
Finished May 28 01:03:49 PM PDT 24
Peak memory 194484 kb
Host smart-da8e3e0c-313a-4285-97e8-add578eae409
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744007849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1744007849
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3250313512
Short name T607
Test name
Test status
Simulation time 48775205 ps
CPU time 0.68 seconds
Started May 28 01:04:02 PM PDT 24
Finished May 28 01:04:05 PM PDT 24
Peak memory 194536 kb
Host smart-52a3dfd1-4cba-462a-9257-0947996468f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250313512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3250313512
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3648677641
Short name T711
Test name
Test status
Simulation time 26625410 ps
CPU time 0.6 seconds
Started May 28 01:04:00 PM PDT 24
Finished May 28 01:04:03 PM PDT 24
Peak memory 194452 kb
Host smart-f138ae2d-1b98-467f-92f2-7c5df33772c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648677641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3648677641
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.631701478
Short name T728
Test name
Test status
Simulation time 36552120 ps
CPU time 0.6 seconds
Started May 28 01:04:10 PM PDT 24
Finished May 28 01:04:14 PM PDT 24
Peak memory 194544 kb
Host smart-23125265-e040-4a00-8fe5-62aed1080c28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631701478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.631701478
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1455437898
Short name T613
Test name
Test status
Simulation time 111576171 ps
CPU time 0.57 seconds
Started May 28 01:04:07 PM PDT 24
Finished May 28 01:04:10 PM PDT 24
Peak memory 194480 kb
Host smart-2d0cdcd3-f44b-415e-b003-f3738688955e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455437898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1455437898
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.2252899841
Short name T689
Test name
Test status
Simulation time 16599417 ps
CPU time 0.63 seconds
Started May 28 01:03:51 PM PDT 24
Finished May 28 01:03:55 PM PDT 24
Peak memory 194476 kb
Host smart-16319b09-a00b-40c0-ac84-862b3b9e3b00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252899841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2252899841
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.45867249
Short name T668
Test name
Test status
Simulation time 30984229 ps
CPU time 0.54 seconds
Started May 28 01:03:58 PM PDT 24
Finished May 28 01:04:02 PM PDT 24
Peak memory 194480 kb
Host smart-7552d5c6-412e-4331-8c63-b6d1e1681cbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45867249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.45867249
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1576736
Short name T660
Test name
Test status
Simulation time 30994728 ps
CPU time 0.6 seconds
Started May 28 01:04:01 PM PDT 24
Finished May 28 01:04:03 PM PDT 24
Peak memory 194552 kb
Host smart-b19bb8f8-3fca-412b-83cd-5a43a387352a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1576736
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2147765635
Short name T661
Test name
Test status
Simulation time 76817562 ps
CPU time 0.57 seconds
Started May 28 01:04:03 PM PDT 24
Finished May 28 01:04:06 PM PDT 24
Peak memory 194476 kb
Host smart-20e0e52b-6c33-4082-9d9c-937f6b785356
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147765635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2147765635
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2124619917
Short name T714
Test name
Test status
Simulation time 98055935 ps
CPU time 3.16 seconds
Started May 28 01:03:42 PM PDT 24
Finished May 28 01:03:51 PM PDT 24
Peak memory 215204 kb
Host smart-c32a80ed-e7b6-4227-b88b-5f36d8fba96b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124619917 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2124619917
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3848970998
Short name T635
Test name
Test status
Simulation time 104900674 ps
CPU time 0.79 seconds
Started May 28 01:03:36 PM PDT 24
Finished May 28 01:03:45 PM PDT 24
Peak memory 198572 kb
Host smart-e3acd118-a12a-4107-b578-7f0ee0fd6920
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848970998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3848970998
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1340653707
Short name T715
Test name
Test status
Simulation time 35601077 ps
CPU time 0.6 seconds
Started May 28 01:03:26 PM PDT 24
Finished May 28 01:03:36 PM PDT 24
Peak memory 194560 kb
Host smart-1140633d-c0b4-4fd6-add8-09de79ada9c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340653707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1340653707
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2501789480
Short name T696
Test name
Test status
Simulation time 371352585 ps
CPU time 1.74 seconds
Started May 28 01:03:48 PM PDT 24
Finished May 28 01:03:54 PM PDT 24
Peak memory 199576 kb
Host smart-953062a7-fe37-4119-8a7b-8b5b72af533b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501789480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.2501789480
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.720399720
Short name T657
Test name
Test status
Simulation time 133617104 ps
CPU time 2.93 seconds
Started May 28 01:03:52 PM PDT 24
Finished May 28 01:03:59 PM PDT 24
Peak memory 199764 kb
Host smart-d8849d0e-825c-4a62-8b46-fa74da87cd18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720399720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.720399720
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1723153296
Short name T725
Test name
Test status
Simulation time 523072128 ps
CPU time 1.96 seconds
Started May 28 01:03:48 PM PDT 24
Finished May 28 01:03:55 PM PDT 24
Peak memory 199688 kb
Host smart-33fad344-a552-4ac4-8bfd-6fb406407d8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723153296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1723153296
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1452051830
Short name T643
Test name
Test status
Simulation time 97665249 ps
CPU time 2.66 seconds
Started May 28 01:03:44 PM PDT 24
Finished May 28 01:03:52 PM PDT 24
Peak memory 199840 kb
Host smart-390b4ad3-0011-4821-898a-769700069811
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452051830 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1452051830
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1522182848
Short name T90
Test name
Test status
Simulation time 26894536 ps
CPU time 0.86 seconds
Started May 28 01:03:44 PM PDT 24
Finished May 28 01:03:54 PM PDT 24
Peak memory 198956 kb
Host smart-78807605-46e6-4dfe-adcd-e20c8ec0033c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522182848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1522182848
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2453157032
Short name T649
Test name
Test status
Simulation time 40396620 ps
CPU time 0.62 seconds
Started May 28 01:03:44 PM PDT 24
Finished May 28 01:03:50 PM PDT 24
Peak memory 194644 kb
Host smart-1147aa54-0c03-4f45-bd56-129bfdf5d48c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453157032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2453157032
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1678902202
Short name T611
Test name
Test status
Simulation time 88736092 ps
CPU time 1.22 seconds
Started May 28 01:03:31 PM PDT 24
Finished May 28 01:03:41 PM PDT 24
Peak memory 198220 kb
Host smart-4144d556-6b3b-46e4-9184-9755c07d54ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678902202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1678902202
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3491914247
Short name T673
Test name
Test status
Simulation time 163540566 ps
CPU time 3.01 seconds
Started May 28 01:04:10 PM PDT 24
Finished May 28 01:04:22 PM PDT 24
Peak memory 199768 kb
Host smart-841ecf0d-7fe1-4c86-b611-d3fa60c21408
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491914247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3491914247
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.353470925
Short name T682
Test name
Test status
Simulation time 88819668 ps
CPU time 1.81 seconds
Started May 28 01:03:45 PM PDT 24
Finished May 28 01:03:52 PM PDT 24
Peak memory 199772 kb
Host smart-dde2bd1d-af68-465f-9eb5-bf4ad36c2316
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353470925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.353470925
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1276517619
Short name T653
Test name
Test status
Simulation time 347030984 ps
CPU time 2.48 seconds
Started May 28 01:04:00 PM PDT 24
Finished May 28 01:04:04 PM PDT 24
Peak memory 199736 kb
Host smart-4e079926-3580-43e8-a18e-961a9e2c7355
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276517619 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1276517619
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3410390458
Short name T622
Test name
Test status
Simulation time 30818755 ps
CPU time 0.71 seconds
Started May 28 01:03:44 PM PDT 24
Finished May 28 01:03:50 PM PDT 24
Peak memory 197364 kb
Host smart-b7771c37-6091-4622-8f52-c7201b0fb817
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410390458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3410390458
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.3488151886
Short name T655
Test name
Test status
Simulation time 15370363 ps
CPU time 0.58 seconds
Started May 28 01:03:43 PM PDT 24
Finished May 28 01:03:49 PM PDT 24
Peak memory 194544 kb
Host smart-bed7c5d8-b32e-4634-bb13-38cd57037ebd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488151886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3488151886
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.892044146
Short name T639
Test name
Test status
Simulation time 119476701 ps
CPU time 1.63 seconds
Started May 28 01:03:46 PM PDT 24
Finished May 28 01:03:53 PM PDT 24
Peak memory 199540 kb
Host smart-28c6f4db-dc62-4ffb-b1bf-d53a69a4ec78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892044146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_
outstanding.892044146
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3612459739
Short name T680
Test name
Test status
Simulation time 68165227 ps
CPU time 3.34 seconds
Started May 28 01:03:56 PM PDT 24
Finished May 28 01:04:03 PM PDT 24
Peak memory 199820 kb
Host smart-d6dbfb63-8ba7-4410-bedf-0529591f857b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612459739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3612459739
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3633324085
Short name T55
Test name
Test status
Simulation time 97975637 ps
CPU time 1.86 seconds
Started May 28 01:03:53 PM PDT 24
Finished May 28 01:03:59 PM PDT 24
Peak memory 199712 kb
Host smart-9b25e399-b2be-4a91-a3e7-972054079fba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633324085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3633324085
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.51898546
Short name T698
Test name
Test status
Simulation time 115388767 ps
CPU time 2 seconds
Started May 28 01:03:59 PM PDT 24
Finished May 28 01:04:03 PM PDT 24
Peak memory 199768 kb
Host smart-dfba34f3-789c-479b-941f-0db1b01ccebd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51898546 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.51898546
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2680603685
Short name T100
Test name
Test status
Simulation time 55718299 ps
CPU time 0.89 seconds
Started May 28 01:03:46 PM PDT 24
Finished May 28 01:03:52 PM PDT 24
Peak memory 199284 kb
Host smart-3eedde80-d6b8-4e7a-bc4d-154e84578f34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680603685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2680603685
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.2767534609
Short name T729
Test name
Test status
Simulation time 25226125 ps
CPU time 0.61 seconds
Started May 28 01:03:41 PM PDT 24
Finished May 28 01:03:47 PM PDT 24
Peak memory 194480 kb
Host smart-1e35c30c-d572-4131-89a4-589b0458879c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767534609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2767534609
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3483781081
Short name T656
Test name
Test status
Simulation time 24133983 ps
CPU time 1.11 seconds
Started May 28 01:03:47 PM PDT 24
Finished May 28 01:03:53 PM PDT 24
Peak memory 198220 kb
Host smart-3b5c9d58-84e3-4fb1-8125-d1d96a1bafc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483781081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3483781081
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3900351367
Short name T705
Test name
Test status
Simulation time 328567130 ps
CPU time 4.66 seconds
Started May 28 01:03:45 PM PDT 24
Finished May 28 01:03:55 PM PDT 24
Peak memory 199776 kb
Host smart-44954344-aa98-4272-8188-e52fe2d32a3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900351367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3900351367
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1010094935
Short name T597
Test name
Test status
Simulation time 171349004 ps
CPU time 1.26 seconds
Started May 28 01:03:42 PM PDT 24
Finished May 28 01:03:49 PM PDT 24
Peak memory 199572 kb
Host smart-283de9b5-9250-4c94-a114-1adca4b393b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010094935 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1010094935
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3944311461
Short name T678
Test name
Test status
Simulation time 40464628 ps
CPU time 0.72 seconds
Started May 28 01:03:35 PM PDT 24
Finished May 28 01:03:43 PM PDT 24
Peak memory 197340 kb
Host smart-ee784da7-ae1d-4042-bca2-508c1bce3c6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944311461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3944311461
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.4279840018
Short name T650
Test name
Test status
Simulation time 42947674 ps
CPU time 0.63 seconds
Started May 28 01:03:49 PM PDT 24
Finished May 28 01:03:54 PM PDT 24
Peak memory 194544 kb
Host smart-6305a37f-0326-465d-a94c-a345be7c0fe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279840018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.4279840018
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1157160209
Short name T609
Test name
Test status
Simulation time 64857553 ps
CPU time 1.13 seconds
Started May 28 01:03:45 PM PDT 24
Finished May 28 01:03:52 PM PDT 24
Peak memory 199688 kb
Host smart-ea27640f-c761-47bf-8a61-b6dfa3c94db5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157160209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.1157160209
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.341346245
Short name T674
Test name
Test status
Simulation time 200150742 ps
CPU time 2.78 seconds
Started May 28 01:03:48 PM PDT 24
Finished May 28 01:03:56 PM PDT 24
Peak memory 199740 kb
Host smart-d4d4bfd7-ae0a-41f7-8a95-672f5792cbca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341346245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.341346245
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3105351610
Short name T120
Test name
Test status
Simulation time 318607701 ps
CPU time 2.99 seconds
Started May 28 01:03:53 PM PDT 24
Finished May 28 01:03:59 PM PDT 24
Peak memory 199712 kb
Host smart-df4c4f10-6e94-403d-a3ba-8a91e524f4a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105351610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.3105351610
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.4265214441
Short name T224
Test name
Test status
Simulation time 20222381 ps
CPU time 0.58 seconds
Started May 28 01:15:18 PM PDT 24
Finished May 28 01:15:20 PM PDT 24
Peak memory 195984 kb
Host smart-3d11fc3a-1e82-43f9-b154-8ece681a28c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265214441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.4265214441
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2942744995
Short name T194
Test name
Test status
Simulation time 543534763 ps
CPU time 26.28 seconds
Started May 28 01:15:20 PM PDT 24
Finished May 28 01:15:48 PM PDT 24
Peak memory 208316 kb
Host smart-456d141a-d95b-4be7-9721-eb7947e5dbee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2942744995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2942744995
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1699531294
Short name T376
Test name
Test status
Simulation time 485846715 ps
CPU time 87.45 seconds
Started May 28 01:15:19 PM PDT 24
Finished May 28 01:16:49 PM PDT 24
Peak memory 417636 kb
Host smart-a6950314-e63c-4142-8585-1a874763a240
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1699531294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1699531294
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.3418949583
Short name T270
Test name
Test status
Simulation time 4679949089 ps
CPU time 82.64 seconds
Started May 28 01:15:22 PM PDT 24
Finished May 28 01:16:47 PM PDT 24
Peak memory 200016 kb
Host smart-eaa5164c-4fab-4d16-a4d7-60b8057cd6de
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418949583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.3418949583
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.2737771622
Short name T192
Test name
Test status
Simulation time 3642521797 ps
CPU time 107.9 seconds
Started May 28 01:15:19 PM PDT 24
Finished May 28 01:17:10 PM PDT 24
Peak memory 200156 kb
Host smart-deb17cbf-e054-4ffa-a0dd-5624e5ff9bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737771622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.2737771622
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.2622793692
Short name T33
Test name
Test status
Simulation time 911356352 ps
CPU time 7.36 seconds
Started May 28 01:15:18 PM PDT 24
Finished May 28 01:15:28 PM PDT 24
Peak memory 200076 kb
Host smart-90a815d5-4669-4627-895b-ffdeb585c345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622793692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2622793692
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2941699840
Short name T75
Test name
Test status
Simulation time 22370705817 ps
CPU time 1256.2 seconds
Started May 28 01:15:22 PM PDT 24
Finished May 28 01:36:21 PM PDT 24
Peak memory 710984 kb
Host smart-14acfe30-4b22-4b65-8e70-96005118e5c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941699840 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2941699840
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.3715660371
Short name T154
Test name
Test status
Simulation time 64982305 ps
CPU time 1.14 seconds
Started May 28 01:15:28 PM PDT 24
Finished May 28 01:15:29 PM PDT 24
Peak memory 200096 kb
Host smart-2c58abc8-f22c-4f12-bfa5-dced454276ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715660371 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.3715660371
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.2946245248
Short name T67
Test name
Test status
Simulation time 177216992484 ps
CPU time 507.01 seconds
Started May 28 01:15:21 PM PDT 24
Finished May 28 01:23:50 PM PDT 24
Peak memory 200000 kb
Host smart-82da4143-6e8f-4d0f-8796-98b82b7114a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946245248 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.2946245248
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1058803854
Short name T258
Test name
Test status
Simulation time 2651836129 ps
CPU time 37.75 seconds
Started May 28 01:15:20 PM PDT 24
Finished May 28 01:16:00 PM PDT 24
Peak memory 200148 kb
Host smart-f407cf5f-a44f-4889-a7e3-ff9930d3533b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058803854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1058803854
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.4205178243
Short name T407
Test name
Test status
Simulation time 910818096 ps
CPU time 23.93 seconds
Started May 28 01:15:20 PM PDT 24
Finished May 28 01:15:46 PM PDT 24
Peak memory 216124 kb
Host smart-405b384a-5fa3-490e-8d98-9dd688087f38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4205178243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.4205178243
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.1887074530
Short name T220
Test name
Test status
Simulation time 139054416 ps
CPU time 1.8 seconds
Started May 28 01:15:22 PM PDT 24
Finished May 28 01:15:26 PM PDT 24
Peak memory 200004 kb
Host smart-01dc35a7-f748-4f4e-8fee-3f9b7ffa2a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887074530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1887074530
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1420622634
Short name T400
Test name
Test status
Simulation time 33815771379 ps
CPU time 1050.12 seconds
Started May 28 01:15:17 PM PDT 24
Finished May 28 01:32:48 PM PDT 24
Peak memory 708392 kb
Host smart-06647b85-e49d-40d3-9693-af4813c85f98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1420622634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1420622634
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.896242152
Short name T566
Test name
Test status
Simulation time 7900933052 ps
CPU time 108.3 seconds
Started May 28 01:15:20 PM PDT 24
Finished May 28 01:17:11 PM PDT 24
Peak memory 200116 kb
Host smart-c2207139-171d-4852-99a3-b8dcbdc4afd1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896242152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.896242152
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.124759297
Short name T186
Test name
Test status
Simulation time 688246890 ps
CPU time 29.26 seconds
Started May 28 01:15:20 PM PDT 24
Finished May 28 01:15:52 PM PDT 24
Peak memory 200060 kb
Host smart-5998214d-433f-4b57-8365-6077d71e5ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124759297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.124759297
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3271015280
Short name T30
Test name
Test status
Simulation time 140323595 ps
CPU time 0.83 seconds
Started May 28 01:15:20 PM PDT 24
Finished May 28 01:15:23 PM PDT 24
Peak memory 218188 kb
Host smart-797aa082-23ff-4d6f-8915-c6c85e33840b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271015280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3271015280
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.2675460122
Short name T437
Test name
Test status
Simulation time 431502768 ps
CPU time 1.58 seconds
Started May 28 01:15:18 PM PDT 24
Finished May 28 01:15:22 PM PDT 24
Peak memory 199908 kb
Host smart-4a99f000-87d4-4ca8-b023-649e4c247241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675460122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2675460122
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1251995045
Short name T157
Test name
Test status
Simulation time 2733677377 ps
CPU time 133.63 seconds
Started May 28 01:15:19 PM PDT 24
Finished May 28 01:17:35 PM PDT 24
Peak memory 200112 kb
Host smart-2375d12f-ad55-466a-8fd5-a4a01afe9ce9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251995045 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1251995045
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.2079157939
Short name T65
Test name
Test status
Simulation time 59734261 ps
CPU time 1.33 seconds
Started May 28 01:15:19 PM PDT 24
Finished May 28 01:15:23 PM PDT 24
Peak memory 200044 kb
Host smart-c8ff52d8-e66e-4a81-9f31-380f6224e14c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079157939 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.2079157939
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.2496561222
Short name T468
Test name
Test status
Simulation time 33460127416 ps
CPU time 464.22 seconds
Started May 28 01:15:20 PM PDT 24
Finished May 28 01:23:06 PM PDT 24
Peak memory 200108 kb
Host smart-21c68751-a3a8-4a93-875c-95e93a02b9d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496561222 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.2496561222
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1808706220
Short name T305
Test name
Test status
Simulation time 1313432114 ps
CPU time 56.04 seconds
Started May 28 01:15:20 PM PDT 24
Finished May 28 01:16:19 PM PDT 24
Peak memory 199908 kb
Host smart-ef7166ba-2bd0-4bfe-82e9-596f130e60b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808706220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1808706220
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3405156129
Short name T429
Test name
Test status
Simulation time 21505751 ps
CPU time 0.6 seconds
Started May 28 01:16:09 PM PDT 24
Finished May 28 01:16:13 PM PDT 24
Peak memory 194996 kb
Host smart-e2abc84c-6676-4e81-9136-5c9ca08123b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405156129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3405156129
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3241443845
Short name T195
Test name
Test status
Simulation time 1064377235 ps
CPU time 14.06 seconds
Started May 28 01:15:51 PM PDT 24
Finished May 28 01:16:08 PM PDT 24
Peak memory 199968 kb
Host smart-d3288e90-3ee5-4b98-ad16-059c2fa209b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3241443845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3241443845
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.992577255
Short name T196
Test name
Test status
Simulation time 856404759 ps
CPU time 46.18 seconds
Started May 28 01:16:05 PM PDT 24
Finished May 28 01:16:53 PM PDT 24
Peak memory 200012 kb
Host smart-c32ae97f-c892-4a2d-a0b4-375d72dbcc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992577255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.992577255
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1289649936
Short name T332
Test name
Test status
Simulation time 284267233 ps
CPU time 28.75 seconds
Started May 28 01:16:07 PM PDT 24
Finished May 28 01:16:40 PM PDT 24
Peak memory 301912 kb
Host smart-da54a045-0836-406b-8d81-9a36a4f3a536
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1289649936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1289649936
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.4285760221
Short name T244
Test name
Test status
Simulation time 45714415010 ps
CPU time 139.84 seconds
Started May 28 01:16:09 PM PDT 24
Finished May 28 01:18:32 PM PDT 24
Peak memory 200068 kb
Host smart-25760127-40ef-49e2-ad26-36d060b9a875
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285760221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.4285760221
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3406806742
Short name T338
Test name
Test status
Simulation time 3487484302 ps
CPU time 114.39 seconds
Started May 28 01:15:53 PM PDT 24
Finished May 28 01:17:50 PM PDT 24
Peak memory 200136 kb
Host smart-12868f14-5267-46ea-8995-6480a977f15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406806742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3406806742
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1733056271
Short name T434
Test name
Test status
Simulation time 260445262 ps
CPU time 4.88 seconds
Started May 28 01:15:53 PM PDT 24
Finished May 28 01:16:01 PM PDT 24
Peak memory 199996 kb
Host smart-b712ebbd-d5d1-4b44-9a63-fceb99427a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733056271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1733056271
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.4034053768
Short name T384
Test name
Test status
Simulation time 110131751 ps
CPU time 1.12 seconds
Started May 28 01:16:04 PM PDT 24
Finished May 28 01:16:06 PM PDT 24
Peak memory 200112 kb
Host smart-94f2bbce-7842-4934-baeb-fe1bdbb4c0b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034053768 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.4034053768
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.1990547089
Short name T238
Test name
Test status
Simulation time 389757348616 ps
CPU time 459.77 seconds
Started May 28 01:16:08 PM PDT 24
Finished May 28 01:23:51 PM PDT 24
Peak memory 200004 kb
Host smart-f700eff9-00d1-4df2-bb6a-bddef4f9e703
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990547089 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.1990547089
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.226288453
Short name T143
Test name
Test status
Simulation time 3709464323 ps
CPU time 51.65 seconds
Started May 28 01:16:07 PM PDT 24
Finished May 28 01:17:02 PM PDT 24
Peak memory 200024 kb
Host smart-f455d5d1-40b8-41f3-a180-63239794f92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226288453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.226288453
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.79734180
Short name T163
Test name
Test status
Simulation time 31422739 ps
CPU time 0.56 seconds
Started May 28 01:16:06 PM PDT 24
Finished May 28 01:16:09 PM PDT 24
Peak memory 194936 kb
Host smart-4c3c6622-a6e2-4b44-a35b-49a03cf6ca17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79734180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.79734180
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2027251234
Short name T443
Test name
Test status
Simulation time 2421785015 ps
CPU time 27.85 seconds
Started May 28 01:16:06 PM PDT 24
Finished May 28 01:16:36 PM PDT 24
Peak memory 208244 kb
Host smart-eafaa896-6dd4-4771-86ef-89b49e94dc5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2027251234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2027251234
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.13907622
Short name T146
Test name
Test status
Simulation time 2633681205 ps
CPU time 48.85 seconds
Started May 28 01:16:06 PM PDT 24
Finished May 28 01:16:57 PM PDT 24
Peak memory 200044 kb
Host smart-b70e9922-3b55-4149-82b7-52d0cd10a458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13907622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.13907622
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.976275995
Short name T475
Test name
Test status
Simulation time 9090045642 ps
CPU time 591.9 seconds
Started May 28 01:16:04 PM PDT 24
Finished May 28 01:25:57 PM PDT 24
Peak memory 682848 kb
Host smart-04ba832c-8715-4bcb-ac81-b1f93887e3c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=976275995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.976275995
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1303606368
Short name T457
Test name
Test status
Simulation time 12398655261 ps
CPU time 155.49 seconds
Started May 28 01:16:08 PM PDT 24
Finished May 28 01:18:47 PM PDT 24
Peak memory 200072 kb
Host smart-6e50abec-9e10-4b27-97b8-2774a874e3bb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303606368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1303606368
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.383033317
Short name T49
Test name
Test status
Simulation time 8831438826 ps
CPU time 115.51 seconds
Started May 28 01:16:05 PM PDT 24
Finished May 28 01:18:02 PM PDT 24
Peak memory 200200 kb
Host smart-2b249d37-fdc5-4889-9071-f1ac82e0b745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383033317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.383033317
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1455858762
Short name T413
Test name
Test status
Simulation time 127046000 ps
CPU time 2.38 seconds
Started May 28 01:16:07 PM PDT 24
Finished May 28 01:16:12 PM PDT 24
Peak memory 200092 kb
Host smart-3417e937-48a1-45a2-b393-2fd4cc81e0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455858762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1455858762
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.710817803
Short name T295
Test name
Test status
Simulation time 55081778103 ps
CPU time 4753.32 seconds
Started May 28 01:16:05 PM PDT 24
Finished May 28 02:35:21 PM PDT 24
Peak memory 800512 kb
Host smart-7901bbfc-ac31-491d-a424-67673443aca1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710817803 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.710817803
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.156198744
Short name T234
Test name
Test status
Simulation time 62987878 ps
CPU time 1.42 seconds
Started May 28 01:16:04 PM PDT 24
Finished May 28 01:16:07 PM PDT 24
Peak memory 199972 kb
Host smart-4656a4e7-4d19-496f-96ec-9fad9dd38ced
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156198744 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_test_hmac_vectors.156198744
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.1786605716
Short name T243
Test name
Test status
Simulation time 7691099344 ps
CPU time 423.84 seconds
Started May 28 01:16:07 PM PDT 24
Finished May 28 01:23:14 PM PDT 24
Peak memory 200048 kb
Host smart-2d7ea14d-1d7e-4270-ae40-49fc5e2c1778
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786605716 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.1786605716
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_alert_test.4239833476
Short name T236
Test name
Test status
Simulation time 26485654 ps
CPU time 0.57 seconds
Started May 28 01:16:08 PM PDT 24
Finished May 28 01:16:12 PM PDT 24
Peak memory 194724 kb
Host smart-bdac9cfe-f5c9-49b1-ad8d-423967b83ae0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239833476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.4239833476
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.2535203627
Short name T222
Test name
Test status
Simulation time 571911530 ps
CPU time 32.42 seconds
Started May 28 01:16:07 PM PDT 24
Finished May 28 01:16:42 PM PDT 24
Peak memory 230848 kb
Host smart-f95eddb4-df18-4b6a-8cca-956f6a2ba7b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2535203627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.2535203627
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2659496351
Short name T474
Test name
Test status
Simulation time 3769124436 ps
CPU time 53.67 seconds
Started May 28 01:16:06 PM PDT 24
Finished May 28 01:17:03 PM PDT 24
Peak memory 200152 kb
Host smart-eeb2e2cd-c92a-40fe-8aad-921d9f06c835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659496351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2659496351
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.604498191
Short name T307
Test name
Test status
Simulation time 11631119191 ps
CPU time 712.76 seconds
Started May 28 01:16:06 PM PDT 24
Finished May 28 01:28:01 PM PDT 24
Peak memory 700028 kb
Host smart-5315ae13-7f55-4ccf-8704-8c24b2a4fd69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=604498191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.604498191
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.917301841
Short name T336
Test name
Test status
Simulation time 40949691618 ps
CPU time 183.01 seconds
Started May 28 01:16:08 PM PDT 24
Finished May 28 01:19:14 PM PDT 24
Peak memory 200052 kb
Host smart-d1792e93-c2e9-4684-8737-24660fe3b980
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917301841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.917301841
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.923172497
Short name T491
Test name
Test status
Simulation time 3223583511 ps
CPU time 43.34 seconds
Started May 28 01:16:07 PM PDT 24
Finished May 28 01:16:54 PM PDT 24
Peak memory 200200 kb
Host smart-ee3e3d59-1442-47f2-bebf-5c5f137b3987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923172497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.923172497
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3271913550
Short name T249
Test name
Test status
Simulation time 324587382 ps
CPU time 5.63 seconds
Started May 28 01:16:08 PM PDT 24
Finished May 28 01:16:17 PM PDT 24
Peak memory 200092 kb
Host smart-51ac9a03-278c-4a49-a02a-04eddea38ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271913550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3271913550
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1319553502
Short name T386
Test name
Test status
Simulation time 4847118503 ps
CPU time 893.76 seconds
Started May 28 01:16:08 PM PDT 24
Finished May 28 01:31:05 PM PDT 24
Peak memory 748568 kb
Host smart-7eaac7c7-15eb-4056-92f6-39aab3268b8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319553502 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1319553502
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.1371318098
Short name T501
Test name
Test status
Simulation time 125694569 ps
CPU time 1.45 seconds
Started May 28 01:16:06 PM PDT 24
Finished May 28 01:16:09 PM PDT 24
Peak memory 199912 kb
Host smart-76c5c4bf-5c38-4eb7-8cb4-d1e3828bc5af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371318098 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.1371318098
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.2401158573
Short name T128
Test name
Test status
Simulation time 125026948662 ps
CPU time 549.6 seconds
Started May 28 01:16:06 PM PDT 24
Finished May 28 01:25:19 PM PDT 24
Peak memory 200104 kb
Host smart-e2d28821-4614-4ba9-8474-6e39c6b5c65f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401158573 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.2401158573
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2561817278
Short name T359
Test name
Test status
Simulation time 1318044756 ps
CPU time 16.55 seconds
Started May 28 01:16:06 PM PDT 24
Finished May 28 01:16:25 PM PDT 24
Peak memory 200068 kb
Host smart-c2776815-3bad-4934-9a56-5ece9af20b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561817278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2561817278
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/122.hmac_stress_all_with_rand_reset.189933546
Short name T567
Test name
Test status
Simulation time 53728621934 ps
CPU time 2563.58 seconds
Started May 28 01:18:57 PM PDT 24
Finished May 28 02:01:42 PM PDT 24
Peak memory 701628 kb
Host smart-7ebd5c52-d38b-4bd2-9ea0-0656abd85e81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=189933546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.hmac_stress_all_with_rand_reset.189933546
Directory /workspace/122.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2450399081
Short name T587
Test name
Test status
Simulation time 10711538 ps
CPU time 0.57 seconds
Started May 28 01:16:05 PM PDT 24
Finished May 28 01:16:07 PM PDT 24
Peak memory 194940 kb
Host smart-addbef58-277c-4417-977e-af1bddf6433d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450399081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2450399081
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3777725934
Short name T47
Test name
Test status
Simulation time 1207485616 ps
CPU time 23.31 seconds
Started May 28 01:16:08 PM PDT 24
Finished May 28 01:16:35 PM PDT 24
Peak memory 208136 kb
Host smart-ef998065-a93f-41ae-aaaf-3fa8975ad679
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3777725934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3777725934
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.520588671
Short name T306
Test name
Test status
Simulation time 257294830 ps
CPU time 4.25 seconds
Started May 28 01:16:05 PM PDT 24
Finished May 28 01:16:10 PM PDT 24
Peak memory 200080 kb
Host smart-3bd2d4d1-89ed-4680-898b-8b989f7a9412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520588671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.520588671
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.3133661920
Short name T115
Test name
Test status
Simulation time 17042088773 ps
CPU time 580.59 seconds
Started May 28 01:16:09 PM PDT 24
Finished May 28 01:25:53 PM PDT 24
Peak memory 651928 kb
Host smart-42b9e71b-1268-4f54-b491-50a1da937d29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3133661920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.3133661920
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2052835130
Short name T356
Test name
Test status
Simulation time 13132628713 ps
CPU time 171.32 seconds
Started May 28 01:16:08 PM PDT 24
Finished May 28 01:19:03 PM PDT 24
Peak memory 200024 kb
Host smart-7a0d0772-b93d-48d1-9e4d-97c596605702
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052835130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2052835130
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2065736477
Short name T521
Test name
Test status
Simulation time 2515210474 ps
CPU time 36.64 seconds
Started May 28 01:16:07 PM PDT 24
Finished May 28 01:16:46 PM PDT 24
Peak memory 199148 kb
Host smart-63c25be3-c0ec-4cc6-a1cc-5ef725696784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065736477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2065736477
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3491876380
Short name T278
Test name
Test status
Simulation time 84864167 ps
CPU time 2.1 seconds
Started May 28 01:16:09 PM PDT 24
Finished May 28 01:16:14 PM PDT 24
Peak memory 200032 kb
Host smart-37e5dc04-1991-4578-b7a9-bfdd75bac2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491876380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3491876380
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.2069815233
Short name T88
Test name
Test status
Simulation time 69607678 ps
CPU time 1.21 seconds
Started May 28 01:16:05 PM PDT 24
Finished May 28 01:16:07 PM PDT 24
Peak memory 200096 kb
Host smart-33a8ed1f-980f-4ef2-9297-32cc00b2d1d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069815233 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.2069815233
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.913198781
Short name T344
Test name
Test status
Simulation time 78136568975 ps
CPU time 525.35 seconds
Started May 28 01:16:06 PM PDT 24
Finished May 28 01:24:54 PM PDT 24
Peak memory 200152 kb
Host smart-100f364b-e5d4-4bdc-9f8a-875de0e183a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913198781 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.913198781
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3066064723
Short name T89
Test name
Test status
Simulation time 235760635 ps
CPU time 5.4 seconds
Started May 28 01:16:08 PM PDT 24
Finished May 28 01:16:17 PM PDT 24
Peak memory 199984 kb
Host smart-2866b7ab-4ff7-4655-9ccf-ba1386f6480e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066064723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3066064723
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/137.hmac_stress_all_with_rand_reset.4076125184
Short name T25
Test name
Test status
Simulation time 85404441720 ps
CPU time 2788.79 seconds
Started May 28 01:18:59 PM PDT 24
Finished May 28 02:05:31 PM PDT 24
Peak memory 825764 kb
Host smart-a9ce9563-ea7b-40b1-868c-69b48ea47dd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4076125184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.hmac_stress_all_with_rand_reset.4076125184
Directory /workspace/137.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/138.hmac_stress_all_with_rand_reset.1048313372
Short name T11
Test name
Test status
Simulation time 69100409603 ps
CPU time 4645.7 seconds
Started May 28 01:18:57 PM PDT 24
Finished May 28 02:36:24 PM PDT 24
Peak memory 833324 kb
Host smart-d4941696-44b5-4509-80cc-af12fffcdca1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1048313372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.hmac_stress_all_with_rand_reset.1048313372
Directory /workspace/138.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1752991596
Short name T160
Test name
Test status
Simulation time 105157925 ps
CPU time 0.58 seconds
Started May 28 01:16:08 PM PDT 24
Finished May 28 01:16:12 PM PDT 24
Peak memory 194888 kb
Host smart-ac3a583d-e66e-4b4f-a279-43a1bb534405
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752991596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1752991596
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.245416771
Short name T19
Test name
Test status
Simulation time 1368847248 ps
CPU time 52.91 seconds
Started May 28 01:16:06 PM PDT 24
Finished May 28 01:17:02 PM PDT 24
Peak memory 225624 kb
Host smart-3c821be6-180d-4772-afb4-97e5b4b6b3f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=245416771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.245416771
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.1159230972
Short name T365
Test name
Test status
Simulation time 4975229597 ps
CPU time 66.85 seconds
Started May 28 01:16:07 PM PDT 24
Finished May 28 01:17:17 PM PDT 24
Peak memory 200100 kb
Host smart-a5fbb36a-b84c-4b24-81ea-fe0091147ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159230972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.1159230972
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3775258599
Short name T426
Test name
Test status
Simulation time 1141343965 ps
CPU time 193.67 seconds
Started May 28 01:16:09 PM PDT 24
Finished May 28 01:19:26 PM PDT 24
Peak memory 468196 kb
Host smart-3c92bb15-f7fa-4bb3-a91e-90feb72e79b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3775258599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3775258599
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.1513073887
Short name T576
Test name
Test status
Simulation time 16786015244 ps
CPU time 168.68 seconds
Started May 28 01:16:09 PM PDT 24
Finished May 28 01:19:01 PM PDT 24
Peak memory 200124 kb
Host smart-acbeab05-2be2-4cfa-a17c-cb4bd0279f14
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513073887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1513073887
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.64234988
Short name T131
Test name
Test status
Simulation time 11076321091 ps
CPU time 42.54 seconds
Started May 28 01:16:09 PM PDT 24
Finished May 28 01:16:55 PM PDT 24
Peak memory 200432 kb
Host smart-63676e58-6803-4e80-9cca-6d820e3c543a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64234988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.64234988
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.934497526
Short name T64
Test name
Test status
Simulation time 476934776 ps
CPU time 3.21 seconds
Started May 28 01:16:09 PM PDT 24
Finished May 28 01:16:15 PM PDT 24
Peak memory 200116 kb
Host smart-c4012cf2-3711-4201-8157-a4ee3b331412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934497526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.934497526
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2391958282
Short name T449
Test name
Test status
Simulation time 8073713037 ps
CPU time 412.29 seconds
Started May 28 01:16:06 PM PDT 24
Finished May 28 01:23:02 PM PDT 24
Peak memory 247968 kb
Host smart-1b305e48-f480-40c7-8f14-f51f9dc3ab8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391958282 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2391958282
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.1518169723
Short name T281
Test name
Test status
Simulation time 95291561 ps
CPU time 1.04 seconds
Started May 28 01:16:06 PM PDT 24
Finished May 28 01:16:10 PM PDT 24
Peak memory 199948 kb
Host smart-3129522d-56c7-4f70-bbe4-4cbc246f85ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518169723 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.1518169723
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.3120277431
Short name T499
Test name
Test status
Simulation time 9485055868 ps
CPU time 514.22 seconds
Started May 28 01:16:08 PM PDT 24
Finished May 28 01:24:45 PM PDT 24
Peak memory 200052 kb
Host smart-66c89739-3ce7-4fca-880c-c927aa6811e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120277431 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.3120277431
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.1225033396
Short name T130
Test name
Test status
Simulation time 391225772 ps
CPU time 6.89 seconds
Started May 28 01:16:09 PM PDT 24
Finished May 28 01:16:19 PM PDT 24
Peak memory 200036 kb
Host smart-496ebd19-bbb2-4e45-a19d-20b9712c9b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225033396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.1225033396
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.2915428454
Short name T164
Test name
Test status
Simulation time 35338427 ps
CPU time 0.6 seconds
Started May 28 01:16:26 PM PDT 24
Finished May 28 01:16:29 PM PDT 24
Peak memory 195984 kb
Host smart-921b2fad-a460-4d47-ac71-47a857fa1657
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915428454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2915428454
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3107154681
Short name T335
Test name
Test status
Simulation time 1070332751 ps
CPU time 44.77 seconds
Started May 28 01:16:05 PM PDT 24
Finished May 28 01:16:52 PM PDT 24
Peak memory 221280 kb
Host smart-c1dbf91c-3706-4c32-ad0f-a08059101b56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3107154681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3107154681
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2503783523
Short name T517
Test name
Test status
Simulation time 1433662898 ps
CPU time 37.75 seconds
Started May 28 01:16:07 PM PDT 24
Finished May 28 01:16:48 PM PDT 24
Peak memory 200024 kb
Host smart-cc5a02f7-5658-4d2d-b410-31c60729d9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503783523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2503783523
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.791434598
Short name T159
Test name
Test status
Simulation time 3820023154 ps
CPU time 1049.94 seconds
Started May 28 01:16:09 PM PDT 24
Finished May 28 01:33:42 PM PDT 24
Peak memory 777408 kb
Host smart-a37642f5-3a04-4389-a44b-21852c462b2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=791434598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.791434598
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.1880431474
Short name T7
Test name
Test status
Simulation time 3129701476 ps
CPU time 59.7 seconds
Started May 28 01:16:09 PM PDT 24
Finished May 28 01:17:12 PM PDT 24
Peak memory 200032 kb
Host smart-70eed6df-264e-4cfa-afc1-21f0ace7a7d2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880431474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1880431474
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1511931122
Short name T87
Test name
Test status
Simulation time 16314837102 ps
CPU time 62.79 seconds
Started May 28 01:16:07 PM PDT 24
Finished May 28 01:17:13 PM PDT 24
Peak memory 200036 kb
Host smart-6389a4ff-2876-40e6-9cf8-8da00c178bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511931122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1511931122
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1927522927
Short name T357
Test name
Test status
Simulation time 542544029 ps
CPU time 7.95 seconds
Started May 28 01:16:07 PM PDT 24
Finished May 28 01:16:19 PM PDT 24
Peak memory 200032 kb
Host smart-21ebbc39-565d-488e-b592-26ca577cd034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927522927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1927522927
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1730942110
Short name T206
Test name
Test status
Simulation time 11408325195 ps
CPU time 1194.87 seconds
Started May 28 01:16:20 PM PDT 24
Finished May 28 01:36:16 PM PDT 24
Peak memory 737924 kb
Host smart-423d9f98-16a0-4af8-ba97-9f676e76d7ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730942110 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1730942110
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.1553622283
Short name T161
Test name
Test status
Simulation time 128820176 ps
CPU time 1.08 seconds
Started May 28 01:16:24 PM PDT 24
Finished May 28 01:16:27 PM PDT 24
Peak memory 199996 kb
Host smart-b51c5e78-1fe3-4744-b969-9f8adf523335
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553622283 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.1553622283
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.425105236
Short name T589
Test name
Test status
Simulation time 417653436511 ps
CPU time 464.09 seconds
Started May 28 01:16:08 PM PDT 24
Finished May 28 01:23:56 PM PDT 24
Peak memory 199976 kb
Host smart-4d565d64-397a-44d8-a334-002b0c130ed3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425105236 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.425105236
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.4275217841
Short name T448
Test name
Test status
Simulation time 3746789384 ps
CPU time 69.26 seconds
Started May 28 01:16:10 PM PDT 24
Finished May 28 01:17:22 PM PDT 24
Peak memory 200384 kb
Host smart-5f596824-25a6-4d9f-bf12-d286c6d81f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275217841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.4275217841
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3221896522
Short name T20
Test name
Test status
Simulation time 36900707 ps
CPU time 0.58 seconds
Started May 28 01:16:26 PM PDT 24
Finished May 28 01:16:30 PM PDT 24
Peak memory 195984 kb
Host smart-bd7dc371-1b8b-48df-8480-5cc43b99de6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221896522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3221896522
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1236289645
Short name T455
Test name
Test status
Simulation time 195694378 ps
CPU time 3.12 seconds
Started May 28 01:16:21 PM PDT 24
Finished May 28 01:16:26 PM PDT 24
Peak memory 200012 kb
Host smart-418931cb-cf35-42f0-938e-139755f5cafe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1236289645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1236289645
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.3270195087
Short name T419
Test name
Test status
Simulation time 2437138807 ps
CPU time 46.92 seconds
Started May 28 01:16:25 PM PDT 24
Finished May 28 01:17:13 PM PDT 24
Peak memory 200092 kb
Host smart-b906e30e-7d44-4802-bcf7-e422e63c0527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270195087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.3270195087
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.1167832237
Short name T283
Test name
Test status
Simulation time 566057691 ps
CPU time 55.79 seconds
Started May 28 01:16:22 PM PDT 24
Finished May 28 01:17:19 PM PDT 24
Peak memory 319088 kb
Host smart-fe45be1f-3635-446f-8577-14f5447d89ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1167832237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1167832237
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.1725621279
Short name T557
Test name
Test status
Simulation time 16178759952 ps
CPU time 208.51 seconds
Started May 28 01:16:24 PM PDT 24
Finished May 28 01:19:54 PM PDT 24
Peak memory 200072 kb
Host smart-e9bbda09-c6a7-47c5-aaf2-9c59484389cf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725621279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1725621279
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1448968357
Short name T543
Test name
Test status
Simulation time 4223764164 ps
CPU time 63.32 seconds
Started May 28 01:16:21 PM PDT 24
Finished May 28 01:17:26 PM PDT 24
Peak memory 200132 kb
Host smart-f7b1aa69-c162-423b-914d-4efa6643b58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448968357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1448968357
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.1909951653
Short name T36
Test name
Test status
Simulation time 752704396 ps
CPU time 9.67 seconds
Started May 28 01:16:22 PM PDT 24
Finished May 28 01:16:33 PM PDT 24
Peak memory 200092 kb
Host smart-fc9996a7-1444-486a-9581-33de631b0cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909951653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1909951653
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.1746579929
Short name T553
Test name
Test status
Simulation time 238657897629 ps
CPU time 1646.42 seconds
Started May 28 01:16:23 PM PDT 24
Finished May 28 01:43:51 PM PDT 24
Peak memory 769584 kb
Host smart-eeae986d-597a-44a7-bd99-ce875304c1f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746579929 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1746579929
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.2956671304
Short name T292
Test name
Test status
Simulation time 61038417 ps
CPU time 1.17 seconds
Started May 28 01:16:26 PM PDT 24
Finished May 28 01:16:30 PM PDT 24
Peak memory 200104 kb
Host smart-7974db92-9361-4a28-a81e-9546d3967c93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956671304 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.2956671304
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.2537173377
Short name T582
Test name
Test status
Simulation time 41439221988 ps
CPU time 541.69 seconds
Started May 28 01:16:21 PM PDT 24
Finished May 28 01:25:23 PM PDT 24
Peak memory 199996 kb
Host smart-757df333-4763-4783-b49e-9dd6e10a523a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537173377 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.2537173377
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1737270215
Short name T241
Test name
Test status
Simulation time 17212146101 ps
CPU time 87.77 seconds
Started May 28 01:16:22 PM PDT 24
Finished May 28 01:17:51 PM PDT 24
Peak memory 200180 kb
Host smart-252851b5-7c1a-4cef-8412-039daaacbeda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737270215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1737270215
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3636406607
Short name T191
Test name
Test status
Simulation time 164745123 ps
CPU time 0.58 seconds
Started May 28 01:16:26 PM PDT 24
Finished May 28 01:16:30 PM PDT 24
Peak memory 196716 kb
Host smart-83ff068c-892a-4443-a446-a67570413708
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636406607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3636406607
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.4172614203
Short name T392
Test name
Test status
Simulation time 2202423093 ps
CPU time 42.5 seconds
Started May 28 01:16:25 PM PDT 24
Finished May 28 01:17:09 PM PDT 24
Peak memory 210648 kb
Host smart-5fa39130-5503-43ab-b243-63e4d77a909e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4172614203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.4172614203
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.853653697
Short name T310
Test name
Test status
Simulation time 3023221548 ps
CPU time 49.99 seconds
Started May 28 01:16:23 PM PDT 24
Finished May 28 01:17:15 PM PDT 24
Peak memory 200020 kb
Host smart-1d8eb251-f529-469c-84bd-5641129a841f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853653697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.853653697
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.749258559
Short name T342
Test name
Test status
Simulation time 1379526183 ps
CPU time 73.63 seconds
Started May 28 01:16:21 PM PDT 24
Finished May 28 01:17:35 PM PDT 24
Peak memory 463888 kb
Host smart-643fc747-65e3-4a7e-9739-9e30cf5a45f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=749258559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.749258559
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.2540337591
Short name T343
Test name
Test status
Simulation time 7024636722 ps
CPU time 100.29 seconds
Started May 28 01:16:24 PM PDT 24
Finished May 28 01:18:05 PM PDT 24
Peak memory 200124 kb
Host smart-b089040b-ab29-419b-979b-93704eb16e93
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540337591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2540337591
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.763327896
Short name T232
Test name
Test status
Simulation time 270083065 ps
CPU time 3.44 seconds
Started May 28 01:16:25 PM PDT 24
Finished May 28 01:16:30 PM PDT 24
Peak memory 200088 kb
Host smart-aeb043d6-1008-40ed-b288-88ba3fa79ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763327896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.763327896
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.4211299487
Short name T279
Test name
Test status
Simulation time 2510702757 ps
CPU time 7.69 seconds
Started May 28 01:16:22 PM PDT 24
Finished May 28 01:16:31 PM PDT 24
Peak memory 200204 kb
Host smart-c32d60a4-a2f6-4e87-9b88-30bf1eecf5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211299487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.4211299487
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.1366590380
Short name T348
Test name
Test status
Simulation time 6001196167 ps
CPU time 56.17 seconds
Started May 28 01:16:22 PM PDT 24
Finished May 28 01:17:19 PM PDT 24
Peak memory 232804 kb
Host smart-f528372b-46da-42b5-9f83-0ba2c79f4f3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366590380 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.1366590380
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.2717772434
Short name T16
Test name
Test status
Simulation time 73746885 ps
CPU time 1.38 seconds
Started May 28 01:16:21 PM PDT 24
Finished May 28 01:16:24 PM PDT 24
Peak memory 200088 kb
Host smart-a0ce3d17-c8dc-462b-9e0a-57fb03c72ce8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717772434 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.2717772434
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.2451521241
Short name T322
Test name
Test status
Simulation time 8480009451 ps
CPU time 473.82 seconds
Started May 28 01:16:21 PM PDT 24
Finished May 28 01:24:16 PM PDT 24
Peak memory 200072 kb
Host smart-a0a7be97-9dba-45b1-aef7-a0234e2656c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451521241 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.2451521241
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1985744238
Short name T272
Test name
Test status
Simulation time 1800585754 ps
CPU time 26.52 seconds
Started May 28 01:16:27 PM PDT 24
Finished May 28 01:16:57 PM PDT 24
Peak memory 200068 kb
Host smart-91aac108-384f-40ab-af19-d3f397c6d4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985744238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1985744238
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2835834264
Short name T568
Test name
Test status
Simulation time 45836095 ps
CPU time 0.58 seconds
Started May 28 01:16:29 PM PDT 24
Finished May 28 01:16:32 PM PDT 24
Peak memory 195828 kb
Host smart-5dfaf425-be0e-4b67-bb46-4f8a27f7a123
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835834264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2835834264
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.962548270
Short name T43
Test name
Test status
Simulation time 1958066303 ps
CPU time 16.83 seconds
Started May 28 01:16:22 PM PDT 24
Finished May 28 01:16:40 PM PDT 24
Peak memory 215628 kb
Host smart-434c25d4-a343-42d8-83f1-df8bb27a758c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=962548270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.962548270
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.643462114
Short name T328
Test name
Test status
Simulation time 784493151 ps
CPU time 126.44 seconds
Started May 28 01:16:28 PM PDT 24
Finished May 28 01:18:37 PM PDT 24
Peak memory 363084 kb
Host smart-6ec53d58-dad4-4d92-9270-6137e59000c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=643462114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.643462114
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.362685256
Short name T406
Test name
Test status
Simulation time 8680006290 ps
CPU time 112.8 seconds
Started May 28 01:16:26 PM PDT 24
Finished May 28 01:18:22 PM PDT 24
Peak memory 200168 kb
Host smart-b36153a7-1fa5-4797-b096-ea596f5948b8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362685256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.362685256
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.114289926
Short name T302
Test name
Test status
Simulation time 4350479620 ps
CPU time 46.2 seconds
Started May 28 01:16:21 PM PDT 24
Finished May 28 01:17:09 PM PDT 24
Peak memory 199988 kb
Host smart-1548fa1b-9d29-419d-864e-3825f98fd806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114289926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.114289926
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3757134383
Short name T502
Test name
Test status
Simulation time 350055069 ps
CPU time 5.82 seconds
Started May 28 01:16:26 PM PDT 24
Finished May 28 01:16:35 PM PDT 24
Peak memory 199992 kb
Host smart-90ae10f9-40f0-4788-8c26-2a5c2362cf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757134383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3757134383
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1762759804
Short name T113
Test name
Test status
Simulation time 171564944485 ps
CPU time 1130.55 seconds
Started May 28 01:16:25 PM PDT 24
Finished May 28 01:35:18 PM PDT 24
Peak memory 703544 kb
Host smart-15278cd3-790c-4801-84dd-5426733249d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762759804 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1762759804
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.244163130
Short name T548
Test name
Test status
Simulation time 66221748 ps
CPU time 1.45 seconds
Started May 28 01:16:21 PM PDT 24
Finished May 28 01:16:24 PM PDT 24
Peak memory 200020 kb
Host smart-339d23c4-3bd0-4e56-9f16-6bca03d2d2a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244163130 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_hmac_vectors.244163130
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.185250544
Short name T127
Test name
Test status
Simulation time 267886256900 ps
CPU time 553 seconds
Started May 28 01:16:22 PM PDT 24
Finished May 28 01:25:37 PM PDT 24
Peak memory 200048 kb
Host smart-7edeba5f-a5ec-4e76-82f0-8fad6bf18877
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185250544 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.185250544
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.219656225
Short name T519
Test name
Test status
Simulation time 546202159 ps
CPU time 11.43 seconds
Started May 28 01:16:26 PM PDT 24
Finished May 28 01:16:41 PM PDT 24
Peak memory 200052 kb
Host smart-94d71b6a-5189-419f-97f8-f40adfd3287e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219656225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.219656225
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1886796391
Short name T513
Test name
Test status
Simulation time 20779654 ps
CPU time 0.61 seconds
Started May 28 01:16:24 PM PDT 24
Finished May 28 01:16:26 PM PDT 24
Peak memory 195852 kb
Host smart-f64ad102-e85c-4c0b-8237-87bca4b93ad1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886796391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1886796391
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.4201461851
Short name T171
Test name
Test status
Simulation time 36637326 ps
CPU time 1.98 seconds
Started May 28 01:16:22 PM PDT 24
Finished May 28 01:16:25 PM PDT 24
Peak memory 200020 kb
Host smart-38d36f9b-205c-4035-96c1-53e1037d198a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4201461851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.4201461851
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.4079058031
Short name T472
Test name
Test status
Simulation time 6518678408 ps
CPU time 62.19 seconds
Started May 28 01:16:27 PM PDT 24
Finished May 28 01:17:33 PM PDT 24
Peak memory 200156 kb
Host smart-7ef261b2-d31a-4a17-91cc-6a802c6f4a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079058031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.4079058031
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3534410768
Short name T291
Test name
Test status
Simulation time 2070220309 ps
CPU time 369.06 seconds
Started May 28 01:16:22 PM PDT 24
Finished May 28 01:22:33 PM PDT 24
Peak memory 667952 kb
Host smart-48c174d1-cf21-4c06-8269-c56fa4a65f7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3534410768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3534410768
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2565915179
Short name T533
Test name
Test status
Simulation time 15229138472 ps
CPU time 109.38 seconds
Started May 28 01:16:22 PM PDT 24
Finished May 28 01:18:13 PM PDT 24
Peak memory 199968 kb
Host smart-6a163a06-01b9-4a6a-a2a9-bd4c54ad89a1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565915179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2565915179
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.51509810
Short name T385
Test name
Test status
Simulation time 18649442724 ps
CPU time 66.26 seconds
Started May 28 01:16:24 PM PDT 24
Finished May 28 01:17:32 PM PDT 24
Peak memory 200156 kb
Host smart-f9fe4432-a48b-4c10-863e-bd16cadda101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51509810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.51509810
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.949051358
Short name T398
Test name
Test status
Simulation time 397335850 ps
CPU time 4.14 seconds
Started May 28 01:16:23 PM PDT 24
Finished May 28 01:16:29 PM PDT 24
Peak memory 199932 kb
Host smart-f708840b-05ca-483f-ae63-51a6aee79f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949051358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.949051358
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.2096134565
Short name T41
Test name
Test status
Simulation time 23179958807 ps
CPU time 485.58 seconds
Started May 28 01:16:25 PM PDT 24
Finished May 28 01:24:33 PM PDT 24
Peak memory 511004 kb
Host smart-60a16259-9c22-4232-b396-33658e5ca164
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096134565 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2096134565
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.2760766633
Short name T366
Test name
Test status
Simulation time 33587955 ps
CPU time 1.36 seconds
Started May 28 01:16:27 PM PDT 24
Finished May 28 01:16:32 PM PDT 24
Peak memory 200108 kb
Host smart-8c55b7d1-d672-4a59-902e-37da722ad341
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760766633 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.2760766633
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.2303993196
Short name T150
Test name
Test status
Simulation time 154788724201 ps
CPU time 490.55 seconds
Started May 28 01:16:27 PM PDT 24
Finished May 28 01:24:41 PM PDT 24
Peak memory 200052 kb
Host smart-a6c1ddf7-28cb-4914-a583-7be9b601730f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303993196 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.2303993196
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3877623068
Short name T571
Test name
Test status
Simulation time 481238627 ps
CPU time 7.73 seconds
Started May 28 01:16:25 PM PDT 24
Finished May 28 01:16:34 PM PDT 24
Peak memory 200064 kb
Host smart-5ca4e3f1-7e3c-4971-903a-c5511d8f89f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877623068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3877623068
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2853387163
Short name T459
Test name
Test status
Simulation time 33183667 ps
CPU time 0.61 seconds
Started May 28 01:15:18 PM PDT 24
Finished May 28 01:15:21 PM PDT 24
Peak memory 194856 kb
Host smart-e7d1145b-cf0a-4a2b-a511-115e60aa8548
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853387163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2853387163
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.977963301
Short name T263
Test name
Test status
Simulation time 777835836 ps
CPU time 38.53 seconds
Started May 28 01:15:21 PM PDT 24
Finished May 28 01:16:02 PM PDT 24
Peak memory 214396 kb
Host smart-a4e82199-ba5b-4487-9cf1-28e6a3f4e70d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=977963301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.977963301
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1442418768
Short name T539
Test name
Test status
Simulation time 3509696008 ps
CPU time 51.61 seconds
Started May 28 01:15:18 PM PDT 24
Finished May 28 01:16:11 PM PDT 24
Peak memory 200136 kb
Host smart-0eb80351-77fc-4c7f-bcde-4df0891bc47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442418768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1442418768
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.2117739381
Short name T34
Test name
Test status
Simulation time 3655008119 ps
CPU time 444.05 seconds
Started May 28 01:15:22 PM PDT 24
Finished May 28 01:22:48 PM PDT 24
Peak memory 671400 kb
Host smart-f2b2d03a-c26c-48d8-ab90-e4f8069ad87f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2117739381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2117739381
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.2804038523
Short name T162
Test name
Test status
Simulation time 28074736947 ps
CPU time 98.97 seconds
Started May 28 01:15:19 PM PDT 24
Finished May 28 01:17:00 PM PDT 24
Peak memory 200020 kb
Host smart-275ac16e-eb3d-4c68-b7a9-0c630962836f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804038523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2804038523
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3164253521
Short name T268
Test name
Test status
Simulation time 6081475140 ps
CPU time 82.3 seconds
Started May 28 01:15:24 PM PDT 24
Finished May 28 01:16:47 PM PDT 24
Peak memory 200148 kb
Host smart-8bae3fa5-dc96-4d49-957c-b437be1e5ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164253521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3164253521
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3132880170
Short name T31
Test name
Test status
Simulation time 577194643 ps
CPU time 1.28 seconds
Started May 28 01:15:22 PM PDT 24
Finished May 28 01:15:25 PM PDT 24
Peak memory 219228 kb
Host smart-de0d4dc9-69a8-4377-8342-d14cc76e92d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132880170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3132880170
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.1957174198
Short name T489
Test name
Test status
Simulation time 186129649 ps
CPU time 2.1 seconds
Started May 28 01:15:17 PM PDT 24
Finished May 28 01:15:20 PM PDT 24
Peak memory 200072 kb
Host smart-ede0880b-5721-43fc-a214-46a38b5f3891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957174198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1957174198
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.3399090245
Short name T564
Test name
Test status
Simulation time 64433945 ps
CPU time 1.19 seconds
Started May 28 01:15:21 PM PDT 24
Finished May 28 01:15:25 PM PDT 24
Peak memory 199636 kb
Host smart-81e10990-64bc-49de-9395-51514b7ee9f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399090245 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.3399090245
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.1537382347
Short name T223
Test name
Test status
Simulation time 17394397500 ps
CPU time 465.6 seconds
Started May 28 01:15:20 PM PDT 24
Finished May 28 01:23:08 PM PDT 24
Peak memory 199960 kb
Host smart-0593a5b7-8a62-4c39-884f-845b74b167c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537382347 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.1537382347
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.118713095
Short name T213
Test name
Test status
Simulation time 9917137123 ps
CPU time 91.13 seconds
Started May 28 01:15:19 PM PDT 24
Finished May 28 01:16:53 PM PDT 24
Peak memory 200144 kb
Host smart-a0d78b48-2c7d-4aa9-a3b3-08b5332dedcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118713095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.118713095
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2437399975
Short name T323
Test name
Test status
Simulation time 30814095 ps
CPU time 0.58 seconds
Started May 28 01:16:24 PM PDT 24
Finished May 28 01:16:26 PM PDT 24
Peak memory 195588 kb
Host smart-307582b4-5f9f-41f8-9738-9e46769bc6fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437399975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2437399975
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2162864259
Short name T404
Test name
Test status
Simulation time 705957131 ps
CPU time 22.85 seconds
Started May 28 01:16:27 PM PDT 24
Finished May 28 01:16:53 PM PDT 24
Peak memory 208224 kb
Host smart-5a2a0c57-447a-4ba7-a4fc-74d3fdb8449d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2162864259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2162864259
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2789198302
Short name T466
Test name
Test status
Simulation time 13107847568 ps
CPU time 44.3 seconds
Started May 28 01:16:26 PM PDT 24
Finished May 28 01:17:13 PM PDT 24
Peak memory 200104 kb
Host smart-625e51b3-026f-4d06-a664-a154b772c6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789198302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2789198302
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.801217120
Short name T531
Test name
Test status
Simulation time 10143788003 ps
CPU time 643.94 seconds
Started May 28 01:16:27 PM PDT 24
Finished May 28 01:27:14 PM PDT 24
Peak memory 697108 kb
Host smart-44fbb083-26c3-4842-acad-b9ec0a4bd9d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=801217120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.801217120
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.538749836
Short name T132
Test name
Test status
Simulation time 2119334113 ps
CPU time 13.63 seconds
Started May 28 01:16:29 PM PDT 24
Finished May 28 01:16:45 PM PDT 24
Peak memory 199912 kb
Host smart-358bb4e1-fa80-43e9-9da0-b84f3a6311f9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538749836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.538749836
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1480166603
Short name T380
Test name
Test status
Simulation time 32000798969 ps
CPU time 98.21 seconds
Started May 28 01:16:28 PM PDT 24
Finished May 28 01:18:09 PM PDT 24
Peak memory 200156 kb
Host smart-ba99c211-2a77-47a2-895c-80ee9dbb9ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480166603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1480166603
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.2312247285
Short name T225
Test name
Test status
Simulation time 99575238 ps
CPU time 2 seconds
Started May 28 01:16:29 PM PDT 24
Finished May 28 01:16:33 PM PDT 24
Peak memory 199920 kb
Host smart-9a2340b7-0556-4dc3-bd14-476817702c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312247285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2312247285
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2368015784
Short name T510
Test name
Test status
Simulation time 68962288339 ps
CPU time 2113.61 seconds
Started May 28 01:16:28 PM PDT 24
Finished May 28 01:51:45 PM PDT 24
Peak memory 690852 kb
Host smart-daa5a182-e5b1-4169-a26a-fa755be4ab52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368015784 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2368015784
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.1851633857
Short name T153
Test name
Test status
Simulation time 169387182 ps
CPU time 1.06 seconds
Started May 28 01:16:27 PM PDT 24
Finished May 28 01:16:31 PM PDT 24
Peak memory 199916 kb
Host smart-2266fb0a-1bec-4619-a840-e4e493d81321
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851633857 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.1851633857
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.1455334942
Short name T269
Test name
Test status
Simulation time 49238499271 ps
CPU time 604.89 seconds
Started May 28 01:16:29 PM PDT 24
Finished May 28 01:26:37 PM PDT 24
Peak memory 199980 kb
Host smart-5e799969-59ac-4dd3-8f93-6912c85123dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455334942 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.1455334942
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.780225663
Short name T221
Test name
Test status
Simulation time 3979585606 ps
CPU time 73.33 seconds
Started May 28 01:16:29 PM PDT 24
Finished May 28 01:17:45 PM PDT 24
Peak memory 200124 kb
Host smart-0b91afb6-01b3-4978-8ecb-0191aa1c2d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780225663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.780225663
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.182080487
Short name T81
Test name
Test status
Simulation time 11624370 ps
CPU time 0.59 seconds
Started May 28 01:16:37 PM PDT 24
Finished May 28 01:16:39 PM PDT 24
Peak memory 194960 kb
Host smart-7d27b772-5203-47bf-b6ad-2b9cc4c38bb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182080487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.182080487
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.797199307
Short name T523
Test name
Test status
Simulation time 1249823852 ps
CPU time 16.42 seconds
Started May 28 01:16:22 PM PDT 24
Finished May 28 01:16:41 PM PDT 24
Peak memory 228700 kb
Host smart-3ad29fdc-2587-4a4b-a4a5-2ff61d5c08b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=797199307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.797199307
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.79617429
Short name T496
Test name
Test status
Simulation time 1161079007 ps
CPU time 60.37 seconds
Started May 28 01:16:27 PM PDT 24
Finished May 28 01:17:31 PM PDT 24
Peak memory 199828 kb
Host smart-1e54c84d-8561-48bf-9467-9703748e03bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79617429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.79617429
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.2675840681
Short name T504
Test name
Test status
Simulation time 3727606124 ps
CPU time 950.42 seconds
Started May 28 01:16:25 PM PDT 24
Finished May 28 01:32:18 PM PDT 24
Peak memory 741652 kb
Host smart-339efe16-069f-4475-bda1-050aa4b6697f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2675840681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2675840681
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.207648829
Short name T528
Test name
Test status
Simulation time 1291619981 ps
CPU time 16.58 seconds
Started May 28 01:16:27 PM PDT 24
Finished May 28 01:16:47 PM PDT 24
Peak memory 199832 kb
Host smart-278a964d-183a-431b-a8cc-07c0b2edf171
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207648829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.207648829
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2361899842
Short name T1
Test name
Test status
Simulation time 1928110749 ps
CPU time 27.95 seconds
Started May 28 01:16:27 PM PDT 24
Finished May 28 01:16:58 PM PDT 24
Peak memory 199956 kb
Host smart-c5703c69-c4b5-46ed-bd0e-6a73849df722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361899842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2361899842
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.1006404936
Short name T360
Test name
Test status
Simulation time 302842712 ps
CPU time 5.65 seconds
Started May 28 01:16:27 PM PDT 24
Finished May 28 01:16:36 PM PDT 24
Peak memory 199984 kb
Host smart-73b8a19e-72e5-4400-8f91-5c10374b9a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006404936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.1006404936
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3075312365
Short name T71
Test name
Test status
Simulation time 335043651188 ps
CPU time 942.64 seconds
Started May 28 01:16:40 PM PDT 24
Finished May 28 01:32:23 PM PDT 24
Peak memory 476452 kb
Host smart-20ae803d-712a-4996-ae63-66e3e9f61be0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075312365 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3075312365
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.3220651792
Short name T578
Test name
Test status
Simulation time 95960136 ps
CPU time 1.18 seconds
Started May 28 01:16:41 PM PDT 24
Finished May 28 01:16:44 PM PDT 24
Peak memory 200128 kb
Host smart-f4fe9b7a-0cee-4c37-8929-9101b35bd795
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220651792 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.3220651792
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.2254588651
Short name T82
Test name
Test status
Simulation time 13940020517 ps
CPU time 395.56 seconds
Started May 28 01:16:37 PM PDT 24
Finished May 28 01:23:14 PM PDT 24
Peak memory 200076 kb
Host smart-e51ff66c-5bbc-4e19-8e6b-bc073ae62d35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254588651 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.2254588651
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2734095984
Short name T581
Test name
Test status
Simulation time 5757769809 ps
CPU time 62.85 seconds
Started May 28 01:16:25 PM PDT 24
Finished May 28 01:17:30 PM PDT 24
Peak memory 200116 kb
Host smart-094c10a3-90a6-4ae3-bf99-cff82cef9b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734095984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2734095984
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1463595891
Short name T215
Test name
Test status
Simulation time 12108113 ps
CPU time 0.61 seconds
Started May 28 01:16:40 PM PDT 24
Finished May 28 01:16:42 PM PDT 24
Peak memory 194884 kb
Host smart-27bb19f7-eeec-46f9-b6c2-2b637c3c66e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463595891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1463595891
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2243564950
Short name T540
Test name
Test status
Simulation time 1569306603 ps
CPU time 17.25 seconds
Started May 28 01:16:36 PM PDT 24
Finished May 28 01:16:54 PM PDT 24
Peak memory 208308 kb
Host smart-d0208b21-4356-4e27-8261-d80a5f203946
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2243564950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2243564950
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2052758726
Short name T560
Test name
Test status
Simulation time 2196374102 ps
CPU time 27.23 seconds
Started May 28 01:16:38 PM PDT 24
Finished May 28 01:17:06 PM PDT 24
Peak memory 199968 kb
Host smart-cdb32cea-5c31-40bc-8dd6-3ee72bc07323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052758726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2052758726
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3253256395
Short name T141
Test name
Test status
Simulation time 7958504721 ps
CPU time 943.86 seconds
Started May 28 01:16:38 PM PDT 24
Finished May 28 01:32:24 PM PDT 24
Peak memory 733768 kb
Host smart-ef4686df-5e9e-4d23-9532-241f269a3f16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3253256395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3253256395
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.3199936521
Short name T151
Test name
Test status
Simulation time 3307482163 ps
CPU time 49.63 seconds
Started May 28 01:16:37 PM PDT 24
Finished May 28 01:17:29 PM PDT 24
Peak memory 200064 kb
Host smart-becf9fae-d9d2-415c-b14f-dc41f8bcbd7c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199936521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3199936521
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3927834503
Short name T296
Test name
Test status
Simulation time 3524752621 ps
CPU time 17.32 seconds
Started May 28 01:16:36 PM PDT 24
Finished May 28 01:16:54 PM PDT 24
Peak memory 200036 kb
Host smart-fb170338-1db3-4690-b15d-8cd4a60de397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927834503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3927834503
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2034954041
Short name T371
Test name
Test status
Simulation time 59152238 ps
CPU time 0.93 seconds
Started May 28 01:16:35 PM PDT 24
Finished May 28 01:16:37 PM PDT 24
Peak memory 198440 kb
Host smart-8c5a7d11-0149-4de2-b42a-a081680a4ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034954041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2034954041
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.82784831
Short name T327
Test name
Test status
Simulation time 202347551327 ps
CPU time 1338.69 seconds
Started May 28 01:16:39 PM PDT 24
Finished May 28 01:38:59 PM PDT 24
Peak memory 802008 kb
Host smart-f31dee4a-9e98-4796-9b5d-22e89b355cb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82784831 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.82784831
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.4066289271
Short name T436
Test name
Test status
Simulation time 57941340 ps
CPU time 1.14 seconds
Started May 28 01:16:37 PM PDT 24
Finished May 28 01:16:39 PM PDT 24
Peak memory 199840 kb
Host smart-e3f09839-4bf4-480f-843c-e6fec60bac6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066289271 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.4066289271
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.2200802112
Short name T266
Test name
Test status
Simulation time 146500328919 ps
CPU time 493.3 seconds
Started May 28 01:16:42 PM PDT 24
Finished May 28 01:24:56 PM PDT 24
Peak memory 200088 kb
Host smart-95e005d9-e912-40ed-82e6-80dfaf601caf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200802112 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.2200802112
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.3573035763
Short name T287
Test name
Test status
Simulation time 2636133186 ps
CPU time 17.84 seconds
Started May 28 01:16:35 PM PDT 24
Finished May 28 01:16:54 PM PDT 24
Peak memory 200028 kb
Host smart-0c734f72-0604-4065-92c4-5c1d1d0018f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573035763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3573035763
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2065712965
Short name T341
Test name
Test status
Simulation time 40491891 ps
CPU time 0.64 seconds
Started May 28 01:16:36 PM PDT 24
Finished May 28 01:16:38 PM PDT 24
Peak memory 194852 kb
Host smart-50a7c227-b8e9-43bf-8855-fe0a22a48245
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065712965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2065712965
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1900281302
Short name T228
Test name
Test status
Simulation time 3487450938 ps
CPU time 38.6 seconds
Started May 28 01:16:37 PM PDT 24
Finished May 28 01:17:16 PM PDT 24
Peak memory 225304 kb
Host smart-d88d7cf3-4dca-4228-91bf-3e3eb20d1751
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1900281302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1900281302
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.2338659153
Short name T440
Test name
Test status
Simulation time 830767824 ps
CPU time 32.5 seconds
Started May 28 01:16:41 PM PDT 24
Finished May 28 01:17:14 PM PDT 24
Peak memory 200072 kb
Host smart-2686dbf2-fc69-46ae-809f-b002ad38c776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338659153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2338659153
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1870766851
Short name T349
Test name
Test status
Simulation time 95916486926 ps
CPU time 1880.39 seconds
Started May 28 01:16:40 PM PDT 24
Finished May 28 01:48:02 PM PDT 24
Peak memory 795428 kb
Host smart-09de3789-1997-48e8-b9e4-83375b9712e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1870766851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1870766851
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.868380733
Short name T467
Test name
Test status
Simulation time 80174152447 ps
CPU time 122.18 seconds
Started May 28 01:16:40 PM PDT 24
Finished May 28 01:18:43 PM PDT 24
Peak memory 199952 kb
Host smart-7b985417-f4f7-4ccd-88f6-8e00c116e253
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868380733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.868380733
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2545200633
Short name T169
Test name
Test status
Simulation time 7886923841 ps
CPU time 116.49 seconds
Started May 28 01:16:34 PM PDT 24
Finished May 28 01:18:32 PM PDT 24
Peak memory 200152 kb
Host smart-a7fdde3b-7032-4a63-8128-aa9c18376948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545200633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2545200633
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2938248305
Short name T463
Test name
Test status
Simulation time 137086723 ps
CPU time 2.46 seconds
Started May 28 01:16:42 PM PDT 24
Finished May 28 01:16:45 PM PDT 24
Peak memory 200092 kb
Host smart-7c486ec8-98ce-42a5-9b67-e6aa55f6778b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938248305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2938248305
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.1300953657
Short name T395
Test name
Test status
Simulation time 45203184775 ps
CPU time 858.2 seconds
Started May 28 01:16:39 PM PDT 24
Finished May 28 01:30:58 PM PDT 24
Peak memory 638480 kb
Host smart-06a6f62b-57b1-45bd-8430-9cb4acc3d532
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300953657 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1300953657
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.2919585716
Short name T337
Test name
Test status
Simulation time 57137435 ps
CPU time 1.05 seconds
Started May 28 01:16:38 PM PDT 24
Finished May 28 01:16:41 PM PDT 24
Peak memory 199900 kb
Host smart-73498361-150f-4093-97a7-a47a1274b532
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919585716 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.2919585716
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.2141223801
Short name T175
Test name
Test status
Simulation time 107549451857 ps
CPU time 487.76 seconds
Started May 28 01:16:38 PM PDT 24
Finished May 28 01:24:47 PM PDT 24
Peak memory 200104 kb
Host smart-db5f1b54-ac4e-4c36-9093-ca2882429ee6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141223801 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.2141223801
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.446225232
Short name T446
Test name
Test status
Simulation time 3331123656 ps
CPU time 60.67 seconds
Started May 28 01:16:41 PM PDT 24
Finished May 28 01:17:43 PM PDT 24
Peak memory 200128 kb
Host smart-fbd67402-8a87-4f88-ae1f-b6236aca7f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446225232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.446225232
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3463068991
Short name T182
Test name
Test status
Simulation time 29020570 ps
CPU time 0.59 seconds
Started May 28 01:16:51 PM PDT 24
Finished May 28 01:16:54 PM PDT 24
Peak memory 194660 kb
Host smart-ff71a50a-b774-4592-a4df-ed3d2d71cd10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463068991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3463068991
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1381563855
Short name T45
Test name
Test status
Simulation time 887121823 ps
CPU time 40.21 seconds
Started May 28 01:16:37 PM PDT 24
Finished May 28 01:17:19 PM PDT 24
Peak memory 218976 kb
Host smart-036f9570-af83-438f-ad51-b21f08f8cef5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1381563855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1381563855
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2142072549
Short name T212
Test name
Test status
Simulation time 839170024 ps
CPU time 13.38 seconds
Started May 28 01:16:37 PM PDT 24
Finished May 28 01:16:52 PM PDT 24
Peak memory 200024 kb
Host smart-dee1d330-2521-4d52-b946-00532a3a9652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142072549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2142072549
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3625882883
Short name T583
Test name
Test status
Simulation time 33072128969 ps
CPU time 621.23 seconds
Started May 28 01:16:41 PM PDT 24
Finished May 28 01:27:04 PM PDT 24
Peak memory 683960 kb
Host smart-1f0a14f8-8173-465c-94e3-00fd78ee6959
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3625882883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3625882883
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.579686414
Short name T565
Test name
Test status
Simulation time 36422403064 ps
CPU time 112.94 seconds
Started May 28 01:16:38 PM PDT 24
Finished May 28 01:18:32 PM PDT 24
Peak memory 199988 kb
Host smart-10f3c61e-ee56-4f42-b28c-a0f66359af6e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579686414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.579686414
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1372498317
Short name T247
Test name
Test status
Simulation time 27442618819 ps
CPU time 104.33 seconds
Started May 28 01:16:41 PM PDT 24
Finished May 28 01:18:26 PM PDT 24
Peak memory 200048 kb
Host smart-678ef152-9861-43c7-9c09-42cdfff52cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372498317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1372498317
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1115317731
Short name T205
Test name
Test status
Simulation time 126432653 ps
CPU time 4.53 seconds
Started May 28 01:16:38 PM PDT 24
Finished May 28 01:16:44 PM PDT 24
Peak memory 199964 kb
Host smart-b2970e01-5d73-4955-b88d-f99d87d5caaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115317731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1115317731
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.77217519
Short name T117
Test name
Test status
Simulation time 113833930560 ps
CPU time 1005.05 seconds
Started May 28 01:16:56 PM PDT 24
Finished May 28 01:33:42 PM PDT 24
Peak memory 650332 kb
Host smart-57393ff9-9cd2-4dcb-a99f-d9a7e8284257
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77217519 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.77217519
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.2706696920
Short name T378
Test name
Test status
Simulation time 51463722 ps
CPU time 1.25 seconds
Started May 28 01:16:55 PM PDT 24
Finished May 28 01:16:58 PM PDT 24
Peak memory 200144 kb
Host smart-ca7a34e3-6f07-4acc-9e5a-672e2692d744
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706696920 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.2706696920
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.280539553
Short name T303
Test name
Test status
Simulation time 24605531686 ps
CPU time 414.76 seconds
Started May 28 01:16:37 PM PDT 24
Finished May 28 01:23:32 PM PDT 24
Peak memory 200004 kb
Host smart-d02ffb11-ef81-49ba-8594-85bfa8304963
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280539553 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.280539553
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3695483208
Short name T447
Test name
Test status
Simulation time 1834918531 ps
CPU time 32.94 seconds
Started May 28 01:16:40 PM PDT 24
Finished May 28 01:17:14 PM PDT 24
Peak memory 200040 kb
Host smart-7e58d5bd-8f67-4742-aae4-5e637cf526a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695483208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3695483208
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2387616219
Short name T22
Test name
Test status
Simulation time 91355035 ps
CPU time 0.57 seconds
Started May 28 01:16:55 PM PDT 24
Finished May 28 01:16:58 PM PDT 24
Peak memory 194960 kb
Host smart-5767644e-56fa-4572-940c-0fdeaedd941a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387616219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2387616219
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.468806425
Short name T584
Test name
Test status
Simulation time 1807933468 ps
CPU time 24.08 seconds
Started May 28 01:16:48 PM PDT 24
Finished May 28 01:17:15 PM PDT 24
Peak memory 215524 kb
Host smart-ce3202f1-c8fb-4bda-90ca-8497f89101ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=468806425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.468806425
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.595848263
Short name T488
Test name
Test status
Simulation time 692933416 ps
CPU time 10.04 seconds
Started May 28 01:16:54 PM PDT 24
Finished May 28 01:17:06 PM PDT 24
Peak memory 200140 kb
Host smart-68f805dd-323e-470a-83d0-2ce6d9328e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595848263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.595848263
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1703573616
Short name T267
Test name
Test status
Simulation time 667950462 ps
CPU time 10.39 seconds
Started May 28 01:16:51 PM PDT 24
Finished May 28 01:17:04 PM PDT 24
Peak memory 216488 kb
Host smart-1d53cb27-cea8-433a-9db4-432172aa401d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1703573616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1703573616
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2003944392
Short name T542
Test name
Test status
Simulation time 29404777716 ps
CPU time 209.77 seconds
Started May 28 01:16:48 PM PDT 24
Finished May 28 01:20:20 PM PDT 24
Peak memory 200408 kb
Host smart-21f2b40c-5899-4f7d-a52e-ac93f1baeae3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003944392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2003944392
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1461378673
Short name T246
Test name
Test status
Simulation time 23251790278 ps
CPU time 115.05 seconds
Started May 28 01:16:49 PM PDT 24
Finished May 28 01:18:46 PM PDT 24
Peak memory 200048 kb
Host smart-cfc5b9ba-b2e8-41b9-85a9-f140f27a586a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461378673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1461378673
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3979451064
Short name T257
Test name
Test status
Simulation time 164630639 ps
CPU time 3.07 seconds
Started May 28 01:16:50 PM PDT 24
Finished May 28 01:16:55 PM PDT 24
Peak memory 200012 kb
Host smart-23288490-e117-4cf8-9e4c-8969ee0e02c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979451064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3979451064
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.3836627964
Short name T537
Test name
Test status
Simulation time 98468717810 ps
CPU time 2440.28 seconds
Started May 28 01:16:54 PM PDT 24
Finished May 28 01:57:37 PM PDT 24
Peak memory 785696 kb
Host smart-e88ab5b1-0484-455c-90da-604192519654
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836627964 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.3836627964
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.1673982143
Short name T210
Test name
Test status
Simulation time 151510984 ps
CPU time 1.53 seconds
Started May 28 01:16:51 PM PDT 24
Finished May 28 01:16:55 PM PDT 24
Peak memory 200104 kb
Host smart-f436434c-54bc-4555-8cb9-1f796f073269
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673982143 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.1673982143
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.2943460493
Short name T149
Test name
Test status
Simulation time 50933784762 ps
CPU time 483.67 seconds
Started May 28 01:16:50 PM PDT 24
Finished May 28 01:24:57 PM PDT 24
Peak memory 200084 kb
Host smart-7169ac44-e077-44c6-9185-dbac338d1253
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943460493 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.2943460493
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3566536366
Short name T253
Test name
Test status
Simulation time 42620044485 ps
CPU time 95.96 seconds
Started May 28 01:16:54 PM PDT 24
Finished May 28 01:18:32 PM PDT 24
Peak memory 200052 kb
Host smart-c0d68987-5529-4587-949f-810813817ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566536366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3566536366
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.3983842407
Short name T544
Test name
Test status
Simulation time 17926061 ps
CPU time 0.6 seconds
Started May 28 01:16:55 PM PDT 24
Finished May 28 01:16:57 PM PDT 24
Peak memory 195880 kb
Host smart-450c7a0e-8fc0-4583-ba8e-8a6555efd614
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983842407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3983842407
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.1568356946
Short name T433
Test name
Test status
Simulation time 1347201419 ps
CPU time 20.37 seconds
Started May 28 01:16:48 PM PDT 24
Finished May 28 01:17:11 PM PDT 24
Peak memory 211180 kb
Host smart-e4d4ea8a-df9d-4a48-b3dd-f097f4a3d601
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1568356946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1568356946
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2843855276
Short name T110
Test name
Test status
Simulation time 3339779392 ps
CPU time 24.96 seconds
Started May 28 01:16:54 PM PDT 24
Finished May 28 01:17:21 PM PDT 24
Peak memory 200152 kb
Host smart-1b6eceeb-41e0-49cb-b29b-186178d69ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843855276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2843855276
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1106927887
Short name T369
Test name
Test status
Simulation time 694851639 ps
CPU time 214.87 seconds
Started May 28 01:17:03 PM PDT 24
Finished May 28 01:20:40 PM PDT 24
Peak memory 647540 kb
Host smart-2de5111e-1f88-457a-a3bf-c6563fabf597
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1106927887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1106927887
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.546342348
Short name T347
Test name
Test status
Simulation time 9661573894 ps
CPU time 173.97 seconds
Started May 28 01:16:51 PM PDT 24
Finished May 28 01:19:48 PM PDT 24
Peak memory 200024 kb
Host smart-f31796cd-f498-42be-9f02-c42a4203eaf7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546342348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.546342348
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.4079141689
Short name T562
Test name
Test status
Simulation time 363086506 ps
CPU time 10.79 seconds
Started May 28 01:16:51 PM PDT 24
Finished May 28 01:17:05 PM PDT 24
Peak memory 200136 kb
Host smart-198b13a1-3046-4deb-90b9-2fdcfd3c86ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079141689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.4079141689
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3901024082
Short name T363
Test name
Test status
Simulation time 383299011 ps
CPU time 7.15 seconds
Started May 28 01:16:51 PM PDT 24
Finished May 28 01:17:01 PM PDT 24
Peak memory 200160 kb
Host smart-12939009-9d0a-4b09-bf96-e1ec4cf5c018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901024082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3901024082
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3376091917
Short name T78
Test name
Test status
Simulation time 265858638229 ps
CPU time 1172.22 seconds
Started May 28 01:16:55 PM PDT 24
Finished May 28 01:36:29 PM PDT 24
Peak memory 215472 kb
Host smart-93c6efbd-f73a-4a81-9923-79d391d9e886
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376091917 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3376091917
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.49164156
Short name T493
Test name
Test status
Simulation time 449298212 ps
CPU time 1.28 seconds
Started May 28 01:16:53 PM PDT 24
Finished May 28 01:16:57 PM PDT 24
Peak memory 200056 kb
Host smart-96488f8a-0175-45ec-aaf6-ec343f7cee10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49164156 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.hmac_test_hmac_vectors.49164156
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.3478445078
Short name T35
Test name
Test status
Simulation time 9542369633 ps
CPU time 510.64 seconds
Started May 28 01:16:48 PM PDT 24
Finished May 28 01:25:21 PM PDT 24
Peak memory 200000 kb
Host smart-67dbfc6c-2309-4040-a244-a922c07e805d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478445078 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.3478445078
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3464021249
Short name T445
Test name
Test status
Simulation time 4916831861 ps
CPU time 9.77 seconds
Started May 28 01:16:50 PM PDT 24
Finished May 28 01:17:03 PM PDT 24
Peak memory 200048 kb
Host smart-0dcfd72a-3448-4c6b-a668-d82bcdf636d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464021249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3464021249
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.3799590387
Short name T168
Test name
Test status
Simulation time 30203385 ps
CPU time 0.53 seconds
Started May 28 01:16:49 PM PDT 24
Finished May 28 01:16:52 PM PDT 24
Peak memory 194828 kb
Host smart-876ebfe8-27fc-4eed-bf98-ca7b565b7149
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799590387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3799590387
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.114796127
Short name T274
Test name
Test status
Simulation time 43880160 ps
CPU time 1.47 seconds
Started May 28 01:16:50 PM PDT 24
Finished May 28 01:16:54 PM PDT 24
Peak memory 199932 kb
Host smart-26e38ee7-0a2c-4626-975d-22f0fa6b61de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=114796127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.114796127
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.1779442725
Short name T529
Test name
Test status
Simulation time 1271545157 ps
CPU time 33.16 seconds
Started May 28 01:16:49 PM PDT 24
Finished May 28 01:17:24 PM PDT 24
Peak memory 199972 kb
Host smart-8cebe07d-5117-431b-8d23-4ca4764c9d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779442725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.1779442725
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1679110975
Short name T383
Test name
Test status
Simulation time 3553700298 ps
CPU time 920.29 seconds
Started May 28 01:16:51 PM PDT 24
Finished May 28 01:32:14 PM PDT 24
Peak memory 730108 kb
Host smart-813cd1d9-d310-4fc7-bf51-cb00efe5ce52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1679110975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1679110975
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3545497527
Short name T262
Test name
Test status
Simulation time 1236148674 ps
CPU time 6.74 seconds
Started May 28 01:16:56 PM PDT 24
Finished May 28 01:17:04 PM PDT 24
Peak memory 200052 kb
Host smart-8e848b28-67f7-4569-86b7-4cd7165ffa20
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545497527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3545497527
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.1244886929
Short name T208
Test name
Test status
Simulation time 2484716875 ps
CPU time 39.87 seconds
Started May 28 01:16:49 PM PDT 24
Finished May 28 01:17:32 PM PDT 24
Peak memory 200156 kb
Host smart-984cd9ad-152d-45cf-b880-f79006980537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244886929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.1244886929
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.502713213
Short name T245
Test name
Test status
Simulation time 1233065521 ps
CPU time 8.44 seconds
Started May 28 01:16:49 PM PDT 24
Finished May 28 01:17:00 PM PDT 24
Peak memory 200052 kb
Host smart-e2a5e39b-56fe-4423-8970-b47d8ebb338b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502713213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.502713213
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.649485726
Short name T231
Test name
Test status
Simulation time 64505107694 ps
CPU time 1288.43 seconds
Started May 28 01:16:52 PM PDT 24
Finished May 28 01:38:23 PM PDT 24
Peak memory 752568 kb
Host smart-06748dc6-6eae-46fd-a72f-865bfc95d138
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649485726 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.649485726
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.3633099116
Short name T425
Test name
Test status
Simulation time 183729922 ps
CPU time 1.12 seconds
Started May 28 01:16:49 PM PDT 24
Finished May 28 01:16:52 PM PDT 24
Peak memory 200004 kb
Host smart-553591ae-8b1e-4274-a1d6-6aa46ca796e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633099116 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.3633099116
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.1635038502
Short name T591
Test name
Test status
Simulation time 162297353123 ps
CPU time 515.06 seconds
Started May 28 01:16:50 PM PDT 24
Finished May 28 01:25:28 PM PDT 24
Peak memory 200104 kb
Host smart-88bf95c3-aa35-475d-978b-0f603e9e2e28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635038502 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.1635038502
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.2947878266
Short name T492
Test name
Test status
Simulation time 467117939 ps
CPU time 24.46 seconds
Started May 28 01:16:52 PM PDT 24
Finished May 28 01:17:19 PM PDT 24
Peak memory 200040 kb
Host smart-10bef928-e947-470b-9ea7-9cf4295e35e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947878266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2947878266
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1356496784
Short name T172
Test name
Test status
Simulation time 54398475 ps
CPU time 0.58 seconds
Started May 28 01:17:05 PM PDT 24
Finished May 28 01:17:07 PM PDT 24
Peak memory 195816 kb
Host smart-383d7ff1-4edc-4994-bca1-5195717ee697
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356496784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1356496784
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.4223982016
Short name T389
Test name
Test status
Simulation time 3840908682 ps
CPU time 51.29 seconds
Started May 28 01:16:51 PM PDT 24
Finished May 28 01:17:45 PM PDT 24
Peak memory 218572 kb
Host smart-eb77b4a4-fd4b-4d32-8a29-a8796c729b89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4223982016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.4223982016
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3490045840
Short name T226
Test name
Test status
Simulation time 9818969060 ps
CPU time 40.07 seconds
Started May 28 01:16:54 PM PDT 24
Finished May 28 01:17:36 PM PDT 24
Peak memory 200124 kb
Host smart-bb1db37f-ab54-4eb5-8abf-34fee7eed6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490045840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3490045840
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.1169042359
Short name T209
Test name
Test status
Simulation time 1381128535 ps
CPU time 320.58 seconds
Started May 28 01:16:54 PM PDT 24
Finished May 28 01:22:17 PM PDT 24
Peak memory 657716 kb
Host smart-8be1b8d9-0e98-49f0-a47a-11a930928b23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1169042359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1169042359
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3813801371
Short name T2
Test name
Test status
Simulation time 8104329036 ps
CPU time 115.41 seconds
Started May 28 01:16:51 PM PDT 24
Finished May 28 01:18:49 PM PDT 24
Peak memory 200128 kb
Host smart-34ee10ef-b136-4145-ab5e-e1601f3fb5ef
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813801371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3813801371
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.4152980848
Short name T329
Test name
Test status
Simulation time 1434744615 ps
CPU time 19.9 seconds
Started May 28 01:16:55 PM PDT 24
Finished May 28 01:17:16 PM PDT 24
Peak memory 200088 kb
Host smart-576252f3-9552-4b9c-b321-d572f78326db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152980848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.4152980848
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.830443278
Short name T525
Test name
Test status
Simulation time 677440920 ps
CPU time 4.39 seconds
Started May 28 01:16:50 PM PDT 24
Finished May 28 01:16:57 PM PDT 24
Peak memory 200140 kb
Host smart-ee2ac215-c0b9-4aea-9f10-fb82b169024b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830443278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.830443278
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2491453063
Short name T204
Test name
Test status
Simulation time 86493964 ps
CPU time 1.46 seconds
Started May 28 01:17:06 PM PDT 24
Finished May 28 01:17:09 PM PDT 24
Peak memory 200096 kb
Host smart-0420a447-c706-48d4-8e8d-f67384497585
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491453063 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2491453063
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.944789628
Short name T515
Test name
Test status
Simulation time 103640911 ps
CPU time 1.06 seconds
Started May 28 01:17:04 PM PDT 24
Finished May 28 01:17:06 PM PDT 24
Peak memory 199540 kb
Host smart-be878bbc-8fbe-431f-83f4-28ac63e4aecf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944789628 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_hmac_vectors.944789628
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.3639145784
Short name T394
Test name
Test status
Simulation time 34908764291 ps
CPU time 468.96 seconds
Started May 28 01:17:06 PM PDT 24
Finished May 28 01:24:56 PM PDT 24
Peak memory 200152 kb
Host smart-32216e2a-795e-4449-80e8-9904848f77c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639145784 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.3639145784
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.4026862699
Short name T577
Test name
Test status
Simulation time 1154555758 ps
CPU time 19.11 seconds
Started May 28 01:16:51 PM PDT 24
Finished May 28 01:17:13 PM PDT 24
Peak memory 200112 kb
Host smart-4a543a8c-df46-4782-8966-d16bbace916d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026862699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.4026862699
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.2668450965
Short name T207
Test name
Test status
Simulation time 35909243 ps
CPU time 0.57 seconds
Started May 28 01:17:05 PM PDT 24
Finished May 28 01:17:07 PM PDT 24
Peak memory 194904 kb
Host smart-320d7d57-3075-4b5a-8d3c-8a97fc87a37e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668450965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2668450965
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3049111636
Short name T458
Test name
Test status
Simulation time 292548415 ps
CPU time 9.85 seconds
Started May 28 01:17:04 PM PDT 24
Finished May 28 01:17:16 PM PDT 24
Peak memory 200048 kb
Host smart-f3590c56-d371-4d0f-ba1b-bf173425022c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3049111636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3049111636
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2659209210
Short name T104
Test name
Test status
Simulation time 9912233377 ps
CPU time 45.3 seconds
Started May 28 01:17:03 PM PDT 24
Finished May 28 01:17:49 PM PDT 24
Peak memory 200060 kb
Host smart-5787d862-bd56-482c-a383-c4fce107a469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659209210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2659209210
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3573654240
Short name T415
Test name
Test status
Simulation time 4176947231 ps
CPU time 1180.07 seconds
Started May 28 01:17:02 PM PDT 24
Finished May 28 01:36:44 PM PDT 24
Peak memory 770644 kb
Host smart-c81332df-d432-4ce1-a72b-ca1b0d3c5b15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3573654240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3573654240
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.1602003354
Short name T441
Test name
Test status
Simulation time 2403965865 ps
CPU time 45.71 seconds
Started May 28 01:17:07 PM PDT 24
Finished May 28 01:17:54 PM PDT 24
Peak memory 200048 kb
Host smart-87047bce-0b44-425a-a0d4-5c18d33efb96
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602003354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1602003354
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1114638640
Short name T178
Test name
Test status
Simulation time 6995923249 ps
CPU time 34.95 seconds
Started May 28 01:17:04 PM PDT 24
Finished May 28 01:17:41 PM PDT 24
Peak memory 200152 kb
Host smart-f935c927-dd2b-48f2-b119-cdbe6f4aea77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114638640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1114638640
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.3252514524
Short name T242
Test name
Test status
Simulation time 1399398676 ps
CPU time 9.39 seconds
Started May 28 01:17:03 PM PDT 24
Finished May 28 01:17:14 PM PDT 24
Peak memory 199980 kb
Host smart-ea5cd572-96ce-4c61-8623-74e225f9be5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252514524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.3252514524
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2703733903
Short name T107
Test name
Test status
Simulation time 7171955651 ps
CPU time 1035.8 seconds
Started May 28 01:17:04 PM PDT 24
Finished May 28 01:34:22 PM PDT 24
Peak memory 756784 kb
Host smart-3a380c70-b52e-48fb-81cd-392d99f88b0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703733903 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2703733903
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.2369282012
Short name T252
Test name
Test status
Simulation time 80017684 ps
CPU time 1.36 seconds
Started May 28 01:17:04 PM PDT 24
Finished May 28 01:17:07 PM PDT 24
Peak memory 200092 kb
Host smart-4245551c-f3ce-42cf-807a-e0a2df9581cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369282012 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.2369282012
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.2732155253
Short name T585
Test name
Test status
Simulation time 120706615223 ps
CPU time 426.61 seconds
Started May 28 01:17:03 PM PDT 24
Finished May 28 01:24:11 PM PDT 24
Peak memory 200084 kb
Host smart-6e9dfb71-6e4c-4bba-b9f2-e37f7f8ef998
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732155253 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.2732155253
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1924131202
Short name T39
Test name
Test status
Simulation time 681446143 ps
CPU time 6.19 seconds
Started May 28 01:17:07 PM PDT 24
Finished May 28 01:17:14 PM PDT 24
Peak memory 200104 kb
Host smart-e9f5fcec-86cc-4ab6-beb0-d35d24637352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924131202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1924131202
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.346877872
Short name T80
Test name
Test status
Simulation time 10844878 ps
CPU time 0.66 seconds
Started May 28 01:15:35 PM PDT 24
Finished May 28 01:15:38 PM PDT 24
Peak memory 194988 kb
Host smart-00f9aaf6-a190-4257-a3c7-126c94f39a0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346877872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.346877872
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.1642152588
Short name T498
Test name
Test status
Simulation time 2033299658 ps
CPU time 28.56 seconds
Started May 28 01:15:17 PM PDT 24
Finished May 28 01:15:47 PM PDT 24
Peak memory 217408 kb
Host smart-470e46bf-9160-48f4-a3e5-1f92c592e15e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1642152588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1642152588
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3397698732
Short name T391
Test name
Test status
Simulation time 119136634 ps
CPU time 3.26 seconds
Started May 28 01:15:17 PM PDT 24
Finished May 28 01:15:22 PM PDT 24
Peak memory 200072 kb
Host smart-b84f64a0-2a0d-4060-b9f2-dc9065b03d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397698732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3397698732
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1966310347
Short name T397
Test name
Test status
Simulation time 3258349321 ps
CPU time 255.2 seconds
Started May 28 01:15:17 PM PDT 24
Finished May 28 01:19:34 PM PDT 24
Peak memory 662968 kb
Host smart-fedbcacc-db32-49c0-93ad-b8ebd21d622c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1966310347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1966310347
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.3813961884
Short name T158
Test name
Test status
Simulation time 14879541195 ps
CPU time 46.49 seconds
Started May 28 01:15:18 PM PDT 24
Finished May 28 01:16:07 PM PDT 24
Peak memory 200044 kb
Host smart-2138f70b-cd38-44d9-9e0b-a09a00d16c4f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813961884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.3813961884
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3119549642
Short name T250
Test name
Test status
Simulation time 3175612668 ps
CPU time 43.34 seconds
Started May 28 01:15:22 PM PDT 24
Finished May 28 01:16:08 PM PDT 24
Peak memory 200028 kb
Host smart-3fd1f02e-8cb0-422a-a1c9-c0a0b4b4c2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119549642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3119549642
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3612740098
Short name T29
Test name
Test status
Simulation time 138869686 ps
CPU time 0.83 seconds
Started May 28 01:15:35 PM PDT 24
Finished May 28 01:15:38 PM PDT 24
Peak memory 218112 kb
Host smart-8cd99a34-1ed2-489a-9471-b1cb9aa6fed4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612740098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3612740098
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3299459114
Short name T388
Test name
Test status
Simulation time 119037718 ps
CPU time 4.69 seconds
Started May 28 01:15:20 PM PDT 24
Finished May 28 01:15:27 PM PDT 24
Peak memory 200000 kb
Host smart-04093d8b-4ce8-4631-9086-0b60389b2bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299459114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3299459114
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.614107187
Short name T251
Test name
Test status
Simulation time 2281339427 ps
CPU time 56.41 seconds
Started May 28 01:15:35 PM PDT 24
Finished May 28 01:16:33 PM PDT 24
Peak memory 216016 kb
Host smart-f7b9deab-ed85-4b0e-8fd1-6e9e25c2db12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614107187 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.614107187
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.1481077379
Short name T569
Test name
Test status
Simulation time 100809033 ps
CPU time 1.01 seconds
Started May 28 01:15:35 PM PDT 24
Finished May 28 01:15:38 PM PDT 24
Peak memory 199964 kb
Host smart-87b74530-a30b-449d-8914-26609eaafadb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481077379 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.1481077379
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.3323497237
Short name T530
Test name
Test status
Simulation time 35273107710 ps
CPU time 477.36 seconds
Started May 28 01:15:35 PM PDT 24
Finished May 28 01:23:35 PM PDT 24
Peak memory 200136 kb
Host smart-ff0f0efa-ba08-4c9d-aacf-8570339dcae4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323497237 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.3323497237
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.2496488752
Short name T37
Test name
Test status
Simulation time 2962979765 ps
CPU time 53.46 seconds
Started May 28 01:15:21 PM PDT 24
Finished May 28 01:16:17 PM PDT 24
Peak memory 199980 kb
Host smart-2f338bd4-c409-4fd7-9a6c-c668ae3ec37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496488752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2496488752
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.2406764662
Short name T351
Test name
Test status
Simulation time 35364494 ps
CPU time 0.63 seconds
Started May 28 01:17:04 PM PDT 24
Finished May 28 01:17:07 PM PDT 24
Peak memory 195584 kb
Host smart-15e2d8ce-e513-472a-a6b6-1658fd763c61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406764662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2406764662
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1024862436
Short name T367
Test name
Test status
Simulation time 15330313861 ps
CPU time 60.72 seconds
Started May 28 01:17:04 PM PDT 24
Finished May 28 01:18:06 PM PDT 24
Peak memory 210324 kb
Host smart-81888252-075d-4358-a746-91ce73b77dd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1024862436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1024862436
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1564060636
Short name T411
Test name
Test status
Simulation time 3041406343 ps
CPU time 12.74 seconds
Started May 28 01:17:04 PM PDT 24
Finished May 28 01:17:18 PM PDT 24
Peak memory 200152 kb
Host smart-70467af9-85c3-4396-bbb9-bcb603f85543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564060636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1564060636
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.399856359
Short name T299
Test name
Test status
Simulation time 72005367188 ps
CPU time 1135.49 seconds
Started May 28 01:17:03 PM PDT 24
Finished May 28 01:35:59 PM PDT 24
Peak memory 755344 kb
Host smart-90736d6c-5fcd-4304-a21e-750f1a7dc534
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=399856359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.399856359
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1519987061
Short name T454
Test name
Test status
Simulation time 4903544562 ps
CPU time 91.9 seconds
Started May 28 01:17:03 PM PDT 24
Finished May 28 01:18:37 PM PDT 24
Peak memory 200080 kb
Host smart-679707e8-ce69-470a-afbb-8d2abc3a2177
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519987061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1519987061
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.625329826
Short name T68
Test name
Test status
Simulation time 12965381995 ps
CPU time 101.93 seconds
Started May 28 01:17:07 PM PDT 24
Finished May 28 01:18:50 PM PDT 24
Peak memory 200204 kb
Host smart-df311181-be8d-4c62-bc81-703ba45d680a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625329826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.625329826
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2759853430
Short name T42
Test name
Test status
Simulation time 488488081 ps
CPU time 7.87 seconds
Started May 28 01:17:04 PM PDT 24
Finished May 28 01:17:14 PM PDT 24
Peak memory 199988 kb
Host smart-c16b8eab-b388-4290-b626-7ec63d7371d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759853430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2759853430
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.2733232189
Short name T183
Test name
Test status
Simulation time 10456966487 ps
CPU time 54.31 seconds
Started May 28 01:17:10 PM PDT 24
Finished May 28 01:18:05 PM PDT 24
Peak memory 229216 kb
Host smart-85f1c3dd-cad1-4ba0-9aea-f7fb00132c28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733232189 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2733232189
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.2890036104
Short name T483
Test name
Test status
Simulation time 499543902 ps
CPU time 1.33 seconds
Started May 28 01:17:04 PM PDT 24
Finished May 28 01:17:07 PM PDT 24
Peak memory 200052 kb
Host smart-1f68a5f2-4acc-4314-a1fc-407996c1a41d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890036104 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.2890036104
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.204943648
Short name T139
Test name
Test status
Simulation time 7255601935 ps
CPU time 420.14 seconds
Started May 28 01:17:05 PM PDT 24
Finished May 28 01:24:07 PM PDT 24
Peak memory 200052 kb
Host smart-564083c2-8869-4cb9-8458-9257ead3d753
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204943648 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.204943648
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.80635459
Short name T301
Test name
Test status
Simulation time 1146442614 ps
CPU time 32.45 seconds
Started May 28 01:17:05 PM PDT 24
Finished May 28 01:17:39 PM PDT 24
Peak memory 199928 kb
Host smart-dc86a58e-6d3a-4b90-8441-85f495a0264c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80635459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.80635459
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1521351251
Short name T173
Test name
Test status
Simulation time 21124338 ps
CPU time 0.55 seconds
Started May 28 01:17:17 PM PDT 24
Finished May 28 01:17:20 PM PDT 24
Peak memory 194860 kb
Host smart-51accfcd-8ec3-4235-b5cc-3c9eb08e2eb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521351251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1521351251
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.394700207
Short name T427
Test name
Test status
Simulation time 2386213746 ps
CPU time 16.85 seconds
Started May 28 01:17:02 PM PDT 24
Finished May 28 01:17:19 PM PDT 24
Peak memory 208284 kb
Host smart-fdca410a-4410-4696-93b0-41ee28dc085d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=394700207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.394700207
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.4006336478
Short name T421
Test name
Test status
Simulation time 634159308 ps
CPU time 1.69 seconds
Started May 28 01:17:17 PM PDT 24
Finished May 28 01:17:22 PM PDT 24
Peak memory 199968 kb
Host smart-8192f172-da90-4b52-8b32-ef94c7df1ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006336478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.4006336478
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2279831523
Short name T103
Test name
Test status
Simulation time 8761721369 ps
CPU time 516.17 seconds
Started May 28 01:17:18 PM PDT 24
Finished May 28 01:25:58 PM PDT 24
Peak memory 689568 kb
Host smart-9dd5b6c8-8b4b-4b2d-9b27-316db866ded5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2279831523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2279831523
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3876811262
Short name T140
Test name
Test status
Simulation time 743861323 ps
CPU time 8.29 seconds
Started May 28 01:17:16 PM PDT 24
Finished May 28 01:17:25 PM PDT 24
Peak memory 200004 kb
Host smart-808782a5-59d9-47e7-866b-b390fcd90ef9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876811262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3876811262
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1780761267
Short name T559
Test name
Test status
Simulation time 400470084 ps
CPU time 22.09 seconds
Started May 28 01:17:05 PM PDT 24
Finished May 28 01:17:29 PM PDT 24
Peak memory 199960 kb
Host smart-e5359370-405a-4925-9304-4c98c4669dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780761267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1780761267
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.206706946
Short name T402
Test name
Test status
Simulation time 202254182 ps
CPU time 7.22 seconds
Started May 28 01:17:02 PM PDT 24
Finished May 28 01:17:10 PM PDT 24
Peak memory 199984 kb
Host smart-cdde3c1c-2fbe-4bed-a9aa-fdc46bbf97da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206706946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.206706946
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.3522156850
Short name T315
Test name
Test status
Simulation time 50417562737 ps
CPU time 768.96 seconds
Started May 28 01:17:20 PM PDT 24
Finished May 28 01:30:12 PM PDT 24
Peak memory 236512 kb
Host smart-c7ebc100-2d8e-4b03-986e-ee08466b97ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522156850 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.3522156850
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.1670366362
Short name T319
Test name
Test status
Simulation time 112661836 ps
CPU time 1.24 seconds
Started May 28 01:17:17 PM PDT 24
Finished May 28 01:17:21 PM PDT 24
Peak memory 199960 kb
Host smart-73690420-ec04-4be9-84b0-8c0d0d9063f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670366362 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.1670366362
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.3091219922
Short name T142
Test name
Test status
Simulation time 32445538273 ps
CPU time 494.22 seconds
Started May 28 01:17:16 PM PDT 24
Finished May 28 01:25:33 PM PDT 24
Peak memory 200104 kb
Host smart-53940087-dc7a-4398-ae7f-014626fdd904
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091219922 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.3091219922
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.3092098716
Short name T26
Test name
Test status
Simulation time 31093562048 ps
CPU time 106.56 seconds
Started May 28 01:17:17 PM PDT 24
Finished May 28 01:19:07 PM PDT 24
Peak memory 199992 kb
Host smart-3c507463-bb0b-4f93-9ea4-69b03d23c9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092098716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.3092098716
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3602362766
Short name T177
Test name
Test status
Simulation time 36470272 ps
CPU time 0.61 seconds
Started May 28 01:17:17 PM PDT 24
Finished May 28 01:17:21 PM PDT 24
Peak memory 196000 kb
Host smart-2f95f169-5179-4e71-9033-51befc0007e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602362766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3602362766
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1019679808
Short name T416
Test name
Test status
Simulation time 97583710 ps
CPU time 5.39 seconds
Started May 28 01:17:17 PM PDT 24
Finished May 28 01:17:25 PM PDT 24
Peak memory 200112 kb
Host smart-9c911139-a625-465c-98cb-c1697e72ee42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1019679808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1019679808
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1065396507
Short name T370
Test name
Test status
Simulation time 26750331991 ps
CPU time 33.68 seconds
Started May 28 01:17:16 PM PDT 24
Finished May 28 01:17:52 PM PDT 24
Peak memory 200104 kb
Host smart-ed5eadae-9995-4041-90e6-cf7d0d315d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065396507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1065396507
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.1650247988
Short name T109
Test name
Test status
Simulation time 3970628458 ps
CPU time 1156.54 seconds
Started May 28 01:17:16 PM PDT 24
Finished May 28 01:36:33 PM PDT 24
Peak memory 773624 kb
Host smart-63073101-05e0-4a85-9cf9-41c23e0f18ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1650247988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1650247988
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.2420343815
Short name T509
Test name
Test status
Simulation time 683496154 ps
CPU time 35.77 seconds
Started May 28 01:17:14 PM PDT 24
Finished May 28 01:17:51 PM PDT 24
Peak memory 200040 kb
Host smart-3a0927f5-304f-4e18-a6d3-b42980fbb1f1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420343815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2420343815
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.1040180457
Short name T312
Test name
Test status
Simulation time 979164618 ps
CPU time 57.46 seconds
Started May 28 01:17:18 PM PDT 24
Finished May 28 01:18:19 PM PDT 24
Peak memory 200092 kb
Host smart-d3baa9e2-75fb-4471-ab0e-6f2844cb8399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040180457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1040180457
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.3976326705
Short name T134
Test name
Test status
Simulation time 70344327 ps
CPU time 1.49 seconds
Started May 28 01:17:17 PM PDT 24
Finished May 28 01:17:22 PM PDT 24
Peak memory 200084 kb
Host smart-051a7435-a0c8-4710-91f7-80140e474211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976326705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.3976326705
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.3425848371
Short name T324
Test name
Test status
Simulation time 142354895398 ps
CPU time 874.85 seconds
Started May 28 01:17:21 PM PDT 24
Finished May 28 01:31:58 PM PDT 24
Peak memory 692084 kb
Host smart-4bb93552-2960-4ebf-8978-97a1941a1df0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425848371 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.3425848371
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.731318773
Short name T546
Test name
Test status
Simulation time 553764591 ps
CPU time 1.41 seconds
Started May 28 01:17:18 PM PDT 24
Finished May 28 01:17:23 PM PDT 24
Peak memory 199956 kb
Host smart-ab6759f8-d1d5-4089-9efc-3b95c1dcd432
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731318773 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_hmac_vectors.731318773
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.746339655
Short name T144
Test name
Test status
Simulation time 124060281741 ps
CPU time 501.14 seconds
Started May 28 01:17:17 PM PDT 24
Finished May 28 01:25:41 PM PDT 24
Peak memory 200092 kb
Host smart-7e8d2f7f-a66f-420c-ae5e-62f665e4996f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746339655 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.746339655
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.2304833875
Short name T379
Test name
Test status
Simulation time 22326654902 ps
CPU time 70.97 seconds
Started May 28 01:17:18 PM PDT 24
Finished May 28 01:18:33 PM PDT 24
Peak memory 200028 kb
Host smart-b38610da-b694-432b-811a-c06d64cc4d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304833875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.2304833875
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.637334009
Short name T318
Test name
Test status
Simulation time 36543834 ps
CPU time 0.59 seconds
Started May 28 01:17:16 PM PDT 24
Finished May 28 01:17:19 PM PDT 24
Peak memory 196612 kb
Host smart-3d489ab1-f7d8-4854-b3b1-dfd34ebf6469
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637334009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.637334009
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.414236266
Short name T573
Test name
Test status
Simulation time 55750532 ps
CPU time 2.53 seconds
Started May 28 01:17:15 PM PDT 24
Finished May 28 01:17:18 PM PDT 24
Peak memory 216252 kb
Host smart-9a105eef-0520-4552-959f-4612f467b821
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=414236266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.414236266
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.4043850049
Short name T18
Test name
Test status
Simulation time 464010583 ps
CPU time 12.96 seconds
Started May 28 01:17:17 PM PDT 24
Finished May 28 01:17:34 PM PDT 24
Peak memory 199932 kb
Host smart-1b0bd545-61fe-486b-a4b7-724c699ba596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043850049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.4043850049
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.391707428
Short name T396
Test name
Test status
Simulation time 13281675 ps
CPU time 0.75 seconds
Started May 28 01:17:16 PM PDT 24
Finished May 28 01:17:19 PM PDT 24
Peak memory 198116 kb
Host smart-cf71bfd0-915b-4751-8d93-c9c031bab8e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=391707428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.391707428
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.2894719118
Short name T77
Test name
Test status
Simulation time 837161903 ps
CPU time 50.18 seconds
Started May 28 01:17:16 PM PDT 24
Finished May 28 01:18:10 PM PDT 24
Peak memory 199924 kb
Host smart-cb8df23a-2e79-44f8-aab1-ef35e1100db1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894719118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2894719118
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.931007622
Short name T393
Test name
Test status
Simulation time 58938546160 ps
CPU time 83.66 seconds
Started May 28 01:17:17 PM PDT 24
Finished May 28 01:18:45 PM PDT 24
Peak memory 200124 kb
Host smart-17eabff6-2bd0-4c20-b237-2a32ae8bc3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931007622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.931007622
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1863813059
Short name T248
Test name
Test status
Simulation time 721869095 ps
CPU time 3.38 seconds
Started May 28 01:17:21 PM PDT 24
Finished May 28 01:17:26 PM PDT 24
Peak memory 200088 kb
Host smart-577274d4-7356-4346-9a9e-21d1220b27d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863813059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1863813059
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2702045503
Short name T259
Test name
Test status
Simulation time 110412768159 ps
CPU time 1670.1 seconds
Started May 28 01:17:17 PM PDT 24
Finished May 28 01:45:11 PM PDT 24
Peak memory 613028 kb
Host smart-f67c3800-9f27-4ea3-a82c-f9e0dd079884
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702045503 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2702045503
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.2414094376
Short name T579
Test name
Test status
Simulation time 274244515 ps
CPU time 1.39 seconds
Started May 28 01:17:16 PM PDT 24
Finished May 28 01:17:19 PM PDT 24
Peak memory 199972 kb
Host smart-35e59ace-aa8b-4a84-9bc6-f18d65191211
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414094376 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.2414094376
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.2353266111
Short name T294
Test name
Test status
Simulation time 83669848145 ps
CPU time 442.23 seconds
Started May 28 01:17:19 PM PDT 24
Finished May 28 01:24:45 PM PDT 24
Peak memory 200048 kb
Host smart-c1b1c484-27e9-49bf-a6e3-337026d5bf2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353266111 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.2353266111
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.3377390029
Short name T129
Test name
Test status
Simulation time 11532389400 ps
CPU time 55.31 seconds
Started May 28 01:17:18 PM PDT 24
Finished May 28 01:18:17 PM PDT 24
Peak memory 200180 kb
Host smart-0b7a1dd5-7cbe-4576-92cc-0a2a6571bab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377390029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3377390029
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3898241671
Short name T514
Test name
Test status
Simulation time 57767850 ps
CPU time 0.58 seconds
Started May 28 01:17:17 PM PDT 24
Finished May 28 01:17:22 PM PDT 24
Peak memory 195880 kb
Host smart-e9f51a99-54ad-477a-acf5-9ffe5ebb7d35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898241671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3898241671
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3538657445
Short name T174
Test name
Test status
Simulation time 591335644 ps
CPU time 28.97 seconds
Started May 28 01:17:17 PM PDT 24
Finished May 28 01:17:49 PM PDT 24
Peak memory 232812 kb
Host smart-c079679b-186d-49a5-9bf1-ceec69d6b33f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3538657445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3538657445
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1246473526
Short name T114
Test name
Test status
Simulation time 380637943 ps
CPU time 19.03 seconds
Started May 28 01:17:18 PM PDT 24
Finished May 28 01:17:41 PM PDT 24
Peak memory 199984 kb
Host smart-834c0478-3b7a-4525-9b94-a8f06f621c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246473526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1246473526
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.1645287354
Short name T460
Test name
Test status
Simulation time 5876196454 ps
CPU time 1618.76 seconds
Started May 28 01:17:17 PM PDT 24
Finished May 28 01:44:19 PM PDT 24
Peak memory 794296 kb
Host smart-87112dd8-d193-4a74-8315-a10fc6583b50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1645287354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1645287354
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1778808311
Short name T588
Test name
Test status
Simulation time 17185278436 ps
CPU time 61.77 seconds
Started May 28 01:17:17 PM PDT 24
Finished May 28 01:18:22 PM PDT 24
Peak memory 200104 kb
Host smart-1eeb3fec-3a35-4aaf-906e-a53325d69595
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778808311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1778808311
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3780794372
Short name T275
Test name
Test status
Simulation time 6651579879 ps
CPU time 91.22 seconds
Started May 28 01:17:17 PM PDT 24
Finished May 28 01:18:52 PM PDT 24
Peak memory 200104 kb
Host smart-bfa7dcf0-6dc2-4419-a800-353e1aad9f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780794372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3780794372
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1468471659
Short name T290
Test name
Test status
Simulation time 600214197 ps
CPU time 5.59 seconds
Started May 28 01:17:16 PM PDT 24
Finished May 28 01:17:25 PM PDT 24
Peak memory 199944 kb
Host smart-9eaa35ae-8a2a-4226-87db-51818e9872fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468471659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1468471659
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.895085846
Short name T353
Test name
Test status
Simulation time 206003431430 ps
CPU time 613.99 seconds
Started May 28 01:17:22 PM PDT 24
Finished May 28 01:27:37 PM PDT 24
Peak memory 200188 kb
Host smart-e5aef311-5f3b-4526-84d6-ef70a3855e5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895085846 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.895085846
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.259515045
Short name T418
Test name
Test status
Simulation time 167660720 ps
CPU time 1.06 seconds
Started May 28 01:17:18 PM PDT 24
Finished May 28 01:17:22 PM PDT 24
Peak memory 199964 kb
Host smart-88247d2f-7935-4027-9184-3764b7fec510
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259515045 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.hmac_test_hmac_vectors.259515045
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.414906127
Short name T334
Test name
Test status
Simulation time 72732380817 ps
CPU time 501.03 seconds
Started May 28 01:17:21 PM PDT 24
Finished May 28 01:25:44 PM PDT 24
Peak memory 200108 kb
Host smart-8cf2af97-cc4d-405a-8c67-e13c87e8bc00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414906127 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.414906127
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.382120133
Short name T138
Test name
Test status
Simulation time 3239449027 ps
CPU time 44.02 seconds
Started May 28 01:17:18 PM PDT 24
Finished May 28 01:18:06 PM PDT 24
Peak memory 200072 kb
Host smart-df93b8b1-cd2e-49d0-b4db-63c13b092195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382120133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.382120133
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3786036781
Short name T345
Test name
Test status
Simulation time 15016375 ps
CPU time 0.6 seconds
Started May 28 01:17:29 PM PDT 24
Finished May 28 01:17:32 PM PDT 24
Peak memory 195632 kb
Host smart-9858a21d-1ef6-4c83-bf55-15081a116f44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786036781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3786036781
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.743280212
Short name T316
Test name
Test status
Simulation time 3652431094 ps
CPU time 41.94 seconds
Started May 28 01:17:17 PM PDT 24
Finished May 28 01:18:03 PM PDT 24
Peak memory 209248 kb
Host smart-69d66e0f-feee-4baf-8878-12cd3f16f88f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=743280212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.743280212
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2069999265
Short name T203
Test name
Test status
Simulation time 4702007340 ps
CPU time 86.45 seconds
Started May 28 01:17:31 PM PDT 24
Finished May 28 01:19:00 PM PDT 24
Peak memory 200156 kb
Host smart-42830884-4b52-48d3-aa31-d58eaaa6c5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069999265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2069999265
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3463235113
Short name T570
Test name
Test status
Simulation time 2152514026 ps
CPU time 589.67 seconds
Started May 28 01:17:29 PM PDT 24
Finished May 28 01:27:21 PM PDT 24
Peak memory 704596 kb
Host smart-ab636354-1093-4cf6-8e10-4ece93bc230e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3463235113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3463235113
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.2773604183
Short name T503
Test name
Test status
Simulation time 19779049449 ps
CPU time 62.41 seconds
Started May 28 01:17:32 PM PDT 24
Finished May 28 01:18:37 PM PDT 24
Peak memory 199964 kb
Host smart-3982ec25-8fb9-46d4-aae6-6162ccf9be15
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773604183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2773604183
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3901309180
Short name T375
Test name
Test status
Simulation time 19966888 ps
CPU time 0.88 seconds
Started May 28 01:17:20 PM PDT 24
Finished May 28 01:17:24 PM PDT 24
Peak memory 198952 kb
Host smart-ed2d5e64-6c9e-4870-b772-f2a9fe8e8720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901309180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3901309180
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2956799531
Short name T432
Test name
Test status
Simulation time 96323454 ps
CPU time 3.39 seconds
Started May 28 01:17:17 PM PDT 24
Finished May 28 01:17:24 PM PDT 24
Peak memory 199984 kb
Host smart-064e2560-8245-48dd-89a5-522b9590301e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956799531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2956799531
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3591283543
Short name T40
Test name
Test status
Simulation time 127772683 ps
CPU time 1.67 seconds
Started May 28 01:17:32 PM PDT 24
Finished May 28 01:17:36 PM PDT 24
Peak memory 200104 kb
Host smart-0bd2019e-583e-412a-b19e-4eb7431578a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591283543 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3591283543
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.1363354707
Short name T563
Test name
Test status
Simulation time 180414601 ps
CPU time 1.1 seconds
Started May 28 01:17:29 PM PDT 24
Finished May 28 01:17:33 PM PDT 24
Peak memory 199856 kb
Host smart-1d18a886-28d8-4261-b348-186650fd791a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363354707 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.1363354707
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.1920257664
Short name T408
Test name
Test status
Simulation time 62182107988 ps
CPU time 565.25 seconds
Started May 28 01:17:27 PM PDT 24
Finished May 28 01:26:54 PM PDT 24
Peak memory 200132 kb
Host smart-97ed210a-39bb-481e-a110-0d2bc59eea10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920257664 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.1920257664
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.857212409
Short name T260
Test name
Test status
Simulation time 1559986268 ps
CPU time 79.32 seconds
Started May 28 01:17:31 PM PDT 24
Finished May 28 01:18:53 PM PDT 24
Peak memory 200064 kb
Host smart-1be57c7b-a5c4-433a-91fc-008837e1b564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857212409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.857212409
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3540767320
Short name T239
Test name
Test status
Simulation time 13935421 ps
CPU time 0.62 seconds
Started May 28 01:17:29 PM PDT 24
Finished May 28 01:17:32 PM PDT 24
Peak memory 195624 kb
Host smart-8f0732c6-b3ba-4475-98e2-12412afe8087
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540767320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3540767320
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.266595404
Short name T46
Test name
Test status
Simulation time 235867701 ps
CPU time 11.56 seconds
Started May 28 01:17:29 PM PDT 24
Finished May 28 01:17:43 PM PDT 24
Peak memory 208248 kb
Host smart-a5ec6629-f292-423a-865d-140dab5f6d17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=266595404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.266595404
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.162656198
Short name T352
Test name
Test status
Simulation time 1293585880 ps
CPU time 35.75 seconds
Started May 28 01:17:33 PM PDT 24
Finished May 28 01:18:11 PM PDT 24
Peak memory 200112 kb
Host smart-1a20a7ff-ce98-4440-a3cb-1ed026bd2a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162656198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.162656198
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3081297177
Short name T497
Test name
Test status
Simulation time 4096047530 ps
CPU time 428.1 seconds
Started May 28 01:17:32 PM PDT 24
Finished May 28 01:24:43 PM PDT 24
Peak memory 670984 kb
Host smart-ab709556-2bfe-41ce-b4e9-bbf0cc9d491a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3081297177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3081297177
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2850288365
Short name T84
Test name
Test status
Simulation time 1033896218 ps
CPU time 59.53 seconds
Started May 28 01:17:29 PM PDT 24
Finished May 28 01:18:30 PM PDT 24
Peak memory 200036 kb
Host smart-a1ea0d80-65e0-4f87-84cd-b9c94f498186
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850288365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2850288365
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3304508500
Short name T390
Test name
Test status
Simulation time 11568066822 ps
CPU time 62.54 seconds
Started May 28 01:17:27 PM PDT 24
Finished May 28 01:18:30 PM PDT 24
Peak memory 199996 kb
Host smart-a25c6b8f-9cd9-44f7-9e66-78aec88b6096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304508500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3304508500
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.1422052234
Short name T438
Test name
Test status
Simulation time 172993517 ps
CPU time 6.17 seconds
Started May 28 01:17:33 PM PDT 24
Finished May 28 01:17:41 PM PDT 24
Peak memory 200092 kb
Host smart-a934bea8-1832-40c6-bb95-281416179b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422052234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1422052234
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.4073259453
Short name T362
Test name
Test status
Simulation time 23502815534 ps
CPU time 2233.61 seconds
Started May 28 01:17:28 PM PDT 24
Finished May 28 01:54:44 PM PDT 24
Peak memory 652652 kb
Host smart-2946dde9-b46d-446d-9d61-10f6acbfe787
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073259453 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.4073259453
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.1848966178
Short name T176
Test name
Test status
Simulation time 100281830 ps
CPU time 1.05 seconds
Started May 28 01:17:30 PM PDT 24
Finished May 28 01:17:34 PM PDT 24
Peak memory 199856 kb
Host smart-ae30aa57-90cd-4aad-8c1f-f1a7ca6c4249
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848966178 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.1848966178
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.3978595354
Short name T387
Test name
Test status
Simulation time 31409367473 ps
CPU time 558.65 seconds
Started May 28 01:17:31 PM PDT 24
Finished May 28 01:26:53 PM PDT 24
Peak memory 199764 kb
Host smart-414de96c-983e-4787-a995-fac84e4b1c47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978595354 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.3978595354
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1427708787
Short name T189
Test name
Test status
Simulation time 1666045711 ps
CPU time 26.01 seconds
Started May 28 01:17:29 PM PDT 24
Finished May 28 01:17:58 PM PDT 24
Peak memory 200052 kb
Host smart-682869e1-ae5a-419b-a593-b6125d3fce82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427708787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1427708787
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.1836564424
Short name T355
Test name
Test status
Simulation time 12793206 ps
CPU time 0.56 seconds
Started May 28 01:17:31 PM PDT 24
Finished May 28 01:17:34 PM PDT 24
Peak memory 195836 kb
Host smart-599a74e5-1d29-4f1d-aaeb-49f6693cc1de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836564424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.1836564424
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1095550229
Short name T381
Test name
Test status
Simulation time 1065785099 ps
CPU time 12.46 seconds
Started May 28 01:17:24 PM PDT 24
Finished May 28 01:17:37 PM PDT 24
Peak memory 208228 kb
Host smart-826e4d0b-4251-4bd7-90d8-854c76d0144a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1095550229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1095550229
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.2082786196
Short name T331
Test name
Test status
Simulation time 735475178 ps
CPU time 18.65 seconds
Started May 28 01:17:29 PM PDT 24
Finished May 28 01:17:50 PM PDT 24
Peak memory 199972 kb
Host smart-3bba25d3-2ee1-443b-80a6-287244247a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082786196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2082786196
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2758995883
Short name T211
Test name
Test status
Simulation time 3483613311 ps
CPU time 963.18 seconds
Started May 28 01:17:31 PM PDT 24
Finished May 28 01:33:37 PM PDT 24
Peak memory 709960 kb
Host smart-c8d4941e-fc1e-49cb-ada7-2cec0ed98e7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2758995883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2758995883
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.4198726174
Short name T289
Test name
Test status
Simulation time 1958005382 ps
CPU time 26.77 seconds
Started May 28 01:17:31 PM PDT 24
Finished May 28 01:18:01 PM PDT 24
Peak memory 200012 kb
Host smart-c06a67bb-3a55-491d-a845-d8c46ca1de56
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198726174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.4198726174
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3585178239
Short name T311
Test name
Test status
Simulation time 8629432109 ps
CPU time 134.26 seconds
Started May 28 01:17:30 PM PDT 24
Finished May 28 01:19:46 PM PDT 24
Peak memory 199836 kb
Host smart-e0b4e5ca-af5c-4d3f-aad2-8dbd11378e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585178239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3585178239
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.116354155
Short name T482
Test name
Test status
Simulation time 558682179 ps
CPU time 7.89 seconds
Started May 28 01:17:30 PM PDT 24
Finished May 28 01:17:40 PM PDT 24
Peak memory 199984 kb
Host smart-37750161-dc0e-4e4d-8422-dc5b54d6f84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116354155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.116354155
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.3699565402
Short name T286
Test name
Test status
Simulation time 48077498427 ps
CPU time 801.11 seconds
Started May 28 01:17:28 PM PDT 24
Finished May 28 01:30:50 PM PDT 24
Peak memory 650468 kb
Host smart-ddd37e89-52a5-4635-8949-1034383189d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699565402 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3699565402
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.3937965058
Short name T69
Test name
Test status
Simulation time 184172578 ps
CPU time 1.06 seconds
Started May 28 01:17:32 PM PDT 24
Finished May 28 01:17:35 PM PDT 24
Peak memory 199572 kb
Host smart-a0ec75c7-4e52-4b60-bc87-5653d180d406
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937965058 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.3937965058
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.3003096193
Short name T201
Test name
Test status
Simulation time 34829661714 ps
CPU time 478.26 seconds
Started May 28 01:17:28 PM PDT 24
Finished May 28 01:25:28 PM PDT 24
Peak memory 200152 kb
Host smart-8472bb7b-45cd-4969-ad54-eab10d6a3138
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003096193 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.3003096193
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.836333197
Short name T470
Test name
Test status
Simulation time 1251996443 ps
CPU time 19.1 seconds
Started May 28 01:17:32 PM PDT 24
Finished May 28 01:17:54 PM PDT 24
Peak memory 200068 kb
Host smart-c13dad17-b295-4f4f-8dac-75fbde5a3449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836333197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.836333197
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.1003530381
Short name T254
Test name
Test status
Simulation time 14289896 ps
CPU time 0.61 seconds
Started May 28 01:17:40 PM PDT 24
Finished May 28 01:17:43 PM PDT 24
Peak memory 196612 kb
Host smart-5be76207-62c1-489d-8561-9dbffabe9f6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003530381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1003530381
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.794669720
Short name T541
Test name
Test status
Simulation time 420999124 ps
CPU time 18.71 seconds
Started May 28 01:17:43 PM PDT 24
Finished May 28 01:18:04 PM PDT 24
Peak memory 208220 kb
Host smart-c6d93dc4-8bfd-466a-a612-5542d91f4f5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=794669720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.794669720
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3693187050
Short name T147
Test name
Test status
Simulation time 970875632 ps
CPU time 49.41 seconds
Started May 28 01:17:41 PM PDT 24
Finished May 28 01:18:32 PM PDT 24
Peak memory 200112 kb
Host smart-12f9ce63-7a3a-4fd5-8443-c4591023fe34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693187050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3693187050
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.873700496
Short name T293
Test name
Test status
Simulation time 19885294115 ps
CPU time 669.24 seconds
Started May 28 01:17:45 PM PDT 24
Finished May 28 01:28:57 PM PDT 24
Peak memory 747588 kb
Host smart-3aac1f2a-97c3-4eb8-98e6-9a51c793f595
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=873700496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.873700496
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.4048973593
Short name T586
Test name
Test status
Simulation time 33707599610 ps
CPU time 122.05 seconds
Started May 28 01:17:37 PM PDT 24
Finished May 28 01:19:40 PM PDT 24
Peak memory 200088 kb
Host smart-40eea09e-06c6-4666-9aca-c1f84f4a18c9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048973593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.4048973593
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1977257927
Short name T420
Test name
Test status
Simulation time 2061455536 ps
CPU time 31.33 seconds
Started May 28 01:17:31 PM PDT 24
Finished May 28 01:18:05 PM PDT 24
Peak memory 199988 kb
Host smart-f170bce2-25f4-41dc-b578-4bf20c41422a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977257927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1977257927
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1598524701
Short name T593
Test name
Test status
Simulation time 347169474 ps
CPU time 6.76 seconds
Started May 28 01:17:30 PM PDT 24
Finished May 28 01:17:39 PM PDT 24
Peak memory 199856 kb
Host smart-43691b2f-1b91-46ed-8a89-0a9593595391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598524701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1598524701
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.617540286
Short name T535
Test name
Test status
Simulation time 112041189854 ps
CPU time 2010.81 seconds
Started May 28 01:17:44 PM PDT 24
Finished May 28 01:51:17 PM PDT 24
Peak memory 629744 kb
Host smart-a682d052-293b-4121-9c2b-256f78efa7a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617540286 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.617540286
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.3447804069
Short name T524
Test name
Test status
Simulation time 52953207 ps
CPU time 1.21 seconds
Started May 28 01:17:41 PM PDT 24
Finished May 28 01:17:45 PM PDT 24
Peak memory 200088 kb
Host smart-77e553dd-b11a-4038-b34c-7e6b8e44e0f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447804069 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.3447804069
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.3232314365
Short name T285
Test name
Test status
Simulation time 8493689188 ps
CPU time 474.67 seconds
Started May 28 01:17:43 PM PDT 24
Finished May 28 01:25:41 PM PDT 24
Peak memory 200104 kb
Host smart-29b99148-0e30-4d16-ae79-7f207fed908b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232314365 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.3232314365
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.4099798192
Short name T526
Test name
Test status
Simulation time 1350309131 ps
CPU time 49.08 seconds
Started May 28 01:17:43 PM PDT 24
Finished May 28 01:18:35 PM PDT 24
Peak memory 200016 kb
Host smart-1b394ba6-b3cc-4c03-8f02-f891dba4b126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099798192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.4099798192
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.3380695724
Short name T354
Test name
Test status
Simulation time 13913898 ps
CPU time 0.63 seconds
Started May 28 01:17:40 PM PDT 24
Finished May 28 01:17:43 PM PDT 24
Peak memory 195620 kb
Host smart-36f285be-a5ba-475d-8e47-b23c54f13ac5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380695724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3380695724
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.220902228
Short name T444
Test name
Test status
Simulation time 773782649 ps
CPU time 30.06 seconds
Started May 28 01:17:45 PM PDT 24
Finished May 28 01:18:17 PM PDT 24
Peak memory 228800 kb
Host smart-5639b52a-9120-4f12-b669-876f42db4ad0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=220902228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.220902228
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3014674157
Short name T518
Test name
Test status
Simulation time 2273069699 ps
CPU time 18.88 seconds
Started May 28 01:17:43 PM PDT 24
Finished May 28 01:18:04 PM PDT 24
Peak memory 200028 kb
Host smart-7c603e02-cf44-4b6b-87b7-29e71a4e42b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014674157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3014674157
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2985435583
Short name T86
Test name
Test status
Simulation time 20360252371 ps
CPU time 1347.14 seconds
Started May 28 01:17:47 PM PDT 24
Finished May 28 01:40:16 PM PDT 24
Peak memory 730720 kb
Host smart-7d9716e1-68bc-4b09-ad26-6750bfbaf3e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2985435583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2985435583
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.2246732020
Short name T85
Test name
Test status
Simulation time 11511941610 ps
CPU time 160.11 seconds
Started May 28 01:17:40 PM PDT 24
Finished May 28 01:20:22 PM PDT 24
Peak memory 200168 kb
Host smart-114d4115-31d1-4dc3-bbdd-333b1c9b3c70
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246732020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.2246732020
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1081428629
Short name T264
Test name
Test status
Simulation time 14610858605 ps
CPU time 64.16 seconds
Started May 28 01:17:41 PM PDT 24
Finished May 28 01:18:48 PM PDT 24
Peak memory 200156 kb
Host smart-14548686-3553-4f7c-b358-a941cd3c7709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081428629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1081428629
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3923577426
Short name T190
Test name
Test status
Simulation time 162235142 ps
CPU time 2.9 seconds
Started May 28 01:17:41 PM PDT 24
Finished May 28 01:17:47 PM PDT 24
Peak memory 200076 kb
Host smart-0ce3ab64-de33-4377-bfc1-922986afe8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923577426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3923577426
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.2392389346
Short name T276
Test name
Test status
Simulation time 228424832 ps
CPU time 2.84 seconds
Started May 28 01:17:47 PM PDT 24
Finished May 28 01:17:52 PM PDT 24
Peak memory 199952 kb
Host smart-7633c546-efa9-439b-b23e-bbbb54fc25c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392389346 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2392389346
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.1572913045
Short name T451
Test name
Test status
Simulation time 173753852 ps
CPU time 1.44 seconds
Started May 28 01:17:41 PM PDT 24
Finished May 28 01:17:45 PM PDT 24
Peak memory 200308 kb
Host smart-35789b32-ebb9-42b0-9ed1-bcaa0e652525
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572913045 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.1572913045
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.3285243948
Short name T136
Test name
Test status
Simulation time 7005175193 ps
CPU time 393.43 seconds
Started May 28 01:17:42 PM PDT 24
Finished May 28 01:24:18 PM PDT 24
Peak memory 200084 kb
Host smart-2b980038-3b05-4f11-b5af-5b3be3c5f85a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285243948 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.3285243948
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.2411745847
Short name T594
Test name
Test status
Simulation time 3729298864 ps
CPU time 73.6 seconds
Started May 28 01:17:41 PM PDT 24
Finished May 28 01:18:57 PM PDT 24
Peak memory 200124 kb
Host smart-a8352cda-07e6-435c-ba9f-0a15f4e99bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411745847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2411745847
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3720637761
Short name T409
Test name
Test status
Simulation time 14597909 ps
CPU time 0.58 seconds
Started May 28 01:15:37 PM PDT 24
Finished May 28 01:15:39 PM PDT 24
Peak memory 194804 kb
Host smart-e809de13-9370-44a3-81e1-dd6aa480b2cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720637761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3720637761
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.96581228
Short name T495
Test name
Test status
Simulation time 3534189126 ps
CPU time 41.83 seconds
Started May 28 01:15:34 PM PDT 24
Finished May 28 01:16:18 PM PDT 24
Peak memory 215504 kb
Host smart-8f6917b5-e946-4c25-b582-91ebbdcd435f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=96581228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.96581228
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2983032709
Short name T166
Test name
Test status
Simulation time 5460766660 ps
CPU time 44.61 seconds
Started May 28 01:15:36 PM PDT 24
Finished May 28 01:16:23 PM PDT 24
Peak memory 200056 kb
Host smart-9bef25e1-8aa5-4927-9581-4c689553967e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983032709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2983032709
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.748896992
Short name T550
Test name
Test status
Simulation time 55438703 ps
CPU time 0.82 seconds
Started May 28 01:15:36 PM PDT 24
Finished May 28 01:15:39 PM PDT 24
Peak memory 200008 kb
Host smart-9e59a54d-89ec-45eb-b94e-e06200daebf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=748896992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.748896992
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.3746622653
Short name T373
Test name
Test status
Simulation time 4916665088 ps
CPU time 69.15 seconds
Started May 28 01:15:36 PM PDT 24
Finished May 28 01:16:47 PM PDT 24
Peak memory 200168 kb
Host smart-b0dc43a7-7c84-44de-89c9-3adf2453431d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746622653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3746622653
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.967858740
Short name T500
Test name
Test status
Simulation time 7147782410 ps
CPU time 36.02 seconds
Started May 28 01:15:34 PM PDT 24
Finished May 28 01:16:12 PM PDT 24
Peak memory 200204 kb
Host smart-2845780d-2fa2-48ab-b249-d542b526d3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967858740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.967858740
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2526339872
Short name T28
Test name
Test status
Simulation time 635739204 ps
CPU time 0.79 seconds
Started May 28 01:15:34 PM PDT 24
Finished May 28 01:15:37 PM PDT 24
Peak memory 218168 kb
Host smart-956301b0-3d8f-45c1-a432-7c8627e08c0b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526339872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2526339872
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.147542052
Short name T536
Test name
Test status
Simulation time 197562150 ps
CPU time 6.72 seconds
Started May 28 01:15:32 PM PDT 24
Finished May 28 01:15:40 PM PDT 24
Peak memory 199992 kb
Host smart-cdaedc54-d5a9-4480-80d5-bf5fde040dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147542052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.147542052
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.3153189196
Short name T377
Test name
Test status
Simulation time 84813584959 ps
CPU time 305.36 seconds
Started May 28 01:15:34 PM PDT 24
Finished May 28 01:20:42 PM PDT 24
Peak memory 452696 kb
Host smart-7e36e4cb-531b-4ef4-bc67-b787fb27d2a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153189196 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.3153189196
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.3484018117
Short name T478
Test name
Test status
Simulation time 36889996 ps
CPU time 1.31 seconds
Started May 28 01:15:33 PM PDT 24
Finished May 28 01:15:35 PM PDT 24
Peak memory 200124 kb
Host smart-5fe8c02d-8c2d-4187-9680-096a20fde10a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484018117 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.3484018117
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.2748215807
Short name T185
Test name
Test status
Simulation time 26837929317 ps
CPU time 497.7 seconds
Started May 28 01:15:36 PM PDT 24
Finished May 28 01:23:56 PM PDT 24
Peak memory 199980 kb
Host smart-b1f9ce38-c46b-4878-b73c-4caa8517fd9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748215807 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.2748215807
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.34766163
Short name T487
Test name
Test status
Simulation time 4893985425 ps
CPU time 40.79 seconds
Started May 28 01:15:35 PM PDT 24
Finished May 28 01:16:18 PM PDT 24
Peak memory 200176 kb
Host smart-3e441d69-fba8-4ea6-b838-9fbfb36b5a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34766163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.34766163
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.623243023
Short name T255
Test name
Test status
Simulation time 29144076 ps
CPU time 0.56 seconds
Started May 28 01:17:40 PM PDT 24
Finished May 28 01:17:43 PM PDT 24
Peak memory 194920 kb
Host smart-0b4f14e2-158f-4ab2-bc78-aeeab7369023
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623243023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.623243023
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.632819294
Short name T44
Test name
Test status
Simulation time 119060232 ps
CPU time 3.86 seconds
Started May 28 01:17:44 PM PDT 24
Finished May 28 01:17:50 PM PDT 24
Peak memory 208188 kb
Host smart-87951898-dbc8-4e7e-b627-357b9e815366
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=632819294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.632819294
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2913460235
Short name T372
Test name
Test status
Simulation time 18485185506 ps
CPU time 55.01 seconds
Started May 28 01:17:45 PM PDT 24
Finished May 28 01:18:43 PM PDT 24
Peak memory 200032 kb
Host smart-73732956-decb-4a31-a3a8-e08d3c69c429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913460235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2913460235
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.186556931
Short name T452
Test name
Test status
Simulation time 18482932596 ps
CPU time 459.52 seconds
Started May 28 01:17:39 PM PDT 24
Finished May 28 01:25:20 PM PDT 24
Peak memory 671012 kb
Host smart-8202d33a-bc5e-4fae-b3cd-91c82f858578
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=186556931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.186556931
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.259698548
Short name T148
Test name
Test status
Simulation time 2512333028 ps
CPU time 145.04 seconds
Started May 28 01:17:43 PM PDT 24
Finished May 28 01:20:11 PM PDT 24
Peak memory 200120 kb
Host smart-d85de235-7c1d-485c-b288-93d6c304b85c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259698548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.259698548
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.1359938043
Short name T461
Test name
Test status
Simulation time 2331424404 ps
CPU time 32.51 seconds
Started May 28 01:17:44 PM PDT 24
Finished May 28 01:18:19 PM PDT 24
Peak memory 200156 kb
Host smart-5b829d59-147a-4786-99b1-2bbd19faf406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359938043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1359938043
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2076527264
Short name T340
Test name
Test status
Simulation time 630399532 ps
CPU time 6.08 seconds
Started May 28 01:17:47 PM PDT 24
Finished May 28 01:17:55 PM PDT 24
Peak memory 200028 kb
Host smart-1ea4ae48-c2bc-4d46-a320-7d7f8714e204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076527264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2076527264
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.179392653
Short name T214
Test name
Test status
Simulation time 34578953087 ps
CPU time 679.46 seconds
Started May 28 01:17:44 PM PDT 24
Finished May 28 01:29:06 PM PDT 24
Peak memory 200140 kb
Host smart-055aea80-0f72-4645-8aff-699e4f431825
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179392653 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.179392653
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.906097087
Short name T469
Test name
Test status
Simulation time 56983334 ps
CPU time 1.08 seconds
Started May 28 01:17:44 PM PDT 24
Finished May 28 01:17:47 PM PDT 24
Peak memory 199556 kb
Host smart-6732ac59-90f2-491b-b243-e03334ac0074
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906097087 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_hmac_vectors.906097087
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.3322598944
Short name T181
Test name
Test status
Simulation time 40232491852 ps
CPU time 460.58 seconds
Started May 28 01:17:43 PM PDT 24
Finished May 28 01:25:26 PM PDT 24
Peak memory 200052 kb
Host smart-c96cc8a2-a1ff-4feb-b6bd-eeee4d271d1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322598944 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.3322598944
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2063531509
Short name T199
Test name
Test status
Simulation time 7419919936 ps
CPU time 81.27 seconds
Started May 28 01:17:43 PM PDT 24
Finished May 28 01:19:07 PM PDT 24
Peak memory 199972 kb
Host smart-ea7581a3-b27d-47b9-ab2b-e37a25b3c338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063531509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2063531509
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.3656280126
Short name T494
Test name
Test status
Simulation time 153162220 ps
CPU time 0.6 seconds
Started May 28 01:17:54 PM PDT 24
Finished May 28 01:17:55 PM PDT 24
Peak memory 196000 kb
Host smart-93fea620-cbd8-48e4-9f38-57ae6d40a6cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656280126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3656280126
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.681195361
Short name T368
Test name
Test status
Simulation time 603386156 ps
CPU time 29.18 seconds
Started May 28 01:17:46 PM PDT 24
Finished May 28 01:18:18 PM PDT 24
Peak memory 218396 kb
Host smart-bc791bca-837b-4423-aa45-5ce65a6fa196
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=681195361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.681195361
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2990910583
Short name T304
Test name
Test status
Simulation time 22779239221 ps
CPU time 55.34 seconds
Started May 28 01:17:47 PM PDT 24
Finished May 28 01:18:45 PM PDT 24
Peak memory 200100 kb
Host smart-29faed13-adfc-429e-88ca-b2541fe2588c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990910583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2990910583
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.426652848
Short name T6
Test name
Test status
Simulation time 5053474015 ps
CPU time 201.18 seconds
Started May 28 01:17:40 PM PDT 24
Finished May 28 01:21:04 PM PDT 24
Peak memory 475340 kb
Host smart-8d476b22-af95-41e3-9c06-5414eee22d99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=426652848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.426652848
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1809040683
Short name T51
Test name
Test status
Simulation time 1316919831 ps
CPU time 3.83 seconds
Started May 28 01:17:41 PM PDT 24
Finished May 28 01:17:47 PM PDT 24
Peak memory 200004 kb
Host smart-1f226699-1587-4751-b75d-e3f8ce41c2fb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809040683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1809040683
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.2076919718
Short name T170
Test name
Test status
Simulation time 3058163941 ps
CPU time 85.96 seconds
Started May 28 01:17:44 PM PDT 24
Finished May 28 01:19:13 PM PDT 24
Peak memory 200024 kb
Host smart-65791af1-e00a-4a12-9489-089702fd8c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076919718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.2076919718
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.418856129
Short name T227
Test name
Test status
Simulation time 59002944 ps
CPU time 1.09 seconds
Started May 28 01:17:46 PM PDT 24
Finished May 28 01:17:50 PM PDT 24
Peak memory 199048 kb
Host smart-8c271620-50ff-4620-bf91-40fdf1238bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418856129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.418856129
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.2082972493
Short name T350
Test name
Test status
Simulation time 61961608306 ps
CPU time 1313.84 seconds
Started May 28 01:17:54 PM PDT 24
Finished May 28 01:39:49 PM PDT 24
Peak memory 726300 kb
Host smart-66dd01de-738e-423c-94e6-136a12ee938c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082972493 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2082972493
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.1347372302
Short name T321
Test name
Test status
Simulation time 49779642 ps
CPU time 1.07 seconds
Started May 28 01:17:59 PM PDT 24
Finished May 28 01:18:01 PM PDT 24
Peak memory 200016 kb
Host smart-bff37b1a-5844-4e68-b480-d073efb3884f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347372302 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.1347372302
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.35647353
Short name T439
Test name
Test status
Simulation time 106119914352 ps
CPU time 505.48 seconds
Started May 28 01:17:41 PM PDT 24
Finished May 28 01:26:09 PM PDT 24
Peak memory 200108 kb
Host smart-8b807098-38aa-4b81-9350-39bc0918f3bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35647353 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.35647353
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.1738298751
Short name T216
Test name
Test status
Simulation time 2501423677 ps
CPU time 51.26 seconds
Started May 28 01:17:44 PM PDT 24
Finished May 28 01:18:38 PM PDT 24
Peak memory 200032 kb
Host smart-57ac9977-d68b-45ad-b708-74ca490f975d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738298751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1738298751
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1238166960
Short name T256
Test name
Test status
Simulation time 48717952 ps
CPU time 0.63 seconds
Started May 28 01:18:00 PM PDT 24
Finished May 28 01:18:01 PM PDT 24
Peak memory 195876 kb
Host smart-7a6f5f4f-7be3-4f05-8f90-5388b931c990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238166960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1238166960
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1310250361
Short name T309
Test name
Test status
Simulation time 4188843347 ps
CPU time 52.57 seconds
Started May 28 01:18:00 PM PDT 24
Finished May 28 01:18:54 PM PDT 24
Peak memory 224760 kb
Host smart-1ebbef16-d2b3-4647-a870-f5a91ad4e187
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1310250361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1310250361
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2889892529
Short name T527
Test name
Test status
Simulation time 627830974 ps
CPU time 30.71 seconds
Started May 28 01:17:55 PM PDT 24
Finished May 28 01:18:27 PM PDT 24
Peak memory 199792 kb
Host smart-0fcb316e-a601-4755-b7a5-c1f25435999f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889892529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2889892529
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.3579387296
Short name T284
Test name
Test status
Simulation time 1044266143 ps
CPU time 202.33 seconds
Started May 28 01:17:56 PM PDT 24
Finished May 28 01:21:20 PM PDT 24
Peak memory 442172 kb
Host smart-7704bc4f-f9ca-417d-8c88-1cd32608ca3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3579387296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3579387296
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2267502724
Short name T15
Test name
Test status
Simulation time 2915639947 ps
CPU time 84.64 seconds
Started May 28 01:17:55 PM PDT 24
Finished May 28 01:19:20 PM PDT 24
Peak memory 200064 kb
Host smart-f3a9fd32-15fd-496d-b9c1-21dcfe3230f0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267502724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2267502724
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3388883598
Short name T187
Test name
Test status
Simulation time 1175053501 ps
CPU time 64.63 seconds
Started May 28 01:17:55 PM PDT 24
Finished May 28 01:19:01 PM PDT 24
Peak memory 199784 kb
Host smart-9882245a-7b30-4a51-80f0-bdbee3cb40bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388883598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3388883598
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.4294458773
Short name T361
Test name
Test status
Simulation time 1935003512 ps
CPU time 11.81 seconds
Started May 28 01:17:55 PM PDT 24
Finished May 28 01:18:08 PM PDT 24
Peak memory 200092 kb
Host smart-fedaec1a-3859-482f-8cd2-65e7eafd2d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294458773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.4294458773
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.415419882
Short name T401
Test name
Test status
Simulation time 27911375472 ps
CPU time 145.63 seconds
Started May 28 01:17:55 PM PDT 24
Finished May 28 01:20:22 PM PDT 24
Peak memory 229796 kb
Host smart-ed715f8e-91a7-4d7e-ad5e-a318cfd7c05b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415419882 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.415419882
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.2719102237
Short name T339
Test name
Test status
Simulation time 446350744 ps
CPU time 1.21 seconds
Started May 28 01:17:54 PM PDT 24
Finished May 28 01:17:57 PM PDT 24
Peak memory 199836 kb
Host smart-d065c23b-58f7-4074-b147-c1c425753338
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719102237 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.2719102237
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.2595362721
Short name T66
Test name
Test status
Simulation time 116945846876 ps
CPU time 501.83 seconds
Started May 28 01:17:56 PM PDT 24
Finished May 28 01:26:20 PM PDT 24
Peak memory 200012 kb
Host smart-2f20cba8-4721-4b01-abcf-c7f9f121ac43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595362721 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.2595362721
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.2720962377
Short name T179
Test name
Test status
Simulation time 12568577768 ps
CPU time 77.03 seconds
Started May 28 01:17:58 PM PDT 24
Finished May 28 01:19:16 PM PDT 24
Peak memory 200112 kb
Host smart-dba2f1dd-3ed4-44cd-82fe-fb418750b2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720962377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2720962377
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1866062959
Short name T453
Test name
Test status
Simulation time 32064416 ps
CPU time 0.61 seconds
Started May 28 01:17:56 PM PDT 24
Finished May 28 01:17:58 PM PDT 24
Peak memory 195192 kb
Host smart-4bf39c0f-15d6-44b8-b61e-d806b62d62a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866062959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1866062959
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.618246247
Short name T105
Test name
Test status
Simulation time 2989741870 ps
CPU time 29.83 seconds
Started May 28 01:18:00 PM PDT 24
Finished May 28 01:18:31 PM PDT 24
Peak memory 224748 kb
Host smart-d5cca4b4-d837-4441-82e8-4b3bad7d8dda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=618246247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.618246247
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3720491369
Short name T481
Test name
Test status
Simulation time 1478059196 ps
CPU time 68.01 seconds
Started May 28 01:17:55 PM PDT 24
Finished May 28 01:19:05 PM PDT 24
Peak memory 199960 kb
Host smart-7f5bd2a0-e7cb-4c88-bf8d-6f3b33a77626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720491369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3720491369
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2083548098
Short name T484
Test name
Test status
Simulation time 11391528984 ps
CPU time 589.59 seconds
Started May 28 01:17:56 PM PDT 24
Finished May 28 01:27:47 PM PDT 24
Peak memory 692056 kb
Host smart-13a3c122-8a6c-4e63-81b0-87ac9701a2f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2083548098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2083548098
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.364479082
Short name T556
Test name
Test status
Simulation time 13909562943 ps
CPU time 134.89 seconds
Started May 28 01:18:00 PM PDT 24
Finished May 28 01:20:16 PM PDT 24
Peak memory 199980 kb
Host smart-186d65cf-9e6f-41c7-a31a-0be2094e2bcf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364479082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.364479082
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.2156273972
Short name T300
Test name
Test status
Simulation time 14152150647 ps
CPU time 73.41 seconds
Started May 28 01:17:56 PM PDT 24
Finished May 28 01:19:11 PM PDT 24
Peak memory 200016 kb
Host smart-53ad315a-a064-4845-beeb-f5d6ad8d8318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156273972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2156273972
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.595654407
Short name T180
Test name
Test status
Simulation time 94797660 ps
CPU time 1.6 seconds
Started May 28 01:17:56 PM PDT 24
Finished May 28 01:17:59 PM PDT 24
Peak memory 199296 kb
Host smart-f88a117d-b37c-4f9a-aa5b-cc7d8602fc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595654407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.595654407
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.2191224110
Short name T218
Test name
Test status
Simulation time 178735119191 ps
CPU time 2006.54 seconds
Started May 28 01:17:55 PM PDT 24
Finished May 28 01:51:23 PM PDT 24
Peak memory 721200 kb
Host smart-e68343dc-c940-4d94-bfd8-231abad06028
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191224110 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2191224110
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.3789117251
Short name T417
Test name
Test status
Simulation time 59091456 ps
CPU time 1.16 seconds
Started May 28 01:17:54 PM PDT 24
Finished May 28 01:17:56 PM PDT 24
Peak memory 200000 kb
Host smart-4cff0068-f5ab-428b-9066-08e85560983b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789117251 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.3789117251
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.2888274224
Short name T575
Test name
Test status
Simulation time 138192447547 ps
CPU time 480.35 seconds
Started May 28 01:17:55 PM PDT 24
Finished May 28 01:25:57 PM PDT 24
Peak memory 200076 kb
Host smart-588767d2-6dbb-4806-b20e-e80ba9a76c80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888274224 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.2888274224
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.530349728
Short name T317
Test name
Test status
Simulation time 13361579054 ps
CPU time 63.76 seconds
Started May 28 01:17:59 PM PDT 24
Finished May 28 01:19:04 PM PDT 24
Peak memory 200024 kb
Host smart-1824668e-88cc-4ab8-a0ce-608525870f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530349728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.530349728
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2851927285
Short name T549
Test name
Test status
Simulation time 34125242 ps
CPU time 0.59 seconds
Started May 28 01:18:07 PM PDT 24
Finished May 28 01:18:10 PM PDT 24
Peak memory 195964 kb
Host smart-5a776e86-ac9f-4031-af46-fc6f6c5a5f43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851927285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2851927285
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2296196230
Short name T422
Test name
Test status
Simulation time 541778231 ps
CPU time 7.33 seconds
Started May 28 01:17:57 PM PDT 24
Finished May 28 01:18:05 PM PDT 24
Peak memory 199884 kb
Host smart-852bfd3f-d450-4af0-aecb-1a6cc0f9a55b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2296196230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2296196230
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.2053236114
Short name T561
Test name
Test status
Simulation time 627956558 ps
CPU time 32.23 seconds
Started May 28 01:17:54 PM PDT 24
Finished May 28 01:18:27 PM PDT 24
Peak memory 200064 kb
Host smart-28df370b-0520-4992-be38-8e4a1adabea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053236114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2053236114
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.172794258
Short name T188
Test name
Test status
Simulation time 2602660532 ps
CPU time 318.73 seconds
Started May 28 01:17:55 PM PDT 24
Finished May 28 01:23:15 PM PDT 24
Peak memory 660792 kb
Host smart-bfa1fb1e-f777-4b27-ad18-2b15d4f7a8c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=172794258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.172794258
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1329174080
Short name T424
Test name
Test status
Simulation time 13324855596 ps
CPU time 170.55 seconds
Started May 28 01:17:55 PM PDT 24
Finished May 28 01:20:48 PM PDT 24
Peak memory 200020 kb
Host smart-c5f47a35-8f2a-42c2-8ead-8088044bd059
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329174080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1329174080
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2631766255
Short name T431
Test name
Test status
Simulation time 9901163188 ps
CPU time 58.61 seconds
Started May 28 01:17:54 PM PDT 24
Finished May 28 01:18:53 PM PDT 24
Peak memory 200044 kb
Host smart-7f114534-5a01-4487-9515-6a8cdcef4758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631766255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2631766255
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2032245593
Short name T235
Test name
Test status
Simulation time 380119256 ps
CPU time 6.75 seconds
Started May 28 01:17:54 PM PDT 24
Finished May 28 01:18:02 PM PDT 24
Peak memory 200320 kb
Host smart-7e1c4d6f-dea1-43c9-baea-2ffb8d544c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032245593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2032245593
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.1576108483
Short name T399
Test name
Test status
Simulation time 79073913392 ps
CPU time 1743.64 seconds
Started May 28 01:18:08 PM PDT 24
Finished May 28 01:47:14 PM PDT 24
Peak memory 760652 kb
Host smart-dd37f44e-8925-437a-bea0-7ce73fe3a3ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576108483 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1576108483
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.477137658
Short name T555
Test name
Test status
Simulation time 217557866 ps
CPU time 1.22 seconds
Started May 28 01:18:08 PM PDT 24
Finished May 28 01:18:11 PM PDT 24
Peak memory 200068 kb
Host smart-390281ee-0d30-4b57-9071-b59f6eb26621
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477137658 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.hmac_test_hmac_vectors.477137658
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.3962857937
Short name T261
Test name
Test status
Simulation time 117064967458 ps
CPU time 585.83 seconds
Started May 28 01:18:07 PM PDT 24
Finished May 28 01:27:56 PM PDT 24
Peak memory 199996 kb
Host smart-2a9d89f4-6462-4ab8-8067-75ca2834e1f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962857937 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.3962857937
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.3388206907
Short name T313
Test name
Test status
Simulation time 47635245888 ps
CPU time 51.56 seconds
Started May 28 01:18:07 PM PDT 24
Finished May 28 01:19:00 PM PDT 24
Peak memory 200060 kb
Host smart-127c443e-3bd7-4920-813a-feb856da63cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388206907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.3388206907
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.1219033967
Short name T288
Test name
Test status
Simulation time 14196806 ps
CPU time 0.54 seconds
Started May 28 01:18:05 PM PDT 24
Finished May 28 01:18:07 PM PDT 24
Peak memory 194812 kb
Host smart-5d90a925-6fa5-4646-a75f-302578184c2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219033967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1219033967
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.754175778
Short name T512
Test name
Test status
Simulation time 2742607615 ps
CPU time 33.27 seconds
Started May 28 01:18:10 PM PDT 24
Finished May 28 01:18:46 PM PDT 24
Peak memory 208180 kb
Host smart-b12934b5-6a52-4fd4-a7f2-dffd894b7524
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=754175778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.754175778
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2007760256
Short name T62
Test name
Test status
Simulation time 6869993844 ps
CPU time 38.78 seconds
Started May 28 01:18:08 PM PDT 24
Finished May 28 01:18:49 PM PDT 24
Peak memory 200104 kb
Host smart-6753ed09-91ef-43ba-b191-803deb549d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007760256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2007760256
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3029509519
Short name T193
Test name
Test status
Simulation time 12472220758 ps
CPU time 714.55 seconds
Started May 28 01:18:08 PM PDT 24
Finished May 28 01:30:05 PM PDT 24
Peak memory 730084 kb
Host smart-c917b626-4c99-437c-b17a-0aa18e173df0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3029509519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3029509519
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.2903395740
Short name T410
Test name
Test status
Simulation time 6087578537 ps
CPU time 26.48 seconds
Started May 28 01:18:08 PM PDT 24
Finished May 28 01:18:37 PM PDT 24
Peak memory 200360 kb
Host smart-85dd08a5-5f8c-4b46-bbef-ecc3243997a6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903395740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2903395740
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1563793102
Short name T280
Test name
Test status
Simulation time 22646909406 ps
CPU time 93.55 seconds
Started May 28 01:18:08 PM PDT 24
Finished May 28 01:19:44 PM PDT 24
Peak memory 200140 kb
Host smart-3a427f36-8be6-48f2-89c5-048962d16717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563793102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1563793102
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1333137455
Short name T522
Test name
Test status
Simulation time 40906378 ps
CPU time 1.49 seconds
Started May 28 01:18:14 PM PDT 24
Finished May 28 01:18:16 PM PDT 24
Peak memory 200092 kb
Host smart-682bff42-7102-4e47-8a37-988f727d99df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333137455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1333137455
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.1285924918
Short name T126
Test name
Test status
Simulation time 98320554 ps
CPU time 1.09 seconds
Started May 28 01:18:09 PM PDT 24
Finished May 28 01:18:13 PM PDT 24
Peak memory 200016 kb
Host smart-5e7cfbbf-16a8-4310-a40c-a3d010f1198a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285924918 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.1285924918
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.1165326930
Short name T63
Test name
Test status
Simulation time 35523864841 ps
CPU time 524.21 seconds
Started May 28 01:18:14 PM PDT 24
Finished May 28 01:26:59 PM PDT 24
Peak memory 200112 kb
Host smart-6dc50da0-a356-46b4-91b4-4ef1de8788ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165326930 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.1165326930
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3756980632
Short name T27
Test name
Test status
Simulation time 4703251792 ps
CPU time 46.06 seconds
Started May 28 01:18:09 PM PDT 24
Finished May 28 01:18:57 PM PDT 24
Peak memory 200132 kb
Host smart-1b3a7845-3d79-42c6-8ed7-b47b58d30d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756980632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3756980632
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.2059460082
Short name T592
Test name
Test status
Simulation time 25862973 ps
CPU time 0.57 seconds
Started May 28 01:18:06 PM PDT 24
Finished May 28 01:18:08 PM PDT 24
Peak memory 195944 kb
Host smart-0a1b9ecd-e6ad-4398-b72d-9f324b86a9c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059460082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2059460082
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.211308793
Short name T486
Test name
Test status
Simulation time 284144416 ps
CPU time 16.1 seconds
Started May 28 01:18:09 PM PDT 24
Finished May 28 01:18:28 PM PDT 24
Peak memory 199940 kb
Host smart-3157c4c3-cae9-481b-a606-e6da06ace677
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=211308793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.211308793
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1769345401
Short name T450
Test name
Test status
Simulation time 1938860448 ps
CPU time 55.74 seconds
Started May 28 01:18:10 PM PDT 24
Finished May 28 01:19:08 PM PDT 24
Peak memory 200036 kb
Host smart-94bbd460-4bc4-462c-a1d3-4ceca0bf6fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769345401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1769345401
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3567914619
Short name T197
Test name
Test status
Simulation time 4732569520 ps
CPU time 1154.74 seconds
Started May 28 01:18:07 PM PDT 24
Finished May 28 01:37:24 PM PDT 24
Peak memory 766792 kb
Host smart-4ef6af17-4e81-4ea4-8f86-e41c7ff1cc76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3567914619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3567914619
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.1141979864
Short name T326
Test name
Test status
Simulation time 28384540990 ps
CPU time 249.43 seconds
Started May 28 01:18:07 PM PDT 24
Finished May 28 01:22:19 PM PDT 24
Peak memory 199972 kb
Host smart-1158c819-2d81-491e-b4d4-04a4faf9dfbe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141979864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1141979864
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.308454973
Short name T145
Test name
Test status
Simulation time 1498062244 ps
CPU time 88.21 seconds
Started May 28 01:18:11 PM PDT 24
Finished May 28 01:19:41 PM PDT 24
Peak memory 200140 kb
Host smart-d03c6104-bdf1-4866-98f7-7948fb1c0a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308454973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.308454973
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.918366229
Short name T333
Test name
Test status
Simulation time 137065031 ps
CPU time 2.64 seconds
Started May 28 01:18:06 PM PDT 24
Finished May 28 01:18:09 PM PDT 24
Peak memory 200072 kb
Host smart-a90a8402-0161-43cc-800c-5a78d3ade7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918366229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.918366229
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1807563538
Short name T70
Test name
Test status
Simulation time 1328680029672 ps
CPU time 1728.23 seconds
Started May 28 01:18:11 PM PDT 24
Finished May 28 01:47:01 PM PDT 24
Peak memory 208292 kb
Host smart-c4392799-0f3a-42ee-82d6-6db9bea406c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807563538 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1807563538
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.2969185007
Short name T534
Test name
Test status
Simulation time 32664092 ps
CPU time 1.34 seconds
Started May 28 01:18:14 PM PDT 24
Finished May 28 01:18:16 PM PDT 24
Peak memory 199492 kb
Host smart-5e070cb7-e4d8-486f-a8b3-dbe36d37dfb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969185007 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.2969185007
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.3357588999
Short name T52
Test name
Test status
Simulation time 31993135594 ps
CPU time 457.88 seconds
Started May 28 01:18:07 PM PDT 24
Finished May 28 01:25:47 PM PDT 24
Peak memory 200044 kb
Host smart-b722781f-0498-4667-9645-89bd689a5766
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357588999 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.3357588999
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1967978847
Short name T165
Test name
Test status
Simulation time 469547234 ps
CPU time 18.55 seconds
Started May 28 01:18:08 PM PDT 24
Finished May 28 01:18:29 PM PDT 24
Peak memory 200064 kb
Host smart-0efdf7e4-1b44-4176-b35b-8e58d86db295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967978847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1967978847
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.978106348
Short name T240
Test name
Test status
Simulation time 15255748 ps
CPU time 0.6 seconds
Started May 28 01:18:08 PM PDT 24
Finished May 28 01:18:11 PM PDT 24
Peak memory 195984 kb
Host smart-3247c858-853f-44cd-afc6-ac52220e4692
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978106348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.978106348
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.3254908011
Short name T358
Test name
Test status
Simulation time 7060368886 ps
CPU time 53.11 seconds
Started May 28 01:18:05 PM PDT 24
Finished May 28 01:18:59 PM PDT 24
Peak memory 216844 kb
Host smart-fc7b154e-bcb0-4f69-8473-7562a9b0a6ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3254908011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3254908011
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1795687453
Short name T551
Test name
Test status
Simulation time 21986479041 ps
CPU time 64.28 seconds
Started May 28 01:18:08 PM PDT 24
Finished May 28 01:19:15 PM PDT 24
Peak memory 200156 kb
Host smart-2d9eca65-2aca-4756-ae7c-5aa75c7769c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795687453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1795687453
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.85978879
Short name T545
Test name
Test status
Simulation time 1068083527 ps
CPU time 27.22 seconds
Started May 28 01:18:10 PM PDT 24
Finished May 28 01:18:39 PM PDT 24
Peak memory 243628 kb
Host smart-72a694c7-d0f3-41e3-a956-08e2db116f5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=85978879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.85978879
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.592384653
Short name T330
Test name
Test status
Simulation time 2826397461 ps
CPU time 76.01 seconds
Started May 28 01:18:09 PM PDT 24
Finished May 28 01:19:28 PM PDT 24
Peak memory 200024 kb
Host smart-050c2671-f172-478d-8694-38de9fb9cb2c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592384653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.592384653
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1554206620
Short name T4
Test name
Test status
Simulation time 4994450028 ps
CPU time 69.34 seconds
Started May 28 01:18:08 PM PDT 24
Finished May 28 01:19:19 PM PDT 24
Peak memory 200156 kb
Host smart-0b87c856-037b-4e19-9f84-5a27694d5961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554206620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1554206620
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3795611042
Short name T574
Test name
Test status
Simulation time 760171628 ps
CPU time 1.04 seconds
Started May 28 01:18:06 PM PDT 24
Finished May 28 01:18:08 PM PDT 24
Peak memory 200084 kb
Host smart-4dc540bd-3614-4b2f-bfb1-372ee7563e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795611042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3795611042
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.876036896
Short name T217
Test name
Test status
Simulation time 2933120091 ps
CPU time 155.34 seconds
Started May 28 01:18:07 PM PDT 24
Finished May 28 01:20:45 PM PDT 24
Peak memory 241192 kb
Host smart-0d6ad744-28a8-424e-a99a-3de0073eb59c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876036896 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.876036896
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_stress_all_with_rand_reset.1872828792
Short name T60
Test name
Test status
Simulation time 211671422593 ps
CPU time 5117.19 seconds
Started May 28 01:18:14 PM PDT 24
Finished May 28 02:43:33 PM PDT 24
Peak memory 881496 kb
Host smart-db5069ab-ed53-488e-b069-9a5bdcc58be8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1872828792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all_with_rand_reset.1872828792
Directory /workspace/47.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.1372848127
Short name T403
Test name
Test status
Simulation time 49441047 ps
CPU time 1.13 seconds
Started May 28 01:18:10 PM PDT 24
Finished May 28 01:18:13 PM PDT 24
Peak memory 199852 kb
Host smart-84f3452b-411e-4b8e-8b74-90b2717a6c71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372848127 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.1372848127
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.2647720415
Short name T265
Test name
Test status
Simulation time 7120281318 ps
CPU time 414.03 seconds
Started May 28 01:18:14 PM PDT 24
Finished May 28 01:25:09 PM PDT 24
Peak memory 200068 kb
Host smart-223b1376-2682-4ce9-94ef-03d955b5efce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647720415 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.2647720415
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1453399067
Short name T477
Test name
Test status
Simulation time 5948989227 ps
CPU time 27.35 seconds
Started May 28 01:18:09 PM PDT 24
Finished May 28 01:18:39 PM PDT 24
Peak memory 200000 kb
Host smart-1d275e80-dae2-4395-9791-81db26a69858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453399067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1453399067
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1213943007
Short name T229
Test name
Test status
Simulation time 27319604 ps
CPU time 0.62 seconds
Started May 28 01:18:25 PM PDT 24
Finished May 28 01:18:27 PM PDT 24
Peak memory 194840 kb
Host smart-a4b58514-c333-42eb-a25d-30dc06967268
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213943007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1213943007
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.4103360924
Short name T423
Test name
Test status
Simulation time 961391569 ps
CPU time 10.8 seconds
Started May 28 01:18:09 PM PDT 24
Finished May 28 01:18:22 PM PDT 24
Peak memory 208216 kb
Host smart-59aa2c02-d93a-4c17-9666-9c63717ddbb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4103360924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.4103360924
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.1558064430
Short name T112
Test name
Test status
Simulation time 3042473124 ps
CPU time 44.11 seconds
Started May 28 01:18:08 PM PDT 24
Finished May 28 01:18:54 PM PDT 24
Peak memory 200168 kb
Host smart-eb49fe74-5727-46b7-89aa-55ea809fe2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558064430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.1558064430
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.1849925559
Short name T554
Test name
Test status
Simulation time 8374373618 ps
CPU time 329.13 seconds
Started May 28 01:18:07 PM PDT 24
Finished May 28 01:23:37 PM PDT 24
Peak memory 664536 kb
Host smart-d91dbee4-8afe-42ed-b4b3-d471dfe5ff3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1849925559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1849925559
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1871411143
Short name T237
Test name
Test status
Simulation time 59040364305 ps
CPU time 180.57 seconds
Started May 28 01:18:08 PM PDT 24
Finished May 28 01:21:11 PM PDT 24
Peak memory 200128 kb
Host smart-3e95e35f-fea1-46ae-81e2-4041fbcfd122
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871411143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1871411143
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.363816266
Short name T198
Test name
Test status
Simulation time 933277547 ps
CPU time 52.55 seconds
Started May 28 01:18:08 PM PDT 24
Finished May 28 01:19:03 PM PDT 24
Peak memory 199952 kb
Host smart-e2437c85-a233-4b9c-94a7-d9ead6ef9dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363816266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.363816266
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3035217330
Short name T552
Test name
Test status
Simulation time 856436801 ps
CPU time 5.23 seconds
Started May 28 01:18:08 PM PDT 24
Finished May 28 01:18:15 PM PDT 24
Peak memory 200112 kb
Host smart-b8aec3ba-e1f0-41e5-af3a-5bfec53d73ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035217330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3035217330
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2952285471
Short name T74
Test name
Test status
Simulation time 390784217737 ps
CPU time 1958.31 seconds
Started May 28 01:18:24 PM PDT 24
Finished May 28 01:51:04 PM PDT 24
Peak memory 670820 kb
Host smart-abe9e539-818c-4993-92ca-96c0728fcbdf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952285471 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2952285471
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.1431248410
Short name T230
Test name
Test status
Simulation time 314884862 ps
CPU time 1.31 seconds
Started May 28 01:18:24 PM PDT 24
Finished May 28 01:18:27 PM PDT 24
Peak memory 199332 kb
Host smart-3fc3c5c5-b345-4896-893d-a94dbd948e1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431248410 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.1431248410
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.2436934261
Short name T133
Test name
Test status
Simulation time 22751758906 ps
CPU time 409.59 seconds
Started May 28 01:18:10 PM PDT 24
Finished May 28 01:25:02 PM PDT 24
Peak memory 200000 kb
Host smart-e0b41a9c-4e90-4f2e-85a9-8417b270675a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436934261 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.2436934261
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3424937921
Short name T325
Test name
Test status
Simulation time 413387840 ps
CPU time 7.8 seconds
Started May 28 01:18:09 PM PDT 24
Finished May 28 01:18:19 PM PDT 24
Peak memory 199936 kb
Host smart-555c046b-f064-493e-908f-b31a428999e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424937921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3424937921
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3925702051
Short name T314
Test name
Test status
Simulation time 38874243 ps
CPU time 0.59 seconds
Started May 28 01:18:27 PM PDT 24
Finished May 28 01:18:29 PM PDT 24
Peak memory 194952 kb
Host smart-de649db0-129b-45b3-9f36-5a15cbefd32d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925702051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3925702051
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.970921602
Short name T506
Test name
Test status
Simulation time 435748941 ps
CPU time 4.48 seconds
Started May 28 01:18:24 PM PDT 24
Finished May 28 01:18:30 PM PDT 24
Peak memory 200068 kb
Host smart-9e37ae41-7147-4541-a4e6-4ce589bcc0d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=970921602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.970921602
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3400524176
Short name T152
Test name
Test status
Simulation time 987025455 ps
CPU time 53.77 seconds
Started May 28 01:18:24 PM PDT 24
Finished May 28 01:19:20 PM PDT 24
Peak memory 200032 kb
Host smart-80e03a79-c1f7-4d40-a09c-ec27bd697372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400524176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3400524176
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.663025620
Short name T456
Test name
Test status
Simulation time 1507474524 ps
CPU time 260.52 seconds
Started May 28 01:18:24 PM PDT 24
Finished May 28 01:22:46 PM PDT 24
Peak memory 445824 kb
Host smart-9b947c6c-4909-4b99-9385-eca3be4c4951
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=663025620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.663025620
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.1419719942
Short name T572
Test name
Test status
Simulation time 2294930634 ps
CPU time 127.34 seconds
Started May 28 01:18:24 PM PDT 24
Finished May 28 01:20:32 PM PDT 24
Peak memory 200068 kb
Host smart-a51512b0-e1f1-49c3-b16c-8b4b69646049
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419719942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1419719942
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.559311911
Short name T505
Test name
Test status
Simulation time 18617705424 ps
CPU time 66.17 seconds
Started May 28 01:18:24 PM PDT 24
Finished May 28 01:19:31 PM PDT 24
Peak memory 200132 kb
Host smart-d099f0c1-53d0-4bbe-871e-2a0650738f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559311911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.559311911
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3243781871
Short name T580
Test name
Test status
Simulation time 335437816 ps
CPU time 4.7 seconds
Started May 28 01:18:26 PM PDT 24
Finished May 28 01:18:32 PM PDT 24
Peak memory 200092 kb
Host smart-0675cf1d-af57-4129-af0f-f74e76b13be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243781871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3243781871
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.79260441
Short name T83
Test name
Test status
Simulation time 20726573885 ps
CPU time 1121.63 seconds
Started May 28 01:18:25 PM PDT 24
Finished May 28 01:37:08 PM PDT 24
Peak memory 232316 kb
Host smart-545be45a-b6d5-4518-820f-92170938ce78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79260441 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.79260441
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.2343830436
Short name T382
Test name
Test status
Simulation time 60599208 ps
CPU time 1.27 seconds
Started May 28 01:18:24 PM PDT 24
Finished May 28 01:18:27 PM PDT 24
Peak memory 200104 kb
Host smart-dd247b69-26bd-45f5-a36c-bc8f3ee35bfb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343830436 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.2343830436
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.2157127707
Short name T79
Test name
Test status
Simulation time 7736911924 ps
CPU time 438.31 seconds
Started May 28 01:18:24 PM PDT 24
Finished May 28 01:25:44 PM PDT 24
Peak memory 200104 kb
Host smart-ec685f26-c20f-4e12-bb24-67ac7840c8c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157127707 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.2157127707
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.945109312
Short name T590
Test name
Test status
Simulation time 1726477650 ps
CPU time 57.87 seconds
Started May 28 01:18:24 PM PDT 24
Finished May 28 01:19:23 PM PDT 24
Peak memory 200008 kb
Host smart-4a037dd4-568f-446c-ba0b-406fd6c06118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945109312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.945109312
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.460909557
Short name T485
Test name
Test status
Simulation time 109299934 ps
CPU time 0.59 seconds
Started May 28 01:15:34 PM PDT 24
Finished May 28 01:15:37 PM PDT 24
Peak memory 195988 kb
Host smart-f25562f1-09e9-45a4-ab2d-ca726c9f53f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460909557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.460909557
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1705002578
Short name T547
Test name
Test status
Simulation time 627419501 ps
CPU time 28.89 seconds
Started May 28 01:15:35 PM PDT 24
Finished May 28 01:16:06 PM PDT 24
Peak memory 209380 kb
Host smart-58dd1411-f537-4978-871b-9bf4cb6cdb02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1705002578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1705002578
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1621013381
Short name T118
Test name
Test status
Simulation time 204724966 ps
CPU time 2.24 seconds
Started May 28 01:15:34 PM PDT 24
Finished May 28 01:15:37 PM PDT 24
Peak memory 199984 kb
Host smart-5f40cf2b-bc7c-4bdc-ae57-5e6f364e2fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621013381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1621013381
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.318254018
Short name T320
Test name
Test status
Simulation time 5254271039 ps
CPU time 1466.49 seconds
Started May 28 01:15:34 PM PDT 24
Finished May 28 01:40:02 PM PDT 24
Peak memory 753500 kb
Host smart-37e23e7b-6e1f-4e83-8d51-fcaab86761f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=318254018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.318254018
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1180504444
Short name T38
Test name
Test status
Simulation time 7898830888 ps
CPU time 146.19 seconds
Started May 28 01:15:35 PM PDT 24
Finished May 28 01:18:03 PM PDT 24
Peak memory 200120 kb
Host smart-5ae96c10-b33e-4bc8-bb56-2de6b4dc89d6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180504444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1180504444
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.916487417
Short name T462
Test name
Test status
Simulation time 1878855398 ps
CPU time 111.86 seconds
Started May 28 01:15:34 PM PDT 24
Finished May 28 01:17:28 PM PDT 24
Peak memory 199980 kb
Host smart-c4d51e8e-7a46-46c2-a11e-c2476660bd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916487417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.916487417
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.2454738326
Short name T428
Test name
Test status
Simulation time 129622613 ps
CPU time 4.9 seconds
Started May 28 01:15:34 PM PDT 24
Finished May 28 01:15:40 PM PDT 24
Peak memory 200080 kb
Host smart-372d2491-61d1-4795-bb61-e9adccf627b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454738326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2454738326
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1090109687
Short name T430
Test name
Test status
Simulation time 435802804338 ps
CPU time 2367.94 seconds
Started May 28 01:15:33 PM PDT 24
Finished May 28 01:55:02 PM PDT 24
Peak memory 762612 kb
Host smart-51bcfabd-5311-4675-a673-bc222b77ed49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090109687 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1090109687
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.1783352878
Short name T271
Test name
Test status
Simulation time 85290589 ps
CPU time 1.46 seconds
Started May 28 01:15:35 PM PDT 24
Finished May 28 01:15:39 PM PDT 24
Peak memory 200016 kb
Host smart-b7babe0e-204b-46b2-b561-6efbaeda78e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783352878 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.1783352878
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.667116115
Short name T508
Test name
Test status
Simulation time 7067361497 ps
CPU time 395.1 seconds
Started May 28 01:15:34 PM PDT 24
Finished May 28 01:22:11 PM PDT 24
Peak memory 200032 kb
Host smart-01bf54d0-6b67-4f05-9e43-8622dee9faef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667116115 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.667116115
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.2394853667
Short name T516
Test name
Test status
Simulation time 2091796066 ps
CPU time 18.04 seconds
Started May 28 01:15:37 PM PDT 24
Finished May 28 01:15:57 PM PDT 24
Peak memory 200064 kb
Host smart-51465411-fe64-45e1-b4d1-311ee0e204d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394853667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.2394853667
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/53.hmac_stress_all_with_rand_reset.3440207971
Short name T10
Test name
Test status
Simulation time 52895242171 ps
CPU time 1745.04 seconds
Started May 28 01:18:24 PM PDT 24
Finished May 28 01:47:31 PM PDT 24
Peak memory 239992 kb
Host smart-a0c8c841-5960-423f-b2aa-ab48a6e398f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3440207971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.hmac_stress_all_with_rand_reset.3440207971
Directory /workspace/53.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_alert_test.29877075
Short name T364
Test name
Test status
Simulation time 32110359 ps
CPU time 0.58 seconds
Started May 28 01:15:51 PM PDT 24
Finished May 28 01:15:54 PM PDT 24
Peak memory 195528 kb
Host smart-880fa93e-00e7-43a4-bd59-48813f4902d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29877075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.29877075
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.552761773
Short name T167
Test name
Test status
Simulation time 1633680679 ps
CPU time 22.54 seconds
Started May 28 01:15:51 PM PDT 24
Finished May 28 01:16:17 PM PDT 24
Peak memory 216384 kb
Host smart-5a18cb91-685c-445f-8ad2-0b8bfe11dc5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=552761773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.552761773
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1377054402
Short name T476
Test name
Test status
Simulation time 3222555212 ps
CPU time 43.72 seconds
Started May 28 01:15:49 PM PDT 24
Finished May 28 01:16:33 PM PDT 24
Peak memory 200156 kb
Host smart-510385ff-2c05-46a7-9dca-c21cfb8959a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377054402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1377054402
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.791938781
Short name T435
Test name
Test status
Simulation time 19858249233 ps
CPU time 1259.86 seconds
Started May 28 01:15:50 PM PDT 24
Finished May 28 01:36:52 PM PDT 24
Peak memory 760660 kb
Host smart-afe829e6-2ed1-4e40-b34e-da69ec5994d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=791938781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.791938781
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1080299711
Short name T202
Test name
Test status
Simulation time 9009047512 ps
CPU time 59.27 seconds
Started May 28 01:15:52 PM PDT 24
Finished May 28 01:16:54 PM PDT 24
Peak memory 200100 kb
Host smart-8c0125d6-e425-4dce-ba20-9620ab61229b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080299711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1080299711
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.4248954363
Short name T184
Test name
Test status
Simulation time 670753256 ps
CPU time 12.5 seconds
Started May 28 01:15:52 PM PDT 24
Finished May 28 01:16:07 PM PDT 24
Peak memory 200088 kb
Host smart-df05c685-9533-4e4e-9567-9fe3cbf46254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248954363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.4248954363
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.4267380832
Short name T473
Test name
Test status
Simulation time 744298890 ps
CPU time 6.85 seconds
Started May 28 01:15:49 PM PDT 24
Finished May 28 01:15:57 PM PDT 24
Peak memory 200076 kb
Host smart-89c2b0b0-6382-4a99-8291-97d80baf9542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267380832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.4267380832
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.3696432591
Short name T507
Test name
Test status
Simulation time 31386278 ps
CPU time 1.1 seconds
Started May 28 01:15:51 PM PDT 24
Finished May 28 01:15:54 PM PDT 24
Peak memory 199960 kb
Host smart-a794bb00-701b-4921-9fd3-7f0227d936b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696432591 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.3696432591
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.710760629
Short name T137
Test name
Test status
Simulation time 31497314501 ps
CPU time 446.69 seconds
Started May 28 01:15:53 PM PDT 24
Finished May 28 01:23:23 PM PDT 24
Peak memory 200156 kb
Host smart-26dfde2a-c36d-4092-a963-5f895d29bb64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710760629 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.710760629
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.4091571895
Short name T405
Test name
Test status
Simulation time 1435165305 ps
CPU time 73.14 seconds
Started May 28 01:15:53 PM PDT 24
Finished May 28 01:17:09 PM PDT 24
Peak memory 199972 kb
Host smart-5bfe6ed2-965b-4e1f-b5ea-f060c77a4205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091571895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.4091571895
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2264508562
Short name T23
Test name
Test status
Simulation time 32019549 ps
CPU time 0.56 seconds
Started May 28 01:15:53 PM PDT 24
Finished May 28 01:15:57 PM PDT 24
Peak memory 194960 kb
Host smart-80c61188-3169-4acc-950f-cc7ef3aafedf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264508562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2264508562
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1850990549
Short name T490
Test name
Test status
Simulation time 1072650233 ps
CPU time 61.75 seconds
Started May 28 01:15:50 PM PDT 24
Finished May 28 01:16:54 PM PDT 24
Peak memory 232712 kb
Host smart-d3ae3ee9-83fc-4ecb-ab2b-465dd49b0cfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1850990549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1850990549
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.325480871
Short name T538
Test name
Test status
Simulation time 1482771361 ps
CPU time 11.94 seconds
Started May 28 01:15:51 PM PDT 24
Finished May 28 01:16:06 PM PDT 24
Peak memory 200088 kb
Host smart-36834a0e-64ef-4da3-9762-8d6e508632a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325480871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.325480871
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.531427512
Short name T5
Test name
Test status
Simulation time 2487888964 ps
CPU time 666.09 seconds
Started May 28 01:15:50 PM PDT 24
Finished May 28 01:26:58 PM PDT 24
Peak memory 694340 kb
Host smart-fbe94689-689f-4301-872a-d9562704bcd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=531427512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.531427512
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2600633477
Short name T464
Test name
Test status
Simulation time 13920290391 ps
CPU time 255.07 seconds
Started May 28 01:15:52 PM PDT 24
Finished May 28 01:20:11 PM PDT 24
Peak memory 199952 kb
Host smart-8f8f9182-dd9b-4d94-9e78-1bc5b0506660
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600633477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2600633477
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2061455228
Short name T471
Test name
Test status
Simulation time 4719324911 ps
CPU time 92.86 seconds
Started May 28 01:15:53 PM PDT 24
Finished May 28 01:17:29 PM PDT 24
Peak memory 200156 kb
Host smart-82e1e0e5-86ef-4129-a7c8-8011daf909ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061455228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2061455228
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2551462409
Short name T346
Test name
Test status
Simulation time 631192254 ps
CPU time 8.99 seconds
Started May 28 01:15:52 PM PDT 24
Finished May 28 01:16:05 PM PDT 24
Peak memory 200076 kb
Host smart-9312d233-f505-429b-95be-4a0f8f539c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551462409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2551462409
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.2397869007
Short name T73
Test name
Test status
Simulation time 143341932495 ps
CPU time 1105.25 seconds
Started May 28 01:15:51 PM PDT 24
Finished May 28 01:34:18 PM PDT 24
Peak memory 681080 kb
Host smart-828de9ba-dc48-4842-b84b-f8da9d3af986
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397869007 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.2397869007
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.2297788182
Short name T219
Test name
Test status
Simulation time 251366379 ps
CPU time 1.35 seconds
Started May 28 01:15:51 PM PDT 24
Finished May 28 01:15:56 PM PDT 24
Peak memory 200056 kb
Host smart-1977ac7c-3838-4130-a3d0-7742c5a56daf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297788182 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.2297788182
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.2312761415
Short name T412
Test name
Test status
Simulation time 34945387067 ps
CPU time 483.44 seconds
Started May 28 01:15:52 PM PDT 24
Finished May 28 01:23:59 PM PDT 24
Peak memory 200156 kb
Host smart-92bf85f2-3fa9-4e9a-bc9b-8e6eff25c6a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312761415 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.2312761415
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2538400879
Short name T282
Test name
Test status
Simulation time 7007808241 ps
CPU time 72.19 seconds
Started May 28 01:15:51 PM PDT 24
Finished May 28 01:17:07 PM PDT 24
Peak memory 200100 kb
Host smart-35e6ec58-6d5b-4012-b0cd-3578f7c1e5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538400879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2538400879
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3130913310
Short name T200
Test name
Test status
Simulation time 14891228 ps
CPU time 0.62 seconds
Started May 28 01:15:52 PM PDT 24
Finished May 28 01:15:56 PM PDT 24
Peak memory 196612 kb
Host smart-9a76ef42-25c7-4737-afa2-d0fce1c39e1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130913310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3130913310
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3312158993
Short name T273
Test name
Test status
Simulation time 303133059 ps
CPU time 3.47 seconds
Started May 28 01:15:49 PM PDT 24
Finished May 28 01:15:54 PM PDT 24
Peak memory 199936 kb
Host smart-43617660-6c69-4462-bd25-ef3ed8bf1118
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3312158993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3312158993
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3058133606
Short name T414
Test name
Test status
Simulation time 4522236489 ps
CPU time 18.89 seconds
Started May 28 01:15:51 PM PDT 24
Finished May 28 01:16:13 PM PDT 24
Peak memory 200000 kb
Host smart-3d800caa-5360-4bf7-be30-02c431141d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058133606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3058133606
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.2937486358
Short name T298
Test name
Test status
Simulation time 9169057258 ps
CPU time 1283.82 seconds
Started May 28 01:15:51 PM PDT 24
Finished May 28 01:37:18 PM PDT 24
Peak memory 765636 kb
Host smart-cac9723c-dec9-4464-bc97-99e15b364276
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2937486358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.2937486358
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.4090175365
Short name T511
Test name
Test status
Simulation time 20324324589 ps
CPU time 127.16 seconds
Started May 28 01:15:50 PM PDT 24
Finished May 28 01:17:59 PM PDT 24
Peak memory 200096 kb
Host smart-a9168398-7733-4bb5-b97b-6485884687c6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090175365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.4090175365
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.263748703
Short name T156
Test name
Test status
Simulation time 3800656676 ps
CPU time 35.64 seconds
Started May 28 01:15:48 PM PDT 24
Finished May 28 01:16:25 PM PDT 24
Peak memory 200200 kb
Host smart-87cc4fbf-c56e-4c22-aac7-3a57e83f1d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263748703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.263748703
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3855612087
Short name T558
Test name
Test status
Simulation time 1354084807 ps
CPU time 9.3 seconds
Started May 28 01:15:50 PM PDT 24
Finished May 28 01:16:00 PM PDT 24
Peak memory 199984 kb
Host smart-a3dcc688-6266-46b7-87de-2d35a76d921c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855612087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3855612087
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.3845864533
Short name T374
Test name
Test status
Simulation time 10605740661 ps
CPU time 590.3 seconds
Started May 28 01:15:53 PM PDT 24
Finished May 28 01:25:46 PM PDT 24
Peak memory 199996 kb
Host smart-349da486-ae34-4177-a0ad-99804a10e79a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845864533 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3845864533
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.1485771363
Short name T442
Test name
Test status
Simulation time 224799417 ps
CPU time 1.47 seconds
Started May 28 01:15:50 PM PDT 24
Finished May 28 01:15:53 PM PDT 24
Peak memory 199976 kb
Host smart-c26db16c-a0cc-4c59-962f-f2545a662f50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485771363 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.1485771363
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.3917856184
Short name T297
Test name
Test status
Simulation time 32704145031 ps
CPU time 488.52 seconds
Started May 28 01:15:53 PM PDT 24
Finished May 28 01:24:05 PM PDT 24
Peak memory 200012 kb
Host smart-a1b3e44d-5dc7-4bea-ac7a-31e328d5ee7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917856184 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.3917856184
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2634452648
Short name T520
Test name
Test status
Simulation time 3335096391 ps
CPU time 39.81 seconds
Started May 28 01:15:52 PM PDT 24
Finished May 28 01:16:35 PM PDT 24
Peak memory 200176 kb
Host smart-f878a8bc-76dc-40bd-b45f-fc70e032d7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634452648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2634452648
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.496790197
Short name T465
Test name
Test status
Simulation time 22974963 ps
CPU time 0.58 seconds
Started May 28 01:15:50 PM PDT 24
Finished May 28 01:15:52 PM PDT 24
Peak memory 195560 kb
Host smart-1699f0ee-21c4-4e19-b31c-0e06b0d9d761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496790197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.496790197
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1064438038
Short name T17
Test name
Test status
Simulation time 4701660019 ps
CPU time 58.16 seconds
Started May 28 01:15:53 PM PDT 24
Finished May 28 01:16:54 PM PDT 24
Peak memory 247864 kb
Host smart-a8f1e29d-455a-4540-97ff-08180704d60b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1064438038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1064438038
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.114991562
Short name T479
Test name
Test status
Simulation time 2917486880 ps
CPU time 46.32 seconds
Started May 28 01:15:52 PM PDT 24
Finished May 28 01:16:42 PM PDT 24
Peak memory 200128 kb
Host smart-5a57fa87-c5b3-41e2-8ff4-30a28b0556de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114991562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.114991562
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.2008149042
Short name T308
Test name
Test status
Simulation time 3668937577 ps
CPU time 1036.8 seconds
Started May 28 01:15:53 PM PDT 24
Finished May 28 01:33:13 PM PDT 24
Peak memory 734064 kb
Host smart-4a0b6aaa-7b97-4945-8297-e3f6b0610bd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2008149042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2008149042
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3704645667
Short name T480
Test name
Test status
Simulation time 6751889688 ps
CPU time 58.25 seconds
Started May 28 01:15:52 PM PDT 24
Finished May 28 01:16:53 PM PDT 24
Peak memory 200064 kb
Host smart-7d2eaf06-6c65-4298-9b33-fd3b495d3502
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704645667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3704645667
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3671480828
Short name T135
Test name
Test status
Simulation time 33410494364 ps
CPU time 124.67 seconds
Started May 28 01:15:50 PM PDT 24
Finished May 28 01:17:56 PM PDT 24
Peak memory 200184 kb
Host smart-d1b9e945-2387-42bd-85a1-7d3f31c20063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671480828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3671480828
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3908216991
Short name T48
Test name
Test status
Simulation time 721712063 ps
CPU time 3.55 seconds
Started May 28 01:15:53 PM PDT 24
Finished May 28 01:15:59 PM PDT 24
Peak memory 199992 kb
Host smart-5400c303-4726-4b3c-982c-d69e29b96637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908216991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3908216991
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.2783482783
Short name T532
Test name
Test status
Simulation time 29491665152 ps
CPU time 1219.96 seconds
Started May 28 01:15:50 PM PDT 24
Finished May 28 01:36:12 PM PDT 24
Peak memory 488268 kb
Host smart-fbc0c067-e7e1-4d77-b760-297218fd2c7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783482783 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2783482783
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.889865344
Short name T233
Test name
Test status
Simulation time 228054370 ps
CPU time 1.35 seconds
Started May 28 01:15:52 PM PDT 24
Finished May 28 01:15:57 PM PDT 24
Peak memory 199912 kb
Host smart-c8867387-2d64-4e66-84d6-7104859a4370
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889865344 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.hmac_test_hmac_vectors.889865344
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.1243624629
Short name T155
Test name
Test status
Simulation time 41272165969 ps
CPU time 510.68 seconds
Started May 28 01:15:53 PM PDT 24
Finished May 28 01:24:27 PM PDT 24
Peak memory 200008 kb
Host smart-4ae90742-1604-40f5-8f5f-8d51daa41063
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243624629 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.1243624629
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.453079773
Short name T277
Test name
Test status
Simulation time 13059676139 ps
CPU time 45.82 seconds
Started May 28 01:15:51 PM PDT 24
Finished May 28 01:16:40 PM PDT 24
Peak memory 199908 kb
Host smart-e91834ec-0261-4547-b027-848e829a67f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453079773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.453079773
Directory /workspace/9.hmac_wipe_secret/latest
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