Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	12530359	1			T1	93		T2	13927		T3	70991
all_values[1]	12530359	1			T1	93		T2	13927		T3	70991
all_values[2]	12530359	1			T1	93		T2	13927		T3	70991

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

129989

1

T4

768

T5

205

T7

3

auto[1]

37461088

1

T1

279

T2

41781

T3

212973

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31405342

1

T1

221

T2

37598

T3

179252

auto[1]

6185735

1

T1

58

T2

4183

T3

33721

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	48296	1			T4	382		T5	75		T16	3
all_values[0]	auto[0]	auto[1]	315	1			T4	2		T17	4		T111	2
all_values[0]	auto[1]	auto[0]	12450495	1			T1	89		T2	13892		T3	70797
all_values[0]	auto[1]	auto[1]	31253	1			T1	4		T2	35		T3	194
all_values[1]	auto[0]	auto[0]	46764	1			T4	384		T7	3		T19	2
all_values[1]	auto[0]	auto[1]	148	1			T48	1		T10	3		T28	2
all_values[1]	auto[1]	auto[0]	12483241	1			T1	93		T2	13927		T3	70991
all_values[1]	auto[1]	auto[1]	206	1			T17	2		T36	2		T38	1
all_values[2]	auto[0]	auto[0]	20029	1			T17	4049		T53	164		T123	1
all_values[2]	auto[0]	auto[1]	14437	1			T5	130		T19	2		T17	4
all_values[2]	auto[1]	auto[0]	6356517	1			T1	39		T2	9779		T3	37464
all_values[2]	auto[1]	auto[1]	6139376	1			T1	54		T2	4148		T3	33527