Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5801348

1

T1

34

T2

6643

T3

37269

auto[1]

2486723

1

T2

7196

T4

601

T5

3496

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2416441

1

T2

7188

T4

353

T5

5890

auto[1]

5871630

1

T1

34

T2

6651

T3

37269

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4630365

1

T2

7774

T3

37269

T5

3399

auto[1]

3657706

1

T1

34

T2

6065

T4

969

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6584165	1			T1	31		T2	13001		T3	24303
fifo_depth[1]	267431	1			T1	3		T2	397		T3	2417
fifo_depth[2]	222487	1			T2	255		T3	2385		T4	2
fifo_depth[3]	182546	1			T2	116		T3	1980		T5	56
fifo_depth[4]	154600	1			T2	46		T3	1551		T5	107
fifo_depth[5]	135063	1			T2	19		T3	1307		T5	25
fifo_depth[6]	129444	1			T2	4		T3	1129		T5	50
fifo_depth[7]	107631	1			T3	864		T5	12		T6	46

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1703906

1

T1

3

T2

838

T3

12966

auto[1]

6584165

1

T1

31

T2

13001

T3

24303

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8277113

1

T1

34

T2

13839

T3

37269

auto[1]

10958

1

T6

132

T14

508

T19

1

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

82566

1

T2

61

T5

99

T25

167

auto[0]

auto[0]

auto[0]

auto[1]

68793

1

T2

174

T5

39

T6

1004

auto[0]

auto[0]

auto[1]

auto[0]

762544

1

T2

186

T3

12966

T5

39

auto[0]

auto[0]

auto[1]

auto[1]

77799

1

T2

37

T5

124

T6

578

auto[0]

auto[1]

auto[0]

auto[0]

172920

1

T2

28

T5

18

T6

705

auto[0]

auto[1]

auto[0]

auto[1]

189391

1

T2

68

T4

1

T5

43

auto[0]

auto[1]

auto[1]

auto[0]

173321

1

T1

3

T2

7

T4

4

auto[0]

auto[1]

auto[1]

auto[1]

176572

1

T2

277

T4

5

T5

45

auto[1]

auto[0]

auto[0]

auto[0]

237868

1

T2

2116

T5

2035

T6

69

auto[1]

auto[0]

auto[0]

auto[1]

225934

1

T2

2289

T5

287

T6

84

auto[1]

auto[0]

auto[1]

auto[0]

2949952

1

T2

1659

T3

24303

T5

64

auto[1]

auto[0]

auto[1]

auto[1]

224909

1

T2

1252

T5

712

T6

100

auto[1]

auto[1]

auto[0]

auto[0]

692377

1

T2

2041

T5

2781

T6

16

auto[1]

auto[1]

auto[0]

auto[1]

746592

1

T2

411

T4

352

T5

588

auto[1]

auto[1]

auto[1]

auto[0]

729800

1

T1

31

T2

545

T4

364

auto[1]

auto[1]

auto[1]

auto[1]

776733

1

T2

2688

T4

243

T5

1658

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

319580

1

T2

2177

T5

2134

T6

69

auto[0]

auto[0]

auto[0]

auto[1]

294244

1

T2

2463

T5

326

T6

1079

auto[0]

auto[0]

auto[1]

auto[0]

3709749

1

T2

1845

T3

37269

T5

103

auto[0]

auto[0]

auto[1]

auto[1]

301610

1

T2

1289

T5

836

T6

675

auto[0]

auto[1]

auto[0]

auto[0]

863755

1

T2

2069

T5

2799

T6

720

auto[0]

auto[1]

auto[0]

auto[1]

934253

1

T2

479

T4

353

T5

631

auto[0]

auto[1]

auto[1]

auto[0]

901625

1

T1

34

T2

552

T4

368

auto[0]

auto[1]

auto[1]

auto[1]

952297

1

T2

2965

T4

248

T5

1703

auto[1]

auto[0]

auto[0]

auto[0]

854

1

T36

142

T39

7

T110

6

auto[1]

auto[0]

auto[0]

auto[1]

483

1

T6

9

T14

2

T20

1

auto[1]

auto[0]

auto[1]

auto[0]

2747

1

T6

1

T17

9

T21

1

auto[1]

auto[0]

auto[1]

auto[1]

1098

1

T6

3

T14

50

T17

1

auto[1]

auto[1]

auto[0]

auto[0]

1542

1

T6

1

T14

30

T17

15

auto[1]

auto[1]

auto[0]

auto[1]

1730

1

T6

118

T14

422

T19

1

auto[1]

auto[1]

auto[1]

auto[0]

1496

1

T17

1

T138

3

T47

1

auto[1]

auto[1]

auto[1]

auto[1]

1008

1

T14

4

T17

374

T21

2

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	237868	1			T2	2116		T5	2035		T6	69
fifo_depth[0]	auto[0]	auto[0]	auto[1]	225934	1			T2	2289		T5	287		T6	84
fifo_depth[0]	auto[0]	auto[1]	auto[0]	2949952	1			T2	1659		T3	24303		T5	64
fifo_depth[0]	auto[0]	auto[1]	auto[1]	224909	1			T2	1252		T5	712		T6	100
fifo_depth[0]	auto[1]	auto[0]	auto[0]	692377	1			T2	2041		T5	2781		T6	16
fifo_depth[0]	auto[1]	auto[0]	auto[1]	746592	1			T2	411		T4	352		T5	588
fifo_depth[0]	auto[1]	auto[1]	auto[0]	729800	1			T1	31		T2	545		T4	364
fifo_depth[0]	auto[1]	auto[1]	auto[1]	776733	1			T2	2688		T4	243		T5	1658
fifo_depth[1]	auto[0]	auto[0]	auto[0]	6443	1			T2	31		T5	36		T25	18
fifo_depth[1]	auto[0]	auto[0]	auto[1]	5969	1			T2	80		T5	5		T6	9
fifo_depth[1]	auto[0]	auto[1]	auto[0]	172597	1			T2	90		T3	2417		T5	7
fifo_depth[1]	auto[0]	auto[1]	auto[1]	6782	1			T2	20		T5	6		T6	17
fifo_depth[1]	auto[1]	auto[0]	auto[0]	17400	1			T2	20		T5	8		T6	2
fifo_depth[1]	auto[1]	auto[0]	auto[1]	20349	1			T2	35		T4	1		T5	3
fifo_depth[1]	auto[1]	auto[1]	auto[0]	18611	1			T1	3		T2	5		T4	4
fifo_depth[1]	auto[1]	auto[1]	auto[1]	19280	1			T2	116		T4	3		T9	110
fifo_depth[2]	auto[0]	auto[0]	auto[0]	5868	1			T2	18		T5	33		T25	24
fifo_depth[2]	auto[0]	auto[0]	auto[1]	5199	1			T2	48		T5	6		T6	12
fifo_depth[2]	auto[0]	auto[1]	auto[0]	134954	1			T2	58		T3	2385		T5	4
fifo_depth[2]	auto[0]	auto[1]	auto[1]	6117	1			T2	12		T5	34		T6	13
fifo_depth[2]	auto[1]	auto[0]	auto[0]	15986	1			T2	5		T5	2		T6	9
fifo_depth[2]	auto[1]	auto[0]	auto[1]	19018	1			T2	24		T5	22		T6	6
fifo_depth[2]	auto[1]	auto[1]	auto[0]	17363	1			T2	1		T5	58		T26	2
fifo_depth[2]	auto[1]	auto[1]	auto[1]	17982	1			T2	89		T4	2		T5	1
fifo_depth[3]	auto[0]	auto[0]	auto[0]	4805	1			T2	5		T5	22		T25	17
fifo_depth[3]	auto[0]	auto[0]	auto[1]	4142	1			T2	28		T5	6		T6	12
fifo_depth[3]	auto[0]	auto[1]	auto[0]	103801	1			T2	24		T3	1980		T5	4
fifo_depth[3]	auto[0]	auto[1]	auto[1]	4962	1			T2	5		T5	5		T6	17
fifo_depth[3]	auto[1]	auto[0]	auto[0]	14753	1			T2	3		T5	1		T6	4
fifo_depth[3]	auto[1]	auto[0]	auto[1]	17631	1			T2	4		T5	2		T7	295
fifo_depth[3]	auto[1]	auto[1]	auto[0]	15848	1			T5	14		T7	48		T9	25
fifo_depth[3]	auto[1]	auto[1]	auto[1]	16604	1			T2	47		T5	2		T9	132
fifo_depth[4]	auto[0]	auto[0]	auto[0]	5448	1			T2	6		T5	5		T25	17
fifo_depth[4]	auto[0]	auto[0]	auto[1]	4100	1			T2	11		T5	5		T6	8
fifo_depth[4]	auto[0]	auto[1]	auto[0]	76725	1			T2	7		T3	1551		T5	4
fifo_depth[4]	auto[0]	auto[1]	auto[1]	4785	1			T5	31		T6	13		T58	23
fifo_depth[4]	auto[1]	auto[0]	auto[0]	14414	1			T5	5		T6	3		T7	315
fifo_depth[4]	auto[1]	auto[0]	auto[1]	17325	1			T2	4		T5	12		T6	9
fifo_depth[4]	auto[1]	auto[1]	auto[0]	15593	1			T5	17		T26	2		T7	57
fifo_depth[4]	auto[1]	auto[1]	auto[1]	16210	1			T2	18		T5	28		T9	123
fifo_depth[5]	auto[0]	auto[0]	auto[0]	4122	1			T2	1		T5	3		T25	20
fifo_depth[5]	auto[0]	auto[0]	auto[1]	3478	1			T2	5		T5	3		T6	18
fifo_depth[5]	auto[0]	auto[1]	auto[0]	62855	1			T2	7		T3	1307		T5	7
fifo_depth[5]	auto[0]	auto[1]	auto[1]	4268	1			T5	2		T6	15		T58	16
fifo_depth[5]	auto[1]	auto[0]	auto[0]	13903	1			T6	6		T7	297		T9	4
fifo_depth[5]	auto[1]	auto[0]	auto[1]	16462	1			T2	1		T6	1		T7	294
fifo_depth[5]	auto[1]	auto[1]	auto[0]	14913	1			T2	1		T5	6		T26	2
fifo_depth[5]	auto[1]	auto[1]	auto[1]	15062	1			T2	4		T5	4		T9	116
fifo_depth[6]	auto[0]	auto[0]	auto[0]	5709	1			T25	19		T29	41		T51	11
fifo_depth[6]	auto[0]	auto[0]	auto[1]	4240	1			T2	2		T5	8		T6	11
fifo_depth[6]	auto[0]	auto[1]	auto[0]	54596	1			T3	1129		T5	5		T6	2
fifo_depth[6]	auto[0]	auto[1]	auto[1]	4738	1			T5	26		T6	22		T58	13
fifo_depth[6]	auto[1]	auto[0]	auto[0]	13567	1			T5	1		T6	12		T7	263
fifo_depth[6]	auto[1]	auto[0]	auto[1]	16421	1			T5	2		T6	6		T7	286
fifo_depth[6]	auto[1]	auto[1]	auto[0]	15067	1			T5	8		T7	44		T9	18
fifo_depth[6]	auto[1]	auto[1]	auto[1]	15106	1			T2	2		T9	105		T25	19
fifo_depth[7]	auto[0]	auto[0]	auto[0]	3696	1			T25	24		T29	22		T51	17
fifo_depth[7]	auto[0]	auto[0]	auto[1]	3350	1			T5	3		T6	13		T25	9
fifo_depth[7]	auto[0]	auto[1]	auto[0]	41812	1			T3	864		T5	4		T6	2
fifo_depth[7]	auto[0]	auto[1]	auto[1]	3772	1			T5	2		T6	25		T58	14
fifo_depth[7]	auto[1]	auto[0]	auto[0]	12852	1			T6	6		T7	260		T9	3
fifo_depth[7]	auto[1]	auto[0]	auto[1]	14909	1			T7	246		T9	18		T25	21
fifo_depth[7]	auto[1]	auto[1]	auto[0]	13610	1			T5	2		T7	48		T9	32
fifo_depth[7]	auto[1]	auto[1]	auto[1]	13630	1			T5	1		T9	102		T25	11