Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	12530359	1			T1	93		T2	13927		T3	70991
all_pins[1]	12530359	1			T1	93		T2	13927		T3	70991
all_pins[2]	12530359	1			T1	93		T2	13927		T3	70991

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	31419630	1			T1	221		T2	37598		T3	179252
values[0x1]	6171447	1			T1	58		T2	4183		T3	33721
transitions[0x0=>0x1]	6171319	1			T1	58		T2	4183		T3	33721
transitions[0x1=>0x0]	6171337	1			T1	58		T2	4183		T3	33721

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	12498501	1			T1	89		T2	13892		T3	70797
all_pins[0]	values[0x1]	31858	1			T1	4		T2	35		T3	194
all_pins[0]	transitions[0x0=>0x1]	31784	1			T1	4		T2	35		T3	194
all_pins[0]	transitions[0x1=>0x0]	6139320	1			T1	54		T2	4148		T3	33527
all_pins[1]	values[0x0]	12530146	1			T1	93		T2	13927		T3	70991
all_pins[1]	values[0x1]	213	1			T17	2		T36	2		T38	1
all_pins[1]	transitions[0x0=>0x1]	184	1			T17	1		T36	2		T38	1
all_pins[1]	transitions[0x1=>0x0]	31829	1			T1	4		T2	35		T3	194
all_pins[2]	values[0x0]	6390983	1			T1	39		T2	9779		T3	37464
all_pins[2]	values[0x1]	6139376	1			T1	54		T2	4148		T3	33527
all_pins[2]	transitions[0x0=>0x1]	6139351	1			T1	54		T2	4148		T3	33527
all_pins[2]	transitions[0x1=>0x0]	188	1			T17	2		T36	2		T38	1