Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 653 1 T17 4 T38 4 T48 4
all_values[1] 653 1 T17 4 T38 4 T48 4
all_values[2] 653 1 T17 4 T38 4 T48 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1032 1 T17 3 T38 6 T48 4
auto[1] 927 1 T17 9 T38 6 T48 8


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 708 1 T17 4 T38 9 T48 8
auto[1] 1251 1 T17 8 T38 3 T48 4


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1135 1 T17 9 T38 10 T48 9
auto[1] 824 1 T17 3 T38 2 T48 3


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 134 1 T38 2 T48 1 T10 7
all_values[0] auto[0] auto[0] auto[1] 60 1 T10 2 T124 2 T125 1
all_values[0] auto[0] auto[1] auto[0] 123 1 T38 2 T48 3 T110 2
all_values[0] auto[0] auto[1] auto[1] 63 1 T17 3 T124 2 T126 1
all_values[0] auto[1] auto[0] auto[1] 131 1 T10 3 T124 3 T125 3
all_values[0] auto[1] auto[1] auto[1] 142 1 T17 1 T110 2 T28 2
all_values[1] auto[0] auto[0] auto[0] 114 1 T38 1 T110 1 T10 2
all_values[1] auto[0] auto[0] auto[1] 91 1 T38 1 T48 1 T10 3
all_values[1] auto[0] auto[1] auto[0] 100 1 T17 2 T38 1 T48 1
all_values[1] auto[0] auto[1] auto[1] 75 1 T17 1 T110 1 T10 2
all_values[1] auto[1] auto[0] auto[1] 156 1 T110 1 T10 3 T28 2
all_values[1] auto[1] auto[1] auto[1] 117 1 T17 1 T38 1 T48 2
all_values[2] auto[0] auto[0] auto[0] 137 1 T17 2 T38 1 T48 1
all_values[2] auto[0] auto[0] auto[1] 68 1 T17 1 T10 1 T124 2
all_values[2] auto[0] auto[1] auto[0] 100 1 T38 2 T48 2 T110 1
all_values[2] auto[0] auto[1] auto[1] 70 1 T10 3 T125 2 T126 4
all_values[2] auto[1] auto[0] auto[1] 141 1 T38 1 T48 1 T10 4
all_values[2] auto[1] auto[1] auto[1] 137 1 T17 1 T110 3 T10 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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