Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.62 95.60 93.53 100.00 76.32 91.06 99.49 71.33


Total test records in report: 724
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T542 /workspace/coverage/default/28.hmac_smoke.835384889 May 30 02:51:31 PM PDT 24 May 30 02:51:38 PM PDT 24 529580998 ps
T543 /workspace/coverage/default/34.hmac_datapath_stress.1195407448 May 30 02:52:08 PM PDT 24 May 30 02:53:33 PM PDT 24 531518599 ps
T544 /workspace/coverage/default/40.hmac_back_pressure.4294186439 May 30 02:52:45 PM PDT 24 May 30 02:52:49 PM PDT 24 536487923 ps
T545 /workspace/coverage/default/33.hmac_wipe_secret.988220415 May 30 02:52:08 PM PDT 24 May 30 02:52:49 PM PDT 24 3633593807 ps
T546 /workspace/coverage/default/13.hmac_long_msg.3209344174 May 30 02:50:23 PM PDT 24 May 30 02:50:31 PM PDT 24 414094744 ps
T547 /workspace/coverage/default/7.hmac_error.2230419036 May 30 02:50:11 PM PDT 24 May 30 02:51:56 PM PDT 24 7180431964 ps
T548 /workspace/coverage/default/6.hmac_datapath_stress.1469339418 May 30 02:50:08 PM PDT 24 May 30 03:02:35 PM PDT 24 3349138887 ps
T549 /workspace/coverage/default/32.hmac_datapath_stress.3436299177 May 30 02:52:07 PM PDT 24 May 30 03:00:09 PM PDT 24 2233084611 ps
T550 /workspace/coverage/default/30.hmac_alert_test.2351403914 May 30 02:51:54 PM PDT 24 May 30 02:51:57 PM PDT 24 11973208 ps
T551 /workspace/coverage/default/1.hmac_alert_test.1183941634 May 30 02:49:40 PM PDT 24 May 30 02:49:42 PM PDT 24 14196153 ps
T552 /workspace/coverage/default/3.hmac_stress_all.3550608461 May 30 02:49:55 PM PDT 24 May 30 03:13:58 PM PDT 24 199799455234 ps
T553 /workspace/coverage/default/34.hmac_burst_wr.2001363520 May 30 02:52:09 PM PDT 24 May 30 02:52:17 PM PDT 24 404061482 ps
T554 /workspace/coverage/default/26.hmac_datapath_stress.2431123159 May 30 02:51:32 PM PDT 24 May 30 03:13:23 PM PDT 24 18830786586 ps
T555 /workspace/coverage/default/11.hmac_back_pressure.704696586 May 30 02:50:19 PM PDT 24 May 30 02:50:39 PM PDT 24 4605183670 ps
T556 /workspace/coverage/default/0.hmac_long_msg.1291007627 May 30 02:49:42 PM PDT 24 May 30 02:50:16 PM PDT 24 2148094846 ps
T557 /workspace/coverage/default/37.hmac_test_hmac_vectors.4017635702 May 30 02:52:21 PM PDT 24 May 30 02:52:25 PM PDT 24 44540361 ps
T558 /workspace/coverage/default/12.hmac_smoke.2622663777 May 30 02:50:22 PM PDT 24 May 30 02:50:25 PM PDT 24 52228792 ps
T559 /workspace/coverage/default/4.hmac_long_msg.1953250003 May 30 02:49:58 PM PDT 24 May 30 02:50:52 PM PDT 24 899296522 ps
T560 /workspace/coverage/default/1.hmac_burst_wr.2067666256 May 30 02:49:42 PM PDT 24 May 30 02:49:51 PM PDT 24 348875004 ps
T561 /workspace/coverage/default/35.hmac_test_hmac_vectors.312596105 May 30 02:52:19 PM PDT 24 May 30 02:52:23 PM PDT 24 176372859 ps
T562 /workspace/coverage/default/4.hmac_back_pressure.2103182384 May 30 02:49:55 PM PDT 24 May 30 02:50:29 PM PDT 24 556303473 ps
T563 /workspace/coverage/default/24.hmac_datapath_stress.3468956114 May 30 02:51:24 PM PDT 24 May 30 02:52:26 PM PDT 24 1140539497 ps
T564 /workspace/coverage/default/42.hmac_error.2114990959 May 30 02:52:59 PM PDT 24 May 30 02:56:01 PM PDT 24 3214112317 ps
T565 /workspace/coverage/default/10.hmac_back_pressure.2446759291 May 30 02:50:20 PM PDT 24 May 30 02:50:49 PM PDT 24 571711872 ps
T566 /workspace/coverage/default/5.hmac_test_hmac_vectors.2062003219 May 30 02:49:57 PM PDT 24 May 30 02:50:00 PM PDT 24 97709197 ps
T567 /workspace/coverage/default/14.hmac_test_hmac_vectors.473733455 May 30 02:50:32 PM PDT 24 May 30 02:50:35 PM PDT 24 40227628 ps
T568 /workspace/coverage/default/15.hmac_stress_all.2581052817 May 30 02:50:34 PM PDT 24 May 30 02:52:39 PM PDT 24 6699745846 ps
T35 /workspace/coverage/default/0.hmac_sec_cm.3588313491 May 30 02:49:41 PM PDT 24 May 30 02:49:43 PM PDT 24 68452497 ps
T569 /workspace/coverage/default/44.hmac_datapath_stress.261842357 May 30 02:53:02 PM PDT 24 May 30 02:54:25 PM PDT 24 865390267 ps
T570 /workspace/coverage/default/11.hmac_test_sha_vectors.1733354840 May 30 02:50:22 PM PDT 24 May 30 02:58:21 PM PDT 24 8673161118 ps
T571 /workspace/coverage/default/36.hmac_long_msg.2707728819 May 30 02:52:20 PM PDT 24 May 30 02:52:41 PM PDT 24 4738167072 ps
T572 /workspace/coverage/default/17.hmac_back_pressure.1319422340 May 30 02:50:50 PM PDT 24 May 30 02:51:23 PM PDT 24 2533874239 ps
T573 /workspace/coverage/default/36.hmac_test_hmac_vectors.2531175870 May 30 02:52:22 PM PDT 24 May 30 02:52:26 PM PDT 24 78713603 ps
T574 /workspace/coverage/default/4.hmac_wipe_secret.2076160101 May 30 02:49:54 PM PDT 24 May 30 02:50:07 PM PDT 24 216295779 ps
T575 /workspace/coverage/default/14.hmac_alert_test.900628954 May 30 02:50:32 PM PDT 24 May 30 02:50:35 PM PDT 24 40436978 ps
T576 /workspace/coverage/default/20.hmac_burst_wr.4130231329 May 30 02:51:05 PM PDT 24 May 30 02:51:40 PM PDT 24 626106453 ps
T577 /workspace/coverage/default/33.hmac_error.1398662289 May 30 02:52:07 PM PDT 24 May 30 02:53:26 PM PDT 24 4279715460 ps
T578 /workspace/coverage/default/7.hmac_test_hmac_vectors.250483353 May 30 02:50:08 PM PDT 24 May 30 02:50:12 PM PDT 24 539653802 ps
T579 /workspace/coverage/default/18.hmac_burst_wr.684872150 May 30 02:50:46 PM PDT 24 May 30 02:51:23 PM PDT 24 2404557313 ps
T580 /workspace/coverage/default/12.hmac_wipe_secret.3999754642 May 30 02:50:19 PM PDT 24 May 30 02:50:30 PM PDT 24 949995420 ps
T581 /workspace/coverage/default/35.hmac_back_pressure.2389841470 May 30 02:52:22 PM PDT 24 May 30 02:52:49 PM PDT 24 1850620480 ps
T582 /workspace/coverage/default/49.hmac_burst_wr.4083219039 May 30 02:53:40 PM PDT 24 May 30 02:54:46 PM PDT 24 4516952540 ps
T82 /workspace/coverage/default/19.hmac_stress_all.1221333626 May 30 02:51:05 PM PDT 24 May 30 03:10:58 PM PDT 24 51595218461 ps
T583 /workspace/coverage/default/31.hmac_alert_test.408110958 May 30 02:51:56 PM PDT 24 May 30 02:51:59 PM PDT 24 19439353 ps
T584 /workspace/coverage/default/7.hmac_alert_test.3069722201 May 30 02:50:11 PM PDT 24 May 30 02:50:14 PM PDT 24 23528986 ps
T585 /workspace/coverage/default/24.hmac_alert_test.3709107514 May 30 02:51:18 PM PDT 24 May 30 02:51:22 PM PDT 24 13302165 ps
T586 /workspace/coverage/default/3.hmac_datapath_stress.674935378 May 30 02:49:58 PM PDT 24 May 30 03:05:04 PM PDT 24 7143399809 ps
T587 /workspace/coverage/default/22.hmac_stress_all.3340962324 May 30 02:51:18 PM PDT 24 May 30 03:00:33 PM PDT 24 2275930010 ps
T588 /workspace/coverage/default/15.hmac_test_hmac_vectors.2042879477 May 30 02:50:36 PM PDT 24 May 30 02:50:39 PM PDT 24 510400721 ps
T589 /workspace/coverage/default/22.hmac_error.378787717 May 30 02:51:18 PM PDT 24 May 30 02:52:31 PM PDT 24 14793105952 ps
T590 /workspace/coverage/default/48.hmac_test_hmac_vectors.3739333111 May 30 02:53:38 PM PDT 24 May 30 02:53:41 PM PDT 24 78603601 ps
T591 /workspace/coverage/default/39.hmac_test_hmac_vectors.2682261215 May 30 02:52:47 PM PDT 24 May 30 02:52:49 PM PDT 24 109165387 ps
T592 /workspace/coverage/default/35.hmac_burst_wr.807748145 May 30 02:52:23 PM PDT 24 May 30 02:52:40 PM PDT 24 1935533850 ps
T593 /workspace/coverage/default/36.hmac_datapath_stress.3442611269 May 30 02:52:19 PM PDT 24 May 30 02:56:12 PM PDT 24 11850704510 ps
T594 /workspace/coverage/default/45.hmac_long_msg.852862186 May 30 02:53:21 PM PDT 24 May 30 02:54:10 PM PDT 24 2263830688 ps
T595 /workspace/coverage/default/16.hmac_datapath_stress.3761145340 May 30 02:50:33 PM PDT 24 May 30 02:57:03 PM PDT 24 2452260328 ps
T596 /workspace/coverage/default/46.hmac_stress_all.80495574 May 30 02:53:22 PM PDT 24 May 30 03:27:58 PM PDT 24 80450994335 ps
T597 /workspace/coverage/default/1.hmac_smoke.2677094173 May 30 02:49:41 PM PDT 24 May 30 02:49:48 PM PDT 24 278940529 ps
T598 /workspace/coverage/default/45.hmac_smoke.1320158327 May 30 02:53:00 PM PDT 24 May 30 02:53:09 PM PDT 24 1005111163 ps
T64 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.534036718 May 30 02:43:26 PM PDT 24 May 30 02:43:33 PM PDT 24 2226532578 ps
T60 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2124520302 May 30 02:43:29 PM PDT 24 May 30 02:43:31 PM PDT 24 159455147 ps
T599 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3453312454 May 30 02:44:48 PM PDT 24 May 30 02:44:51 PM PDT 24 45958355 ps
T600 /workspace/coverage/cover_reg_top/11.hmac_intr_test.2368260671 May 30 02:44:02 PM PDT 24 May 30 02:44:04 PM PDT 24 138065378 ps
T65 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.119809816 May 30 02:44:13 PM PDT 24 May 30 02:44:16 PM PDT 24 178863820 ps
T61 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3848088229 May 30 02:43:50 PM PDT 24 May 30 02:43:54 PM PDT 24 37845647 ps
T62 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1358469140 May 30 02:43:34 PM PDT 24 May 30 02:43:38 PM PDT 24 211343361 ps
T601 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2392564761 May 30 02:44:01 PM PDT 24 May 30 02:44:03 PM PDT 24 13636056 ps
T63 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2439487907 May 30 02:43:39 PM PDT 24 May 30 02:43:43 PM PDT 24 112953540 ps
T602 /workspace/coverage/cover_reg_top/48.hmac_intr_test.3510218315 May 30 02:44:47 PM PDT 24 May 30 02:44:49 PM PDT 24 48669701 ps
T603 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3819815948 May 30 02:44:14 PM PDT 24 May 30 02:44:16 PM PDT 24 124348734 ps
T66 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.457855549 May 30 02:44:18 PM PDT 24 May 30 03:00:11 PM PDT 24 564663527947 ps
T604 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.4154015392 May 30 02:44:32 PM PDT 24 May 30 02:44:35 PM PDT 24 120653018 ps
T67 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.240009116 May 30 02:43:51 PM PDT 24 May 30 02:43:55 PM PDT 24 97895984 ps
T68 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.691741527 May 30 02:44:16 PM PDT 24 May 30 02:44:19 PM PDT 24 610029901 ps
T55 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1800252813 May 30 02:44:12 PM PDT 24 May 30 02:44:15 PM PDT 24 88298990 ps
T605 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1553033747 May 30 02:43:50 PM PDT 24 May 30 02:43:53 PM PDT 24 45159954 ps
T606 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3314085720 May 30 02:44:33 PM PDT 24 May 30 02:44:36 PM PDT 24 77166455 ps
T607 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.623897978 May 30 02:43:28 PM PDT 24 May 30 02:43:33 PM PDT 24 1357434593 ps
T608 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2981994579 May 30 02:44:46 PM PDT 24 May 30 02:44:48 PM PDT 24 172822785 ps
T609 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.523151545 May 30 02:43:27 PM PDT 24 May 30 02:43:34 PM PDT 24 300673944 ps
T610 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2074331594 May 30 02:44:05 PM PDT 24 May 30 02:44:09 PM PDT 24 549201705 ps
T611 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.478742308 May 30 02:44:02 PM PDT 24 May 30 02:44:05 PM PDT 24 102617824 ps
T612 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2848011740 May 30 02:44:32 PM PDT 24 May 30 02:44:34 PM PDT 24 22446577 ps
T613 /workspace/coverage/cover_reg_top/5.hmac_intr_test.778222588 May 30 02:43:52 PM PDT 24 May 30 02:43:54 PM PDT 24 11156036 ps
T96 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2705801349 May 30 02:44:15 PM PDT 24 May 30 02:44:17 PM PDT 24 27853444 ps
T56 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3030157913 May 30 02:44:02 PM PDT 24 May 30 02:44:07 PM PDT 24 2980741759 ps
T614 /workspace/coverage/cover_reg_top/20.hmac_intr_test.4189049398 May 30 02:44:32 PM PDT 24 May 30 02:44:34 PM PDT 24 22318530 ps
T83 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3231175280 May 30 02:44:01 PM PDT 24 May 30 02:44:04 PM PDT 24 77642459 ps
T57 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2818632510 May 30 02:44:00 PM PDT 24 May 30 02:44:06 PM PDT 24 869933047 ps
T615 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3642812806 May 30 02:43:37 PM PDT 24 May 30 02:43:40 PM PDT 24 132771234 ps
T616 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2469146998 May 30 02:44:00 PM PDT 24 May 30 02:44:03 PM PDT 24 537110635 ps
T84 /workspace/coverage/cover_reg_top/25.hmac_intr_test.1882270965 May 30 02:44:31 PM PDT 24 May 30 02:44:33 PM PDT 24 78304029 ps
T617 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2345711532 May 30 02:43:29 PM PDT 24 May 30 02:43:31 PM PDT 24 136590228 ps
T97 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.4262830614 May 30 02:43:39 PM PDT 24 May 30 02:43:41 PM PDT 24 81339543 ps
T618 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1442344989 May 30 02:44:46 PM PDT 24 May 30 02:44:48 PM PDT 24 13364710 ps
T619 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2587168022 May 30 02:44:33 PM PDT 24 May 30 02:44:35 PM PDT 24 22697769 ps
T127 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3760573258 May 30 02:44:31 PM PDT 24 May 30 02:44:35 PM PDT 24 159241413 ps
T620 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3121387024 May 30 02:44:15 PM PDT 24 May 30 02:44:17 PM PDT 24 192471272 ps
T621 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.115979976 May 30 02:44:14 PM PDT 24 May 30 02:44:18 PM PDT 24 63946736 ps
T622 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3316295938 May 30 02:44:03 PM PDT 24 May 30 02:44:06 PM PDT 24 38967064 ps
T623 /workspace/coverage/cover_reg_top/8.hmac_intr_test.598578431 May 30 02:44:01 PM PDT 24 May 30 02:44:04 PM PDT 24 32950785 ps
T134 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.925260096 May 30 02:44:13 PM PDT 24 May 30 02:44:17 PM PDT 24 880583383 ps
T624 /workspace/coverage/cover_reg_top/24.hmac_intr_test.46859609 May 30 02:44:33 PM PDT 24 May 30 02:44:35 PM PDT 24 11779058 ps
T625 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1272297974 May 30 02:44:03 PM PDT 24 May 30 02:47:36 PM PDT 24 60634855961 ps
T626 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2002482564 May 30 02:43:53 PM PDT 24 May 30 02:43:58 PM PDT 24 69596885 ps
T627 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3322805884 May 30 02:44:17 PM PDT 24 May 30 02:44:19 PM PDT 24 31577034 ps
T628 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3916632036 May 30 02:43:38 PM PDT 24 May 30 02:43:41 PM PDT 24 260510445 ps
T629 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.641995242 May 30 02:44:31 PM PDT 24 May 30 02:44:35 PM PDT 24 334407538 ps
T630 /workspace/coverage/cover_reg_top/23.hmac_intr_test.497517646 May 30 02:44:32 PM PDT 24 May 30 02:44:34 PM PDT 24 25381266 ps
T631 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2097649527 May 30 02:43:49 PM PDT 24 May 30 02:43:53 PM PDT 24 231963117 ps
T136 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2411249021 May 30 02:43:28 PM PDT 24 May 30 02:43:32 PM PDT 24 751378873 ps
T632 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3761431098 May 30 02:43:50 PM PDT 24 May 30 02:43:54 PM PDT 24 25392297 ps
T633 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2516227948 May 30 02:44:31 PM PDT 24 May 30 02:46:22 PM PDT 24 21194770394 ps
T634 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2356907140 May 30 02:43:36 PM PDT 24 May 30 02:43:38 PM PDT 24 11862353 ps
T98 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3802774427 May 30 02:43:37 PM PDT 24 May 30 02:43:39 PM PDT 24 49823654 ps
T635 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2068488886 May 30 02:44:45 PM PDT 24 May 30 02:44:47 PM PDT 24 36605312 ps
T636 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3411723129 May 30 02:43:51 PM PDT 24 May 30 02:43:54 PM PDT 24 51154449 ps
T99 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.4097814768 May 30 02:43:50 PM PDT 24 May 30 02:43:53 PM PDT 24 85623449 ps
T637 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1767535178 May 30 02:43:50 PM PDT 24 May 30 02:43:57 PM PDT 24 734515669 ps
T638 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3727811518 May 30 02:44:02 PM PDT 24 May 30 02:44:09 PM PDT 24 1294049953 ps
T100 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3579877823 May 30 02:43:27 PM PDT 24 May 30 02:43:28 PM PDT 24 21587821 ps
T639 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3885098454 May 30 02:44:31 PM PDT 24 May 30 02:44:35 PM PDT 24 314591828 ps
T640 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2227886784 May 30 02:44:31 PM PDT 24 May 30 02:44:35 PM PDT 24 83708847 ps
T641 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1328069088 May 30 02:44:31 PM PDT 24 May 30 02:44:33 PM PDT 24 50982269 ps
T642 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.4241635914 May 30 02:44:05 PM PDT 24 May 30 02:44:08 PM PDT 24 141486802 ps
T643 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3342715124 May 30 02:44:48 PM PDT 24 May 30 02:44:50 PM PDT 24 12722331 ps
T644 /workspace/coverage/cover_reg_top/3.hmac_intr_test.3532198791 May 30 02:43:38 PM PDT 24 May 30 02:43:40 PM PDT 24 18877633 ps
T645 /workspace/coverage/cover_reg_top/38.hmac_intr_test.117213107 May 30 02:44:46 PM PDT 24 May 30 02:44:47 PM PDT 24 12384051 ps
T646 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2667546286 May 30 02:44:31 PM PDT 24 May 30 02:44:33 PM PDT 24 58010592 ps
T647 /workspace/coverage/cover_reg_top/0.hmac_intr_test.854736413 May 30 02:43:13 PM PDT 24 May 30 02:43:14 PM PDT 24 48941087 ps
T101 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.958016045 May 30 02:43:52 PM PDT 24 May 30 02:43:56 PM PDT 24 300996288 ps
T130 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2638804927 May 30 02:43:37 PM PDT 24 May 30 02:43:40 PM PDT 24 140216129 ps
T648 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3732327362 May 30 02:43:38 PM PDT 24 May 30 02:43:41 PM PDT 24 34380919 ps
T129 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1432196891 May 30 02:43:15 PM PDT 24 May 30 02:43:20 PM PDT 24 866338203 ps
T649 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.331808236 May 30 02:44:03 PM PDT 24 May 30 02:44:05 PM PDT 24 11998287 ps
T135 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.45368250 May 30 02:44:02 PM PDT 24 May 30 02:44:09 PM PDT 24 232671081 ps
T650 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1130546436 May 30 02:44:14 PM PDT 24 May 30 02:44:17 PM PDT 24 85447039 ps
T651 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.4150624421 May 30 02:43:50 PM PDT 24 May 30 02:43:55 PM PDT 24 108958826 ps
T652 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3488254996 May 30 02:43:38 PM PDT 24 May 30 02:43:57 PM PDT 24 4373622209 ps
T653 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2132162280 May 30 02:43:51 PM PDT 24 May 30 02:43:54 PM PDT 24 182775228 ps
T654 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2046146772 May 30 02:43:26 PM PDT 24 May 30 02:43:28 PM PDT 24 73022025 ps
T655 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1996850514 May 30 02:44:05 PM PDT 24 May 30 02:44:09 PM PDT 24 404969641 ps
T656 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1168092928 May 30 02:44:48 PM PDT 24 May 30 02:44:51 PM PDT 24 14052722 ps
T657 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2046925192 May 30 02:44:15 PM PDT 24 May 30 02:44:18 PM PDT 24 850544816 ps
T658 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1992572436 May 30 02:43:49 PM PDT 24 May 30 02:43:57 PM PDT 24 711322504 ps
T659 /workspace/coverage/cover_reg_top/18.hmac_intr_test.154567684 May 30 02:44:31 PM PDT 24 May 30 02:44:32 PM PDT 24 12567824 ps
T660 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1547656225 May 30 02:43:52 PM PDT 24 May 30 02:43:55 PM PDT 24 83558002 ps
T661 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2514119150 May 30 02:44:45 PM PDT 24 May 30 02:44:47 PM PDT 24 14036721 ps
T662 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.441609316 May 30 02:44:01 PM PDT 24 May 30 02:44:03 PM PDT 24 350280252 ps
T663 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3744371858 May 30 02:43:49 PM PDT 24 May 30 02:43:52 PM PDT 24 49885698 ps
T131 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.244068084 May 30 02:44:13 PM PDT 24 May 30 02:44:17 PM PDT 24 348964310 ps
T664 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2224438528 May 30 02:43:26 PM PDT 24 May 30 02:43:30 PM PDT 24 53870674 ps
T665 /workspace/coverage/cover_reg_top/49.hmac_intr_test.1344871453 May 30 02:44:47 PM PDT 24 May 30 02:44:49 PM PDT 24 29168336 ps
T666 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3729080009 May 30 02:44:45 PM PDT 24 May 30 02:44:47 PM PDT 24 11262228 ps
T667 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1106300096 May 30 02:44:32 PM PDT 24 May 30 02:44:34 PM PDT 24 38887012 ps
T668 /workspace/coverage/cover_reg_top/32.hmac_intr_test.10259979 May 30 02:44:47 PM PDT 24 May 30 02:44:49 PM PDT 24 25738020 ps
T669 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1066571356 May 30 02:44:02 PM PDT 24 May 30 02:44:05 PM PDT 24 53126423 ps
T670 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1625697603 May 30 02:44:13 PM PDT 24 May 30 02:44:16 PM PDT 24 82632221 ps
T671 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3866507133 May 30 02:43:28 PM PDT 24 May 30 02:43:31 PM PDT 24 226217996 ps
T672 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.4134835642 May 30 02:44:18 PM PDT 24 May 30 02:44:20 PM PDT 24 39359105 ps
T673 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3584597403 May 30 02:44:01 PM PDT 24 May 30 02:44:05 PM PDT 24 96268621 ps
T674 /workspace/coverage/cover_reg_top/40.hmac_intr_test.8567973 May 30 02:44:46 PM PDT 24 May 30 02:44:48 PM PDT 24 46345214 ps
T128 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2651796187 May 30 02:43:50 PM PDT 24 May 30 02:43:55 PM PDT 24 356183033 ps
T675 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2632380521 May 30 02:44:14 PM PDT 24 May 30 02:44:15 PM PDT 24 36726832 ps
T676 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1583767085 May 30 02:44:02 PM PDT 24 May 30 02:44:05 PM PDT 24 1403779196 ps
T677 /workspace/coverage/cover_reg_top/36.hmac_intr_test.3261930354 May 30 02:44:46 PM PDT 24 May 30 02:44:47 PM PDT 24 13332939 ps
T678 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2103011292 May 30 02:43:50 PM PDT 24 May 30 02:43:54 PM PDT 24 108687025 ps
T132 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.470184864 May 30 02:44:15 PM PDT 24 May 30 02:44:19 PM PDT 24 1068694616 ps
T679 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1090912251 May 30 02:44:47 PM PDT 24 May 30 02:44:49 PM PDT 24 45609230 ps
T680 /workspace/coverage/cover_reg_top/31.hmac_intr_test.1233722280 May 30 02:44:33 PM PDT 24 May 30 02:44:35 PM PDT 24 15039494 ps
T681 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1837259981 May 30 02:44:32 PM PDT 24 May 30 02:44:34 PM PDT 24 14693933 ps
T682 /workspace/coverage/cover_reg_top/35.hmac_intr_test.367626693 May 30 02:44:47 PM PDT 24 May 30 02:44:49 PM PDT 24 13279311 ps
T137 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1671645145 May 30 02:43:25 PM PDT 24 May 30 02:43:27 PM PDT 24 231733009 ps
T683 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.4062744191 May 30 02:44:15 PM PDT 24 May 30 02:44:18 PM PDT 24 684852527 ps
T684 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1493366075 May 30 02:44:00 PM PDT 24 May 30 02:44:02 PM PDT 24 193183458 ps
T685 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.895063207 May 30 02:44:00 PM PDT 24 May 30 02:44:03 PM PDT 24 47881485 ps
T686 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3107507016 May 30 02:44:49 PM PDT 24 May 30 02:44:51 PM PDT 24 11572751 ps
T687 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.4105897605 May 30 02:44:14 PM PDT 24 May 30 02:44:17 PM PDT 24 510899165 ps
T688 /workspace/coverage/cover_reg_top/1.hmac_intr_test.2810337893 May 30 02:43:26 PM PDT 24 May 30 02:43:28 PM PDT 24 18917700 ps
T689 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1556916688 May 30 02:44:12 PM PDT 24 May 30 02:44:16 PM PDT 24 88402899 ps
T102 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1948360866 May 30 02:43:29 PM PDT 24 May 30 02:43:36 PM PDT 24 313473596 ps
T690 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2133655438 May 30 02:43:16 PM PDT 24 May 30 02:43:20 PM PDT 24 167544865 ps
T691 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2135252072 May 30 02:44:33 PM PDT 24 May 30 02:57:36 PM PDT 24 218450871664 ps
T692 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2194340286 May 30 02:43:49 PM PDT 24 May 30 02:43:53 PM PDT 24 213578590 ps
T693 /workspace/coverage/cover_reg_top/47.hmac_intr_test.394597779 May 30 02:44:47 PM PDT 24 May 30 02:44:50 PM PDT 24 27700312 ps
T103 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3062098794 May 30 02:43:49 PM PDT 24 May 30 02:43:59 PM PDT 24 558049814 ps
T694 /workspace/coverage/cover_reg_top/4.hmac_intr_test.322307628 May 30 02:43:51 PM PDT 24 May 30 02:43:54 PM PDT 24 77598891 ps
T133 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2973768184 May 30 02:44:01 PM PDT 24 May 30 02:44:05 PM PDT 24 211978155 ps
T695 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.610881260 May 30 02:43:54 PM PDT 24 May 30 02:43:58 PM PDT 24 182313824 ps
T104 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.854257503 May 30 02:44:01 PM PDT 24 May 30 02:44:04 PM PDT 24 78941708 ps
T105 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.482819633 May 30 02:44:13 PM PDT 24 May 30 02:44:15 PM PDT 24 63938623 ps
T106 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1460965936 May 30 02:43:37 PM PDT 24 May 30 02:43:44 PM PDT 24 304545423 ps
T108 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2756375284 May 30 02:43:25 PM PDT 24 May 30 02:43:26 PM PDT 24 65723291 ps
T109 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3714643683 May 30 02:43:37 PM PDT 24 May 30 02:43:39 PM PDT 24 22498660 ps
T696 /workspace/coverage/cover_reg_top/14.hmac_intr_test.230591208 May 30 02:44:14 PM PDT 24 May 30 02:44:15 PM PDT 24 12928260 ps
T697 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1239702725 May 30 02:44:05 PM PDT 24 May 30 02:44:06 PM PDT 24 13405436 ps
T698 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3524899906 May 30 02:44:32 PM PDT 24 May 30 02:44:35 PM PDT 24 33882939 ps
T699 /workspace/coverage/cover_reg_top/17.hmac_intr_test.943287068 May 30 02:44:33 PM PDT 24 May 30 02:44:35 PM PDT 24 41430895 ps
T700 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1644477869 May 30 02:44:14 PM PDT 24 May 30 02:44:19 PM PDT 24 185535173 ps
T107 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2593072433 May 30 02:43:26 PM PDT 24 May 30 02:43:40 PM PDT 24 9591555488 ps
T701 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3315173408 May 30 02:44:14 PM PDT 24 May 30 02:44:16 PM PDT 24 29887906 ps
T702 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1152235454 May 30 02:43:27 PM PDT 24 May 30 02:52:45 PM PDT 24 140196784993 ps
T703 /workspace/coverage/cover_reg_top/27.hmac_intr_test.3010878542 May 30 02:44:33 PM PDT 24 May 30 02:44:35 PM PDT 24 53468537 ps
T704 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1295258733 May 30 02:43:49 PM PDT 24 May 30 02:43:52 PM PDT 24 74081158 ps
T705 /workspace/coverage/cover_reg_top/30.hmac_intr_test.74802630 May 30 02:44:34 PM PDT 24 May 30 02:44:36 PM PDT 24 54804872 ps
T706 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2671164692 May 30 02:44:12 PM PDT 24 May 30 02:44:15 PM PDT 24 36970038 ps
T707 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2023545607 May 30 02:44:31 PM PDT 24 May 30 02:44:33 PM PDT 24 117044133 ps
T708 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.786795930 May 30 02:44:15 PM PDT 24 May 30 02:44:17 PM PDT 24 21998393 ps
T709 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3041381617 May 30 02:44:31 PM PDT 24 May 30 02:44:33 PM PDT 24 43145599 ps
T710 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.643264731 May 30 02:44:32 PM PDT 24 May 30 02:44:36 PM PDT 24 47782581 ps
T711 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2247503898 May 30 02:43:28 PM PDT 24 May 30 02:43:30 PM PDT 24 43302896 ps
T712 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.743515346 May 30 02:43:50 PM PDT 24 May 30 02:43:53 PM PDT 24 133428901 ps
T713 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1285995087 May 30 02:44:03 PM PDT 24 May 30 02:44:06 PM PDT 24 23223200 ps
T714 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1600205110 May 30 02:44:14 PM PDT 24 May 30 02:44:17 PM PDT 24 86809502 ps
T715 /workspace/coverage/cover_reg_top/6.hmac_intr_test.954842722 May 30 02:43:53 PM PDT 24 May 30 02:43:56 PM PDT 24 29461013 ps
T716 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3661719189 May 30 02:43:37 PM PDT 24 May 30 02:43:55 PM PDT 24 2107179111 ps
T717 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.4090679006 May 30 02:44:01 PM PDT 24 May 30 02:44:04 PM PDT 24 625652505 ps
T718 /workspace/coverage/cover_reg_top/7.hmac_intr_test.426805776 May 30 02:43:51 PM PDT 24 May 30 02:43:54 PM PDT 24 14536335 ps
T719 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2884505578 May 30 02:44:12 PM PDT 24 May 30 02:44:14 PM PDT 24 17614554 ps
T720 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1414007045 May 30 02:44:33 PM PDT 24 May 30 02:44:35 PM PDT 24 12175270 ps
T721 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2019881391 May 30 02:44:14 PM PDT 24 May 30 02:44:17 PM PDT 24 58293304 ps
T722 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2167671217 May 30 02:44:00 PM PDT 24 May 30 02:44:03 PM PDT 24 38354604 ps
T723 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2404325126 May 30 02:44:03 PM PDT 24 May 30 02:44:05 PM PDT 24 20872409 ps
T724 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2842159326 May 30 02:43:50 PM PDT 24 May 30 02:43:57 PM PDT 24 336867812 ps

Test location /workspace/coverage/default/44.hmac_burst_wr.2046847197
Short name T5
Test name
Test status
Simulation time 3808444274 ps
CPU time 74.9 seconds
Started May 30 02:53:00 PM PDT 24
Finished May 30 02:54:17 PM PDT 24
Peak memory 200060 kb
Host smart-318f74c0-6785-4f8d-9de2-337b0e61b76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046847197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2046847197
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.3382462656
Short name T11
Test name
Test status
Simulation time 10965353856 ps
CPU time 556.75 seconds
Started May 30 02:50:09 PM PDT 24
Finished May 30 02:59:28 PM PDT 24
Peak memory 214052 kb
Host smart-81b04751-301b-4784-a6e2-06b0e820f8dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3382462656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.3382462656
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2836604995
Short name T17
Test name
Test status
Simulation time 13570479059 ps
CPU time 2225.79 seconds
Started May 30 02:53:02 PM PDT 24
Finished May 30 03:30:09 PM PDT 24
Peak memory 814176 kb
Host smart-871c5300-256b-42a1-bcfe-e4f3b86d690e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836604995 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2836604995
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3032952661
Short name T31
Test name
Test status
Simulation time 87032004 ps
CPU time 1.01 seconds
Started May 30 02:49:56 PM PDT 24
Finished May 30 02:49:59 PM PDT 24
Peak memory 219268 kb
Host smart-16d72418-4134-4bd0-8e87-95cec292e062
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032952661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3032952661
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1800252813
Short name T55
Test name
Test status
Simulation time 88298990 ps
CPU time 1.79 seconds
Started May 30 02:44:12 PM PDT 24
Finished May 30 02:44:15 PM PDT 24
Peak memory 199824 kb
Host smart-a2bad6c8-566b-4bb2-8022-f793d3841830
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800252813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1800252813
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/73.hmac_stress_all_with_rand_reset.2023835201
Short name T13
Test name
Test status
Simulation time 71841974948 ps
CPU time 1277.18 seconds
Started May 30 02:53:47 PM PDT 24
Finished May 30 03:15:06 PM PDT 24
Peak memory 581992 kb
Host smart-c5294f9e-0d54-46f6-a3a3-295694d7e920
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2023835201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.hmac_stress_all_with_rand_reset.2023835201
Directory /workspace/73.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3933175847
Short name T19
Test name
Test status
Simulation time 1190713046 ps
CPU time 31.37 seconds
Started May 30 02:52:32 PM PDT 24
Finished May 30 02:53:05 PM PDT 24
Peak memory 225588 kb
Host smart-9ad568d7-a88f-450a-a63e-c8cf60b4739d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3933175847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3933175847
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3579877823
Short name T100
Test name
Test status
Simulation time 21587821 ps
CPU time 0.8 seconds
Started May 30 02:43:27 PM PDT 24
Finished May 30 02:43:28 PM PDT 24
Peak memory 197664 kb
Host smart-3c51ae04-63f1-4859-98b2-b650869002f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579877823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3579877823
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3030157913
Short name T56
Test name
Test status
Simulation time 2980741759 ps
CPU time 3.25 seconds
Started May 30 02:44:02 PM PDT 24
Finished May 30 02:44:07 PM PDT 24
Peak memory 199868 kb
Host smart-9cc55c0a-9ac8-4884-bef2-72e8706168ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030157913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3030157913
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1992108717
Short name T81
Test name
Test status
Simulation time 2467718660810 ps
CPU time 3167.11 seconds
Started May 30 02:51:09 PM PDT 24
Finished May 30 03:43:58 PM PDT 24
Peak memory 783492 kb
Host smart-80931f37-d72a-484e-a155-e33d8238c5b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992108717 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1992108717
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3920551382
Short name T428
Test name
Test status
Simulation time 116584711170 ps
CPU time 1565.63 seconds
Started May 30 02:50:47 PM PDT 24
Finished May 30 03:16:55 PM PDT 24
Peak memory 703560 kb
Host smart-e799eeaa-819a-49ef-8ad4-846017d8647e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920551382 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3920551382
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2998899708
Short name T165
Test name
Test status
Simulation time 11839783 ps
CPU time 0.57 seconds
Started May 30 02:50:21 PM PDT 24
Finished May 30 02:50:23 PM PDT 24
Peak memory 194984 kb
Host smart-607cbce0-4892-477c-ba9d-ef88f5e36c96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998899708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2998899708
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1318470916
Short name T117
Test name
Test status
Simulation time 17180491916 ps
CPU time 1798.51 seconds
Started May 30 02:53:37 PM PDT 24
Finished May 30 03:23:39 PM PDT 24
Peak memory 749200 kb
Host smart-94981a93-c91b-4fff-8ec9-add3d65065dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318470916 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1318470916
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2443049981
Short name T4
Test name
Test status
Simulation time 2729167370 ps
CPU time 8.94 seconds
Started May 30 02:51:34 PM PDT 24
Finished May 30 02:51:44 PM PDT 24
Peak memory 200112 kb
Host smart-dfd21972-f1fc-4ec8-b69c-c6e15c99381d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443049981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2443049981
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1644477869
Short name T700
Test name
Test status
Simulation time 185535173 ps
CPU time 3.29 seconds
Started May 30 02:44:14 PM PDT 24
Finished May 30 02:44:19 PM PDT 24
Peak memory 199908 kb
Host smart-7591558e-32e8-4ca2-b374-fe1b4863d559
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644477869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1644477869
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1671645145
Short name T137
Test name
Test status
Simulation time 231733009 ps
CPU time 1.84 seconds
Started May 30 02:43:25 PM PDT 24
Finished May 30 02:43:27 PM PDT 24
Peak memory 199884 kb
Host smart-5dfa365d-fe9a-46d9-96d6-38d1645d0262
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671645145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1671645145
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.470184864
Short name T132
Test name
Test status
Simulation time 1068694616 ps
CPU time 3.23 seconds
Started May 30 02:44:15 PM PDT 24
Finished May 30 02:44:19 PM PDT 24
Peak memory 199724 kb
Host smart-0213d6c7-21bb-427c-b812-6555942a31ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470184864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.470184864
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3898014096
Short name T390
Test name
Test status
Simulation time 115039129933 ps
CPU time 2227.98 seconds
Started May 30 02:50:22 PM PDT 24
Finished May 30 03:27:32 PM PDT 24
Peak memory 751572 kb
Host smart-c8bf16dc-ef90-4e9c-90fc-a74b7022e5a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898014096 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3898014096
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.523151545
Short name T609
Test name
Test status
Simulation time 300673944 ps
CPU time 6.04 seconds
Started May 30 02:43:27 PM PDT 24
Finished May 30 02:43:34 PM PDT 24
Peak memory 199704 kb
Host smart-68d06a40-595a-4eb4-ab8a-63d1be5cf11d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523151545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.523151545
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.534036718
Short name T64
Test name
Test status
Simulation time 2226532578 ps
CPU time 5.66 seconds
Started May 30 02:43:26 PM PDT 24
Finished May 30 02:43:33 PM PDT 24
Peak memory 199928 kb
Host smart-13334b48-a62a-4f01-a509-c6ccda7153b6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534036718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.534036718
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3866507133
Short name T671
Test name
Test status
Simulation time 226217996 ps
CPU time 1.96 seconds
Started May 30 02:43:28 PM PDT 24
Finished May 30 02:43:31 PM PDT 24
Peak memory 199872 kb
Host smart-fe3ff01b-5bd4-4097-b319-5902d541ca4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866507133 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.3866507133
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2345711532
Short name T617
Test name
Test status
Simulation time 136590228 ps
CPU time 0.98 seconds
Started May 30 02:43:29 PM PDT 24
Finished May 30 02:43:31 PM PDT 24
Peak memory 199512 kb
Host smart-256ef714-8834-4d78-9956-82ebbcca356e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345711532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2345711532
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.854736413
Short name T647
Test name
Test status
Simulation time 48941087 ps
CPU time 0.58 seconds
Started May 30 02:43:13 PM PDT 24
Finished May 30 02:43:14 PM PDT 24
Peak memory 194584 kb
Host smart-c7413824-e0d1-4625-95b3-084728f1a55b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854736413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.854736413
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2247503898
Short name T711
Test name
Test status
Simulation time 43302896 ps
CPU time 1.1 seconds
Started May 30 02:43:28 PM PDT 24
Finished May 30 02:43:30 PM PDT 24
Peak memory 199284 kb
Host smart-9cde9ca3-2df2-4541-bd99-38bdb71973bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247503898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2247503898
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2133655438
Short name T690
Test name
Test status
Simulation time 167544865 ps
CPU time 2.45 seconds
Started May 30 02:43:16 PM PDT 24
Finished May 30 02:43:20 PM PDT 24
Peak memory 199868 kb
Host smart-1d798669-a6a2-4c8a-9e4b-1dcb7cf20d66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133655438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2133655438
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1432196891
Short name T129
Test name
Test status
Simulation time 866338203 ps
CPU time 3.11 seconds
Started May 30 02:43:15 PM PDT 24
Finished May 30 02:43:20 PM PDT 24
Peak memory 199832 kb
Host smart-19442673-f782-4665-91cf-4350b445b385
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432196891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1432196891
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1948360866
Short name T102
Test name
Test status
Simulation time 313473596 ps
CPU time 6.08 seconds
Started May 30 02:43:29 PM PDT 24
Finished May 30 02:43:36 PM PDT 24
Peak memory 199852 kb
Host smart-70641443-bb63-428f-b49e-75f9ff5c76fd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948360866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1948360866
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2593072433
Short name T107
Test name
Test status
Simulation time 9591555488 ps
CPU time 12.63 seconds
Started May 30 02:43:26 PM PDT 24
Finished May 30 02:43:40 PM PDT 24
Peak memory 199908 kb
Host smart-f3a73481-f7a7-4345-856e-106e72c2561d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593072433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2593072433
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2046146772
Short name T654
Test name
Test status
Simulation time 73022025 ps
CPU time 1.01 seconds
Started May 30 02:43:26 PM PDT 24
Finished May 30 02:43:28 PM PDT 24
Peak memory 199632 kb
Host smart-2132ab7f-caf7-4f8b-a478-c21c4fc87719
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046146772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2046146772
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1152235454
Short name T702
Test name
Test status
Simulation time 140196784993 ps
CPU time 556.67 seconds
Started May 30 02:43:27 PM PDT 24
Finished May 30 02:52:45 PM PDT 24
Peak memory 216348 kb
Host smart-fd1d8685-faba-46de-b59d-df7d3e6fb163
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152235454 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1152235454
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2756375284
Short name T108
Test name
Test status
Simulation time 65723291 ps
CPU time 0.86 seconds
Started May 30 02:43:25 PM PDT 24
Finished May 30 02:43:26 PM PDT 24
Peak memory 199632 kb
Host smart-f39d423b-ea25-40f1-9d0e-371fb9d05b90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756375284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2756375284
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2810337893
Short name T688
Test name
Test status
Simulation time 18917700 ps
CPU time 0.64 seconds
Started May 30 02:43:26 PM PDT 24
Finished May 30 02:43:28 PM PDT 24
Peak memory 194636 kb
Host smart-d182bb5d-457c-40f7-86e0-a01bf33e886c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810337893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2810337893
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2124520302
Short name T60
Test name
Test status
Simulation time 159455147 ps
CPU time 1.11 seconds
Started May 30 02:43:29 PM PDT 24
Finished May 30 02:43:31 PM PDT 24
Peak memory 198476 kb
Host smart-44db7990-a0a6-4aee-8770-2711aa10cebc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124520302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2124520302
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.623897978
Short name T607
Test name
Test status
Simulation time 1357434593 ps
CPU time 3.95 seconds
Started May 30 02:43:28 PM PDT 24
Finished May 30 02:43:33 PM PDT 24
Peak memory 199840 kb
Host smart-1dce1215-22bf-4d90-8cad-d779e96f1a1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623897978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.623897978
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.4241635914
Short name T642
Test name
Test status
Simulation time 141486802 ps
CPU time 1.24 seconds
Started May 30 02:44:05 PM PDT 24
Finished May 30 02:44:08 PM PDT 24
Peak memory 199724 kb
Host smart-76553c65-9373-4e7e-9620-9a1b756065c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241635914 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.4241635914
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2404325126
Short name T723
Test name
Test status
Simulation time 20872409 ps
CPU time 0.73 seconds
Started May 30 02:44:03 PM PDT 24
Finished May 30 02:44:05 PM PDT 24
Peak memory 197640 kb
Host smart-82cc7913-c252-464c-96c6-7485a53088e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404325126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2404325126
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1239702725
Short name T697
Test name
Test status
Simulation time 13405436 ps
CPU time 0.6 seconds
Started May 30 02:44:05 PM PDT 24
Finished May 30 02:44:06 PM PDT 24
Peak memory 194672 kb
Host smart-f30b4460-8a6d-4915-9ddb-67a1a84a7a80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239702725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1239702725
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3316295938
Short name T622
Test name
Test status
Simulation time 38967064 ps
CPU time 1.76 seconds
Started May 30 02:44:03 PM PDT 24
Finished May 30 02:44:06 PM PDT 24
Peak memory 199828 kb
Host smart-596451ed-3bb8-4981-b03c-433bca371dbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316295938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.3316295938
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.478742308
Short name T611
Test name
Test status
Simulation time 102617824 ps
CPU time 1.86 seconds
Started May 30 02:44:02 PM PDT 24
Finished May 30 02:44:05 PM PDT 24
Peak memory 199880 kb
Host smart-928e36b3-f298-45a4-b683-14ae73a0d21d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478742308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.478742308
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.45368250
Short name T135
Test name
Test status
Simulation time 232671081 ps
CPU time 4.25 seconds
Started May 30 02:44:02 PM PDT 24
Finished May 30 02:44:09 PM PDT 24
Peak memory 199864 kb
Host smart-085ede28-e3ac-4b32-ae26-d8e9325b658b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45368250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.45368250
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3231175280
Short name T83
Test name
Test status
Simulation time 77642459 ps
CPU time 1.18 seconds
Started May 30 02:44:01 PM PDT 24
Finished May 30 02:44:04 PM PDT 24
Peak memory 199620 kb
Host smart-2fa6cbdb-647e-4fab-a1b5-21f0a47d138c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231175280 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.3231175280
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1285995087
Short name T713
Test name
Test status
Simulation time 23223200 ps
CPU time 0.93 seconds
Started May 30 02:44:03 PM PDT 24
Finished May 30 02:44:06 PM PDT 24
Peak memory 199208 kb
Host smart-6e7931a9-2af9-4d8f-913d-40973e941504
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285995087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1285995087
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2368260671
Short name T600
Test name
Test status
Simulation time 138065378 ps
CPU time 0.62 seconds
Started May 30 02:44:02 PM PDT 24
Finished May 30 02:44:04 PM PDT 24
Peak memory 194640 kb
Host smart-742e5fd4-838e-4e91-b852-60a92087a3d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368260671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2368260671
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.4090679006
Short name T717
Test name
Test status
Simulation time 625652505 ps
CPU time 1.12 seconds
Started May 30 02:44:01 PM PDT 24
Finished May 30 02:44:04 PM PDT 24
Peak memory 199896 kb
Host smart-c2343e1e-bc76-4dd1-9cdd-40323b72c622
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090679006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.4090679006
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1493366075
Short name T684
Test name
Test status
Simulation time 193183458 ps
CPU time 1.35 seconds
Started May 30 02:44:00 PM PDT 24
Finished May 30 02:44:02 PM PDT 24
Peak memory 199888 kb
Host smart-0e48316f-98da-4c77-b34b-ca20ece5c654
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493366075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1493366075
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.115979976
Short name T621
Test name
Test status
Simulation time 63946736 ps
CPU time 2.51 seconds
Started May 30 02:44:14 PM PDT 24
Finished May 30 02:44:18 PM PDT 24
Peak memory 208084 kb
Host smart-76d0f945-ded5-496c-893c-f1129a9c9da4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115979976 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.115979976
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.482819633
Short name T105
Test name
Test status
Simulation time 63938623 ps
CPU time 0.98 seconds
Started May 30 02:44:13 PM PDT 24
Finished May 30 02:44:15 PM PDT 24
Peak memory 199372 kb
Host smart-61776696-3197-42d3-adf4-06c0726966f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482819633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.482819633
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1066571356
Short name T669
Test name
Test status
Simulation time 53126423 ps
CPU time 0.66 seconds
Started May 30 02:44:02 PM PDT 24
Finished May 30 02:44:05 PM PDT 24
Peak memory 194680 kb
Host smart-852243b5-7e71-4d88-84ad-b97903736760
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066571356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1066571356
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.4105897605
Short name T687
Test name
Test status
Simulation time 510899165 ps
CPU time 2.35 seconds
Started May 30 02:44:14 PM PDT 24
Finished May 30 02:44:17 PM PDT 24
Peak memory 199844 kb
Host smart-eaf4f588-426d-4913-8436-b7f43986013d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105897605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.4105897605
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1996850514
Short name T655
Test name
Test status
Simulation time 404969641 ps
CPU time 3.53 seconds
Started May 30 02:44:05 PM PDT 24
Finished May 30 02:44:09 PM PDT 24
Peak memory 199864 kb
Host smart-5a7d7537-ec3b-4203-a0e2-702dbae28587
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996850514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1996850514
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3727811518
Short name T638
Test name
Test status
Simulation time 1294049953 ps
CPU time 4.66 seconds
Started May 30 02:44:02 PM PDT 24
Finished May 30 02:44:09 PM PDT 24
Peak memory 199832 kb
Host smart-dd268434-0607-444f-8763-826b8acaaff6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727811518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3727811518
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1625697603
Short name T670
Test name
Test status
Simulation time 82632221 ps
CPU time 1.95 seconds
Started May 30 02:44:13 PM PDT 24
Finished May 30 02:44:16 PM PDT 24
Peak memory 199948 kb
Host smart-365b7033-4b14-4449-a718-1b22c46af9b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625697603 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1625697603
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.786795930
Short name T708
Test name
Test status
Simulation time 21998393 ps
CPU time 0.71 seconds
Started May 30 02:44:15 PM PDT 24
Finished May 30 02:44:17 PM PDT 24
Peak memory 197604 kb
Host smart-afd04671-ea96-4010-a3f4-2eac23c7dbba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786795930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.786795930
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3322805884
Short name T627
Test name
Test status
Simulation time 31577034 ps
CPU time 0.57 seconds
Started May 30 02:44:17 PM PDT 24
Finished May 30 02:44:19 PM PDT 24
Peak memory 194580 kb
Host smart-6f3543c2-921e-4cf1-abe1-ff2ee437944b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322805884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3322805884
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.4062744191
Short name T683
Test name
Test status
Simulation time 684852527 ps
CPU time 1.66 seconds
Started May 30 02:44:15 PM PDT 24
Finished May 30 02:44:18 PM PDT 24
Peak memory 199904 kb
Host smart-caf73d3a-d2fc-40f8-a803-be8530dd685d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062744191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.4062744191
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.119809816
Short name T65
Test name
Test status
Simulation time 178863820 ps
CPU time 1.73 seconds
Started May 30 02:44:13 PM PDT 24
Finished May 30 02:44:16 PM PDT 24
Peak memory 199900 kb
Host smart-bc67a598-9dc9-4e06-a332-3624568da85b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119809816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.119809816
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.925260096
Short name T134
Test name
Test status
Simulation time 880583383 ps
CPU time 3.19 seconds
Started May 30 02:44:13 PM PDT 24
Finished May 30 02:44:17 PM PDT 24
Peak memory 199892 kb
Host smart-18a17c5d-6009-4ccd-8212-8f209bab025f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925260096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.925260096
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.457855549
Short name T66
Test name
Test status
Simulation time 564663527947 ps
CPU time 952.01 seconds
Started May 30 02:44:18 PM PDT 24
Finished May 30 03:00:11 PM PDT 24
Peak memory 216344 kb
Host smart-f7b39e02-660d-4252-95ba-c82b43083003
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457855549 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.457855549
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2705801349
Short name T96
Test name
Test status
Simulation time 27853444 ps
CPU time 0.77 seconds
Started May 30 02:44:15 PM PDT 24
Finished May 30 02:44:17 PM PDT 24
Peak memory 198808 kb
Host smart-9efc2fd3-6605-45f4-b4a7-d8d2594c2bcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705801349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2705801349
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.230591208
Short name T696
Test name
Test status
Simulation time 12928260 ps
CPU time 0.57 seconds
Started May 30 02:44:14 PM PDT 24
Finished May 30 02:44:15 PM PDT 24
Peak memory 194580 kb
Host smart-f776f4bd-1d6c-45cd-b6f0-65b63853ccee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230591208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.230591208
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.4134835642
Short name T672
Test name
Test status
Simulation time 39359105 ps
CPU time 1.09 seconds
Started May 30 02:44:18 PM PDT 24
Finished May 30 02:44:20 PM PDT 24
Peak memory 199804 kb
Host smart-f8644c61-b894-4e8b-9858-5d9bc7fc496f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134835642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.4134835642
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2046925192
Short name T657
Test name
Test status
Simulation time 850544816 ps
CPU time 2.75 seconds
Started May 30 02:44:15 PM PDT 24
Finished May 30 02:44:18 PM PDT 24
Peak memory 199900 kb
Host smart-47f33fd0-e60a-4976-aa57-45d80233a636
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046925192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2046925192
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.691741527
Short name T68
Test name
Test status
Simulation time 610029901 ps
CPU time 1.65 seconds
Started May 30 02:44:16 PM PDT 24
Finished May 30 02:44:19 PM PDT 24
Peak memory 199836 kb
Host smart-00361db5-3b60-481e-80ca-6b289b294ea1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691741527 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.691741527
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2884505578
Short name T719
Test name
Test status
Simulation time 17614554 ps
CPU time 0.7 seconds
Started May 30 02:44:12 PM PDT 24
Finished May 30 02:44:14 PM PDT 24
Peak memory 197348 kb
Host smart-72de2fb3-6268-4356-9c74-67e57220a1cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884505578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2884505578
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2632380521
Short name T675
Test name
Test status
Simulation time 36726832 ps
CPU time 0.6 seconds
Started May 30 02:44:14 PM PDT 24
Finished May 30 02:44:15 PM PDT 24
Peak memory 194688 kb
Host smart-322083ce-f3a1-45d9-8fa4-675976d8465f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632380521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2632380521
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3121387024
Short name T620
Test name
Test status
Simulation time 192471272 ps
CPU time 1.15 seconds
Started May 30 02:44:15 PM PDT 24
Finished May 30 02:44:17 PM PDT 24
Peak memory 199792 kb
Host smart-04a05206-86f2-4293-80bf-3c18e7d3241e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121387024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3121387024
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1130546436
Short name T650
Test name
Test status
Simulation time 85447039 ps
CPU time 1.88 seconds
Started May 30 02:44:14 PM PDT 24
Finished May 30 02:44:17 PM PDT 24
Peak memory 199892 kb
Host smart-76e60a01-4731-46a1-a447-cc39d89bd13f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130546436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1130546436
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2019881391
Short name T721
Test name
Test status
Simulation time 58293304 ps
CPU time 1.09 seconds
Started May 30 02:44:14 PM PDT 24
Finished May 30 02:44:17 PM PDT 24
Peak memory 199692 kb
Host smart-28943ae3-a040-4ad4-8bad-df3bac60ecc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019881391 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2019881391
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3315173408
Short name T701
Test name
Test status
Simulation time 29887906 ps
CPU time 0.92 seconds
Started May 30 02:44:14 PM PDT 24
Finished May 30 02:44:16 PM PDT 24
Peak memory 199440 kb
Host smart-3eafc2c2-d7b7-4387-b105-ee10a8bc8719
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315173408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3315173408
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3819815948
Short name T603
Test name
Test status
Simulation time 124348734 ps
CPU time 0.58 seconds
Started May 30 02:44:14 PM PDT 24
Finished May 30 02:44:16 PM PDT 24
Peak memory 194680 kb
Host smart-addec9b1-994b-47e5-add0-013a750ccc54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819815948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3819815948
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1556916688
Short name T689
Test name
Test status
Simulation time 88402899 ps
CPU time 2.29 seconds
Started May 30 02:44:12 PM PDT 24
Finished May 30 02:44:16 PM PDT 24
Peak memory 199852 kb
Host smart-35c5812f-3015-436c-b497-3e78d382d08c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556916688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1556916688
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2671164692
Short name T706
Test name
Test status
Simulation time 36970038 ps
CPU time 1.75 seconds
Started May 30 02:44:12 PM PDT 24
Finished May 30 02:44:15 PM PDT 24
Peak memory 199896 kb
Host smart-176b64bc-0282-467a-ade8-88994e533003
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671164692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2671164692
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2135252072
Short name T691
Test name
Test status
Simulation time 218450871664 ps
CPU time 781.57 seconds
Started May 30 02:44:33 PM PDT 24
Finished May 30 02:57:36 PM PDT 24
Peak memory 216356 kb
Host smart-4bd97178-f69c-4b61-9858-9ed6e15d3f48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135252072 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2135252072
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1414007045
Short name T720
Test name
Test status
Simulation time 12175270 ps
CPU time 0.68 seconds
Started May 30 02:44:33 PM PDT 24
Finished May 30 02:44:35 PM PDT 24
Peak memory 197636 kb
Host smart-a4136d3d-0c95-4211-b5c9-ad646e51acdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414007045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1414007045
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.943287068
Short name T699
Test name
Test status
Simulation time 41430895 ps
CPU time 0.59 seconds
Started May 30 02:44:33 PM PDT 24
Finished May 30 02:44:35 PM PDT 24
Peak memory 194584 kb
Host smart-a37d196c-61b1-4e77-ac50-a2873647cb15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943287068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.943287068
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.641995242
Short name T629
Test name
Test status
Simulation time 334407538 ps
CPU time 2.56 seconds
Started May 30 02:44:31 PM PDT 24
Finished May 30 02:44:35 PM PDT 24
Peak memory 199752 kb
Host smart-246aaa19-cad5-40f0-80f4-c4cd548b1cc7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641995242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr
_outstanding.641995242
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1600205110
Short name T714
Test name
Test status
Simulation time 86809502 ps
CPU time 1.84 seconds
Started May 30 02:44:14 PM PDT 24
Finished May 30 02:44:17 PM PDT 24
Peak memory 200032 kb
Host smart-ce2c7f71-3665-4f86-aeef-7975ba5efcd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600205110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1600205110
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.244068084
Short name T131
Test name
Test status
Simulation time 348964310 ps
CPU time 2.99 seconds
Started May 30 02:44:13 PM PDT 24
Finished May 30 02:44:17 PM PDT 24
Peak memory 199852 kb
Host smart-3d09973b-7ea2-4d66-bc66-d89dfa90d65c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244068084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.244068084
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2227886784
Short name T640
Test name
Test status
Simulation time 83708847 ps
CPU time 3.02 seconds
Started May 30 02:44:31 PM PDT 24
Finished May 30 02:44:35 PM PDT 24
Peak memory 199928 kb
Host smart-28468589-e992-47aa-a16c-9234fc3db794
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227886784 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2227886784
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2023545607
Short name T707
Test name
Test status
Simulation time 117044133 ps
CPU time 0.97 seconds
Started May 30 02:44:31 PM PDT 24
Finished May 30 02:44:33 PM PDT 24
Peak memory 199544 kb
Host smart-f3279e1c-d94f-41c7-9a7f-724c517872e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023545607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2023545607
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.154567684
Short name T659
Test name
Test status
Simulation time 12567824 ps
CPU time 0.59 seconds
Started May 30 02:44:31 PM PDT 24
Finished May 30 02:44:32 PM PDT 24
Peak memory 194680 kb
Host smart-75b38870-708b-4a10-8798-5e18cf77aea7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154567684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.154567684
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3314085720
Short name T606
Test name
Test status
Simulation time 77166455 ps
CPU time 1.72 seconds
Started May 30 02:44:33 PM PDT 24
Finished May 30 02:44:36 PM PDT 24
Peak memory 199648 kb
Host smart-57516331-379d-4b09-8ba2-6384fe9a0c67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314085720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3314085720
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3524899906
Short name T698
Test name
Test status
Simulation time 33882939 ps
CPU time 1.75 seconds
Started May 30 02:44:32 PM PDT 24
Finished May 30 02:44:35 PM PDT 24
Peak memory 199916 kb
Host smart-350228d2-cc55-4554-a9ba-cb62545c27d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524899906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3524899906
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3885098454
Short name T639
Test name
Test status
Simulation time 314591828 ps
CPU time 3.07 seconds
Started May 30 02:44:31 PM PDT 24
Finished May 30 02:44:35 PM PDT 24
Peak memory 199844 kb
Host smart-4a45ad16-a134-4a29-92ac-94ba7ff30f02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885098454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3885098454
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2516227948
Short name T633
Test name
Test status
Simulation time 21194770394 ps
CPU time 109.94 seconds
Started May 30 02:44:31 PM PDT 24
Finished May 30 02:46:22 PM PDT 24
Peak memory 215596 kb
Host smart-1da3f82f-ba30-4b61-b462-e427d0be14e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516227948 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.2516227948
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2667546286
Short name T646
Test name
Test status
Simulation time 58010592 ps
CPU time 0.69 seconds
Started May 30 02:44:31 PM PDT 24
Finished May 30 02:44:33 PM PDT 24
Peak memory 197656 kb
Host smart-6f18cabd-7767-483e-ac52-0751bb110a6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667546286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2667546286
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1328069088
Short name T641
Test name
Test status
Simulation time 50982269 ps
CPU time 0.7 seconds
Started May 30 02:44:31 PM PDT 24
Finished May 30 02:44:33 PM PDT 24
Peak memory 194564 kb
Host smart-f29c018d-77fc-4bbe-9c51-d1fa0da76e6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328069088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1328069088
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.4154015392
Short name T604
Test name
Test status
Simulation time 120653018 ps
CPU time 2.36 seconds
Started May 30 02:44:32 PM PDT 24
Finished May 30 02:44:35 PM PDT 24
Peak memory 199840 kb
Host smart-a36ac074-6e1f-4091-bf8c-4c0117101ad0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154015392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.4154015392
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.643264731
Short name T710
Test name
Test status
Simulation time 47782581 ps
CPU time 2.47 seconds
Started May 30 02:44:32 PM PDT 24
Finished May 30 02:44:36 PM PDT 24
Peak memory 199860 kb
Host smart-eea1ffbd-c710-4e72-8cff-ba7a061694fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643264731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.643264731
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3760573258
Short name T127
Test name
Test status
Simulation time 159241413 ps
CPU time 2.97 seconds
Started May 30 02:44:31 PM PDT 24
Finished May 30 02:44:35 PM PDT 24
Peak memory 199852 kb
Host smart-9878c1a2-2fbf-4885-a407-9b19c0d47607
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760573258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3760573258
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1460965936
Short name T106
Test name
Test status
Simulation time 304545423 ps
CPU time 6.08 seconds
Started May 30 02:43:37 PM PDT 24
Finished May 30 02:43:44 PM PDT 24
Peak memory 199856 kb
Host smart-9893d3b4-7537-41bd-a04b-13040e4071fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460965936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1460965936
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3661719189
Short name T716
Test name
Test status
Simulation time 2107179111 ps
CPU time 15.76 seconds
Started May 30 02:43:37 PM PDT 24
Finished May 30 02:43:55 PM PDT 24
Peak memory 199788 kb
Host smart-224f5862-080f-4a4b-b1cc-2eddc4da1016
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661719189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3661719189
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3916632036
Short name T628
Test name
Test status
Simulation time 260510445 ps
CPU time 0.89 seconds
Started May 30 02:43:38 PM PDT 24
Finished May 30 02:43:41 PM PDT 24
Peak memory 199104 kb
Host smart-65f97297-190b-46c9-a16d-ee8f1f0778bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916632036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3916632036
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2439487907
Short name T63
Test name
Test status
Simulation time 112953540 ps
CPU time 2.68 seconds
Started May 30 02:43:39 PM PDT 24
Finished May 30 02:43:43 PM PDT 24
Peak memory 215388 kb
Host smart-9d0b4015-02cf-4a17-bd6c-6a1293e3625f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439487907 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2439487907
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3802774427
Short name T98
Test name
Test status
Simulation time 49823654 ps
CPU time 0.85 seconds
Started May 30 02:43:37 PM PDT 24
Finished May 30 02:43:39 PM PDT 24
Peak memory 199236 kb
Host smart-09a2f66d-fb03-4322-b02c-c2d12c8cd22d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802774427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.3802774427
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2356907140
Short name T634
Test name
Test status
Simulation time 11862353 ps
CPU time 0.63 seconds
Started May 30 02:43:36 PM PDT 24
Finished May 30 02:43:38 PM PDT 24
Peak memory 194584 kb
Host smart-dd7a9c22-29da-4969-994b-3227dafd6564
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356907140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2356907140
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3732327362
Short name T648
Test name
Test status
Simulation time 34380919 ps
CPU time 1.68 seconds
Started May 30 02:43:38 PM PDT 24
Finished May 30 02:43:41 PM PDT 24
Peak memory 199656 kb
Host smart-585d0c27-c347-4408-aaa8-17eab476be08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732327362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3732327362
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2224438528
Short name T664
Test name
Test status
Simulation time 53870674 ps
CPU time 2.87 seconds
Started May 30 02:43:26 PM PDT 24
Finished May 30 02:43:30 PM PDT 24
Peak memory 199868 kb
Host smart-93b33784-5384-4d63-879c-28365d8727ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224438528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2224438528
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2411249021
Short name T136
Test name
Test status
Simulation time 751378873 ps
CPU time 3.24 seconds
Started May 30 02:43:28 PM PDT 24
Finished May 30 02:43:32 PM PDT 24
Peak memory 199788 kb
Host smart-4a77051f-ca05-40a3-aa6d-3ffbcebb7339
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411249021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2411249021
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.4189049398
Short name T614
Test name
Test status
Simulation time 22318530 ps
CPU time 0.62 seconds
Started May 30 02:44:32 PM PDT 24
Finished May 30 02:44:34 PM PDT 24
Peak memory 194692 kb
Host smart-3f716176-dc41-43bc-8f38-6aa7e553f662
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189049398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.4189049398
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1837259981
Short name T681
Test name
Test status
Simulation time 14693933 ps
CPU time 0.62 seconds
Started May 30 02:44:32 PM PDT 24
Finished May 30 02:44:34 PM PDT 24
Peak memory 194640 kb
Host smart-4ee1bace-ee9b-439b-ba78-d1706e55d3e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837259981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1837259981
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3041381617
Short name T709
Test name
Test status
Simulation time 43145599 ps
CPU time 0.58 seconds
Started May 30 02:44:31 PM PDT 24
Finished May 30 02:44:33 PM PDT 24
Peak memory 194572 kb
Host smart-1ba17a06-b630-432a-b562-6d9404fd6f39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041381617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3041381617
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.497517646
Short name T630
Test name
Test status
Simulation time 25381266 ps
CPU time 0.61 seconds
Started May 30 02:44:32 PM PDT 24
Finished May 30 02:44:34 PM PDT 24
Peak memory 194584 kb
Host smart-5a1e3409-dac2-4810-a45e-95d902e92d3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497517646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.497517646
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.46859609
Short name T624
Test name
Test status
Simulation time 11779058 ps
CPU time 0.59 seconds
Started May 30 02:44:33 PM PDT 24
Finished May 30 02:44:35 PM PDT 24
Peak memory 194608 kb
Host smart-a766b86e-7029-40ba-85fa-d61e68caa4db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46859609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.46859609
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1882270965
Short name T84
Test name
Test status
Simulation time 78304029 ps
CPU time 0.63 seconds
Started May 30 02:44:31 PM PDT 24
Finished May 30 02:44:33 PM PDT 24
Peak memory 194696 kb
Host smart-ae5b2340-57b2-4900-adfc-eb7513829bed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882270965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1882270965
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1106300096
Short name T667
Test name
Test status
Simulation time 38887012 ps
CPU time 0.59 seconds
Started May 30 02:44:32 PM PDT 24
Finished May 30 02:44:34 PM PDT 24
Peak memory 194656 kb
Host smart-17e0282f-f5bb-43b5-988e-511e6aba264f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106300096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1106300096
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3010878542
Short name T703
Test name
Test status
Simulation time 53468537 ps
CPU time 0.59 seconds
Started May 30 02:44:33 PM PDT 24
Finished May 30 02:44:35 PM PDT 24
Peak memory 194656 kb
Host smart-05d169bb-427a-4b41-a6ae-81eb6000e4ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010878542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3010878542
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2848011740
Short name T612
Test name
Test status
Simulation time 22446577 ps
CPU time 0.67 seconds
Started May 30 02:44:32 PM PDT 24
Finished May 30 02:44:34 PM PDT 24
Peak memory 194616 kb
Host smart-c9eb7fec-6193-4428-88cc-20d78a86de5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848011740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2848011740
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2587168022
Short name T619
Test name
Test status
Simulation time 22697769 ps
CPU time 0.59 seconds
Started May 30 02:44:33 PM PDT 24
Finished May 30 02:44:35 PM PDT 24
Peak memory 194676 kb
Host smart-a5c15c0a-9b6a-4ebf-93d6-3fe14bb33ffa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587168022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2587168022
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1358469140
Short name T62
Test name
Test status
Simulation time 211343361 ps
CPU time 3.68 seconds
Started May 30 02:43:34 PM PDT 24
Finished May 30 02:43:38 PM PDT 24
Peak memory 199828 kb
Host smart-6b56f1e0-a60c-4796-ac0c-06fe507f316d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358469140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1358469140
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3488254996
Short name T652
Test name
Test status
Simulation time 4373622209 ps
CPU time 17.17 seconds
Started May 30 02:43:38 PM PDT 24
Finished May 30 02:43:57 PM PDT 24
Peak memory 199864 kb
Host smart-32a9eed0-82da-40d1-b5d9-535aebe8cd6c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488254996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3488254996
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3714643683
Short name T109
Test name
Test status
Simulation time 22498660 ps
CPU time 0.98 seconds
Started May 30 02:43:37 PM PDT 24
Finished May 30 02:43:39 PM PDT 24
Peak memory 199592 kb
Host smart-0d62a8ac-c5be-4a89-90dd-c98929339161
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714643683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3714643683
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1295258733
Short name T704
Test name
Test status
Simulation time 74081158 ps
CPU time 1.8 seconds
Started May 30 02:43:49 PM PDT 24
Finished May 30 02:43:52 PM PDT 24
Peak memory 199888 kb
Host smart-0049b6fc-f47f-4679-b9bd-92c34001ba2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295258733 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1295258733
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.4262830614
Short name T97
Test name
Test status
Simulation time 81339543 ps
CPU time 0.77 seconds
Started May 30 02:43:39 PM PDT 24
Finished May 30 02:43:41 PM PDT 24
Peak memory 198644 kb
Host smart-6b2a12a4-94c0-42c5-9c35-0b062ecf238e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262830614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.4262830614
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3532198791
Short name T644
Test name
Test status
Simulation time 18877633 ps
CPU time 0.63 seconds
Started May 30 02:43:38 PM PDT 24
Finished May 30 02:43:40 PM PDT 24
Peak memory 194648 kb
Host smart-8f12c651-f7c0-4184-9d93-7017a801ab3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532198791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3532198791
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3848088229
Short name T61
Test name
Test status
Simulation time 37845647 ps
CPU time 1.73 seconds
Started May 30 02:43:50 PM PDT 24
Finished May 30 02:43:54 PM PDT 24
Peak memory 199812 kb
Host smart-1caa87bf-c019-4540-8060-9e0da1303810
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848088229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3848088229
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3642812806
Short name T615
Test name
Test status
Simulation time 132771234 ps
CPU time 1.63 seconds
Started May 30 02:43:37 PM PDT 24
Finished May 30 02:43:40 PM PDT 24
Peak memory 199876 kb
Host smart-2f619fdb-686f-4115-b3fb-0547ef5669e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642812806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.3642812806
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2638804927
Short name T130
Test name
Test status
Simulation time 140216129 ps
CPU time 1.85 seconds
Started May 30 02:43:37 PM PDT 24
Finished May 30 02:43:40 PM PDT 24
Peak memory 199856 kb
Host smart-0ff70a9e-9cd9-4b29-97d7-bf50c9b4befe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638804927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2638804927
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.74802630
Short name T705
Test name
Test status
Simulation time 54804872 ps
CPU time 0.64 seconds
Started May 30 02:44:34 PM PDT 24
Finished May 30 02:44:36 PM PDT 24
Peak memory 194764 kb
Host smart-c5c94253-a96e-47be-835a-4ea11a053e7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74802630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.74802630
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1233722280
Short name T680
Test name
Test status
Simulation time 15039494 ps
CPU time 0.58 seconds
Started May 30 02:44:33 PM PDT 24
Finished May 30 02:44:35 PM PDT 24
Peak memory 194596 kb
Host smart-33ae7686-7bc0-485b-91fb-6633d41d1c6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233722280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1233722280
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.10259979
Short name T668
Test name
Test status
Simulation time 25738020 ps
CPU time 0.62 seconds
Started May 30 02:44:47 PM PDT 24
Finished May 30 02:44:49 PM PDT 24
Peak memory 194704 kb
Host smart-06bfb2c1-2c72-41a5-8fb0-20cae5331362
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10259979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.10259979
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2068488886
Short name T635
Test name
Test status
Simulation time 36605312 ps
CPU time 0.58 seconds
Started May 30 02:44:45 PM PDT 24
Finished May 30 02:44:47 PM PDT 24
Peak memory 194656 kb
Host smart-1243e83f-5e6d-4b14-b8ff-93b459c75d7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068488886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2068488886
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1168092928
Short name T656
Test name
Test status
Simulation time 14052722 ps
CPU time 0.61 seconds
Started May 30 02:44:48 PM PDT 24
Finished May 30 02:44:51 PM PDT 24
Peak memory 194712 kb
Host smart-efcab40f-5a55-45eb-9bf3-772d91d591b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168092928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1168092928
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.367626693
Short name T682
Test name
Test status
Simulation time 13279311 ps
CPU time 0.61 seconds
Started May 30 02:44:47 PM PDT 24
Finished May 30 02:44:49 PM PDT 24
Peak memory 194620 kb
Host smart-c3441298-891e-4df7-ba60-a1923b111a5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367626693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.367626693
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3261930354
Short name T677
Test name
Test status
Simulation time 13332939 ps
CPU time 0.59 seconds
Started May 30 02:44:46 PM PDT 24
Finished May 30 02:44:47 PM PDT 24
Peak memory 194576 kb
Host smart-33cfb1e2-d99e-4870-8ca2-72f49a79d836
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261930354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3261930354
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1090912251
Short name T679
Test name
Test status
Simulation time 45609230 ps
CPU time 0.61 seconds
Started May 30 02:44:47 PM PDT 24
Finished May 30 02:44:49 PM PDT 24
Peak memory 194696 kb
Host smart-7466159a-22b5-473b-898b-7e1ab37dda46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090912251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1090912251
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.117213107
Short name T645
Test name
Test status
Simulation time 12384051 ps
CPU time 0.61 seconds
Started May 30 02:44:46 PM PDT 24
Finished May 30 02:44:47 PM PDT 24
Peak memory 194656 kb
Host smart-a7fee442-85ef-4d9c-908b-3364d704eec0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117213107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.117213107
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1442344989
Short name T618
Test name
Test status
Simulation time 13364710 ps
CPU time 0.58 seconds
Started May 30 02:44:46 PM PDT 24
Finished May 30 02:44:48 PM PDT 24
Peak memory 194536 kb
Host smart-1921ea3f-3f21-4d9b-803e-82c0410af57b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442344989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1442344989
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3062098794
Short name T103
Test name
Test status
Simulation time 558049814 ps
CPU time 8.68 seconds
Started May 30 02:43:49 PM PDT 24
Finished May 30 02:43:59 PM PDT 24
Peak memory 199896 kb
Host smart-886525ac-d94d-46b4-a2f2-eff975fc2a6f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062098794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3062098794
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1992572436
Short name T658
Test name
Test status
Simulation time 711322504 ps
CPU time 5.72 seconds
Started May 30 02:43:49 PM PDT 24
Finished May 30 02:43:57 PM PDT 24
Peak memory 198760 kb
Host smart-a49a3982-eda7-4294-b930-272802fc07a8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992572436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1992572436
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.743515346
Short name T712
Test name
Test status
Simulation time 133428901 ps
CPU time 0.86 seconds
Started May 30 02:43:50 PM PDT 24
Finished May 30 02:43:53 PM PDT 24
Peak memory 199208 kb
Host smart-30e99fe0-cf55-4746-8dfb-2858d8309580
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743515346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.743515346
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2002482564
Short name T626
Test name
Test status
Simulation time 69596885 ps
CPU time 2.34 seconds
Started May 30 02:43:53 PM PDT 24
Finished May 30 02:43:58 PM PDT 24
Peak memory 208096 kb
Host smart-949963b8-a2e8-4804-a172-25cee464a8cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002482564 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.2002482564
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.958016045
Short name T101
Test name
Test status
Simulation time 300996288 ps
CPU time 0.86 seconds
Started May 30 02:43:52 PM PDT 24
Finished May 30 02:43:56 PM PDT 24
Peak memory 199216 kb
Host smart-1c1f2db1-c341-4b9d-8608-ee3ac62ccaf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958016045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.958016045
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.322307628
Short name T694
Test name
Test status
Simulation time 77598891 ps
CPU time 0.61 seconds
Started May 30 02:43:51 PM PDT 24
Finished May 30 02:43:54 PM PDT 24
Peak memory 194684 kb
Host smart-3828d5ea-181e-4d62-ac0b-514d4b9028fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322307628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.322307628
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3411723129
Short name T636
Test name
Test status
Simulation time 51154449 ps
CPU time 1.1 seconds
Started May 30 02:43:51 PM PDT 24
Finished May 30 02:43:54 PM PDT 24
Peak memory 199528 kb
Host smart-0bd6e23b-3157-4798-8e10-369de3ca0127
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411723129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3411723129
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1767535178
Short name T637
Test name
Test status
Simulation time 734515669 ps
CPU time 4.09 seconds
Started May 30 02:43:50 PM PDT 24
Finished May 30 02:43:57 PM PDT 24
Peak memory 199860 kb
Host smart-5d28ea73-87c9-4e20-98b9-c846fbcc9ee3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767535178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1767535178
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2103011292
Short name T678
Test name
Test status
Simulation time 108687025 ps
CPU time 1.81 seconds
Started May 30 02:43:50 PM PDT 24
Finished May 30 02:43:54 PM PDT 24
Peak memory 199832 kb
Host smart-8d838b1c-c9dc-4636-8349-22bf452643c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103011292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2103011292
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.8567973
Short name T674
Test name
Test status
Simulation time 46345214 ps
CPU time 0.57 seconds
Started May 30 02:44:46 PM PDT 24
Finished May 30 02:44:48 PM PDT 24
Peak memory 194616 kb
Host smart-076d7440-85af-46ba-bb14-f48fc1dbd5ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8567973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.8567973
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2514119150
Short name T661
Test name
Test status
Simulation time 14036721 ps
CPU time 0.58 seconds
Started May 30 02:44:45 PM PDT 24
Finished May 30 02:44:47 PM PDT 24
Peak memory 194608 kb
Host smart-f5430f47-4d17-4f48-9314-598681ea54c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514119150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2514119150
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3453312454
Short name T599
Test name
Test status
Simulation time 45958355 ps
CPU time 0.6 seconds
Started May 30 02:44:48 PM PDT 24
Finished May 30 02:44:51 PM PDT 24
Peak memory 194672 kb
Host smart-3be4ffaf-4ca4-4028-90b6-4ef059f0f5b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453312454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3453312454
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3729080009
Short name T666
Test name
Test status
Simulation time 11262228 ps
CPU time 0.62 seconds
Started May 30 02:44:45 PM PDT 24
Finished May 30 02:44:47 PM PDT 24
Peak memory 194664 kb
Host smart-6d1ab799-6215-40c2-b60c-3e80cc3fc5c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729080009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3729080009
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3342715124
Short name T643
Test name
Test status
Simulation time 12722331 ps
CPU time 0.58 seconds
Started May 30 02:44:48 PM PDT 24
Finished May 30 02:44:50 PM PDT 24
Peak memory 194592 kb
Host smart-60cacb4c-f424-43f8-84df-64de022b669a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342715124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3342715124
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2981994579
Short name T608
Test name
Test status
Simulation time 172822785 ps
CPU time 0.62 seconds
Started May 30 02:44:46 PM PDT 24
Finished May 30 02:44:48 PM PDT 24
Peak memory 194576 kb
Host smart-c629a1b5-36bd-4c46-9353-58d0347f1136
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981994579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2981994579
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3107507016
Short name T686
Test name
Test status
Simulation time 11572751 ps
CPU time 0.6 seconds
Started May 30 02:44:49 PM PDT 24
Finished May 30 02:44:51 PM PDT 24
Peak memory 194684 kb
Host smart-e5674f49-40a9-497e-b68d-627108094c1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107507016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3107507016
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.394597779
Short name T693
Test name
Test status
Simulation time 27700312 ps
CPU time 0.6 seconds
Started May 30 02:44:47 PM PDT 24
Finished May 30 02:44:50 PM PDT 24
Peak memory 194648 kb
Host smart-d097935b-d8b2-4789-901d-96ef56b427f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394597779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.394597779
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.3510218315
Short name T602
Test name
Test status
Simulation time 48669701 ps
CPU time 0.62 seconds
Started May 30 02:44:47 PM PDT 24
Finished May 30 02:44:49 PM PDT 24
Peak memory 194644 kb
Host smart-ed465ebd-411d-474d-8034-395fc46198dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510218315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3510218315
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1344871453
Short name T665
Test name
Test status
Simulation time 29168336 ps
CPU time 0.6 seconds
Started May 30 02:44:47 PM PDT 24
Finished May 30 02:44:49 PM PDT 24
Peak memory 194604 kb
Host smart-83070f53-6cd2-43dc-8f03-bb4a5349fbbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344871453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1344871453
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.240009116
Short name T67
Test name
Test status
Simulation time 97895984 ps
CPU time 2.36 seconds
Started May 30 02:43:51 PM PDT 24
Finished May 30 02:43:55 PM PDT 24
Peak memory 199844 kb
Host smart-e2998d73-5e62-4503-a309-8e481cf9e536
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240009116 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.240009116
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1553033747
Short name T605
Test name
Test status
Simulation time 45159954 ps
CPU time 0.71 seconds
Started May 30 02:43:50 PM PDT 24
Finished May 30 02:43:53 PM PDT 24
Peak memory 197580 kb
Host smart-b2381907-989e-4869-95e7-e913bb5996f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553033747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1553033747
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.778222588
Short name T613
Test name
Test status
Simulation time 11156036 ps
CPU time 0.6 seconds
Started May 30 02:43:52 PM PDT 24
Finished May 30 02:43:54 PM PDT 24
Peak memory 194516 kb
Host smart-655dbe38-7517-406c-8690-14a34b84a58a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778222588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.778222588
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1547656225
Short name T660
Test name
Test status
Simulation time 83558002 ps
CPU time 1.17 seconds
Started May 30 02:43:52 PM PDT 24
Finished May 30 02:43:55 PM PDT 24
Peak memory 198108 kb
Host smart-152ac008-efa9-4f4f-a42a-016dee70cbd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547656225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1547656225
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2097649527
Short name T631
Test name
Test status
Simulation time 231963117 ps
CPU time 1.57 seconds
Started May 30 02:43:49 PM PDT 24
Finished May 30 02:43:53 PM PDT 24
Peak memory 199840 kb
Host smart-87fffef8-9cf8-4172-88ed-bd27a0dc4ed9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097649527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.2097649527
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.610881260
Short name T695
Test name
Test status
Simulation time 182313824 ps
CPU time 1.68 seconds
Started May 30 02:43:54 PM PDT 24
Finished May 30 02:43:58 PM PDT 24
Peak memory 199884 kb
Host smart-4a3e2b0b-34ce-4652-9d96-8891aa766a85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610881260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.610881260
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.4150624421
Short name T651
Test name
Test status
Simulation time 108958826 ps
CPU time 2.47 seconds
Started May 30 02:43:50 PM PDT 24
Finished May 30 02:43:55 PM PDT 24
Peak memory 199896 kb
Host smart-eb82ac35-734d-4a3f-93aa-f94a859c36a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150624421 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.4150624421
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3744371858
Short name T663
Test name
Test status
Simulation time 49885698 ps
CPU time 0.87 seconds
Started May 30 02:43:49 PM PDT 24
Finished May 30 02:43:52 PM PDT 24
Peak memory 199604 kb
Host smart-5401ab88-ad3a-46c4-a5a9-12017808bf30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744371858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3744371858
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.954842722
Short name T715
Test name
Test status
Simulation time 29461013 ps
CPU time 0.63 seconds
Started May 30 02:43:53 PM PDT 24
Finished May 30 02:43:56 PM PDT 24
Peak memory 194660 kb
Host smart-86c0ae6e-de85-4fb8-b3d3-d231e9dc1767
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954842722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.954842722
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2132162280
Short name T653
Test name
Test status
Simulation time 182775228 ps
CPU time 1.17 seconds
Started May 30 02:43:51 PM PDT 24
Finished May 30 02:43:54 PM PDT 24
Peak memory 199420 kb
Host smart-d007a34d-d058-4a35-9885-3638e097db20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132162280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2132162280
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3761431098
Short name T632
Test name
Test status
Simulation time 25392297 ps
CPU time 1.15 seconds
Started May 30 02:43:50 PM PDT 24
Finished May 30 02:43:54 PM PDT 24
Peak memory 199944 kb
Host smart-41bcd299-5a2a-475f-8333-075522c8cda8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761431098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3761431098
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2842159326
Short name T724
Test name
Test status
Simulation time 336867812 ps
CPU time 4.52 seconds
Started May 30 02:43:50 PM PDT 24
Finished May 30 02:43:57 PM PDT 24
Peak memory 199828 kb
Host smart-8dc5e425-5bb3-425f-a487-2cc28920e588
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842159326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2842159326
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3584597403
Short name T673
Test name
Test status
Simulation time 96268621 ps
CPU time 2.36 seconds
Started May 30 02:44:01 PM PDT 24
Finished May 30 02:44:05 PM PDT 24
Peak memory 199976 kb
Host smart-4e1ea31a-e239-4920-a908-54d5c4281e1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584597403 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.3584597403
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.4097814768
Short name T99
Test name
Test status
Simulation time 85623449 ps
CPU time 0.83 seconds
Started May 30 02:43:50 PM PDT 24
Finished May 30 02:43:53 PM PDT 24
Peak memory 199360 kb
Host smart-b520de2f-700f-428a-b81d-4eaa3472b1a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097814768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.4097814768
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.426805776
Short name T718
Test name
Test status
Simulation time 14536335 ps
CPU time 0.6 seconds
Started May 30 02:43:51 PM PDT 24
Finished May 30 02:43:54 PM PDT 24
Peak memory 194636 kb
Host smart-62ef8ad0-8c09-46ed-af04-56ea598eabf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426805776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.426805776
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2469146998
Short name T616
Test name
Test status
Simulation time 537110635 ps
CPU time 1.8 seconds
Started May 30 02:44:00 PM PDT 24
Finished May 30 02:44:03 PM PDT 24
Peak memory 199820 kb
Host smart-aa78cef0-3737-404c-8368-a5a4284a1eee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469146998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2469146998
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2194340286
Short name T692
Test name
Test status
Simulation time 213578590 ps
CPU time 3.82 seconds
Started May 30 02:43:49 PM PDT 24
Finished May 30 02:43:53 PM PDT 24
Peak memory 199932 kb
Host smart-1c68ef8f-6afe-4ea9-b049-47eb4af2a3ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194340286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2194340286
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2651796187
Short name T128
Test name
Test status
Simulation time 356183033 ps
CPU time 3.1 seconds
Started May 30 02:43:50 PM PDT 24
Finished May 30 02:43:55 PM PDT 24
Peak memory 199884 kb
Host smart-4cd70f4f-c182-46fe-9197-eaf47818a2aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651796187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2651796187
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1272297974
Short name T625
Test name
Test status
Simulation time 60634855961 ps
CPU time 211.52 seconds
Started May 30 02:44:03 PM PDT 24
Finished May 30 02:47:36 PM PDT 24
Peak memory 215540 kb
Host smart-1c9ba3c5-c975-45d5-a959-353323c3a23b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272297974 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.1272297974
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.854257503
Short name T104
Test name
Test status
Simulation time 78941708 ps
CPU time 0.91 seconds
Started May 30 02:44:01 PM PDT 24
Finished May 30 02:44:04 PM PDT 24
Peak memory 199584 kb
Host smart-cb9ca930-8ce4-430d-8f99-024166117c65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854257503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.854257503
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.598578431
Short name T623
Test name
Test status
Simulation time 32950785 ps
CPU time 0.64 seconds
Started May 30 02:44:01 PM PDT 24
Finished May 30 02:44:04 PM PDT 24
Peak memory 194688 kb
Host smart-cdaba2bf-bab6-4cae-949d-31de5d4f2e64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598578431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.598578431
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.441609316
Short name T662
Test name
Test status
Simulation time 350280252 ps
CPU time 1.18 seconds
Started May 30 02:44:01 PM PDT 24
Finished May 30 02:44:03 PM PDT 24
Peak memory 199492 kb
Host smart-da4cfad0-e1cd-473a-b1d9-1e306d647312
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441609316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_
outstanding.441609316
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.895063207
Short name T685
Test name
Test status
Simulation time 47881485 ps
CPU time 1.3 seconds
Started May 30 02:44:00 PM PDT 24
Finished May 30 02:44:03 PM PDT 24
Peak memory 199932 kb
Host smart-4036911d-8142-4b46-88db-0f17fb92f39b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895063207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.895063207
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2818632510
Short name T57
Test name
Test status
Simulation time 869933047 ps
CPU time 4.37 seconds
Started May 30 02:44:00 PM PDT 24
Finished May 30 02:44:06 PM PDT 24
Peak memory 199812 kb
Host smart-b1274d39-4137-4020-918f-c5b76682d162
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818632510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.2818632510
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2167671217
Short name T722
Test name
Test status
Simulation time 38354604 ps
CPU time 2.34 seconds
Started May 30 02:44:00 PM PDT 24
Finished May 30 02:44:03 PM PDT 24
Peak memory 199880 kb
Host smart-09a98ab2-0371-4b0b-9499-994e30d47927
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167671217 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2167671217
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.331808236
Short name T649
Test name
Test status
Simulation time 11998287 ps
CPU time 0.72 seconds
Started May 30 02:44:03 PM PDT 24
Finished May 30 02:44:05 PM PDT 24
Peak memory 197492 kb
Host smart-4b8fdf41-5f5a-42c9-a25a-f0a3c4f61501
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331808236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.331808236
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2392564761
Short name T601
Test name
Test status
Simulation time 13636056 ps
CPU time 0.64 seconds
Started May 30 02:44:01 PM PDT 24
Finished May 30 02:44:03 PM PDT 24
Peak memory 194704 kb
Host smart-8dccf3ad-3455-49d7-b531-f6c4cc2dea4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392564761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2392564761
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1583767085
Short name T676
Test name
Test status
Simulation time 1403779196 ps
CPU time 1.9 seconds
Started May 30 02:44:02 PM PDT 24
Finished May 30 02:44:05 PM PDT 24
Peak memory 199820 kb
Host smart-6c95c8f8-f4c9-435e-8382-7266c0fd6b4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583767085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.1583767085
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2074331594
Short name T610
Test name
Test status
Simulation time 549201705 ps
CPU time 3.18 seconds
Started May 30 02:44:05 PM PDT 24
Finished May 30 02:44:09 PM PDT 24
Peak memory 199872 kb
Host smart-0e6bdf93-1cb8-47e7-9a06-1f33b067393b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074331594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2074331594
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2973768184
Short name T133
Test name
Test status
Simulation time 211978155 ps
CPU time 3.05 seconds
Started May 30 02:44:01 PM PDT 24
Finished May 30 02:44:05 PM PDT 24
Peak memory 199856 kb
Host smart-05fa3c94-23a9-4844-ab1a-a369bdce8253
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973768184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2973768184
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.795109270
Short name T232
Test name
Test status
Simulation time 20061053 ps
CPU time 0.58 seconds
Started May 30 02:49:41 PM PDT 24
Finished May 30 02:49:43 PM PDT 24
Peak memory 195724 kb
Host smart-e22b5c3a-f89b-436c-9735-003d3b5fe889
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795109270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.795109270
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2606848931
Short name T340
Test name
Test status
Simulation time 1511438628 ps
CPU time 35.96 seconds
Started May 30 02:49:45 PM PDT 24
Finished May 30 02:50:22 PM PDT 24
Peak memory 216452 kb
Host smart-fc1d1f41-c709-4053-9fcb-c822038f3223
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2606848931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2606848931
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.1623277285
Short name T306
Test name
Test status
Simulation time 253476460 ps
CPU time 13.77 seconds
Started May 30 02:49:39 PM PDT 24
Finished May 30 02:49:54 PM PDT 24
Peak memory 200044 kb
Host smart-2694b72e-e3fe-4eec-81fc-1c0326c777d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623277285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1623277285
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.913659519
Short name T118
Test name
Test status
Simulation time 17212708783 ps
CPU time 882.3 seconds
Started May 30 02:49:41 PM PDT 24
Finished May 30 03:04:25 PM PDT 24
Peak memory 727112 kb
Host smart-3ce7ea0e-cf6a-4db3-b66e-68a856c9bde5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=913659519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.913659519
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2489616155
Short name T18
Test name
Test status
Simulation time 11395098663 ps
CPU time 144.65 seconds
Started May 30 02:49:43 PM PDT 24
Finished May 30 02:52:09 PM PDT 24
Peak memory 200068 kb
Host smart-6e1f6cfb-68a6-46e1-a505-0e42b4c002a0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489616155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2489616155
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1291007627
Short name T556
Test name
Test status
Simulation time 2148094846 ps
CPU time 32.67 seconds
Started May 30 02:49:42 PM PDT 24
Finished May 30 02:50:16 PM PDT 24
Peak memory 200108 kb
Host smart-00cebdad-a849-4079-ae96-4bd80f8eab95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291007627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1291007627
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3588313491
Short name T35
Test name
Test status
Simulation time 68452497 ps
CPU time 0.94 seconds
Started May 30 02:49:41 PM PDT 24
Finished May 30 02:49:43 PM PDT 24
Peak memory 218220 kb
Host smart-1b0f4abc-d3d0-4627-9c6c-d71f2ce0137a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588313491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3588313491
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.3401422507
Short name T148
Test name
Test status
Simulation time 323082776 ps
CPU time 4.56 seconds
Started May 30 02:49:31 PM PDT 24
Finished May 30 02:49:38 PM PDT 24
Peak memory 200036 kb
Host smart-589deafb-7369-47ac-92ca-2e5d8fa0dbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401422507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3401422507
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3268490346
Short name T252
Test name
Test status
Simulation time 23246538732 ps
CPU time 1853.68 seconds
Started May 30 02:49:40 PM PDT 24
Finished May 30 03:20:36 PM PDT 24
Peak memory 713168 kb
Host smart-ff0b7f7e-ead7-4201-ba78-21417e062c4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268490346 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3268490346
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.160703159
Short name T520
Test name
Test status
Simulation time 135443499 ps
CPU time 1.31 seconds
Started May 30 02:49:40 PM PDT 24
Finished May 30 02:49:43 PM PDT 24
Peak memory 199044 kb
Host smart-58854f50-7478-4a28-8a98-94971d4e155d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160703159 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_hmac_vectors.160703159
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.3304861881
Short name T427
Test name
Test status
Simulation time 288371339851 ps
CPU time 544.91 seconds
Started May 30 02:49:42 PM PDT 24
Finished May 30 02:58:49 PM PDT 24
Peak memory 200064 kb
Host smart-9f39872f-8021-4fff-97c4-7a717f0a56e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304861881 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.3304861881
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3295755702
Short name T499
Test name
Test status
Simulation time 19795988997 ps
CPU time 54.52 seconds
Started May 30 02:49:40 PM PDT 24
Finished May 30 02:50:35 PM PDT 24
Peak memory 200056 kb
Host smart-36e9bca0-79b8-41d9-9247-bab0ae682f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295755702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3295755702
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.1183941634
Short name T551
Test name
Test status
Simulation time 14196153 ps
CPU time 0.59 seconds
Started May 30 02:49:40 PM PDT 24
Finished May 30 02:49:42 PM PDT 24
Peak memory 196740 kb
Host smart-11541167-3ece-4478-8543-d44a7d116d6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183941634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1183941634
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.30180642
Short name T203
Test name
Test status
Simulation time 1649539482 ps
CPU time 40.43 seconds
Started May 30 02:49:41 PM PDT 24
Finished May 30 02:50:24 PM PDT 24
Peak memory 216380 kb
Host smart-483b8519-9dd3-4e02-b40f-0bd648ca1964
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=30180642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.30180642
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2067666256
Short name T560
Test name
Test status
Simulation time 348875004 ps
CPU time 7 seconds
Started May 30 02:49:42 PM PDT 24
Finished May 30 02:49:51 PM PDT 24
Peak memory 200064 kb
Host smart-04d8d317-d251-4b39-b2f0-229460a92838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067666256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2067666256
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.4268745994
Short name T113
Test name
Test status
Simulation time 7852655058 ps
CPU time 888.79 seconds
Started May 30 02:49:42 PM PDT 24
Finished May 30 03:04:32 PM PDT 24
Peak memory 756020 kb
Host smart-d585e839-63a6-4ea4-b54d-7db833c322ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4268745994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.4268745994
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3531613436
Short name T15
Test name
Test status
Simulation time 2160766487 ps
CPU time 17.63 seconds
Started May 30 02:49:40 PM PDT 24
Finished May 30 02:49:59 PM PDT 24
Peak memory 200004 kb
Host smart-aab8d06d-5074-424c-acd4-680ad0ee11dd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531613436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3531613436
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2956099078
Short name T425
Test name
Test status
Simulation time 1596099578 ps
CPU time 95.33 seconds
Started May 30 02:49:42 PM PDT 24
Finished May 30 02:51:19 PM PDT 24
Peak memory 200080 kb
Host smart-02d742ae-63fe-4808-beb5-318557accbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956099078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2956099078
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1713407318
Short name T32
Test name
Test status
Simulation time 116679179 ps
CPU time 0.83 seconds
Started May 30 02:49:40 PM PDT 24
Finished May 30 02:49:42 PM PDT 24
Peak memory 218152 kb
Host smart-04e8b78c-3d1c-4412-b3ad-da35823e9fb5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713407318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1713407318
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.2677094173
Short name T597
Test name
Test status
Simulation time 278940529 ps
CPU time 4.67 seconds
Started May 30 02:49:41 PM PDT 24
Finished May 30 02:49:48 PM PDT 24
Peak memory 200056 kb
Host smart-16f0373d-7f00-47f1-9fd2-8591b8f82174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677094173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2677094173
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.2232757865
Short name T522
Test name
Test status
Simulation time 112262538020 ps
CPU time 2720.98 seconds
Started May 30 02:49:42 PM PDT 24
Finished May 30 03:35:05 PM PDT 24
Peak memory 723712 kb
Host smart-f232a3f6-9b82-476e-a811-4b332b2592fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232757865 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2232757865
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.124179141
Short name T194
Test name
Test status
Simulation time 103812418 ps
CPU time 1.16 seconds
Started May 30 02:49:41 PM PDT 24
Finished May 30 02:49:44 PM PDT 24
Peak memory 199668 kb
Host smart-061d59b4-a60a-4e3a-a3c8-48abfe4e73ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124179141 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_hmac_vectors.124179141
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.717672042
Short name T173
Test name
Test status
Simulation time 67684928801 ps
CPU time 467.36 seconds
Started May 30 02:49:40 PM PDT 24
Finished May 30 02:57:29 PM PDT 24
Peak memory 200120 kb
Host smart-5c989c00-49cd-4a00-8d25-ccf6af5c22fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717672042 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.717672042
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3211789769
Short name T291
Test name
Test status
Simulation time 3415686059 ps
CPU time 13.86 seconds
Started May 30 02:49:42 PM PDT 24
Finished May 30 02:49:57 PM PDT 24
Peak memory 200052 kb
Host smart-3a7608f3-fb07-4987-9c45-f31a096ef738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211789769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3211789769
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.2446759291
Short name T565
Test name
Test status
Simulation time 571711872 ps
CPU time 27.92 seconds
Started May 30 02:50:20 PM PDT 24
Finished May 30 02:50:49 PM PDT 24
Peak memory 224664 kb
Host smart-aad7867e-3774-47b4-8860-d4eebcd3c0b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2446759291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2446759291
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.1357192786
Short name T14
Test name
Test status
Simulation time 461230487 ps
CPU time 24.53 seconds
Started May 30 02:50:20 PM PDT 24
Finished May 30 02:50:46 PM PDT 24
Peak memory 200012 kb
Host smart-fb97766b-c3c7-4b43-be1c-47a0dd585384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357192786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1357192786
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1026368649
Short name T90
Test name
Test status
Simulation time 1397530664 ps
CPU time 63.27 seconds
Started May 30 02:50:21 PM PDT 24
Finished May 30 02:51:26 PM PDT 24
Peak memory 392632 kb
Host smart-64e2d9f5-d41d-4922-b492-92d96cb6fc42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1026368649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1026368649
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3947476365
Short name T267
Test name
Test status
Simulation time 444788728 ps
CPU time 25.02 seconds
Started May 30 02:50:20 PM PDT 24
Finished May 30 02:50:46 PM PDT 24
Peak memory 200092 kb
Host smart-6ad5c881-a937-4a21-abea-03490fe393c0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947476365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3947476365
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.427441200
Short name T2
Test name
Test status
Simulation time 21982495909 ps
CPU time 103.6 seconds
Started May 30 02:50:21 PM PDT 24
Finished May 30 02:52:06 PM PDT 24
Peak memory 200132 kb
Host smart-60447528-7923-4bec-b06b-74efe93f4f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427441200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.427441200
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.618719776
Short name T293
Test name
Test status
Simulation time 1721257762 ps
CPU time 9.15 seconds
Started May 30 02:50:22 PM PDT 24
Finished May 30 02:50:33 PM PDT 24
Peak memory 200036 kb
Host smart-abb27fff-cc48-4729-aae5-c0c93c9d9143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618719776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.618719776
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.2028545296
Short name T462
Test name
Test status
Simulation time 93533245 ps
CPU time 1.08 seconds
Started May 30 02:50:19 PM PDT 24
Finished May 30 02:50:21 PM PDT 24
Peak memory 200036 kb
Host smart-e3483dd7-bc2f-4cc5-91f0-3a1f63723383
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028545296 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.2028545296
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.373888493
Short name T440
Test name
Test status
Simulation time 27977478037 ps
CPU time 416.44 seconds
Started May 30 02:50:19 PM PDT 24
Finished May 30 02:57:17 PM PDT 24
Peak memory 200020 kb
Host smart-94dc69b4-817f-4590-bec4-fb8c187871db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373888493 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.373888493
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2558716644
Short name T250
Test name
Test status
Simulation time 3803419440 ps
CPU time 74 seconds
Started May 30 02:50:15 PM PDT 24
Finished May 30 02:51:30 PM PDT 24
Peak memory 200116 kb
Host smart-f127aa1c-43c2-46c6-a547-5b3fa292d1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558716644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2558716644
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.720923390
Short name T171
Test name
Test status
Simulation time 13039153 ps
CPU time 0.62 seconds
Started May 30 02:50:24 PM PDT 24
Finished May 30 02:50:27 PM PDT 24
Peak memory 195580 kb
Host smart-f1046fa6-3fbc-48d0-a6ac-8677482203f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720923390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.720923390
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.704696586
Short name T555
Test name
Test status
Simulation time 4605183670 ps
CPU time 18.04 seconds
Started May 30 02:50:19 PM PDT 24
Finished May 30 02:50:39 PM PDT 24
Peak memory 208300 kb
Host smart-eeb18ed3-3d3a-46f1-a82e-d3df0728b7c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=704696586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.704696586
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3533019859
Short name T258
Test name
Test status
Simulation time 2325274055 ps
CPU time 46.02 seconds
Started May 30 02:50:20 PM PDT 24
Finished May 30 02:51:07 PM PDT 24
Peak memory 200104 kb
Host smart-397d77ae-5575-48fd-ac46-210e8218811d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533019859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3533019859
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.3724398725
Short name T115
Test name
Test status
Simulation time 8934328400 ps
CPU time 543.46 seconds
Started May 30 02:50:21 PM PDT 24
Finished May 30 02:59:26 PM PDT 24
Peak memory 635136 kb
Host smart-043a20e4-13a3-48e7-a3b3-50d7fb96be7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3724398725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3724398725
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.3134955391
Short name T364
Test name
Test status
Simulation time 13025254346 ps
CPU time 157.76 seconds
Started May 30 02:50:24 PM PDT 24
Finished May 30 02:53:04 PM PDT 24
Peak memory 200004 kb
Host smart-6b61c256-587e-4483-a762-10c31da76e09
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134955391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.3134955391
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1738170944
Short name T498
Test name
Test status
Simulation time 74404423 ps
CPU time 1.13 seconds
Started May 30 02:50:21 PM PDT 24
Finished May 30 02:50:24 PM PDT 24
Peak memory 200060 kb
Host smart-c03766f4-6978-4efb-8aa6-3a61bb65056d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738170944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1738170944
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1346415723
Short name T199
Test name
Test status
Simulation time 18924975 ps
CPU time 0.73 seconds
Started May 30 02:50:22 PM PDT 24
Finished May 30 02:50:24 PM PDT 24
Peak memory 197960 kb
Host smart-857e9adf-f63d-4d07-a165-a033e3134819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346415723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1346415723
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.2418086951
Short name T402
Test name
Test status
Simulation time 17879358522 ps
CPU time 999.29 seconds
Started May 30 02:50:23 PM PDT 24
Finished May 30 03:07:04 PM PDT 24
Peak memory 240540 kb
Host smart-091f1e8c-9a9e-407c-a12e-e150d382e2de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418086951 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2418086951
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.3693277861
Short name T196
Test name
Test status
Simulation time 85268616 ps
CPU time 1.13 seconds
Started May 30 02:50:22 PM PDT 24
Finished May 30 02:50:25 PM PDT 24
Peak memory 199916 kb
Host smart-602e8de6-7878-49f7-9b71-32f0a123d9b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693277861 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.3693277861
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.1733354840
Short name T570
Test name
Test status
Simulation time 8673161118 ps
CPU time 477.48 seconds
Started May 30 02:50:22 PM PDT 24
Finished May 30 02:58:21 PM PDT 24
Peak memory 200052 kb
Host smart-48d0823e-3e49-4795-8cb7-d42b69fc8640
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733354840 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.1733354840
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.3634515972
Short name T162
Test name
Test status
Simulation time 1336447621 ps
CPU time 48.08 seconds
Started May 30 02:50:18 PM PDT 24
Finished May 30 02:51:07 PM PDT 24
Peak memory 199980 kb
Host smart-5ce6c368-4431-4e36-8c97-b5c3c9da70ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634515972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3634515972
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2938376971
Short name T355
Test name
Test status
Simulation time 44551129 ps
CPU time 0.6 seconds
Started May 30 02:50:24 PM PDT 24
Finished May 30 02:50:26 PM PDT 24
Peak memory 196008 kb
Host smart-c4ff1acc-d401-4d89-99e6-4a9062fff521
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938376971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2938376971
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3883526740
Short name T531
Test name
Test status
Simulation time 445454615 ps
CPU time 11.21 seconds
Started May 30 02:50:22 PM PDT 24
Finished May 30 02:50:35 PM PDT 24
Peak memory 225928 kb
Host smart-be4cef3b-fcac-443c-9ec5-c5b8cf867990
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3883526740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3883526740
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.4067433994
Short name T175
Test name
Test status
Simulation time 465044558 ps
CPU time 4.22 seconds
Started May 30 02:50:22 PM PDT 24
Finished May 30 02:50:27 PM PDT 24
Peak memory 199836 kb
Host smart-d3ccf275-0c05-4783-9327-58dcb8dd22e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067433994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.4067433994
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.767626988
Short name T112
Test name
Test status
Simulation time 4652419605 ps
CPU time 1152.04 seconds
Started May 30 02:50:21 PM PDT 24
Finished May 30 03:09:34 PM PDT 24
Peak memory 730324 kb
Host smart-4d592e7a-28e3-41d5-98c7-36e09a3c5d80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=767626988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.767626988
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.590253893
Short name T378
Test name
Test status
Simulation time 117484449 ps
CPU time 3.48 seconds
Started May 30 02:50:20 PM PDT 24
Finished May 30 02:50:25 PM PDT 24
Peak memory 199880 kb
Host smart-166e8aa9-5ab9-4904-82a0-af4796fac0df
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590253893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.590253893
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3615621669
Short name T226
Test name
Test status
Simulation time 1169186300 ps
CPU time 67.25 seconds
Started May 30 02:50:16 PM PDT 24
Finished May 30 02:51:24 PM PDT 24
Peak memory 200004 kb
Host smart-2efa619d-8216-47b2-9fec-634c5dd4b91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615621669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3615621669
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.2622663777
Short name T558
Test name
Test status
Simulation time 52228792 ps
CPU time 1 seconds
Started May 30 02:50:22 PM PDT 24
Finished May 30 02:50:25 PM PDT 24
Peak memory 198628 kb
Host smart-1bd4d027-7353-4e84-997d-f97f9d1850dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622663777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2622663777
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1469989889
Short name T208
Test name
Test status
Simulation time 71893041071 ps
CPU time 2104.63 seconds
Started May 30 02:50:21 PM PDT 24
Finished May 30 03:25:27 PM PDT 24
Peak memory 792920 kb
Host smart-c35c5ccd-b527-4f28-9317-8e44f26662ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469989889 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1469989889
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.342783307
Short name T77
Test name
Test status
Simulation time 47316567 ps
CPU time 1.12 seconds
Started May 30 02:50:21 PM PDT 24
Finished May 30 02:50:23 PM PDT 24
Peak memory 199932 kb
Host smart-038573bd-12c8-4717-966b-5da42b06c541
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342783307 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_hmac_vectors.342783307
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.1918543134
Short name T3
Test name
Test status
Simulation time 51294630307 ps
CPU time 448.69 seconds
Started May 30 02:50:21 PM PDT 24
Finished May 30 02:57:52 PM PDT 24
Peak memory 200048 kb
Host smart-bcf4553f-ef62-42bb-aef6-a0ce77162f7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918543134 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.1918543134
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3999754642
Short name T580
Test name
Test status
Simulation time 949995420 ps
CPU time 9.63 seconds
Started May 30 02:50:19 PM PDT 24
Finished May 30 02:50:30 PM PDT 24
Peak memory 200088 kb
Host smart-9830284c-f546-4162-b3dc-6b28964eaff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999754642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3999754642
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1904180711
Short name T281
Test name
Test status
Simulation time 37151773 ps
CPU time 0.59 seconds
Started May 30 02:50:24 PM PDT 24
Finished May 30 02:50:26 PM PDT 24
Peak memory 195612 kb
Host smart-f246ef7d-f2d3-4d9d-8195-56bdc1500c86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904180711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1904180711
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1520475175
Short name T92
Test name
Test status
Simulation time 1117138671 ps
CPU time 55.97 seconds
Started May 30 02:50:23 PM PDT 24
Finished May 30 02:51:21 PM PDT 24
Peak memory 216392 kb
Host smart-de740126-211c-4c94-9a4c-77740d6b9221
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1520475175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1520475175
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2025140428
Short name T278
Test name
Test status
Simulation time 3270169576 ps
CPU time 21.26 seconds
Started May 30 02:50:23 PM PDT 24
Finished May 30 02:50:46 PM PDT 24
Peak memory 200060 kb
Host smart-e5391f4c-80d0-4e1a-8d34-aaa8b2c21eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025140428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2025140428
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.193740721
Short name T349
Test name
Test status
Simulation time 12926274541 ps
CPU time 817.98 seconds
Started May 30 02:50:22 PM PDT 24
Finished May 30 03:04:02 PM PDT 24
Peak memory 702936 kb
Host smart-d9e37313-bcb6-4500-bafc-ac5f5a833192
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=193740721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.193740721
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.529930777
Short name T54
Test name
Test status
Simulation time 48974821985 ps
CPU time 84.91 seconds
Started May 30 02:50:23 PM PDT 24
Finished May 30 02:51:50 PM PDT 24
Peak memory 200016 kb
Host smart-815e99f1-1cb4-422a-bbdc-31ec123a6355
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529930777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.529930777
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.3209344174
Short name T546
Test name
Test status
Simulation time 414094744 ps
CPU time 6.31 seconds
Started May 30 02:50:23 PM PDT 24
Finished May 30 02:50:31 PM PDT 24
Peak memory 199964 kb
Host smart-223e8c0b-20f1-4de7-9907-b8f05cc838a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209344174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.3209344174
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.4076455394
Short name T356
Test name
Test status
Simulation time 89679311 ps
CPU time 2.08 seconds
Started May 30 02:50:19 PM PDT 24
Finished May 30 02:50:23 PM PDT 24
Peak memory 200028 kb
Host smart-80fa5b26-75d9-4a74-b34e-90938bc4ae37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076455394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.4076455394
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.1280854759
Short name T469
Test name
Test status
Simulation time 26719288629 ps
CPU time 978.07 seconds
Started May 30 02:50:21 PM PDT 24
Finished May 30 03:06:41 PM PDT 24
Peak memory 682312 kb
Host smart-845c268d-7d2c-429c-a210-b0ce32202bf0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280854759 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1280854759
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.563596432
Short name T374
Test name
Test status
Simulation time 33528504 ps
CPU time 1.38 seconds
Started May 30 02:50:24 PM PDT 24
Finished May 30 02:50:27 PM PDT 24
Peak memory 199988 kb
Host smart-4d4106c2-8318-430b-a49d-b91af51f578b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563596432 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_hmac_vectors.563596432
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.2249537914
Short name T259
Test name
Test status
Simulation time 31634165123 ps
CPU time 463.41 seconds
Started May 30 02:50:24 PM PDT 24
Finished May 30 02:58:09 PM PDT 24
Peak memory 200012 kb
Host smart-79f6c24f-49c9-44bc-8b20-caed0ef54474
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249537914 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.2249537914
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2689140394
Short name T480
Test name
Test status
Simulation time 15750240312 ps
CPU time 58.14 seconds
Started May 30 02:50:22 PM PDT 24
Finished May 30 02:51:22 PM PDT 24
Peak memory 200036 kb
Host smart-35381ffe-ebce-49b9-8b6d-6d76cc14236c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689140394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2689140394
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.900628954
Short name T575
Test name
Test status
Simulation time 40436978 ps
CPU time 0.58 seconds
Started May 30 02:50:32 PM PDT 24
Finished May 30 02:50:35 PM PDT 24
Peak memory 195612 kb
Host smart-20add2e7-b684-4d95-93d6-0dfc220c422f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900628954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.900628954
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.957402601
Short name T468
Test name
Test status
Simulation time 850663659 ps
CPU time 36.81 seconds
Started May 30 02:50:23 PM PDT 24
Finished May 30 02:51:02 PM PDT 24
Peak memory 216396 kb
Host smart-b2194c08-b371-4b08-acaa-fe82921e03da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=957402601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.957402601
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3890332739
Short name T410
Test name
Test status
Simulation time 5074537693 ps
CPU time 24.11 seconds
Started May 30 02:50:32 PM PDT 24
Finished May 30 02:50:57 PM PDT 24
Peak memory 200084 kb
Host smart-0e666c15-e37f-4c7a-861c-25c8a5283394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890332739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3890332739
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.1350979193
Short name T452
Test name
Test status
Simulation time 9441965564 ps
CPU time 942.53 seconds
Started May 30 02:50:23 PM PDT 24
Finished May 30 03:06:07 PM PDT 24
Peak memory 720180 kb
Host smart-373b6859-bd9f-48e9-9828-a8e53f14e55a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1350979193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1350979193
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.2875294167
Short name T505
Test name
Test status
Simulation time 1422426373 ps
CPU time 79 seconds
Started May 30 02:50:34 PM PDT 24
Finished May 30 02:51:55 PM PDT 24
Peak memory 200072 kb
Host smart-31340fda-8c52-43b8-bbce-83912e4993bd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875294167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.2875294167
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.4128819985
Short name T538
Test name
Test status
Simulation time 3979117114 ps
CPU time 77.89 seconds
Started May 30 02:50:23 PM PDT 24
Finished May 30 02:51:43 PM PDT 24
Peak memory 200068 kb
Host smart-1d4606fa-a4d4-468e-9250-fbcf0147ca81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128819985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.4128819985
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1920833200
Short name T200
Test name
Test status
Simulation time 692541220 ps
CPU time 4.92 seconds
Started May 30 02:50:23 PM PDT 24
Finished May 30 02:50:30 PM PDT 24
Peak memory 200036 kb
Host smart-6dc98071-b01a-49a6-a39d-94009dfa034e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920833200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1920833200
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.262411185
Short name T211
Test name
Test status
Simulation time 5079023370 ps
CPU time 215.07 seconds
Started May 30 02:50:35 PM PDT 24
Finished May 30 02:54:12 PM PDT 24
Peak memory 235648 kb
Host smart-78f23b56-168f-4fc6-882d-e43ecf641d21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262411185 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.262411185
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.473733455
Short name T567
Test name
Test status
Simulation time 40227628 ps
CPU time 1.31 seconds
Started May 30 02:50:32 PM PDT 24
Finished May 30 02:50:35 PM PDT 24
Peak memory 200080 kb
Host smart-004fe8b2-cf5e-4fdf-8dfc-50a8d1797dd8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473733455 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_test_hmac_vectors.473733455
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.3304899799
Short name T460
Test name
Test status
Simulation time 109315338217 ps
CPU time 493.36 seconds
Started May 30 02:50:33 PM PDT 24
Finished May 30 02:58:48 PM PDT 24
Peak memory 200060 kb
Host smart-6a2e9959-8273-456d-9200-20fc91b2f897
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304899799 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.3304899799
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2804114101
Short name T287
Test name
Test status
Simulation time 23173375909 ps
CPU time 91.24 seconds
Started May 30 02:50:32 PM PDT 24
Finished May 30 02:52:04 PM PDT 24
Peak memory 200096 kb
Host smart-2ce0e64c-bb29-4eaf-875d-c7c7912d480f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804114101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2804114101
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/148.hmac_stress_all_with_rand_reset.3126700608
Short name T28
Test name
Test status
Simulation time 11948326353 ps
CPU time 1036.07 seconds
Started May 30 02:54:16 PM PDT 24
Finished May 30 03:11:34 PM PDT 24
Peak memory 510744 kb
Host smart-5e45445f-f76e-4cd2-b318-a83aba95bee7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3126700608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.hmac_stress_all_with_rand_reset.3126700608
Directory /workspace/148.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_alert_test.4123028237
Short name T273
Test name
Test status
Simulation time 24544414 ps
CPU time 0.57 seconds
Started May 30 02:50:34 PM PDT 24
Finished May 30 02:50:37 PM PDT 24
Peak memory 196732 kb
Host smart-807a92f5-10a7-4c3c-a98d-0760f00c26d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123028237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.4123028237
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1165289017
Short name T224
Test name
Test status
Simulation time 641568566 ps
CPU time 28.2 seconds
Started May 30 02:50:32 PM PDT 24
Finished May 30 02:51:02 PM PDT 24
Peak memory 208196 kb
Host smart-567c5972-a6e7-4bf4-92d8-742c73f9d431
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1165289017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1165289017
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.4116199237
Short name T215
Test name
Test status
Simulation time 776330801 ps
CPU time 8.38 seconds
Started May 30 02:50:32 PM PDT 24
Finished May 30 02:50:43 PM PDT 24
Peak memory 200048 kb
Host smart-18917acf-7f3b-47b6-9d23-fe7d7299a4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116199237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.4116199237
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1498618894
Short name T116
Test name
Test status
Simulation time 5337323203 ps
CPU time 1483.41 seconds
Started May 30 02:50:36 PM PDT 24
Finished May 30 03:15:21 PM PDT 24
Peak memory 782808 kb
Host smart-47017ed8-744a-46c3-8821-8d816b3569fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1498618894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1498618894
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2894088991
Short name T343
Test name
Test status
Simulation time 7756243409 ps
CPU time 137.55 seconds
Started May 30 02:50:35 PM PDT 24
Finished May 30 02:52:55 PM PDT 24
Peak memory 200052 kb
Host smart-39c09bf2-a196-4748-ac6c-84e59d60077b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894088991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2894088991
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.434148256
Short name T114
Test name
Test status
Simulation time 13680226470 ps
CPU time 54.8 seconds
Started May 30 02:50:33 PM PDT 24
Finished May 30 02:51:30 PM PDT 24
Peak memory 200116 kb
Host smart-ac7be860-ea26-46af-94af-9c64da38d716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434148256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.434148256
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.410085900
Short name T491
Test name
Test status
Simulation time 220196250 ps
CPU time 5.6 seconds
Started May 30 02:50:33 PM PDT 24
Finished May 30 02:50:41 PM PDT 24
Peak memory 200036 kb
Host smart-2f853cbc-85b0-4fbb-855f-4e35c761c102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410085900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.410085900
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.2581052817
Short name T568
Test name
Test status
Simulation time 6699745846 ps
CPU time 123.19 seconds
Started May 30 02:50:34 PM PDT 24
Finished May 30 02:52:39 PM PDT 24
Peak memory 200112 kb
Host smart-699fb460-ac9d-4e34-9514-8b8d34dd69e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581052817 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2581052817
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.2042879477
Short name T588
Test name
Test status
Simulation time 510400721 ps
CPU time 1.36 seconds
Started May 30 02:50:36 PM PDT 24
Finished May 30 02:50:39 PM PDT 24
Peak memory 199996 kb
Host smart-567f981f-91b6-41ca-8186-dc1d172615c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042879477 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.2042879477
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.3627794683
Short name T401
Test name
Test status
Simulation time 41540791967 ps
CPU time 516.74 seconds
Started May 30 02:50:32 PM PDT 24
Finished May 30 02:59:10 PM PDT 24
Peak memory 200064 kb
Host smart-03f6993e-b1b1-4be7-b7c2-8de3d4d980ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627794683 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.3627794683
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1319674828
Short name T158
Test name
Test status
Simulation time 12031772992 ps
CPU time 53.32 seconds
Started May 30 02:50:36 PM PDT 24
Finished May 30 02:51:31 PM PDT 24
Peak memory 200076 kb
Host smart-0bb7e087-4d14-4165-b635-f8dac9f85e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319674828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1319674828
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/159.hmac_stress_all_with_rand_reset.3710133193
Short name T12
Test name
Test status
Simulation time 75317105964 ps
CPU time 2460.62 seconds
Started May 30 02:54:28 PM PDT 24
Finished May 30 03:35:31 PM PDT 24
Peak memory 784568 kb
Host smart-2959d7a6-c905-4edd-b46b-1f993b0ef58f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3710133193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.hmac_stress_all_with_rand_reset.3710133193
Directory /workspace/159.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_alert_test.320883756
Short name T312
Test name
Test status
Simulation time 27464871 ps
CPU time 0.58 seconds
Started May 30 02:50:47 PM PDT 24
Finished May 30 02:50:49 PM PDT 24
Peak memory 194980 kb
Host smart-169b801a-9df8-437c-8b3c-8f2887d850e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320883756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.320883756
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1207777182
Short name T354
Test name
Test status
Simulation time 5717211813 ps
CPU time 41.44 seconds
Started May 30 02:50:34 PM PDT 24
Finished May 30 02:51:18 PM PDT 24
Peak memory 208240 kb
Host smart-e47e8e70-9bda-41e2-aea4-2217d40aa5bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1207777182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1207777182
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2822182914
Short name T229
Test name
Test status
Simulation time 1678428774 ps
CPU time 3.99 seconds
Started May 30 02:50:32 PM PDT 24
Finished May 30 02:50:38 PM PDT 24
Peak memory 200000 kb
Host smart-716ec917-2070-4e9f-97b9-b55fd3069908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822182914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2822182914
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3761145340
Short name T595
Test name
Test status
Simulation time 2452260328 ps
CPU time 387.78 seconds
Started May 30 02:50:33 PM PDT 24
Finished May 30 02:57:03 PM PDT 24
Peak memory 655664 kb
Host smart-5fbbcf7c-38ea-495f-9cf7-24d2ddbef670
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3761145340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3761145340
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.1662254832
Short name T154
Test name
Test status
Simulation time 855904902 ps
CPU time 14.09 seconds
Started May 30 02:50:34 PM PDT 24
Finished May 30 02:50:50 PM PDT 24
Peak memory 199856 kb
Host smart-77c6993c-fdac-4cce-ab6c-23d830e1c38d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662254832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1662254832
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.670707529
Short name T420
Test name
Test status
Simulation time 369212678 ps
CPU time 11.11 seconds
Started May 30 02:50:33 PM PDT 24
Finished May 30 02:50:46 PM PDT 24
Peak memory 200056 kb
Host smart-d6898db6-d535-43d2-9ecb-96279fbf856c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670707529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.670707529
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.2427218109
Short name T535
Test name
Test status
Simulation time 2536452325 ps
CPU time 12.77 seconds
Started May 30 02:50:32 PM PDT 24
Finished May 30 02:50:47 PM PDT 24
Peak memory 200136 kb
Host smart-f6b000b5-0c63-4896-8139-998725f9e923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427218109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2427218109
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.426682547
Short name T195
Test name
Test status
Simulation time 84645796 ps
CPU time 1.06 seconds
Started May 30 02:50:46 PM PDT 24
Finished May 30 02:50:49 PM PDT 24
Peak memory 199692 kb
Host smart-d6ba178d-e79b-42ae-83c8-3c5badbdf8d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426682547 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.hmac_test_hmac_vectors.426682547
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.4147455205
Short name T497
Test name
Test status
Simulation time 150962833013 ps
CPU time 511.12 seconds
Started May 30 02:50:49 PM PDT 24
Finished May 30 02:59:22 PM PDT 24
Peak memory 200048 kb
Host smart-4a2393be-c3ac-4131-bd21-d8cd2b06947e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147455205 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.4147455205
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.687908077
Short name T351
Test name
Test status
Simulation time 23971705093 ps
CPU time 83.25 seconds
Started May 30 02:50:47 PM PDT 24
Finished May 30 02:52:12 PM PDT 24
Peak memory 200104 kb
Host smart-5b7abd3c-ca9b-4933-a371-696b50ddebe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687908077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.687908077
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2840413314
Short name T331
Test name
Test status
Simulation time 41202866 ps
CPU time 0.58 seconds
Started May 30 02:50:48 PM PDT 24
Finished May 30 02:50:50 PM PDT 24
Peak memory 196736 kb
Host smart-f7ae186d-07f6-4ee1-8e7b-cf87fc2ff88b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840413314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2840413314
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.1319422340
Short name T572
Test name
Test status
Simulation time 2533874239 ps
CPU time 31.86 seconds
Started May 30 02:50:50 PM PDT 24
Finished May 30 02:51:23 PM PDT 24
Peak memory 208316 kb
Host smart-702d03c2-b5da-4f37-88fe-cf42d43ab765
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1319422340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1319422340
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.488764809
Short name T138
Test name
Test status
Simulation time 190291429 ps
CPU time 10.43 seconds
Started May 30 02:50:49 PM PDT 24
Finished May 30 02:51:01 PM PDT 24
Peak memory 200016 kb
Host smart-82a37f82-2a8f-48de-a7bb-ed1995bb6705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488764809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.488764809
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.1062881607
Short name T415
Test name
Test status
Simulation time 8160736754 ps
CPU time 537.69 seconds
Started May 30 02:50:47 PM PDT 24
Finished May 30 02:59:47 PM PDT 24
Peak memory 710580 kb
Host smart-f33f1e6c-9d3f-4a67-865c-8790f58b8a70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1062881607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1062881607
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.2085786787
Short name T142
Test name
Test status
Simulation time 1592001242 ps
CPU time 47.36 seconds
Started May 30 02:50:48 PM PDT 24
Finished May 30 02:51:37 PM PDT 24
Peak memory 199972 kb
Host smart-ae6df445-0745-4722-88a0-915a4d62a5f3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085786787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2085786787
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3378504359
Short name T228
Test name
Test status
Simulation time 6911245693 ps
CPU time 49.53 seconds
Started May 30 02:50:48 PM PDT 24
Finished May 30 02:51:39 PM PDT 24
Peak memory 200136 kb
Host smart-f82f0b85-e7ff-4480-a8af-f8849ce4f0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378504359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3378504359
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.612111789
Short name T511
Test name
Test status
Simulation time 1388946724 ps
CPU time 9.37 seconds
Started May 30 02:50:47 PM PDT 24
Finished May 30 02:50:58 PM PDT 24
Peak memory 200048 kb
Host smart-48dbbfbf-5e8a-4895-bb1f-17fde7a8c7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612111789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.612111789
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.197921195
Short name T473
Test name
Test status
Simulation time 33487314625 ps
CPU time 938.19 seconds
Started May 30 02:50:46 PM PDT 24
Finished May 30 03:06:26 PM PDT 24
Peak memory 232908 kb
Host smart-f9314582-9fb1-4b2a-883d-9fc26aa09d04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197921195 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.197921195
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.720880900
Short name T516
Test name
Test status
Simulation time 57992794 ps
CPU time 1.13 seconds
Started May 30 02:50:48 PM PDT 24
Finished May 30 02:50:51 PM PDT 24
Peak memory 199916 kb
Host smart-65360e26-da81-4961-880f-3310d66563de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720880900 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.hmac_test_hmac_vectors.720880900
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.3445242199
Short name T95
Test name
Test status
Simulation time 7698577592 ps
CPU time 413.3 seconds
Started May 30 02:50:46 PM PDT 24
Finished May 30 02:57:41 PM PDT 24
Peak memory 200088 kb
Host smart-e1905f46-14a4-4b97-9b0a-4000b66b56da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445242199 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.3445242199
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3352660052
Short name T479
Test name
Test status
Simulation time 653865899 ps
CPU time 38.94 seconds
Started May 30 02:50:47 PM PDT 24
Finished May 30 02:51:27 PM PDT 24
Peak memory 200064 kb
Host smart-e2d4005b-8ca6-47b3-8c1d-3e1678548ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352660052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3352660052
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1236077624
Short name T335
Test name
Test status
Simulation time 15900863 ps
CPU time 0.6 seconds
Started May 30 02:50:46 PM PDT 24
Finished May 30 02:50:49 PM PDT 24
Peak memory 195988 kb
Host smart-e3ceb9c4-0a07-45a0-b4e6-ba22f2373bd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236077624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1236077624
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1670419434
Short name T201
Test name
Test status
Simulation time 1091903588 ps
CPU time 15.14 seconds
Started May 30 02:50:50 PM PDT 24
Finished May 30 02:51:06 PM PDT 24
Peak memory 215508 kb
Host smart-5ef199fb-d57b-4bc2-82a3-9fd61c82c63a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1670419434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1670419434
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.684872150
Short name T579
Test name
Test status
Simulation time 2404557313 ps
CPU time 35.12 seconds
Started May 30 02:50:46 PM PDT 24
Finished May 30 02:51:23 PM PDT 24
Peak memory 200160 kb
Host smart-04c6743b-e162-442b-b86e-af4c007f9b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684872150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.684872150
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.985549399
Short name T486
Test name
Test status
Simulation time 1239146657 ps
CPU time 97.53 seconds
Started May 30 02:50:47 PM PDT 24
Finished May 30 02:52:26 PM PDT 24
Peak memory 472272 kb
Host smart-1d4331c5-a43d-4b6d-97da-51fe150cd9b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=985549399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.985549399
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.4072276187
Short name T409
Test name
Test status
Simulation time 7143755824 ps
CPU time 131.93 seconds
Started May 30 02:50:46 PM PDT 24
Finished May 30 02:53:00 PM PDT 24
Peak memory 200028 kb
Host smart-99485c5e-285a-4ee9-81dc-95a7bb7f3887
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072276187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.4072276187
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.3348405650
Short name T51
Test name
Test status
Simulation time 102036486 ps
CPU time 6.45 seconds
Started May 30 02:50:50 PM PDT 24
Finished May 30 02:50:58 PM PDT 24
Peak memory 200024 kb
Host smart-c941026a-2714-44ad-8ce0-5ee8c7f0f3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348405650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.3348405650
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.1005681093
Short name T76
Test name
Test status
Simulation time 70904608 ps
CPU time 1.56 seconds
Started May 30 02:50:46 PM PDT 24
Finished May 30 02:50:50 PM PDT 24
Peak memory 200084 kb
Host smart-eeeca801-30d4-458f-a134-0cff1f2bea47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005681093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1005681093
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3893500620
Short name T80
Test name
Test status
Simulation time 327364730707 ps
CPU time 1039.3 seconds
Started May 30 02:50:47 PM PDT 24
Finished May 30 03:08:09 PM PDT 24
Peak memory 392480 kb
Host smart-318f6fd1-817a-4ece-8d10-137d3ad7c320
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893500620 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3893500620
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.2768174443
Short name T198
Test name
Test status
Simulation time 180418696 ps
CPU time 1.2 seconds
Started May 30 02:50:50 PM PDT 24
Finished May 30 02:50:52 PM PDT 24
Peak memory 199804 kb
Host smart-015b949b-faa9-4da1-ae83-9412307226c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768174443 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.2768174443
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.2248233219
Short name T153
Test name
Test status
Simulation time 7905039387 ps
CPU time 463.88 seconds
Started May 30 02:50:49 PM PDT 24
Finished May 30 02:58:35 PM PDT 24
Peak memory 200056 kb
Host smart-1ab3b65c-4151-42eb-9ca3-f3f13816283f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248233219 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.2248233219
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2886923710
Short name T304
Test name
Test status
Simulation time 8634691534 ps
CPU time 80 seconds
Started May 30 02:50:48 PM PDT 24
Finished May 30 02:52:10 PM PDT 24
Peak memory 200084 kb
Host smart-0e2d6252-7f6e-4984-95c0-5c6d517a172a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886923710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2886923710
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.3081993318
Short name T379
Test name
Test status
Simulation time 32929498 ps
CPU time 0.57 seconds
Started May 30 02:51:10 PM PDT 24
Finished May 30 02:51:11 PM PDT 24
Peak memory 194980 kb
Host smart-a865496e-5cad-477a-8a46-131e0f20f9a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081993318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3081993318
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2516115715
Short name T421
Test name
Test status
Simulation time 1655270327 ps
CPU time 38.21 seconds
Started May 30 02:50:48 PM PDT 24
Finished May 30 02:51:28 PM PDT 24
Peak memory 216364 kb
Host smart-d61509dc-2b74-49b1-b049-d2a037c5f642
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2516115715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2516115715
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.3161388822
Short name T40
Test name
Test status
Simulation time 14466337831 ps
CPU time 51.08 seconds
Started May 30 02:50:47 PM PDT 24
Finished May 30 02:51:39 PM PDT 24
Peak memory 200100 kb
Host smart-a13c6397-30db-497e-8be7-159cf7fdf115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161388822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.3161388822
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1001316497
Short name T52
Test name
Test status
Simulation time 1613572452 ps
CPU time 363.86 seconds
Started May 30 02:50:47 PM PDT 24
Finished May 30 02:56:52 PM PDT 24
Peak memory 640924 kb
Host smart-a5bc8a99-24cc-4656-80c8-de59c26cc670
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1001316497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1001316497
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.21719787
Short name T332
Test name
Test status
Simulation time 1756574155 ps
CPU time 12.81 seconds
Started May 30 02:51:04 PM PDT 24
Finished May 30 02:51:18 PM PDT 24
Peak memory 199840 kb
Host smart-8c6585d1-5c74-482a-9fbf-34c88c056d50
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21719787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.21719787
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.2637416117
Short name T234
Test name
Test status
Simulation time 7105462103 ps
CPU time 60.12 seconds
Started May 30 02:50:47 PM PDT 24
Finished May 30 02:51:49 PM PDT 24
Peak memory 200136 kb
Host smart-8a8fea2e-fd6c-42d8-a360-afeb1ecbe80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637416117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2637416117
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1774158875
Short name T365
Test name
Test status
Simulation time 107997100 ps
CPU time 0.86 seconds
Started May 30 02:50:48 PM PDT 24
Finished May 30 02:50:51 PM PDT 24
Peak memory 198844 kb
Host smart-27e526b7-f944-4731-bc36-7f36ab80bc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774158875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1774158875
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1221333626
Short name T82
Test name
Test status
Simulation time 51595218461 ps
CPU time 1191.86 seconds
Started May 30 02:51:05 PM PDT 24
Finished May 30 03:10:58 PM PDT 24
Peak memory 695272 kb
Host smart-e13048c7-beda-4717-88a5-0c3ee4247e83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221333626 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1221333626
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.760427363
Short name T537
Test name
Test status
Simulation time 59969297 ps
CPU time 1.45 seconds
Started May 30 02:51:04 PM PDT 24
Finished May 30 02:51:06 PM PDT 24
Peak memory 199976 kb
Host smart-21105427-a005-421b-920e-81093373aeb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760427363 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_hmac_vectors.760427363
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.1981640104
Short name T8
Test name
Test status
Simulation time 80541053835 ps
CPU time 525.68 seconds
Started May 30 02:51:02 PM PDT 24
Finished May 30 02:59:49 PM PDT 24
Peak memory 200096 kb
Host smart-66a393cd-402e-4dd1-a63e-1dd751bda277
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981640104 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.1981640104
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3750244423
Short name T373
Test name
Test status
Simulation time 1965723544 ps
CPU time 39.53 seconds
Started May 30 02:51:11 PM PDT 24
Finished May 30 02:51:52 PM PDT 24
Peak memory 200060 kb
Host smart-70d3b1a7-1b94-4dc4-b5fe-328cfcb47a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750244423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3750244423
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1459598882
Short name T439
Test name
Test status
Simulation time 21977784 ps
CPU time 0.62 seconds
Started May 30 02:49:55 PM PDT 24
Finished May 30 02:49:57 PM PDT 24
Peak memory 194768 kb
Host smart-7940ce34-0d54-42f9-8cf6-f278f0b2bc79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459598882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1459598882
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3719067511
Short name T521
Test name
Test status
Simulation time 1038471309 ps
CPU time 14.86 seconds
Started May 30 02:49:45 PM PDT 24
Finished May 30 02:50:01 PM PDT 24
Peak memory 220644 kb
Host smart-ab7dc4b0-03f1-4f10-ac5f-ec7aec71a8b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3719067511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3719067511
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.4188267582
Short name T120
Test name
Test status
Simulation time 2450918125 ps
CPU time 10.53 seconds
Started May 30 02:49:45 PM PDT 24
Finished May 30 02:49:56 PM PDT 24
Peak memory 200084 kb
Host smart-4c7076bd-778e-4064-a09c-f779990cb8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188267582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.4188267582
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3501917792
Short name T7
Test name
Test status
Simulation time 27024681067 ps
CPU time 988.93 seconds
Started May 30 02:49:41 PM PDT 24
Finished May 30 03:06:12 PM PDT 24
Peak memory 724472 kb
Host smart-ebb7bb76-f7cf-47e7-b59e-3360fe391e5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3501917792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3501917792
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.2223954143
Short name T327
Test name
Test status
Simulation time 2805199039 ps
CPU time 73.08 seconds
Started May 30 02:49:41 PM PDT 24
Finished May 30 02:50:56 PM PDT 24
Peak memory 200048 kb
Host smart-ad01e5e6-e89f-4763-ad92-409f650c09e0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223954143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2223954143
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3345070508
Short name T197
Test name
Test status
Simulation time 16030744075 ps
CPU time 16.97 seconds
Started May 30 02:49:41 PM PDT 24
Finished May 30 02:49:59 PM PDT 24
Peak memory 200056 kb
Host smart-72dc46aa-8b67-4dcf-9cb3-b42e8ca292f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345070508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3345070508
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_smoke.2260717436
Short name T71
Test name
Test status
Simulation time 455381732 ps
CPU time 6.31 seconds
Started May 30 02:49:41 PM PDT 24
Finished May 30 02:49:49 PM PDT 24
Peak memory 200060 kb
Host smart-3f9f8980-7dd4-4488-affd-db91b56026a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260717436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2260717436
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.1033459296
Short name T155
Test name
Test status
Simulation time 4777266762 ps
CPU time 63.14 seconds
Started May 30 02:49:57 PM PDT 24
Finished May 30 02:51:02 PM PDT 24
Peak memory 200040 kb
Host smart-5ef7e275-d65b-4d30-b39e-296aadc4f29c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033459296 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.1033459296
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.1662026750
Short name T299
Test name
Test status
Simulation time 64117233 ps
CPU time 1.22 seconds
Started May 30 02:49:57 PM PDT 24
Finished May 30 02:50:00 PM PDT 24
Peak memory 200060 kb
Host smart-1c492ef2-de20-4883-a250-03aaaba98b13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662026750 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.1662026750
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.3264873858
Short name T223
Test name
Test status
Simulation time 28507477463 ps
CPU time 386.56 seconds
Started May 30 02:49:55 PM PDT 24
Finished May 30 02:56:23 PM PDT 24
Peak memory 200004 kb
Host smart-082978ca-c0ae-4bd5-94e9-4e0a33c616d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264873858 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.3264873858
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2010496165
Short name T429
Test name
Test status
Simulation time 463620023 ps
CPU time 7.99 seconds
Started May 30 02:49:45 PM PDT 24
Finished May 30 02:49:54 PM PDT 24
Peak memory 200008 kb
Host smart-ba0708cc-261e-4a37-9c5c-999d55ad0fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010496165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2010496165
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.879003007
Short name T533
Test name
Test status
Simulation time 41353913 ps
CPU time 0.61 seconds
Started May 30 02:51:10 PM PDT 24
Finished May 30 02:51:12 PM PDT 24
Peak memory 195940 kb
Host smart-a02921b7-9cd2-45de-84f2-d1735bdd1f5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879003007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.879003007
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.3210620629
Short name T495
Test name
Test status
Simulation time 931017050 ps
CPU time 19.72 seconds
Started May 30 02:51:10 PM PDT 24
Finished May 30 02:51:31 PM PDT 24
Peak memory 208248 kb
Host smart-8fd64028-8c4f-47b6-82a7-5bc1d900d2ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3210620629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.3210620629
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.4130231329
Short name T576
Test name
Test status
Simulation time 626106453 ps
CPU time 34.16 seconds
Started May 30 02:51:05 PM PDT 24
Finished May 30 02:51:40 PM PDT 24
Peak memory 200000 kb
Host smart-d061af7d-58b1-46f7-b191-ae262296b35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130231329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.4130231329
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.660149017
Short name T341
Test name
Test status
Simulation time 2062390153 ps
CPU time 445.26 seconds
Started May 30 02:51:11 PM PDT 24
Finished May 30 02:58:38 PM PDT 24
Peak memory 681180 kb
Host smart-416905d8-2a6d-4afa-877f-8cd09ddb760d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=660149017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.660149017
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1754894794
Short name T467
Test name
Test status
Simulation time 2305020449 ps
CPU time 10.07 seconds
Started May 30 02:51:03 PM PDT 24
Finished May 30 02:51:14 PM PDT 24
Peak memory 200028 kb
Host smart-6da5d596-36be-4141-8f9a-d0ee31319921
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754894794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1754894794
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2622645786
Short name T523
Test name
Test status
Simulation time 4668405780 ps
CPU time 67.94 seconds
Started May 30 02:51:13 PM PDT 24
Finished May 30 02:52:22 PM PDT 24
Peak memory 200132 kb
Host smart-ec680ac9-e326-4b48-b910-360f0315b8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622645786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2622645786
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.3338217734
Short name T326
Test name
Test status
Simulation time 1312879644 ps
CPU time 8.65 seconds
Started May 30 02:51:11 PM PDT 24
Finished May 30 02:51:21 PM PDT 24
Peak memory 200016 kb
Host smart-9e2ef5cd-560b-4399-bc90-4ea3d8dc3105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338217734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3338217734
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.4100855342
Short name T477
Test name
Test status
Simulation time 8644544401 ps
CPU time 811.28 seconds
Started May 30 02:51:11 PM PDT 24
Finished May 30 03:04:44 PM PDT 24
Peak memory 718004 kb
Host smart-192a34df-81da-4342-ae84-c8cb5bbc67b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100855342 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.4100855342
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.2763395752
Short name T302
Test name
Test status
Simulation time 97048892 ps
CPU time 1.35 seconds
Started May 30 02:51:10 PM PDT 24
Finished May 30 02:51:13 PM PDT 24
Peak memory 200008 kb
Host smart-c3a7b320-e03c-4d27-8026-dfc02317971b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763395752 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.2763395752
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.3187311268
Short name T93
Test name
Test status
Simulation time 7642729224 ps
CPU time 457.38 seconds
Started May 30 02:51:10 PM PDT 24
Finished May 30 02:58:49 PM PDT 24
Peak memory 200000 kb
Host smart-7fb431e7-b42f-451e-aa57-3447a92c6288
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187311268 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.3187311268
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3769375933
Short name T431
Test name
Test status
Simulation time 1493789446 ps
CPU time 22.74 seconds
Started May 30 02:51:05 PM PDT 24
Finished May 30 02:51:28 PM PDT 24
Peak memory 200020 kb
Host smart-b0468687-058b-44b0-bb2d-7887ce0fff51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769375933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3769375933
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1925153229
Short name T22
Test name
Test status
Simulation time 19539697 ps
CPU time 0.6 seconds
Started May 30 02:51:17 PM PDT 24
Finished May 30 02:51:21 PM PDT 24
Peak memory 196740 kb
Host smart-430f59d7-3fb2-4efd-8b87-823b8d432cb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925153229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1925153229
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.2398508960
Short name T334
Test name
Test status
Simulation time 344155319 ps
CPU time 3.59 seconds
Started May 30 02:51:11 PM PDT 24
Finished May 30 02:51:16 PM PDT 24
Peak memory 200048 kb
Host smart-b243c69a-daed-41e1-94fb-159c9d21bb0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2398508960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.2398508960
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3999595536
Short name T366
Test name
Test status
Simulation time 9242850522 ps
CPU time 48.7 seconds
Started May 30 02:51:05 PM PDT 24
Finished May 30 02:51:55 PM PDT 24
Peak memory 200144 kb
Host smart-ad1e1b53-ada5-42b6-87b5-b43015ef329e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999595536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3999595536
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1483386055
Short name T305
Test name
Test status
Simulation time 9519841811 ps
CPU time 570.51 seconds
Started May 30 02:51:11 PM PDT 24
Finished May 30 03:00:43 PM PDT 24
Peak memory 697748 kb
Host smart-9997adc0-5a02-4e9a-9e88-f7b59a2a79e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1483386055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1483386055
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1497367936
Short name T240
Test name
Test status
Simulation time 13461183 ps
CPU time 0.69 seconds
Started May 30 02:51:05 PM PDT 24
Finished May 30 02:51:07 PM PDT 24
Peak memory 196420 kb
Host smart-8920e9f5-83f6-4615-b906-d20544b42db2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497367936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1497367936
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2257571895
Short name T481
Test name
Test status
Simulation time 15854050869 ps
CPU time 81.36 seconds
Started May 30 02:51:05 PM PDT 24
Finished May 30 02:52:28 PM PDT 24
Peak memory 200020 kb
Host smart-ba16d48c-a8ba-48e5-b362-19abcff2d07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257571895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2257571895
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.854612792
Short name T237
Test name
Test status
Simulation time 1661841653 ps
CPU time 10.06 seconds
Started May 30 02:51:05 PM PDT 24
Finished May 30 02:51:16 PM PDT 24
Peak memory 200052 kb
Host smart-bdb5ca1c-22c0-491a-bbe0-db2aba5ae5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854612792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.854612792
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.546035870
Short name T1
Test name
Test status
Simulation time 79128500 ps
CPU time 1.47 seconds
Started May 30 02:51:10 PM PDT 24
Finished May 30 02:51:13 PM PDT 24
Peak memory 199928 kb
Host smart-b17fa492-aeba-436e-9c54-f8cf90f202f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546035870 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_hmac_vectors.546035870
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.2113792689
Short name T464
Test name
Test status
Simulation time 111938084246 ps
CPU time 480.48 seconds
Started May 30 02:51:11 PM PDT 24
Finished May 30 02:59:13 PM PDT 24
Peak memory 200176 kb
Host smart-5d774f7b-0bb0-4b18-8d3c-08f8dc1502f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113792689 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.2113792689
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.3250885613
Short name T361
Test name
Test status
Simulation time 4394671778 ps
CPU time 61.67 seconds
Started May 30 02:51:06 PM PDT 24
Finished May 30 02:52:09 PM PDT 24
Peak memory 200092 kb
Host smart-a01417a6-ad87-49bc-ad4d-f5a10dd9459d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250885613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3250885613
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.2985960464
Short name T23
Test name
Test status
Simulation time 14211871 ps
CPU time 0.61 seconds
Started May 30 02:51:17 PM PDT 24
Finished May 30 02:51:21 PM PDT 24
Peak memory 195988 kb
Host smart-a7f6f728-ca09-4a9c-9d8d-da6073449720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985960464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2985960464
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2591959627
Short name T485
Test name
Test status
Simulation time 263765975 ps
CPU time 11.78 seconds
Started May 30 02:51:16 PM PDT 24
Finished May 30 02:51:30 PM PDT 24
Peak memory 208228 kb
Host smart-0c73eee2-8321-4108-b561-b87cfad96320
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2591959627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2591959627
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.548298326
Short name T513
Test name
Test status
Simulation time 1474297285 ps
CPU time 40.57 seconds
Started May 30 02:51:15 PM PDT 24
Finished May 30 02:51:58 PM PDT 24
Peak memory 200032 kb
Host smart-54616227-a184-423f-9fe7-2d1daa90f569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548298326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.548298326
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.138774547
Short name T157
Test name
Test status
Simulation time 3113321564 ps
CPU time 941.93 seconds
Started May 30 02:51:20 PM PDT 24
Finished May 30 03:07:05 PM PDT 24
Peak memory 721808 kb
Host smart-5338b458-ca34-4215-848a-f2066a636529
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=138774547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.138774547
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.378787717
Short name T589
Test name
Test status
Simulation time 14793105952 ps
CPU time 69.49 seconds
Started May 30 02:51:18 PM PDT 24
Finished May 30 02:52:31 PM PDT 24
Peak memory 200060 kb
Host smart-3c383a60-426d-4b42-9dbc-768847eb172c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378787717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.378787717
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2400974774
Short name T376
Test name
Test status
Simulation time 9829860337 ps
CPU time 82.81 seconds
Started May 30 02:51:17 PM PDT 24
Finished May 30 02:52:43 PM PDT 24
Peak memory 200112 kb
Host smart-87461332-a570-4c59-bfa0-819213207aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400974774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2400974774
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1744441809
Short name T245
Test name
Test status
Simulation time 2162549328 ps
CPU time 11.3 seconds
Started May 30 02:51:17 PM PDT 24
Finished May 30 02:51:32 PM PDT 24
Peak memory 200088 kb
Host smart-8033dbee-0a06-41a9-bcce-1eb3aeec0562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744441809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1744441809
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.3340962324
Short name T587
Test name
Test status
Simulation time 2275930010 ps
CPU time 551.27 seconds
Started May 30 02:51:18 PM PDT 24
Finished May 30 03:00:33 PM PDT 24
Peak memory 691600 kb
Host smart-ffb384ca-2339-4c5c-aaa6-c1c4c55759b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340962324 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3340962324
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.2522979718
Short name T392
Test name
Test status
Simulation time 35563465 ps
CPU time 1.37 seconds
Started May 30 02:51:20 PM PDT 24
Finished May 30 02:51:24 PM PDT 24
Peak memory 200104 kb
Host smart-1382009b-066d-4607-95a7-08624dcf463c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522979718 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.2522979718
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.642370858
Short name T413
Test name
Test status
Simulation time 171177543509 ps
CPU time 550.88 seconds
Started May 30 02:51:18 PM PDT 24
Finished May 30 03:00:33 PM PDT 24
Peak memory 200092 kb
Host smart-3a377d7a-513d-4948-af62-bb27e5ee56c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642370858 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.642370858
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.706033843
Short name T213
Test name
Test status
Simulation time 272770405 ps
CPU time 4.82 seconds
Started May 30 02:51:20 PM PDT 24
Finished May 30 02:51:28 PM PDT 24
Peak memory 199968 kb
Host smart-d9cff733-606d-4375-bb68-59aadc065aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706033843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.706033843
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.3980350889
Short name T283
Test name
Test status
Simulation time 30371696 ps
CPU time 0.59 seconds
Started May 30 02:51:17 PM PDT 24
Finished May 30 02:51:20 PM PDT 24
Peak memory 194972 kb
Host smart-aedbf0dd-35f2-4f9c-b6b1-2a8038150687
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980350889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3980350889
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2561723703
Short name T519
Test name
Test status
Simulation time 801160907 ps
CPU time 26.17 seconds
Started May 30 02:51:17 PM PDT 24
Finished May 30 02:51:47 PM PDT 24
Peak memory 217404 kb
Host smart-9ae915db-0625-467a-b06d-859a8a973abe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2561723703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2561723703
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.32747318
Short name T236
Test name
Test status
Simulation time 3548149665 ps
CPU time 53.2 seconds
Started May 30 02:51:19 PM PDT 24
Finished May 30 02:52:16 PM PDT 24
Peak memory 200116 kb
Host smart-437a57cf-1844-427d-a459-92bf5f812a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32747318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.32747318
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.514490803
Short name T251
Test name
Test status
Simulation time 5456534753 ps
CPU time 451.69 seconds
Started May 30 02:51:18 PM PDT 24
Finished May 30 02:58:53 PM PDT 24
Peak memory 514328 kb
Host smart-b2e4713b-a0a4-49f1-a239-887347101c24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=514490803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.514490803
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1904481841
Short name T314
Test name
Test status
Simulation time 1467940338 ps
CPU time 42.83 seconds
Started May 30 02:51:19 PM PDT 24
Finished May 30 02:52:05 PM PDT 24
Peak memory 200004 kb
Host smart-f2d22781-8ab4-409e-ac12-ff67ea3f26a8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904481841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1904481841
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.773452997
Short name T260
Test name
Test status
Simulation time 5407601559 ps
CPU time 55.37 seconds
Started May 30 02:51:17 PM PDT 24
Finished May 30 02:52:16 PM PDT 24
Peak memory 200136 kb
Host smart-2424c073-d575-4887-a5bc-053399edf1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773452997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.773452997
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2962037438
Short name T484
Test name
Test status
Simulation time 1016612976 ps
CPU time 5.7 seconds
Started May 30 02:51:17 PM PDT 24
Finished May 30 02:51:26 PM PDT 24
Peak memory 200032 kb
Host smart-4bc4d70f-f753-416c-8fe4-a72ee8daee73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962037438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2962037438
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.2639668787
Short name T286
Test name
Test status
Simulation time 228650046205 ps
CPU time 4040.56 seconds
Started May 30 02:51:18 PM PDT 24
Finished May 30 03:58:42 PM PDT 24
Peak memory 823552 kb
Host smart-b05bb1d8-1347-4399-8335-aaa3875b0662
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639668787 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.2639668787
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.3082523212
Short name T179
Test name
Test status
Simulation time 41639882 ps
CPU time 1.12 seconds
Started May 30 02:51:18 PM PDT 24
Finished May 30 02:51:22 PM PDT 24
Peak memory 200016 kb
Host smart-0a77710c-7531-4874-a2e8-90773899aa25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082523212 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.3082523212
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.2592526810
Short name T141
Test name
Test status
Simulation time 305718062439 ps
CPU time 555.6 seconds
Started May 30 02:51:17 PM PDT 24
Finished May 30 03:00:35 PM PDT 24
Peak memory 200060 kb
Host smart-19a451c4-93de-4a14-bcc6-8b88a497326a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592526810 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.2592526810
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1281576705
Short name T352
Test name
Test status
Simulation time 3764059331 ps
CPU time 76.41 seconds
Started May 30 02:51:20 PM PDT 24
Finished May 30 02:52:39 PM PDT 24
Peak memory 200144 kb
Host smart-bd323eb7-bf2d-472c-b3a2-371ba8289909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281576705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1281576705
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3709107514
Short name T585
Test name
Test status
Simulation time 13302165 ps
CPU time 0.61 seconds
Started May 30 02:51:18 PM PDT 24
Finished May 30 02:51:22 PM PDT 24
Peak memory 196712 kb
Host smart-1ea4b042-d51f-4d41-a9ac-f6b0824320dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709107514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3709107514
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2030877003
Short name T262
Test name
Test status
Simulation time 803580974 ps
CPU time 40.44 seconds
Started May 30 02:51:23 PM PDT 24
Finished May 30 02:52:05 PM PDT 24
Peak memory 241948 kb
Host smart-8854b8e5-76b2-4c30-9cff-522c26e610bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2030877003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2030877003
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2656920944
Short name T386
Test name
Test status
Simulation time 1328929558 ps
CPU time 6.93 seconds
Started May 30 02:51:23 PM PDT 24
Finished May 30 02:51:32 PM PDT 24
Peak memory 200104 kb
Host smart-a04f4207-eec4-4f8a-b051-2c106f192b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656920944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2656920944
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3468956114
Short name T563
Test name
Test status
Simulation time 1140539497 ps
CPU time 61.16 seconds
Started May 30 02:51:24 PM PDT 24
Finished May 30 02:52:26 PM PDT 24
Peak memory 401428 kb
Host smart-fba2f0fb-a711-4115-b410-72bb3cd2c046
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3468956114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3468956114
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.211417217
Short name T220
Test name
Test status
Simulation time 35399365966 ps
CPU time 98.07 seconds
Started May 30 02:51:20 PM PDT 24
Finished May 30 02:53:01 PM PDT 24
Peak memory 200120 kb
Host smart-cb4dd5fe-6516-41ff-a3cf-4891110cb55b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211417217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.211417217
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.755140601
Short name T268
Test name
Test status
Simulation time 3720404316 ps
CPU time 62.8 seconds
Started May 30 02:51:19 PM PDT 24
Finished May 30 02:52:25 PM PDT 24
Peak memory 200116 kb
Host smart-db30b8dc-d51a-494a-90fd-83f7e45df266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755140601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.755140601
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2751403717
Short name T144
Test name
Test status
Simulation time 50451927 ps
CPU time 1.73 seconds
Started May 30 02:51:18 PM PDT 24
Finished May 30 02:51:23 PM PDT 24
Peak memory 200056 kb
Host smart-915f62ff-2c42-4338-b5d4-75eaecc00d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751403717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2751403717
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3516692898
Short name T39
Test name
Test status
Simulation time 42366215291 ps
CPU time 537.33 seconds
Started May 30 02:51:24 PM PDT 24
Finished May 30 03:00:23 PM PDT 24
Peak memory 228824 kb
Host smart-8c5d5cbb-3753-40ce-a750-e1dee82bdb08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516692898 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3516692898
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.3271182912
Short name T168
Test name
Test status
Simulation time 113508333 ps
CPU time 1.08 seconds
Started May 30 02:51:21 PM PDT 24
Finished May 30 02:51:24 PM PDT 24
Peak memory 200052 kb
Host smart-3d0ab7c1-c821-4061-b0b2-cd1d6fe820b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271182912 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.3271182912
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.1493749979
Short name T494
Test name
Test status
Simulation time 51444879884 ps
CPU time 475.18 seconds
Started May 30 02:51:21 PM PDT 24
Finished May 30 02:59:18 PM PDT 24
Peak memory 200068 kb
Host smart-5e31d413-ffde-4f2f-b91b-db8e722cccc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493749979 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.1493749979
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3551513484
Short name T453
Test name
Test status
Simulation time 22642240742 ps
CPU time 66.42 seconds
Started May 30 02:51:24 PM PDT 24
Finished May 30 02:52:32 PM PDT 24
Peak memory 200144 kb
Host smart-96e9b739-7683-47d5-90b6-e541e6ee3f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551513484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3551513484
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.860186765
Short name T450
Test name
Test status
Simulation time 37605112 ps
CPU time 0.59 seconds
Started May 30 02:51:32 PM PDT 24
Finished May 30 02:51:34 PM PDT 24
Peak memory 195996 kb
Host smart-ca79392c-6071-44fe-84ed-93856e8b9272
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860186765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.860186765
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3467545910
Short name T46
Test name
Test status
Simulation time 1548112660 ps
CPU time 16.11 seconds
Started May 30 02:51:19 PM PDT 24
Finished May 30 02:51:38 PM PDT 24
Peak memory 210920 kb
Host smart-4e8704b6-4510-4505-bbff-8ebd5df3b4af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3467545910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3467545910
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3930946585
Short name T492
Test name
Test status
Simulation time 214395867 ps
CPU time 11.26 seconds
Started May 30 02:51:19 PM PDT 24
Finished May 30 02:51:33 PM PDT 24
Peak memory 200048 kb
Host smart-66bff2b0-b9a4-4625-a52f-671895c8b94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930946585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3930946585
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.3179289330
Short name T123
Test name
Test status
Simulation time 18740280997 ps
CPU time 1126.67 seconds
Started May 30 02:51:23 PM PDT 24
Finished May 30 03:10:12 PM PDT 24
Peak memory 720392 kb
Host smart-3f02be77-41e4-4c48-b124-a430bf719a16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3179289330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3179289330
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.4175785545
Short name T41
Test name
Test status
Simulation time 39870263065 ps
CPU time 184 seconds
Started May 30 02:51:20 PM PDT 24
Finished May 30 02:54:27 PM PDT 24
Peak memory 200028 kb
Host smart-45603294-f18a-4484-8f04-1028129dcb47
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175785545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.4175785545
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.618501402
Short name T264
Test name
Test status
Simulation time 10839707477 ps
CPU time 54.06 seconds
Started May 30 02:51:23 PM PDT 24
Finished May 30 02:52:19 PM PDT 24
Peak memory 199976 kb
Host smart-6cedb941-77c9-42e3-8abb-834152da36df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618501402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.618501402
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2632717866
Short name T151
Test name
Test status
Simulation time 45322187 ps
CPU time 1.27 seconds
Started May 30 02:51:20 PM PDT 24
Finished May 30 02:51:25 PM PDT 24
Peak memory 199828 kb
Host smart-59d16f48-6aa0-49e8-9e11-3f8826a66e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632717866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2632717866
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.1454048249
Short name T172
Test name
Test status
Simulation time 61925446790 ps
CPU time 1215.2 seconds
Started May 30 02:51:30 PM PDT 24
Finished May 30 03:11:47 PM PDT 24
Peak memory 241136 kb
Host smart-b6d47860-9722-4c5f-95f9-8f7d8959237e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454048249 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1454048249
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.4225868676
Short name T150
Test name
Test status
Simulation time 28417955 ps
CPU time 1.08 seconds
Started May 30 02:51:18 PM PDT 24
Finished May 30 02:51:22 PM PDT 24
Peak memory 199876 kb
Host smart-ead35212-eac5-4473-b7e7-dcbf1faf8aff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225868676 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.4225868676
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.3410031149
Short name T435
Test name
Test status
Simulation time 24763054824 ps
CPU time 451.94 seconds
Started May 30 02:51:20 PM PDT 24
Finished May 30 02:58:55 PM PDT 24
Peak memory 200008 kb
Host smart-09955a12-ca00-413f-a292-56439acb3386
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410031149 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.3410031149
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1590612760
Short name T342
Test name
Test status
Simulation time 1991435628 ps
CPU time 89.46 seconds
Started May 30 02:51:24 PM PDT 24
Finished May 30 02:52:55 PM PDT 24
Peak memory 200080 kb
Host smart-cf74dac4-af4d-4f9b-940a-6bbd5eda6586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590612760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1590612760
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2250990502
Short name T295
Test name
Test status
Simulation time 25252408 ps
CPU time 0.61 seconds
Started May 30 02:51:29 PM PDT 24
Finished May 30 02:51:32 PM PDT 24
Peak memory 195932 kb
Host smart-1f69d107-6f2b-4e1e-bdd9-d447303d5c49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250990502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2250990502
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2295625645
Short name T368
Test name
Test status
Simulation time 149737910 ps
CPU time 7.21 seconds
Started May 30 02:51:29 PM PDT 24
Finished May 30 02:51:38 PM PDT 24
Peak memory 215740 kb
Host smart-e0279b1f-c54f-4630-8773-80e77008f5f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2295625645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2295625645
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.3834286966
Short name T121
Test name
Test status
Simulation time 2910105091 ps
CPU time 47.21 seconds
Started May 30 02:51:29 PM PDT 24
Finished May 30 02:52:18 PM PDT 24
Peak memory 200148 kb
Host smart-e59fc706-e55d-4e8b-9d29-b3fe28748182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834286966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.3834286966
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.2431123159
Short name T554
Test name
Test status
Simulation time 18830786586 ps
CPU time 1309.3 seconds
Started May 30 02:51:32 PM PDT 24
Finished May 30 03:13:23 PM PDT 24
Peak memory 765784 kb
Host smart-995a058a-02ac-4357-9127-9c715f93e7eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2431123159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2431123159
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.2698529792
Short name T476
Test name
Test status
Simulation time 2533675429 ps
CPU time 44.19 seconds
Started May 30 02:51:28 PM PDT 24
Finished May 30 02:52:14 PM PDT 24
Peak memory 200016 kb
Host smart-ffdb81ab-87e8-4b1a-8cc7-ef4a74c2398e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698529792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2698529792
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3658048567
Short name T370
Test name
Test status
Simulation time 2213713334 ps
CPU time 41.91 seconds
Started May 30 02:51:32 PM PDT 24
Finished May 30 02:52:15 PM PDT 24
Peak memory 200116 kb
Host smart-d9f24f49-22c1-4bc8-8f15-1bb01f9c6f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658048567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3658048567
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2183113837
Short name T192
Test name
Test status
Simulation time 270493202 ps
CPU time 4.22 seconds
Started May 30 02:51:34 PM PDT 24
Finished May 30 02:51:40 PM PDT 24
Peak memory 200048 kb
Host smart-91cc25bf-1f03-4bfa-b437-e7ed51e22298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183113837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2183113837
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.479679844
Short name T309
Test name
Test status
Simulation time 134670322943 ps
CPU time 2393.9 seconds
Started May 30 02:51:29 PM PDT 24
Finished May 30 03:31:25 PM PDT 24
Peak memory 798388 kb
Host smart-9c6dc3a6-3baf-479a-aa20-83f086283432
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479679844 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.479679844
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.531348324
Short name T59
Test name
Test status
Simulation time 77828261 ps
CPU time 1.45 seconds
Started May 30 02:51:34 PM PDT 24
Finished May 30 02:51:37 PM PDT 24
Peak memory 199988 kb
Host smart-c3e63c98-0886-41cb-b57e-a1b7b8709e44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531348324 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_hmac_vectors.531348324
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.557204712
Short name T163
Test name
Test status
Simulation time 10976861473 ps
CPU time 449.89 seconds
Started May 30 02:51:29 PM PDT 24
Finished May 30 02:59:01 PM PDT 24
Peak memory 200084 kb
Host smart-075f8f9e-0a35-461a-aa1b-e9906e3c3009
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557204712 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.557204712
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_alert_test.3895013174
Short name T152
Test name
Test status
Simulation time 11716213 ps
CPU time 0.57 seconds
Started May 30 02:51:31 PM PDT 24
Finished May 30 02:51:33 PM PDT 24
Peak memory 194980 kb
Host smart-58665727-25cd-4aeb-801b-b58c694a160c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895013174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3895013174
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3018257645
Short name T284
Test name
Test status
Simulation time 6887332634 ps
CPU time 59.87 seconds
Started May 30 02:51:32 PM PDT 24
Finished May 30 02:52:33 PM PDT 24
Peak memory 248660 kb
Host smart-5dcca43c-8c09-44f8-ba3e-0f2524a06e4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3018257645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3018257645
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.118880156
Short name T269
Test name
Test status
Simulation time 2611925949 ps
CPU time 48.1 seconds
Started May 30 02:51:29 PM PDT 24
Finished May 30 02:52:20 PM PDT 24
Peak memory 200088 kb
Host smart-342842e0-07e2-4299-9304-7515763276ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118880156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.118880156
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.338457214
Short name T207
Test name
Test status
Simulation time 43835798656 ps
CPU time 827.46 seconds
Started May 30 02:51:28 PM PDT 24
Finished May 30 03:05:17 PM PDT 24
Peak memory 740568 kb
Host smart-87121bb8-6343-465c-91cd-c40c51aeec9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=338457214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.338457214
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2689324138
Short name T169
Test name
Test status
Simulation time 24649849489 ps
CPU time 89.35 seconds
Started May 30 02:51:34 PM PDT 24
Finished May 30 02:53:05 PM PDT 24
Peak memory 200112 kb
Host smart-7db0386e-6216-43ac-8710-e1ff54fe9159
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689324138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2689324138
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2447728465
Short name T25
Test name
Test status
Simulation time 377277301 ps
CPU time 22.77 seconds
Started May 30 02:51:30 PM PDT 24
Finished May 30 02:51:55 PM PDT 24
Peak memory 200040 kb
Host smart-bcd2f75e-6377-4c37-ab6d-8ac44c84661b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447728465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2447728465
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2988694983
Short name T318
Test name
Test status
Simulation time 607888608 ps
CPU time 6.08 seconds
Started May 30 02:51:34 PM PDT 24
Finished May 30 02:51:42 PM PDT 24
Peak memory 200012 kb
Host smart-09ec8ab1-4a14-494a-8963-de17ec79d978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988694983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2988694983
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.46873327
Short name T541
Test name
Test status
Simulation time 43214749441 ps
CPU time 1570.78 seconds
Started May 30 02:51:28 PM PDT 24
Finished May 30 03:17:41 PM PDT 24
Peak memory 714056 kb
Host smart-3eca13cd-1f16-4b82-9058-918bff73849b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46873327 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.46873327
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.783963210
Short name T483
Test name
Test status
Simulation time 546950018 ps
CPU time 1.34 seconds
Started May 30 02:51:29 PM PDT 24
Finished May 30 02:51:32 PM PDT 24
Peak memory 199948 kb
Host smart-51a7e292-1cfb-48cd-86c0-a80fad0b91fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783963210 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_hmac_vectors.783963210
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.4136627444
Short name T216
Test name
Test status
Simulation time 24905338054 ps
CPU time 464.96 seconds
Started May 30 02:51:34 PM PDT 24
Finished May 30 02:59:21 PM PDT 24
Peak memory 200040 kb
Host smart-509448e5-fb5e-4a3e-acac-d3589c8ffa30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136627444 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.4136627444
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.2122221319
Short name T275
Test name
Test status
Simulation time 1847012521 ps
CPU time 24.34 seconds
Started May 30 02:51:32 PM PDT 24
Finished May 30 02:51:58 PM PDT 24
Peak memory 200032 kb
Host smart-88d3ab71-a55c-464a-aeef-5ccf546527a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122221319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2122221319
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.282637133
Short name T396
Test name
Test status
Simulation time 25993767 ps
CPU time 0.59 seconds
Started May 30 02:51:42 PM PDT 24
Finished May 30 02:51:44 PM PDT 24
Peak memory 195988 kb
Host smart-c9260752-6a68-4efb-83a3-574d7e6df5ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282637133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.282637133
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3746400162
Short name T50
Test name
Test status
Simulation time 3283066965 ps
CPU time 32 seconds
Started May 30 02:51:29 PM PDT 24
Finished May 30 02:52:03 PM PDT 24
Peak memory 230848 kb
Host smart-f7c9c2ba-8200-4061-ae4c-61a99b3bf12a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3746400162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3746400162
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.2260810036
Short name T242
Test name
Test status
Simulation time 1002328306 ps
CPU time 14.74 seconds
Started May 30 02:51:28 PM PDT 24
Finished May 30 02:51:45 PM PDT 24
Peak memory 200088 kb
Host smart-afe4b00f-d774-4089-9782-32ffdddfed7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260810036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2260810036
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3821554128
Short name T493
Test name
Test status
Simulation time 1287588544 ps
CPU time 334.99 seconds
Started May 30 02:51:34 PM PDT 24
Finished May 30 02:57:11 PM PDT 24
Peak memory 659840 kb
Host smart-a2f06ff5-9849-45a3-acff-4eef021ce10a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3821554128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3821554128
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.2428037508
Short name T45
Test name
Test status
Simulation time 1099291201 ps
CPU time 15.04 seconds
Started May 30 02:51:40 PM PDT 24
Finished May 30 02:51:56 PM PDT 24
Peak memory 199960 kb
Host smart-8df5b30f-85b4-43c1-9770-95afb43dd9a9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428037508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.2428037508
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.3265498115
Short name T411
Test name
Test status
Simulation time 1353275058 ps
CPU time 10.78 seconds
Started May 30 02:51:33 PM PDT 24
Finished May 30 02:51:45 PM PDT 24
Peak memory 199972 kb
Host smart-14208525-1db2-4fe8-96c1-b756192b3329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265498115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3265498115
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.835384889
Short name T542
Test name
Test status
Simulation time 529580998 ps
CPU time 5.41 seconds
Started May 30 02:51:31 PM PDT 24
Finished May 30 02:51:38 PM PDT 24
Peak memory 200124 kb
Host smart-7422061f-963f-4303-9664-1d9c9a367a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835384889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.835384889
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.652778838
Short name T78
Test name
Test status
Simulation time 101611564340 ps
CPU time 844.65 seconds
Started May 30 02:51:42 PM PDT 24
Finished May 30 03:05:47 PM PDT 24
Peak memory 722088 kb
Host smart-4bb75441-6a4f-46a4-9f54-e69465fce4eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652778838 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.652778838
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.690399171
Short name T89
Test name
Test status
Simulation time 385777303 ps
CPU time 1.3 seconds
Started May 30 02:51:56 PM PDT 24
Finished May 30 02:51:59 PM PDT 24
Peak memory 200004 kb
Host smart-2265fc31-c328-4616-9d53-c94eb27e064e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690399171 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_hmac_vectors.690399171
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.2636551478
Short name T472
Test name
Test status
Simulation time 258714196891 ps
CPU time 538.67 seconds
Started May 30 02:51:42 PM PDT 24
Finished May 30 03:00:42 PM PDT 24
Peak memory 200048 kb
Host smart-a0c49af4-635c-4d4d-9ffe-a86a3e45c8d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636551478 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.2636551478
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.1029828390
Short name T398
Test name
Test status
Simulation time 4785286697 ps
CPU time 22.51 seconds
Started May 30 02:51:42 PM PDT 24
Finished May 30 02:52:05 PM PDT 24
Peak memory 200096 kb
Host smart-2242afe0-90d9-46ff-9b03-99f05ea08ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029828390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.1029828390
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.2966777164
Short name T471
Test name
Test status
Simulation time 30888525 ps
CPU time 0.59 seconds
Started May 30 02:51:41 PM PDT 24
Finished May 30 02:51:43 PM PDT 24
Peak memory 194924 kb
Host smart-d558357b-673a-421e-a7f4-483578422958
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966777164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2966777164
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2136309204
Short name T230
Test name
Test status
Simulation time 531833993 ps
CPU time 25.34 seconds
Started May 30 02:51:56 PM PDT 24
Finished May 30 02:52:24 PM PDT 24
Peak memory 223048 kb
Host smart-b5f613d8-4498-4b51-86da-8bcd0fb913b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2136309204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2136309204
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.1407299256
Short name T310
Test name
Test status
Simulation time 1383512274 ps
CPU time 5.97 seconds
Started May 30 02:51:55 PM PDT 24
Finished May 30 02:52:03 PM PDT 24
Peak memory 199948 kb
Host smart-d7c34608-f1f7-4227-8a52-537ba30cd09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407299256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1407299256
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.996389094
Short name T394
Test name
Test status
Simulation time 3147125558 ps
CPU time 857 seconds
Started May 30 02:51:42 PM PDT 24
Finished May 30 03:06:00 PM PDT 24
Peak memory 692044 kb
Host smart-e20b11ea-8a92-42e3-a327-76e758e51e46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=996389094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.996389094
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.3344837860
Short name T502
Test name
Test status
Simulation time 24096690462 ps
CPU time 59.26 seconds
Started May 30 02:51:56 PM PDT 24
Finished May 30 02:52:57 PM PDT 24
Peak memory 200092 kb
Host smart-3b25186c-5e09-4532-a7db-e8ff173ed1a3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344837860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.3344837860
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2618027926
Short name T243
Test name
Test status
Simulation time 12209399881 ps
CPU time 81.78 seconds
Started May 30 02:51:41 PM PDT 24
Finished May 30 02:53:04 PM PDT 24
Peak memory 200140 kb
Host smart-b5f6e5e2-5e04-4076-8043-a84bc3ebf1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618027926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2618027926
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.401346078
Short name T161
Test name
Test status
Simulation time 348708274 ps
CPU time 3.92 seconds
Started May 30 02:51:55 PM PDT 24
Finished May 30 02:52:01 PM PDT 24
Peak memory 199996 kb
Host smart-84707f80-ec2e-4d98-b157-ca4552f8ee21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401346078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.401346078
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2593040370
Short name T367
Test name
Test status
Simulation time 44804836045 ps
CPU time 1021.76 seconds
Started May 30 02:51:55 PM PDT 24
Finished May 30 03:08:59 PM PDT 24
Peak memory 710816 kb
Host smart-6e7ebcc7-187c-4f5e-a14d-300117ee3cb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593040370 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2593040370
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.1614850852
Short name T30
Test name
Test status
Simulation time 479154440 ps
CPU time 1.35 seconds
Started May 30 02:51:41 PM PDT 24
Finished May 30 02:51:43 PM PDT 24
Peak memory 200120 kb
Host smart-4a59359e-4336-4850-8ee5-277aeafbc315
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614850852 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.1614850852
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.906444962
Short name T222
Test name
Test status
Simulation time 113179823348 ps
CPU time 469.53 seconds
Started May 30 02:51:42 PM PDT 24
Finished May 30 02:59:33 PM PDT 24
Peak memory 200120 kb
Host smart-df3a4159-bb68-4885-8d92-5a984589690c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906444962 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.906444962
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.4289758506
Short name T441
Test name
Test status
Simulation time 18382729104 ps
CPU time 55.19 seconds
Started May 30 02:51:55 PM PDT 24
Finished May 30 02:52:52 PM PDT 24
Peak memory 200020 kb
Host smart-f0008ae6-1e58-4b27-9677-19014e331832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289758506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.4289758506
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.1986913138
Short name T350
Test name
Test status
Simulation time 106107054 ps
CPU time 0.62 seconds
Started May 30 02:49:55 PM PDT 24
Finished May 30 02:49:58 PM PDT 24
Peak memory 196728 kb
Host smart-111306ad-bfec-462d-b094-b8b2b4535ac1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986913138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1986913138
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.1117238793
Short name T47
Test name
Test status
Simulation time 1114203362 ps
CPU time 63.19 seconds
Started May 30 02:49:58 PM PDT 24
Finished May 30 02:51:03 PM PDT 24
Peak memory 226520 kb
Host smart-4e2d7c43-37ff-41c5-86a4-2b67527033eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1117238793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1117238793
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.2084547983
Short name T475
Test name
Test status
Simulation time 2120434845 ps
CPU time 26.69 seconds
Started May 30 02:49:57 PM PDT 24
Finished May 30 02:50:26 PM PDT 24
Peak memory 200020 kb
Host smart-da159aa2-632c-4bba-a009-747596350740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084547983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.2084547983
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.674935378
Short name T586
Test name
Test status
Simulation time 7143399809 ps
CPU time 904.64 seconds
Started May 30 02:49:58 PM PDT 24
Finished May 30 03:05:04 PM PDT 24
Peak memory 711700 kb
Host smart-195ed0e7-f9b1-491f-a3ae-9557f2e1870f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=674935378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.674935378
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.3860753583
Short name T408
Test name
Test status
Simulation time 7526810337 ps
CPU time 83.39 seconds
Started May 30 02:49:54 PM PDT 24
Finished May 30 02:51:19 PM PDT 24
Peak memory 200096 kb
Host smart-6d542615-69eb-47dc-a3c2-fc6c48701f9f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860753583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.3860753583
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.1275015995
Short name T333
Test name
Test status
Simulation time 5509541733 ps
CPU time 92.25 seconds
Started May 30 02:49:56 PM PDT 24
Finished May 30 02:51:30 PM PDT 24
Peak memory 199740 kb
Host smart-39775b0d-8d2f-484c-9d09-9cbeb9b6e7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275015995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1275015995
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3946435607
Short name T34
Test name
Test status
Simulation time 100474790 ps
CPU time 0.79 seconds
Started May 30 02:49:56 PM PDT 24
Finished May 30 02:49:59 PM PDT 24
Peak memory 218180 kb
Host smart-c28a8562-c593-4607-ba19-9f8b0343846a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946435607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3946435607
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.2860439117
Short name T111
Test name
Test status
Simulation time 274211106 ps
CPU time 3.88 seconds
Started May 30 02:49:55 PM PDT 24
Finished May 30 02:50:00 PM PDT 24
Peak memory 200076 kb
Host smart-579a22ee-d90e-48da-aa43-c5abde48bc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860439117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.2860439117
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3550608461
Short name T552
Test name
Test status
Simulation time 199799455234 ps
CPU time 1441.27 seconds
Started May 30 02:49:55 PM PDT 24
Finished May 30 03:13:58 PM PDT 24
Peak memory 658020 kb
Host smart-8bb7d65b-a020-4945-babd-544aa1866fb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550608461 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3550608461
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.3558744022
Short name T508
Test name
Test status
Simulation time 62952823 ps
CPU time 1.44 seconds
Started May 30 02:49:55 PM PDT 24
Finished May 30 02:49:58 PM PDT 24
Peak memory 199984 kb
Host smart-ac0b8edd-c124-450e-b729-98a7e5995194
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558744022 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.3558744022
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.3580796269
Short name T191
Test name
Test status
Simulation time 117251699558 ps
CPU time 533.56 seconds
Started May 30 02:49:57 PM PDT 24
Finished May 30 02:58:52 PM PDT 24
Peak memory 200068 kb
Host smart-ea8776d2-9c2c-401e-84cf-03b5861d39bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580796269 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.3580796269
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1355736318
Short name T176
Test name
Test status
Simulation time 1107356732 ps
CPU time 17.06 seconds
Started May 30 02:49:54 PM PDT 24
Finished May 30 02:50:13 PM PDT 24
Peak memory 200064 kb
Host smart-ca315ad8-61d1-4390-93b3-ee145453ee04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355736318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1355736318
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.2351403914
Short name T550
Test name
Test status
Simulation time 11973208 ps
CPU time 0.66 seconds
Started May 30 02:51:54 PM PDT 24
Finished May 30 02:51:57 PM PDT 24
Peak memory 196732 kb
Host smart-64f57cd9-7786-4cc5-98f9-141fa4baf81e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351403914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2351403914
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.36332794
Short name T412
Test name
Test status
Simulation time 430441230 ps
CPU time 13.57 seconds
Started May 30 02:51:56 PM PDT 24
Finished May 30 02:52:12 PM PDT 24
Peak memory 216364 kb
Host smart-9dd0686d-197b-4459-b9c9-8550b0dc32dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=36332794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.36332794
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1169095739
Short name T527
Test name
Test status
Simulation time 1423737461 ps
CPU time 19.78 seconds
Started May 30 02:51:53 PM PDT 24
Finished May 30 02:52:13 PM PDT 24
Peak memory 199992 kb
Host smart-1728a10b-9835-48b5-948e-d043e1010793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169095739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1169095739
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.189232659
Short name T430
Test name
Test status
Simulation time 3171789827 ps
CPU time 445.87 seconds
Started May 30 02:51:54 PM PDT 24
Finished May 30 02:59:22 PM PDT 24
Peak memory 616832 kb
Host smart-d0e63d25-b031-4fbe-a3a1-38c71b6b5456
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=189232659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.189232659
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1468534444
Short name T257
Test name
Test status
Simulation time 28198251713 ps
CPU time 127.22 seconds
Started May 30 02:51:54 PM PDT 24
Finished May 30 02:54:04 PM PDT 24
Peak memory 200024 kb
Host smart-8b5402af-f593-4637-a0ff-ad5f615f4cc4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468534444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1468534444
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2766757395
Short name T145
Test name
Test status
Simulation time 11631376166 ps
CPU time 103.43 seconds
Started May 30 02:51:55 PM PDT 24
Finished May 30 02:53:41 PM PDT 24
Peak memory 200076 kb
Host smart-2303a282-f169-4458-bd15-bc608d6a76e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766757395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2766757395
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.1770522776
Short name T313
Test name
Test status
Simulation time 140372659 ps
CPU time 2.86 seconds
Started May 30 02:51:56 PM PDT 24
Finished May 30 02:52:01 PM PDT 24
Peak memory 199976 kb
Host smart-adb15212-4160-418d-9922-5509aac7f543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770522776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1770522776
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.1128116455
Short name T261
Test name
Test status
Simulation time 123587222 ps
CPU time 1.38 seconds
Started May 30 02:51:55 PM PDT 24
Finished May 30 02:51:59 PM PDT 24
Peak memory 200064 kb
Host smart-5c28c292-5c28-4e44-84ad-88fcd982188e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128116455 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.1128116455
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.2511765517
Short name T147
Test name
Test status
Simulation time 36969313906 ps
CPU time 524.77 seconds
Started May 30 02:51:54 PM PDT 24
Finished May 30 03:00:41 PM PDT 24
Peak memory 200068 kb
Host smart-bb97f19e-4ee8-4576-9ab9-4c8380ad6f03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511765517 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.2511765517
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.133710257
Short name T205
Test name
Test status
Simulation time 1613751461 ps
CPU time 87.46 seconds
Started May 30 02:51:54 PM PDT 24
Finished May 30 02:53:24 PM PDT 24
Peak memory 200072 kb
Host smart-2fdd37d2-7899-4554-a252-0b0f9542c7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133710257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.133710257
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.408110958
Short name T583
Test name
Test status
Simulation time 19439353 ps
CPU time 0.61 seconds
Started May 30 02:51:56 PM PDT 24
Finished May 30 02:51:59 PM PDT 24
Peak memory 195964 kb
Host smart-a7048d92-a4fe-43d2-afa2-7c32cdeef402
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408110958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.408110958
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1924143386
Short name T426
Test name
Test status
Simulation time 18780914621 ps
CPU time 46.55 seconds
Started May 30 02:51:53 PM PDT 24
Finished May 30 02:52:41 PM PDT 24
Peak memory 208204 kb
Host smart-bb3f96c2-e903-4c75-833b-51ac2fdb1b36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1924143386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1924143386
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.509832690
Short name T506
Test name
Test status
Simulation time 1350112987 ps
CPU time 73.44 seconds
Started May 30 02:51:53 PM PDT 24
Finished May 30 02:53:08 PM PDT 24
Peak memory 200044 kb
Host smart-812a6eeb-bba9-458b-8ea5-c011b4a8a630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509832690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.509832690
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2786414423
Short name T346
Test name
Test status
Simulation time 5151482190 ps
CPU time 1159.96 seconds
Started May 30 02:51:53 PM PDT 24
Finished May 30 03:11:14 PM PDT 24
Peak memory 772080 kb
Host smart-c36f249a-1b40-4960-bb92-a12fcf324656
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2786414423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2786414423
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.1724931879
Short name T328
Test name
Test status
Simulation time 41440332876 ps
CPU time 123.02 seconds
Started May 30 02:51:55 PM PDT 24
Finished May 30 02:54:00 PM PDT 24
Peak memory 200104 kb
Host smart-0b5559c2-b520-4f0e-b11b-cbb2abcb6ac6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724931879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1724931879
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3075454340
Short name T438
Test name
Test status
Simulation time 13979824911 ps
CPU time 107.71 seconds
Started May 30 02:51:55 PM PDT 24
Finished May 30 02:53:45 PM PDT 24
Peak memory 200084 kb
Host smart-7fd2c453-b26b-4792-a7fa-439f8a99fed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075454340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3075454340
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1274373273
Short name T514
Test name
Test status
Simulation time 161776286 ps
CPU time 3.41 seconds
Started May 30 02:51:54 PM PDT 24
Finished May 30 02:51:59 PM PDT 24
Peak memory 200044 kb
Host smart-493f43b0-5be8-4937-addf-fdfd16ab280c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274373273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1274373273
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.3662757848
Short name T43
Test name
Test status
Simulation time 398255060973 ps
CPU time 1376.31 seconds
Started May 30 02:51:55 PM PDT 24
Finished May 30 03:14:54 PM PDT 24
Peak memory 224740 kb
Host smart-98b93ece-cc31-426b-b066-f61a9b63a567
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662757848 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.3662757848
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.1526122318
Short name T465
Test name
Test status
Simulation time 32799914 ps
CPU time 1.28 seconds
Started May 30 02:51:54 PM PDT 24
Finished May 30 02:51:56 PM PDT 24
Peak memory 200096 kb
Host smart-98fe2e27-206c-418b-8044-54617820faa4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526122318 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.1526122318
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.3161431185
Short name T235
Test name
Test status
Simulation time 130750440049 ps
CPU time 513.46 seconds
Started May 30 02:51:54 PM PDT 24
Finished May 30 03:00:29 PM PDT 24
Peak memory 200052 kb
Host smart-2ed13b3e-cb2d-432a-bf35-07b06daf85e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161431185 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.3161431185
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.3336895312
Short name T424
Test name
Test status
Simulation time 2119273319 ps
CPU time 44.07 seconds
Started May 30 02:51:54 PM PDT 24
Finished May 30 02:52:41 PM PDT 24
Peak memory 200024 kb
Host smart-1bae71e8-03a3-4b6b-8180-d7af69a6a243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336895312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.3336895312
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.127080884
Short name T371
Test name
Test status
Simulation time 15857219 ps
CPU time 0.61 seconds
Started May 30 02:52:09 PM PDT 24
Finished May 30 02:52:12 PM PDT 24
Peak memory 195972 kb
Host smart-c908cafe-7a55-4746-a51f-fd75d7511e68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127080884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.127080884
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.152328109
Short name T181
Test name
Test status
Simulation time 384689304 ps
CPU time 17.24 seconds
Started May 30 02:52:07 PM PDT 24
Finished May 30 02:52:28 PM PDT 24
Peak memory 208240 kb
Host smart-8e21e9dd-397c-4e02-bf79-aa0fd8ebf377
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=152328109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.152328109
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1927216056
Short name T159
Test name
Test status
Simulation time 301708570 ps
CPU time 2.2 seconds
Started May 30 02:52:08 PM PDT 24
Finished May 30 02:52:13 PM PDT 24
Peak memory 200000 kb
Host smart-8c6152e1-b0ae-46d3-b15f-36fb341a7d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927216056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1927216056
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3436299177
Short name T549
Test name
Test status
Simulation time 2233084611 ps
CPU time 480.37 seconds
Started May 30 02:52:07 PM PDT 24
Finished May 30 03:00:09 PM PDT 24
Peak memory 625988 kb
Host smart-cfdb2255-195f-46cd-a127-d28ca7650ccc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3436299177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3436299177
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3258287593
Short name T241
Test name
Test status
Simulation time 240880889 ps
CPU time 4.96 seconds
Started May 30 02:52:08 PM PDT 24
Finished May 30 02:52:16 PM PDT 24
Peak memory 199936 kb
Host smart-38f98660-54e2-496d-915d-405c56694419
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258287593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3258287593
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2936987352
Short name T37
Test name
Test status
Simulation time 5848699372 ps
CPU time 86.52 seconds
Started May 30 02:52:08 PM PDT 24
Finished May 30 02:53:37 PM PDT 24
Peak memory 200092 kb
Host smart-afb4f370-0487-4faf-83a3-c77a2436f77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936987352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2936987352
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.997709031
Short name T414
Test name
Test status
Simulation time 369120893 ps
CPU time 2.28 seconds
Started May 30 02:51:55 PM PDT 24
Finished May 30 02:51:59 PM PDT 24
Peak memory 200036 kb
Host smart-0f8de542-535b-439d-9c2b-d5c8bedd6aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997709031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.997709031
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.3469411922
Short name T447
Test name
Test status
Simulation time 15810847152 ps
CPU time 50.21 seconds
Started May 30 02:52:09 PM PDT 24
Finished May 30 02:53:02 PM PDT 24
Peak memory 215996 kb
Host smart-f64731ac-39e9-48e0-9838-692782a15c90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469411922 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.3469411922
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.494232745
Short name T301
Test name
Test status
Simulation time 121449989 ps
CPU time 1.12 seconds
Started May 30 02:52:08 PM PDT 24
Finished May 30 02:52:12 PM PDT 24
Peak memory 199852 kb
Host smart-87798221-2605-4c5f-9905-dd55261f5059
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494232745 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_hmac_vectors.494232745
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.1124995087
Short name T185
Test name
Test status
Simulation time 26257913361 ps
CPU time 369.21 seconds
Started May 30 02:52:08 PM PDT 24
Finished May 30 02:58:20 PM PDT 24
Peak memory 200092 kb
Host smart-df5bb3f4-2950-403e-838f-c3e0c53c1962
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124995087 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.1124995087
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.2158128381
Short name T489
Test name
Test status
Simulation time 408575164 ps
CPU time 23.14 seconds
Started May 30 02:52:07 PM PDT 24
Finished May 30 02:52:34 PM PDT 24
Peak memory 199996 kb
Host smart-eaebc2bf-295c-4c41-b3ba-da0962afc417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158128381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.2158128381
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2241646955
Short name T384
Test name
Test status
Simulation time 38660678 ps
CPU time 0.58 seconds
Started May 30 02:52:06 PM PDT 24
Finished May 30 02:52:09 PM PDT 24
Peak memory 194784 kb
Host smart-b9bfef0a-3225-4322-a234-75a308b929ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241646955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2241646955
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.2822023525
Short name T423
Test name
Test status
Simulation time 630392562 ps
CPU time 34.55 seconds
Started May 30 02:52:07 PM PDT 24
Finished May 30 02:52:45 PM PDT 24
Peak memory 225836 kb
Host smart-7d79a292-2033-44b0-a5df-32948d935f54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2822023525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2822023525
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.2771099430
Short name T525
Test name
Test status
Simulation time 999343985 ps
CPU time 20.46 seconds
Started May 30 02:52:07 PM PDT 24
Finished May 30 02:52:31 PM PDT 24
Peak memory 200016 kb
Host smart-03c54bce-cc7d-4594-a8a8-905bdeb606f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771099430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2771099430
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.970938060
Short name T357
Test name
Test status
Simulation time 3327564448 ps
CPU time 848.57 seconds
Started May 30 02:52:07 PM PDT 24
Finished May 30 03:06:19 PM PDT 24
Peak memory 712112 kb
Host smart-79f79c25-dbb1-4cb6-957b-b9e559ab5af4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=970938060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.970938060
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1398662289
Short name T577
Test name
Test status
Simulation time 4279715460 ps
CPU time 75.74 seconds
Started May 30 02:52:07 PM PDT 24
Finished May 30 02:53:26 PM PDT 24
Peak memory 200092 kb
Host smart-4d163b94-1ed4-469d-abf2-235760a277df
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398662289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1398662289
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.1895137221
Short name T170
Test name
Test status
Simulation time 18309198453 ps
CPU time 88.2 seconds
Started May 30 02:52:08 PM PDT 24
Finished May 30 02:53:39 PM PDT 24
Peak memory 200072 kb
Host smart-310c3229-38ce-4b58-a559-c2aee5b5b1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895137221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1895137221
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.696295092
Short name T72
Test name
Test status
Simulation time 259363578 ps
CPU time 5.3 seconds
Started May 30 02:52:07 PM PDT 24
Finished May 30 02:52:15 PM PDT 24
Peak memory 199960 kb
Host smart-17790037-520c-4dda-9522-b5143669d95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696295092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.696295092
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.916254273
Short name T125
Test name
Test status
Simulation time 17050687297 ps
CPU time 2777.43 seconds
Started May 30 02:52:08 PM PDT 24
Finished May 30 03:38:29 PM PDT 24
Peak memory 804568 kb
Host smart-959fa4d2-d282-4193-bbbf-c42c84c82990
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916254273 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.916254273
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.3019532592
Short name T388
Test name
Test status
Simulation time 133283192 ps
CPU time 1.14 seconds
Started May 30 02:52:07 PM PDT 24
Finished May 30 02:52:11 PM PDT 24
Peak memory 200104 kb
Host smart-12d49042-28b5-4c4b-a2b1-8f40b0aa5882
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019532592 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.3019532592
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.1712520607
Short name T348
Test name
Test status
Simulation time 21342613823 ps
CPU time 403.51 seconds
Started May 30 02:52:08 PM PDT 24
Finished May 30 02:58:54 PM PDT 24
Peak memory 199956 kb
Host smart-8cd4f006-a3c4-40bf-9fd1-d5daecc49a29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712520607 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.1712520607
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.988220415
Short name T545
Test name
Test status
Simulation time 3633593807 ps
CPU time 38.09 seconds
Started May 30 02:52:08 PM PDT 24
Finished May 30 02:52:49 PM PDT 24
Peak memory 200128 kb
Host smart-a816a379-8fb5-4232-85f5-762e80948c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988220415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.988220415
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.528731470
Short name T434
Test name
Test status
Simulation time 13705956 ps
CPU time 0.59 seconds
Started May 30 02:52:07 PM PDT 24
Finished May 30 02:52:11 PM PDT 24
Peak memory 195992 kb
Host smart-3fea15b0-ddd0-4219-a9c5-ebcc824c9e2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528731470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.528731470
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3910344637
Short name T325
Test name
Test status
Simulation time 7143374830 ps
CPU time 55.02 seconds
Started May 30 02:52:08 PM PDT 24
Finished May 30 02:53:06 PM PDT 24
Peak memory 232836 kb
Host smart-8477d5c3-de15-4b35-b967-8f570ce93e03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3910344637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3910344637
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2001363520
Short name T553
Test name
Test status
Simulation time 404061482 ps
CPU time 5.89 seconds
Started May 30 02:52:09 PM PDT 24
Finished May 30 02:52:17 PM PDT 24
Peak memory 199972 kb
Host smart-49f503f4-f31e-46c5-b906-1cfd8eb28296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001363520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2001363520
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.1195407448
Short name T543
Test name
Test status
Simulation time 531518599 ps
CPU time 81.29 seconds
Started May 30 02:52:08 PM PDT 24
Finished May 30 02:53:33 PM PDT 24
Peak memory 338448 kb
Host smart-abcf4bea-78e6-47b6-bf80-248e1c98b15f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1195407448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1195407448
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1817183081
Short name T225
Test name
Test status
Simulation time 8421783499 ps
CPU time 159.92 seconds
Started May 30 02:52:06 PM PDT 24
Finished May 30 02:54:48 PM PDT 24
Peak memory 200032 kb
Host smart-51774989-458f-4a85-a57e-bcd7d0bc968f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817183081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1817183081
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1340231345
Short name T256
Test name
Test status
Simulation time 2051522686 ps
CPU time 22.79 seconds
Started May 30 02:52:09 PM PDT 24
Finished May 30 02:52:35 PM PDT 24
Peak memory 200012 kb
Host smart-0172ebbf-9a87-4f9e-97e3-c0f60fa28af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340231345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1340231345
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.908703497
Short name T442
Test name
Test status
Simulation time 316956192 ps
CPU time 3.44 seconds
Started May 30 02:52:09 PM PDT 24
Finished May 30 02:52:15 PM PDT 24
Peak memory 200060 kb
Host smart-1df85d57-b0ec-4a6b-8a3d-01709f988cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908703497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.908703497
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.3079231135
Short name T70
Test name
Test status
Simulation time 16837027297 ps
CPU time 1093.67 seconds
Started May 30 02:52:08 PM PDT 24
Finished May 30 03:10:25 PM PDT 24
Peak memory 758976 kb
Host smart-5ccecdd4-4834-43ab-a621-6bc9ff454786
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079231135 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.3079231135
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.1446134346
Short name T501
Test name
Test status
Simulation time 82093847 ps
CPU time 1.52 seconds
Started May 30 02:52:07 PM PDT 24
Finished May 30 02:52:11 PM PDT 24
Peak memory 200060 kb
Host smart-50c8fb22-6540-4e7f-9a9c-0eb2c0fe926b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446134346 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.1446134346
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.248629042
Short name T292
Test name
Test status
Simulation time 125604891243 ps
CPU time 478.05 seconds
Started May 30 02:52:09 PM PDT 24
Finished May 30 03:00:10 PM PDT 24
Peak memory 200044 kb
Host smart-74443799-805e-4a86-a50b-989912a083c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248629042 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.248629042
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1302022044
Short name T218
Test name
Test status
Simulation time 2683597461 ps
CPU time 36.89 seconds
Started May 30 02:52:07 PM PDT 24
Finished May 30 02:52:47 PM PDT 24
Peak memory 200028 kb
Host smart-b6e2dbfa-1ca8-4bd6-8762-e94162f4bf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302022044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1302022044
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.332655271
Short name T540
Test name
Test status
Simulation time 13284282 ps
CPU time 0.59 seconds
Started May 30 02:52:20 PM PDT 24
Finished May 30 02:52:24 PM PDT 24
Peak memory 194956 kb
Host smart-e44ad667-256c-46d2-b7e4-6e4eb77ea7d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332655271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.332655271
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.2389841470
Short name T581
Test name
Test status
Simulation time 1850620480 ps
CPU time 24.08 seconds
Started May 30 02:52:22 PM PDT 24
Finished May 30 02:52:49 PM PDT 24
Peak memory 224616 kb
Host smart-eb80982d-0377-4b6a-9b8f-43776ac70348
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2389841470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2389841470
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.807748145
Short name T592
Test name
Test status
Simulation time 1935533850 ps
CPU time 14.73 seconds
Started May 30 02:52:23 PM PDT 24
Finished May 30 02:52:40 PM PDT 24
Peak memory 199996 kb
Host smart-fcb4286c-95b1-4fc7-a273-b0d05cf7ac3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807748145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.807748145
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3577029321
Short name T9
Test name
Test status
Simulation time 5221537784 ps
CPU time 360.89 seconds
Started May 30 02:52:19 PM PDT 24
Finished May 30 02:58:22 PM PDT 24
Peak memory 668832 kb
Host smart-40727278-804f-477b-bee7-f30a61f116e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3577029321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3577029321
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.1367344021
Short name T509
Test name
Test status
Simulation time 12264733930 ps
CPU time 161.91 seconds
Started May 30 02:52:23 PM PDT 24
Finished May 30 02:55:07 PM PDT 24
Peak memory 200016 kb
Host smart-7290082e-386e-447e-9d10-e11ba3c574a9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367344021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1367344021
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1078063469
Short name T202
Test name
Test status
Simulation time 99295084 ps
CPU time 3.01 seconds
Started May 30 02:52:15 PM PDT 24
Finished May 30 02:52:19 PM PDT 24
Peak memory 199996 kb
Host smart-308ae57a-e1bb-466c-8730-0e48b1d206cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078063469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1078063469
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.4209990170
Short name T455
Test name
Test status
Simulation time 288320052 ps
CPU time 4.37 seconds
Started May 30 02:52:09 PM PDT 24
Finished May 30 02:52:16 PM PDT 24
Peak memory 200016 kb
Host smart-087209b6-8324-4441-b0b1-88e3d1a5ac70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209990170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.4209990170
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.2867325539
Short name T79
Test name
Test status
Simulation time 2292284753 ps
CPU time 33.84 seconds
Started May 30 02:52:19 PM PDT 24
Finished May 30 02:52:55 PM PDT 24
Peak memory 200104 kb
Host smart-fe9ddf3a-b977-4ce5-ac02-66fdbae99c1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867325539 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2867325539
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.312596105
Short name T561
Test name
Test status
Simulation time 176372859 ps
CPU time 1.15 seconds
Started May 30 02:52:19 PM PDT 24
Finished May 30 02:52:23 PM PDT 24
Peak memory 200024 kb
Host smart-b50bb5bb-d74a-4e9e-ae6c-180359f57fd8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312596105 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_hmac_vectors.312596105
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.1128881384
Short name T518
Test name
Test status
Simulation time 8788552672 ps
CPU time 518.74 seconds
Started May 30 02:52:20 PM PDT 24
Finished May 30 03:01:01 PM PDT 24
Peak memory 199984 kb
Host smart-aba6fcb1-ccc0-41ac-882b-bebfc31c1da1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128881384 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.1128881384
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.3740678902
Short name T88
Test name
Test status
Simulation time 4957501873 ps
CPU time 93.99 seconds
Started May 30 02:52:20 PM PDT 24
Finished May 30 02:53:57 PM PDT 24
Peak memory 200084 kb
Host smart-1ddbd4b5-ba07-4c13-bbb9-0c1c446d63ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740678902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3740678902
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1598660046
Short name T42
Test name
Test status
Simulation time 36251701 ps
CPU time 0.56 seconds
Started May 30 02:52:19 PM PDT 24
Finished May 30 02:52:21 PM PDT 24
Peak memory 195708 kb
Host smart-c6f9e478-ffcf-4cb0-be50-8a4f9cc96810
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598660046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1598660046
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3906314207
Short name T20
Test name
Test status
Simulation time 622095857 ps
CPU time 31.92 seconds
Started May 30 02:52:21 PM PDT 24
Finished May 30 02:52:55 PM PDT 24
Peak memory 219492 kb
Host smart-08a8a540-6267-4e96-b6a6-fac1bff92a9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3906314207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3906314207
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2641897538
Short name T238
Test name
Test status
Simulation time 1869733825 ps
CPU time 7.76 seconds
Started May 30 02:52:20 PM PDT 24
Finished May 30 02:52:30 PM PDT 24
Peak memory 199956 kb
Host smart-d982b2b6-dce1-472a-a48e-279501d50307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641897538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2641897538
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3442611269
Short name T593
Test name
Test status
Simulation time 11850704510 ps
CPU time 230.02 seconds
Started May 30 02:52:19 PM PDT 24
Finished May 30 02:56:12 PM PDT 24
Peak memory 485316 kb
Host smart-b8b04800-9caa-47aa-8a4a-2d6de9ed1995
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3442611269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3442611269
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2837763299
Short name T391
Test name
Test status
Simulation time 721099094 ps
CPU time 36.1 seconds
Started May 30 02:52:21 PM PDT 24
Finished May 30 02:52:59 PM PDT 24
Peak memory 200032 kb
Host smart-3f502f43-37a5-4618-a17f-180fc5d57ff4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837763299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2837763299
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2707728819
Short name T571
Test name
Test status
Simulation time 4738167072 ps
CPU time 18.7 seconds
Started May 30 02:52:20 PM PDT 24
Finished May 30 02:52:41 PM PDT 24
Peak memory 200148 kb
Host smart-bee5e1ba-1492-48c8-b30a-b2467daaa0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707728819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2707728819
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.4258701178
Short name T146
Test name
Test status
Simulation time 2808033770 ps
CPU time 12.15 seconds
Started May 30 02:52:19 PM PDT 24
Finished May 30 02:52:33 PM PDT 24
Peak memory 200060 kb
Host smart-66ea4fb1-b050-4403-b654-6375c6e2d12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258701178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.4258701178
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.4007320814
Short name T265
Test name
Test status
Simulation time 69142671693 ps
CPU time 893.62 seconds
Started May 30 02:52:18 PM PDT 24
Finished May 30 03:07:13 PM PDT 24
Peak memory 236000 kb
Host smart-c5f14bb7-30db-415e-989a-ee419e04ce79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007320814 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.4007320814
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.2531175870
Short name T573
Test name
Test status
Simulation time 78713603 ps
CPU time 1.11 seconds
Started May 30 02:52:22 PM PDT 24
Finished May 30 02:52:26 PM PDT 24
Peak memory 200000 kb
Host smart-cd59c34a-8ed3-4977-9a94-0037bff6de26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531175870 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.2531175870
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.2218862823
Short name T288
Test name
Test status
Simulation time 73963263888 ps
CPU time 635.48 seconds
Started May 30 02:52:19 PM PDT 24
Finished May 30 03:02:57 PM PDT 24
Peak memory 200052 kb
Host smart-2f152006-2f72-4d52-8af2-5b7b20c0b1e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218862823 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.2218862823
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.4231121824
Short name T456
Test name
Test status
Simulation time 1777160331 ps
CPU time 86.18 seconds
Started May 30 02:52:19 PM PDT 24
Finished May 30 02:53:48 PM PDT 24
Peak memory 199980 kb
Host smart-a22d1b5e-ef0e-499c-b078-fac712c3ec4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231121824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.4231121824
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.30584838
Short name T336
Test name
Test status
Simulation time 12483694 ps
CPU time 0.63 seconds
Started May 30 02:52:32 PM PDT 24
Finished May 30 02:52:34 PM PDT 24
Peak memory 196016 kb
Host smart-3f8a6f53-63d9-4aaa-898e-fb8435061270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30584838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.30584838
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1089366748
Short name T532
Test name
Test status
Simulation time 493307835 ps
CPU time 6.99 seconds
Started May 30 02:52:23 PM PDT 24
Finished May 30 02:52:32 PM PDT 24
Peak memory 199552 kb
Host smart-a290f5bc-d60c-4021-a722-961f87ae9c52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1089366748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1089366748
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.2892730197
Short name T397
Test name
Test status
Simulation time 30507380678 ps
CPU time 52.37 seconds
Started May 30 02:52:21 PM PDT 24
Finished May 30 02:53:16 PM PDT 24
Peak memory 200144 kb
Host smart-865d406e-a6b2-4543-977f-ff8c3eb7eb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892730197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2892730197
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1531666300
Short name T474
Test name
Test status
Simulation time 1477238696 ps
CPU time 118.04 seconds
Started May 30 02:52:20 PM PDT 24
Finished May 30 02:54:20 PM PDT 24
Peak memory 371020 kb
Host smart-dee1ee66-1d94-48c6-9b44-4bc31eb54a4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1531666300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1531666300
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.4046008824
Short name T324
Test name
Test status
Simulation time 3733285678 ps
CPU time 64.47 seconds
Started May 30 02:52:19 PM PDT 24
Finished May 30 02:53:26 PM PDT 24
Peak memory 200116 kb
Host smart-c6729ced-57ef-47da-9d36-d088438a2b18
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046008824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.4046008824
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.844549861
Short name T244
Test name
Test status
Simulation time 1125868163 ps
CPU time 36.62 seconds
Started May 30 02:52:22 PM PDT 24
Finished May 30 02:53:01 PM PDT 24
Peak memory 200076 kb
Host smart-a4524d26-ce9b-4019-9921-67fa31cbcc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844549861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.844549861
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.72115957
Short name T330
Test name
Test status
Simulation time 88827631 ps
CPU time 0.82 seconds
Started May 30 02:52:22 PM PDT 24
Finished May 30 02:52:26 PM PDT 24
Peak memory 197852 kb
Host smart-9f56731f-f332-4729-b7f3-8b288beeecb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72115957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.72115957
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2941251710
Short name T443
Test name
Test status
Simulation time 50649702627 ps
CPU time 2148.06 seconds
Started May 30 02:52:22 PM PDT 24
Finished May 30 03:28:13 PM PDT 24
Peak memory 819632 kb
Host smart-c105291b-f508-4edd-afcf-db6f071d65e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941251710 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2941251710
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.4017635702
Short name T557
Test name
Test status
Simulation time 44540361 ps
CPU time 1.26 seconds
Started May 30 02:52:21 PM PDT 24
Finished May 30 02:52:25 PM PDT 24
Peak memory 199976 kb
Host smart-32644d44-b1fb-4253-a553-dd51e20121db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017635702 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.4017635702
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.1844484392
Short name T510
Test name
Test status
Simulation time 35540581342 ps
CPU time 553.83 seconds
Started May 30 02:52:22 PM PDT 24
Finished May 30 03:01:39 PM PDT 24
Peak memory 200060 kb
Host smart-e6f7d2fb-325f-4850-9b6b-6a6922da3b6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844484392 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.1844484392
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1043244264
Short name T187
Test name
Test status
Simulation time 2063263071 ps
CPU time 38.04 seconds
Started May 30 02:52:23 PM PDT 24
Finished May 30 02:53:04 PM PDT 24
Peak memory 200056 kb
Host smart-5db82e07-57b9-420c-a2f7-9ed07fc32967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043244264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1043244264
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.4076256451
Short name T517
Test name
Test status
Simulation time 80034982 ps
CPU time 0.61 seconds
Started May 30 02:52:32 PM PDT 24
Finished May 30 02:52:34 PM PDT 24
Peak memory 195948 kb
Host smart-4d3b2ea7-1f0d-4e45-81c7-620cbe58507c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076256451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.4076256451
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1917904874
Short name T178
Test name
Test status
Simulation time 4146534465 ps
CPU time 26.06 seconds
Started May 30 02:52:32 PM PDT 24
Finished May 30 02:53:00 PM PDT 24
Peak memory 200144 kb
Host smart-d05cb6a2-98d1-40af-ba54-1b8ef8be6446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917904874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1917904874
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.446351497
Short name T294
Test name
Test status
Simulation time 7357952575 ps
CPU time 995.01 seconds
Started May 30 02:52:31 PM PDT 24
Finished May 30 03:09:08 PM PDT 24
Peak memory 755364 kb
Host smart-57336297-b568-4c7d-81d6-509249c82baf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=446351497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.446351497
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3193933265
Short name T231
Test name
Test status
Simulation time 7470587591 ps
CPU time 27.2 seconds
Started May 30 02:52:31 PM PDT 24
Finished May 30 02:53:00 PM PDT 24
Peak memory 200088 kb
Host smart-254b3c52-9bb4-41e6-9f33-9c532b96b969
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193933265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3193933265
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1032148328
Short name T446
Test name
Test status
Simulation time 19734462924 ps
CPU time 104.48 seconds
Started May 30 02:52:33 PM PDT 24
Finished May 30 02:54:20 PM PDT 24
Peak memory 200136 kb
Host smart-41b96f40-f0e3-43a5-900f-b99d789d1211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032148328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1032148328
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1963736675
Short name T122
Test name
Test status
Simulation time 218520161 ps
CPU time 3.64 seconds
Started May 30 02:52:32 PM PDT 24
Finished May 30 02:52:37 PM PDT 24
Peak memory 199988 kb
Host smart-cc4b26e0-6244-4966-b6f3-b15744bf0378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963736675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1963736675
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3863868383
Short name T290
Test name
Test status
Simulation time 76613889971 ps
CPU time 931.18 seconds
Started May 30 02:52:33 PM PDT 24
Finished May 30 03:08:06 PM PDT 24
Peak memory 643248 kb
Host smart-3fc35204-a8af-424b-a48c-305fc4f2651e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863868383 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3863868383
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.3788847050
Short name T377
Test name
Test status
Simulation time 65054555 ps
CPU time 1.34 seconds
Started May 30 02:52:32 PM PDT 24
Finished May 30 02:52:35 PM PDT 24
Peak memory 199988 kb
Host smart-8435ff9d-f39a-4074-ab22-c70426501f63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788847050 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.3788847050
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.3995539702
Short name T463
Test name
Test status
Simulation time 33571843251 ps
CPU time 514.57 seconds
Started May 30 02:52:33 PM PDT 24
Finished May 30 03:01:10 PM PDT 24
Peak memory 200064 kb
Host smart-d17ebd7b-6897-4e2c-8a92-2ffe35aaa688
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995539702 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.3995539702
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.3685784518
Short name T404
Test name
Test status
Simulation time 241317012 ps
CPU time 4.02 seconds
Started May 30 02:52:32 PM PDT 24
Finished May 30 02:52:38 PM PDT 24
Peak memory 199888 kb
Host smart-fce341be-24a8-4153-9a3e-a4a30ec560b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685784518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.3685784518
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.3969400153
Short name T500
Test name
Test status
Simulation time 40850194 ps
CPU time 0.59 seconds
Started May 30 02:52:45 PM PDT 24
Finished May 30 02:52:47 PM PDT 24
Peak memory 194984 kb
Host smart-c42501b6-e881-44c9-b620-8098182ce7b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969400153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3969400153
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3651977156
Short name T246
Test name
Test status
Simulation time 4637487752 ps
CPU time 71.05 seconds
Started May 30 02:52:31 PM PDT 24
Finished May 30 02:53:44 PM PDT 24
Peak memory 232780 kb
Host smart-67e590ee-4688-4da9-a73f-417893ca4fc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3651977156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3651977156
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.820997203
Short name T359
Test name
Test status
Simulation time 449602783 ps
CPU time 12.69 seconds
Started May 30 02:52:32 PM PDT 24
Finished May 30 02:52:46 PM PDT 24
Peak memory 200044 kb
Host smart-76c64474-5514-48f1-a4d7-e91d0c630a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820997203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.820997203
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.872113721
Short name T239
Test name
Test status
Simulation time 5618696010 ps
CPU time 348.98 seconds
Started May 30 02:52:31 PM PDT 24
Finished May 30 02:58:22 PM PDT 24
Peak memory 611192 kb
Host smart-562d8f46-c4a3-41dc-ad06-7009cba7b8ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=872113721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.872113721
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.863540124
Short name T419
Test name
Test status
Simulation time 7826143037 ps
CPU time 113.6 seconds
Started May 30 02:52:31 PM PDT 24
Finished May 30 02:54:26 PM PDT 24
Peak memory 200080 kb
Host smart-d383cb28-229b-4a15-9a5a-cf6e12a4d9b1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863540124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.863540124
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3186027355
Short name T180
Test name
Test status
Simulation time 1233478680 ps
CPU time 19.66 seconds
Started May 30 02:52:32 PM PDT 24
Finished May 30 02:52:53 PM PDT 24
Peak memory 200020 kb
Host smart-69d82d30-d5d3-485a-bbcc-9daf313e0137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186027355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3186027355
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2481046534
Short name T266
Test name
Test status
Simulation time 409753345 ps
CPU time 4.5 seconds
Started May 30 02:52:32 PM PDT 24
Finished May 30 02:52:39 PM PDT 24
Peak memory 200036 kb
Host smart-460d1d4a-4171-43c3-ae0c-eeeede45be25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481046534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2481046534
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3491990481
Short name T300
Test name
Test status
Simulation time 32638748375 ps
CPU time 4373.21 seconds
Started May 30 02:52:47 PM PDT 24
Finished May 30 04:05:42 PM PDT 24
Peak memory 803992 kb
Host smart-91997b80-10b3-414c-b028-8dd975a2d9de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491990481 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3491990481
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.2682261215
Short name T591
Test name
Test status
Simulation time 109165387 ps
CPU time 1.11 seconds
Started May 30 02:52:47 PM PDT 24
Finished May 30 02:52:49 PM PDT 24
Peak memory 200004 kb
Host smart-22f5a53b-130e-49e1-82a8-f59b6e364a68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682261215 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.2682261215
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.3547679708
Short name T254
Test name
Test status
Simulation time 16980148474 ps
CPU time 418.43 seconds
Started May 30 02:52:46 PM PDT 24
Finished May 30 02:59:45 PM PDT 24
Peak memory 200108 kb
Host smart-db18a5e5-f625-48f2-af8f-f88939176a1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547679708 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.3547679708
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.1792174625
Short name T29
Test name
Test status
Simulation time 1014349866 ps
CPU time 45.23 seconds
Started May 30 02:52:34 PM PDT 24
Finished May 30 02:53:21 PM PDT 24
Peak memory 199992 kb
Host smart-138ef4be-0f8c-476c-848a-83547955ade6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792174625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.1792174625
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2401235364
Short name T375
Test name
Test status
Simulation time 40456809 ps
CPU time 0.6 seconds
Started May 30 02:49:56 PM PDT 24
Finished May 30 02:49:59 PM PDT 24
Peak memory 195648 kb
Host smart-5085d713-9b18-4125-9aa1-e2cdeb6f9531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401235364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2401235364
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.2103182384
Short name T562
Test name
Test status
Simulation time 556303473 ps
CPU time 32.35 seconds
Started May 30 02:49:55 PM PDT 24
Finished May 30 02:50:29 PM PDT 24
Peak memory 231900 kb
Host smart-d497b331-94da-4628-b40e-24d38df79897
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2103182384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2103182384
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2068057825
Short name T204
Test name
Test status
Simulation time 2631677231 ps
CPU time 37.7 seconds
Started May 30 02:49:55 PM PDT 24
Finished May 30 02:50:35 PM PDT 24
Peak memory 200148 kb
Host smart-c94407d7-999b-40c1-b26b-abc0b3915111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068057825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2068057825
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2423661178
Short name T73
Test name
Test status
Simulation time 2225280087 ps
CPU time 203.23 seconds
Started May 30 02:49:54 PM PDT 24
Finished May 30 02:53:19 PM PDT 24
Peak memory 591004 kb
Host smart-cdaeb1a5-5005-4fee-b142-14253b98185d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2423661178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2423661178
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.939540724
Short name T16
Test name
Test status
Simulation time 3538351040 ps
CPU time 48.29 seconds
Started May 30 02:49:57 PM PDT 24
Finished May 30 02:50:47 PM PDT 24
Peak memory 200116 kb
Host smart-6b561b9b-109f-41da-a72b-da84a49c1770
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939540724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.939540724
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1953250003
Short name T559
Test name
Test status
Simulation time 899296522 ps
CPU time 52.11 seconds
Started May 30 02:49:58 PM PDT 24
Finished May 30 02:50:52 PM PDT 24
Peak memory 200124 kb
Host smart-a0dbf2db-c1f0-4787-b415-948d141c415f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953250003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1953250003
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1428194530
Short name T33
Test name
Test status
Simulation time 230216774 ps
CPU time 0.91 seconds
Started May 30 02:49:55 PM PDT 24
Finished May 30 02:49:58 PM PDT 24
Peak memory 218268 kb
Host smart-1e4016a2-c543-4230-b8d3-3f4d25d6793a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428194530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1428194530
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.4142235967
Short name T360
Test name
Test status
Simulation time 143032562 ps
CPU time 4.74 seconds
Started May 30 02:49:53 PM PDT 24
Finished May 30 02:49:59 PM PDT 24
Peak memory 200044 kb
Host smart-c2a54d88-0ef3-4324-8809-bd9a8efcbb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142235967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.4142235967
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.4254623679
Short name T124
Test name
Test status
Simulation time 55055104846 ps
CPU time 692.41 seconds
Started May 30 02:49:57 PM PDT 24
Finished May 30 03:01:31 PM PDT 24
Peak memory 233380 kb
Host smart-6f110218-5385-49c6-acd8-38055fb8bf2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254623679 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.4254623679
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.3848604374
Short name T26
Test name
Test status
Simulation time 127167794 ps
CPU time 1.33 seconds
Started May 30 02:49:57 PM PDT 24
Finished May 30 02:50:00 PM PDT 24
Peak memory 199960 kb
Host smart-f4bd771e-b654-4272-87c1-072ab3cd9274
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848604374 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.3848604374
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.582693811
Short name T221
Test name
Test status
Simulation time 131063303295 ps
CPU time 512.67 seconds
Started May 30 02:49:57 PM PDT 24
Finished May 30 02:58:31 PM PDT 24
Peak memory 200060 kb
Host smart-4df68774-6c82-4bb8-978b-4ea652c1591b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582693811 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.582693811
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2076160101
Short name T574
Test name
Test status
Simulation time 216295779 ps
CPU time 12.25 seconds
Started May 30 02:49:54 PM PDT 24
Finished May 30 02:50:07 PM PDT 24
Peak memory 200048 kb
Host smart-18c5bd70-1c83-4bd1-a19b-73b5e8fc5f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076160101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2076160101
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3871874679
Short name T86
Test name
Test status
Simulation time 13326256 ps
CPU time 0.57 seconds
Started May 30 02:52:48 PM PDT 24
Finished May 30 02:52:50 PM PDT 24
Peak memory 194964 kb
Host smart-7eaa8384-fad6-4794-ab06-61bfeff3b9f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871874679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3871874679
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.4294186439
Short name T544
Test name
Test status
Simulation time 536487923 ps
CPU time 2.79 seconds
Started May 30 02:52:45 PM PDT 24
Finished May 30 02:52:49 PM PDT 24
Peak memory 199912 kb
Host smart-b9468718-7cfa-4c57-a75d-685e0ffc94f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4294186439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.4294186439
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.176068826
Short name T188
Test name
Test status
Simulation time 1409662451 ps
CPU time 28.39 seconds
Started May 30 02:52:45 PM PDT 24
Finished May 30 02:53:14 PM PDT 24
Peak memory 200008 kb
Host smart-e7745984-b76e-4517-b1a8-a96d11b7932b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176068826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.176068826
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3016919687
Short name T233
Test name
Test status
Simulation time 4737528309 ps
CPU time 221.27 seconds
Started May 30 02:52:51 PM PDT 24
Finished May 30 02:56:33 PM PDT 24
Peak memory 646748 kb
Host smart-f4d0e1dc-1c4d-4580-9036-550e707db4b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3016919687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3016919687
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.4193449576
Short name T308
Test name
Test status
Simulation time 692280145 ps
CPU time 36.73 seconds
Started May 30 02:52:51 PM PDT 24
Finished May 30 02:53:28 PM PDT 24
Peak memory 199928 kb
Host smart-01491870-ac4d-4986-83c2-f0f96cba3ecd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193449576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.4193449576
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.1174553515
Short name T206
Test name
Test status
Simulation time 503028363 ps
CPU time 15.6 seconds
Started May 30 02:52:46 PM PDT 24
Finished May 30 02:53:03 PM PDT 24
Peak memory 200048 kb
Host smart-59f496dd-6091-423a-8a97-bfec4a2eb332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174553515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1174553515
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2645837469
Short name T393
Test name
Test status
Simulation time 130470229 ps
CPU time 1.47 seconds
Started May 30 02:52:47 PM PDT 24
Finished May 30 02:52:50 PM PDT 24
Peak memory 200036 kb
Host smart-425d8f99-e3c3-46cd-b348-56392be719a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645837469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2645837469
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2365245880
Short name T38
Test name
Test status
Simulation time 1505798975 ps
CPU time 77.48 seconds
Started May 30 02:52:47 PM PDT 24
Finished May 30 02:54:06 PM PDT 24
Peak memory 241084 kb
Host smart-4400aed4-df01-48ae-a66c-63a0a992acbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365245880 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2365245880
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.118484135
Short name T297
Test name
Test status
Simulation time 59771426 ps
CPU time 1.3 seconds
Started May 30 02:52:51 PM PDT 24
Finished May 30 02:52:53 PM PDT 24
Peak memory 200020 kb
Host smart-fdb46e49-0382-4d4c-9c4e-768b3299c6b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118484135 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_hmac_vectors.118484135
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.584894607
Short name T457
Test name
Test status
Simulation time 7280698013 ps
CPU time 414.22 seconds
Started May 30 02:52:46 PM PDT 24
Finished May 30 02:59:41 PM PDT 24
Peak memory 200044 kb
Host smart-8f52beec-2013-47c0-bd22-b9c5dd5b0276
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584894607 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.584894607
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.3475580925
Short name T507
Test name
Test status
Simulation time 3764667172 ps
CPU time 71.05 seconds
Started May 30 02:52:48 PM PDT 24
Finished May 30 02:54:00 PM PDT 24
Peak memory 200108 kb
Host smart-e5c77d3c-4ac2-4ac0-afb1-a3da7ae70f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475580925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.3475580925
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1226660663
Short name T44
Test name
Test status
Simulation time 12920870 ps
CPU time 0.62 seconds
Started May 30 02:52:47 PM PDT 24
Finished May 30 02:52:49 PM PDT 24
Peak memory 196720 kb
Host smart-e3c51987-8b37-4d30-bb06-cad46430a258
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226660663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1226660663
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2533369834
Short name T488
Test name
Test status
Simulation time 848213220 ps
CPU time 18.98 seconds
Started May 30 02:52:45 PM PDT 24
Finished May 30 02:53:05 PM PDT 24
Peak memory 216412 kb
Host smart-7abe5d4e-e2c2-464d-b306-4a806fec45fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2533369834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2533369834
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.4255382192
Short name T184
Test name
Test status
Simulation time 1495375819 ps
CPU time 43.71 seconds
Started May 30 02:52:46 PM PDT 24
Finished May 30 02:53:31 PM PDT 24
Peak memory 200100 kb
Host smart-4ae89963-387c-425f-a03e-236ea3789c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255382192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.4255382192
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2431957408
Short name T193
Test name
Test status
Simulation time 3020214190 ps
CPU time 743.06 seconds
Started May 30 02:52:49 PM PDT 24
Finished May 30 03:05:13 PM PDT 24
Peak memory 710668 kb
Host smart-b2d24860-f4ab-4f6e-8d6f-1a095fa58ebe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2431957408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2431957408
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1804639920
Short name T451
Test name
Test status
Simulation time 2736834098 ps
CPU time 24.72 seconds
Started May 30 02:52:45 PM PDT 24
Finished May 30 02:53:11 PM PDT 24
Peak memory 200044 kb
Host smart-b89403bc-9c52-4026-856b-214a99184e11
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804639920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1804639920
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.1654827489
Short name T270
Test name
Test status
Simulation time 13820628636 ps
CPU time 67.39 seconds
Started May 30 02:52:50 PM PDT 24
Finished May 30 02:53:58 PM PDT 24
Peak memory 200108 kb
Host smart-f855d85d-3b56-4eb9-9b67-ca4551a79bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654827489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.1654827489
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.127339332
Short name T529
Test name
Test status
Simulation time 240960639 ps
CPU time 2.54 seconds
Started May 30 02:52:46 PM PDT 24
Finished May 30 02:52:50 PM PDT 24
Peak memory 200084 kb
Host smart-3df3978c-f78c-4259-8e49-eba9a18716c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127339332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.127339332
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.3689864177
Short name T27
Test name
Test status
Simulation time 36425587330 ps
CPU time 696.73 seconds
Started May 30 02:52:49 PM PDT 24
Finished May 30 03:04:27 PM PDT 24
Peak memory 232104 kb
Host smart-49c3971c-def5-4786-93dc-6e663a2902b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689864177 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3689864177
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.3039061197
Short name T280
Test name
Test status
Simulation time 62303913 ps
CPU time 1.12 seconds
Started May 30 02:52:47 PM PDT 24
Finished May 30 02:52:49 PM PDT 24
Peak memory 199916 kb
Host smart-55ade9ae-8542-4b8b-9b8a-a5c62fb7927d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039061197 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.3039061197
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.2693884619
Short name T444
Test name
Test status
Simulation time 28015935290 ps
CPU time 466.53 seconds
Started May 30 02:52:46 PM PDT 24
Finished May 30 03:00:34 PM PDT 24
Peak memory 200064 kb
Host smart-73498941-8051-4ae9-a0e1-064edab19c27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693884619 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.2693884619
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.819611426
Short name T214
Test name
Test status
Simulation time 409501495 ps
CPU time 2.15 seconds
Started May 30 02:52:49 PM PDT 24
Finished May 30 02:52:53 PM PDT 24
Peak memory 199864 kb
Host smart-ceaa50e6-97d3-4979-9e98-283ad1c2ec9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819611426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.819611426
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3829764249
Short name T512
Test name
Test status
Simulation time 38450819 ps
CPU time 0.6 seconds
Started May 30 02:52:59 PM PDT 24
Finished May 30 02:53:02 PM PDT 24
Peak memory 195684 kb
Host smart-13cfa7d6-89df-466e-b2b1-2d2660c35f5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829764249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3829764249
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1313969292
Short name T189
Test name
Test status
Simulation time 934326431 ps
CPU time 53.79 seconds
Started May 30 02:53:05 PM PDT 24
Finished May 30 02:54:00 PM PDT 24
Peak memory 225040 kb
Host smart-f832146d-18d3-47c4-9402-44899ad8eb08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1313969292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1313969292
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.577447138
Short name T363
Test name
Test status
Simulation time 1976616853 ps
CPU time 30.22 seconds
Started May 30 02:53:00 PM PDT 24
Finished May 30 02:53:32 PM PDT 24
Peak memory 200148 kb
Host smart-7a01874e-6665-4dbf-9c78-e84f507f240e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577447138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.577447138
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1373169030
Short name T530
Test name
Test status
Simulation time 9094317051 ps
CPU time 586.7 seconds
Started May 30 02:52:59 PM PDT 24
Finished May 30 03:02:47 PM PDT 24
Peak memory 492104 kb
Host smart-4a87ca77-71cd-446b-86c2-b18312f71a21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1373169030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1373169030
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2114990959
Short name T564
Test name
Test status
Simulation time 3214112317 ps
CPU time 179.85 seconds
Started May 30 02:52:59 PM PDT 24
Finished May 30 02:56:01 PM PDT 24
Peak memory 200080 kb
Host smart-4ca61ae9-9788-4b91-ba9f-9366d11b1da6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114990959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2114990959
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1028738742
Short name T319
Test name
Test status
Simulation time 3070625181 ps
CPU time 98.56 seconds
Started May 30 02:52:48 PM PDT 24
Finished May 30 02:54:28 PM PDT 24
Peak memory 200128 kb
Host smart-a29fa0f3-f932-429f-b4a6-ae8a37f0a79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028738742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1028738742
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.4126613421
Short name T315
Test name
Test status
Simulation time 1133267934 ps
CPU time 8.15 seconds
Started May 30 02:52:46 PM PDT 24
Finished May 30 02:52:55 PM PDT 24
Peak memory 200036 kb
Host smart-8c7eb510-7d66-4fbc-bcca-6f9c16ac5b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126613421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.4126613421
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3464957643
Short name T277
Test name
Test status
Simulation time 2077710342 ps
CPU time 109.92 seconds
Started May 30 02:53:04 PM PDT 24
Finished May 30 02:54:55 PM PDT 24
Peak memory 228696 kb
Host smart-9ff385f4-556e-43f3-bb3e-496d3b3be57c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464957643 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3464957643
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.1480799310
Short name T227
Test name
Test status
Simulation time 129580775 ps
CPU time 1.27 seconds
Started May 30 02:53:05 PM PDT 24
Finished May 30 02:53:07 PM PDT 24
Peak memory 200036 kb
Host smart-9899ba51-a84d-4298-b358-4d9aa6dff5ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480799310 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.1480799310
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.3156008809
Short name T454
Test name
Test status
Simulation time 44915905293 ps
CPU time 606.18 seconds
Started May 30 02:53:00 PM PDT 24
Finished May 30 03:03:08 PM PDT 24
Peak memory 200044 kb
Host smart-1040afe4-c85a-4f3d-9ed8-6a505d8e778e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156008809 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.3156008809
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3037769501
Short name T53
Test name
Test status
Simulation time 2496581590 ps
CPU time 48.74 seconds
Started May 30 02:52:59 PM PDT 24
Finished May 30 02:53:49 PM PDT 24
Peak memory 200024 kb
Host smart-32392b8b-d5ed-46f6-90c8-f8d44bfbf374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037769501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3037769501
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3807780552
Short name T190
Test name
Test status
Simulation time 18750725 ps
CPU time 0.58 seconds
Started May 30 02:53:00 PM PDT 24
Finished May 30 02:53:03 PM PDT 24
Peak memory 194940 kb
Host smart-ef15fbaa-eff4-4fb4-a823-3b4700e74067
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807780552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3807780552
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.4053164760
Short name T362
Test name
Test status
Simulation time 248883976 ps
CPU time 14 seconds
Started May 30 02:53:00 PM PDT 24
Finished May 30 02:53:15 PM PDT 24
Peak memory 227824 kb
Host smart-15cc530c-26af-42c3-a63f-a0348cc416a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4053164760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.4053164760
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3892446181
Short name T369
Test name
Test status
Simulation time 960944546 ps
CPU time 50.13 seconds
Started May 30 02:52:59 PM PDT 24
Finished May 30 02:53:51 PM PDT 24
Peak memory 200104 kb
Host smart-22340c05-cd57-49a0-b548-3b6ee37eaed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892446181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3892446181
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2243886330
Short name T303
Test name
Test status
Simulation time 2016998518 ps
CPU time 468.53 seconds
Started May 30 02:53:00 PM PDT 24
Finished May 30 03:00:50 PM PDT 24
Peak memory 671264 kb
Host smart-bd15aff4-165a-4f25-97b4-cc5d22f91d09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2243886330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2243886330
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.4055099668
Short name T75
Test name
Test status
Simulation time 2488249146 ps
CPU time 135.45 seconds
Started May 30 02:53:05 PM PDT 24
Finished May 30 02:55:22 PM PDT 24
Peak memory 200108 kb
Host smart-df8e9875-e096-45af-92e0-cc03884a7d63
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055099668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.4055099668
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3044680210
Short name T58
Test name
Test status
Simulation time 4394345789 ps
CPU time 26.31 seconds
Started May 30 02:53:05 PM PDT 24
Finished May 30 02:53:33 PM PDT 24
Peak memory 200084 kb
Host smart-4bb19a6e-449a-4345-bc5b-ed031377f40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044680210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3044680210
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2145084531
Short name T406
Test name
Test status
Simulation time 307486902 ps
CPU time 5.95 seconds
Started May 30 02:53:00 PM PDT 24
Finished May 30 02:53:07 PM PDT 24
Peak memory 200104 kb
Host smart-396ffac2-cc65-48be-bdf6-33a9c531bcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145084531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2145084531
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.4280976270
Short name T528
Test name
Test status
Simulation time 14921900407 ps
CPU time 494.68 seconds
Started May 30 02:53:00 PM PDT 24
Finished May 30 03:01:17 PM PDT 24
Peak memory 717680 kb
Host smart-d97fb481-8a3d-4194-8347-5a951e8a9fe6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280976270 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.4280976270
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.807570115
Short name T85
Test name
Test status
Simulation time 216135617 ps
CPU time 1.28 seconds
Started May 30 02:53:01 PM PDT 24
Finished May 30 02:53:04 PM PDT 24
Peak memory 200028 kb
Host smart-71dc38bb-9590-43c1-af3a-1f1a91127572
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807570115 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_hmac_vectors.807570115
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.3761889061
Short name T387
Test name
Test status
Simulation time 78949692651 ps
CPU time 516.39 seconds
Started May 30 02:52:59 PM PDT 24
Finished May 30 03:01:37 PM PDT 24
Peak memory 200084 kb
Host smart-4cc407bf-dfee-49fb-bbcd-d03b7f10e5fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761889061 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.3761889061
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.4258004103
Short name T478
Test name
Test status
Simulation time 8226658821 ps
CPU time 79.3 seconds
Started May 30 02:52:59 PM PDT 24
Finished May 30 02:54:20 PM PDT 24
Peak memory 200028 kb
Host smart-89dd9452-c5c6-41c6-8ce1-886092a0f046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258004103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.4258004103
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.783112029
Short name T459
Test name
Test status
Simulation time 31952755 ps
CPU time 0.58 seconds
Started May 30 02:52:59 PM PDT 24
Finished May 30 02:53:01 PM PDT 24
Peak memory 194892 kb
Host smart-175820d2-8e4b-4a54-ab36-d3d04c19be24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783112029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.783112029
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2100628504
Short name T49
Test name
Test status
Simulation time 734407978 ps
CPU time 16.95 seconds
Started May 30 02:52:58 PM PDT 24
Finished May 30 02:53:16 PM PDT 24
Peak memory 199972 kb
Host smart-5d86bb0b-ac5d-4d2d-b927-9119826819d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2100628504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2100628504
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.261842357
Short name T569
Test name
Test status
Simulation time 865390267 ps
CPU time 82.46 seconds
Started May 30 02:53:02 PM PDT 24
Finished May 30 02:54:25 PM PDT 24
Peak memory 547628 kb
Host smart-88f511d5-54ed-4198-930b-84bb488e198c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=261842357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.261842357
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3817803631
Short name T167
Test name
Test status
Simulation time 3871529985 ps
CPU time 115.87 seconds
Started May 30 02:53:05 PM PDT 24
Finished May 30 02:55:02 PM PDT 24
Peak memory 200060 kb
Host smart-f15485d4-3e9e-4724-b7e6-625f9f9b1bbf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817803631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3817803631
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2090020441
Short name T526
Test name
Test status
Simulation time 5329905279 ps
CPU time 86.53 seconds
Started May 30 02:53:01 PM PDT 24
Finished May 30 02:54:29 PM PDT 24
Peak memory 200132 kb
Host smart-6ec0a277-9599-4d5c-9269-edc5ead1df4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090020441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2090020441
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.4050692652
Short name T461
Test name
Test status
Simulation time 571433073 ps
CPU time 7.11 seconds
Started May 30 02:53:05 PM PDT 24
Finished May 30 02:53:14 PM PDT 24
Peak memory 200072 kb
Host smart-58ff5c70-8b02-40cc-a3f7-c5c6dc2d5151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050692652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.4050692652
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.1810445439
Short name T143
Test name
Test status
Simulation time 72885948 ps
CPU time 1.24 seconds
Started May 30 02:52:57 PM PDT 24
Finished May 30 02:52:59 PM PDT 24
Peak memory 199988 kb
Host smart-4e11f284-addb-451c-943b-c6c78891a10f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810445439 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.1810445439
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.2924779871
Short name T338
Test name
Test status
Simulation time 27703562568 ps
CPU time 482.09 seconds
Started May 30 02:52:59 PM PDT 24
Finished May 30 03:01:03 PM PDT 24
Peak memory 200048 kb
Host smart-c776bdd3-9a06-4f03-a85c-69d99d412022
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924779871 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.2924779871
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2848504201
Short name T382
Test name
Test status
Simulation time 648332175 ps
CPU time 6.53 seconds
Started May 30 02:53:00 PM PDT 24
Finished May 30 02:53:08 PM PDT 24
Peak memory 200016 kb
Host smart-9366a917-f1b7-4d6b-9985-b11ffc5eb1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848504201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2848504201
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.1301124149
Short name T403
Test name
Test status
Simulation time 46661767 ps
CPU time 0.62 seconds
Started May 30 02:53:23 PM PDT 24
Finished May 30 02:53:25 PM PDT 24
Peak memory 196752 kb
Host smart-5ae3da59-e891-4de3-b905-6b311d93811b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301124149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1301124149
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.4003765715
Short name T74
Test name
Test status
Simulation time 4797739863 ps
CPU time 27.26 seconds
Started May 30 02:53:22 PM PDT 24
Finished May 30 02:53:50 PM PDT 24
Peak memory 216412 kb
Host smart-c958e8a4-9bb7-4e41-ab30-b45206915d3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4003765715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.4003765715
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3486822778
Short name T416
Test name
Test status
Simulation time 36257069369 ps
CPU time 67.32 seconds
Started May 30 02:53:24 PM PDT 24
Finished May 30 02:54:33 PM PDT 24
Peak memory 200012 kb
Host smart-d3d0267c-7e0e-490d-b727-ed2f91cddc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486822778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3486822778
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.879198884
Short name T433
Test name
Test status
Simulation time 4319765287 ps
CPU time 650.55 seconds
Started May 30 02:53:24 PM PDT 24
Finished May 30 03:04:17 PM PDT 24
Peak memory 750204 kb
Host smart-7bbc7429-1952-4550-8fc6-9c05a9486fac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=879198884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.879198884
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.371969996
Short name T385
Test name
Test status
Simulation time 12348039745 ps
CPU time 45.83 seconds
Started May 30 02:53:23 PM PDT 24
Finished May 30 02:54:10 PM PDT 24
Peak memory 199988 kb
Host smart-ec13c3c5-2041-4ef7-b8e2-4bfab5667f97
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371969996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.371969996
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.852862186
Short name T594
Test name
Test status
Simulation time 2263830688 ps
CPU time 48.71 seconds
Started May 30 02:53:21 PM PDT 24
Finished May 30 02:54:10 PM PDT 24
Peak memory 200092 kb
Host smart-a33a3b4e-5277-4870-83ec-c1b070172475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852862186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.852862186
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1320158327
Short name T598
Test name
Test status
Simulation time 1005111163 ps
CPU time 7.11 seconds
Started May 30 02:53:00 PM PDT 24
Finished May 30 02:53:09 PM PDT 24
Peak memory 200052 kb
Host smart-2fbcd792-52cb-4a5e-9f98-bd5068709521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320158327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1320158327
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2325663915
Short name T110
Test name
Test status
Simulation time 17730517964 ps
CPU time 51.81 seconds
Started May 30 02:53:24 PM PDT 24
Finished May 30 02:54:18 PM PDT 24
Peak memory 200168 kb
Host smart-00c0bfcf-24ea-4b0c-bddc-262eddb0c5cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325663915 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2325663915
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.2507790433
Short name T436
Test name
Test status
Simulation time 118051615 ps
CPU time 1.32 seconds
Started May 30 02:53:23 PM PDT 24
Finished May 30 02:53:26 PM PDT 24
Peak memory 200048 kb
Host smart-0ef0392f-773a-40dd-8740-d6b89d7938a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507790433 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.2507790433
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.41489471
Short name T329
Test name
Test status
Simulation time 7437298746 ps
CPU time 421.2 seconds
Started May 30 02:53:23 PM PDT 24
Finished May 30 03:00:26 PM PDT 24
Peak memory 200056 kb
Host smart-45637c95-e2cf-4e7b-b127-8f9f58defa36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41489471 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.41489471
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.2842832822
Short name T156
Test name
Test status
Simulation time 11831819318 ps
CPU time 89.64 seconds
Started May 30 02:53:22 PM PDT 24
Finished May 30 02:54:53 PM PDT 24
Peak memory 200128 kb
Host smart-b147fa9a-fe8b-4a78-9c7c-fd89afd7084c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842832822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2842832822
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.2144827776
Short name T353
Test name
Test status
Simulation time 93202377 ps
CPU time 0.66 seconds
Started May 30 02:53:22 PM PDT 24
Finished May 30 02:53:25 PM PDT 24
Peak memory 195656 kb
Host smart-24cfbe04-3fe3-4014-aca8-11641a67b112
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144827776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2144827776
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.75689196
Short name T276
Test name
Test status
Simulation time 1213985775 ps
CPU time 36.07 seconds
Started May 30 02:53:24 PM PDT 24
Finished May 30 02:54:02 PM PDT 24
Peak memory 233808 kb
Host smart-14d7927e-1a42-4fac-ab4c-5e073737d817
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=75689196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.75689196
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.3732359918
Short name T36
Test name
Test status
Simulation time 2521001245 ps
CPU time 68.22 seconds
Started May 30 02:53:24 PM PDT 24
Finished May 30 02:54:33 PM PDT 24
Peak memory 200080 kb
Host smart-f88f2815-5c7c-42c2-9d63-f2e9be83162c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732359918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.3732359918
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3605627688
Short name T417
Test name
Test status
Simulation time 22354045078 ps
CPU time 791.2 seconds
Started May 30 02:53:23 PM PDT 24
Finished May 30 03:06:35 PM PDT 24
Peak memory 735696 kb
Host smart-b574bd36-72d8-4589-914e-4fd1b2f15a63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3605627688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3605627688
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.921765439
Short name T212
Test name
Test status
Simulation time 7410184560 ps
CPU time 109.98 seconds
Started May 30 02:53:22 PM PDT 24
Finished May 30 02:55:14 PM PDT 24
Peak memory 200076 kb
Host smart-c9fc5c07-9a5b-4a98-95c5-749a5081ecda
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921765439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.921765439
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.2065851176
Short name T347
Test name
Test status
Simulation time 790158440 ps
CPU time 4.45 seconds
Started May 30 02:53:22 PM PDT 24
Finished May 30 02:53:28 PM PDT 24
Peak memory 199988 kb
Host smart-1e699fa4-6f65-4c66-9ac8-58b9f4232990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065851176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2065851176
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.581464489
Short name T317
Test name
Test status
Simulation time 682491842 ps
CPU time 5.31 seconds
Started May 30 02:53:22 PM PDT 24
Finished May 30 02:53:28 PM PDT 24
Peak memory 200024 kb
Host smart-f5e9ad70-eb83-46d0-96e4-1fbb0f83810a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581464489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.581464489
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.80495574
Short name T596
Test name
Test status
Simulation time 80450994335 ps
CPU time 2074.73 seconds
Started May 30 02:53:22 PM PDT 24
Finished May 30 03:27:58 PM PDT 24
Peak memory 764260 kb
Host smart-3e61c841-691c-49a8-aea0-80fc4e3584ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80495574 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.80495574
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.4276988121
Short name T253
Test name
Test status
Simulation time 596845090 ps
CPU time 1.29 seconds
Started May 30 02:53:22 PM PDT 24
Finished May 30 02:53:25 PM PDT 24
Peak memory 199956 kb
Host smart-da38c02b-0d0e-430a-bc3b-17a0d57ca94e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276988121 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.4276988121
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.4137840165
Short name T345
Test name
Test status
Simulation time 112784346165 ps
CPU time 538.32 seconds
Started May 30 02:53:21 PM PDT 24
Finished May 30 03:02:21 PM PDT 24
Peak memory 200056 kb
Host smart-cf03f2ec-0ff4-493d-a0ce-3745a332b81a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137840165 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.4137840165
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1553968049
Short name T458
Test name
Test status
Simulation time 2761078725 ps
CPU time 24.92 seconds
Started May 30 02:53:21 PM PDT 24
Finished May 30 02:53:47 PM PDT 24
Peak memory 200080 kb
Host smart-8171061a-59ac-4db6-8a6f-aa30cf777861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553968049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1553968049
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3569564301
Short name T296
Test name
Test status
Simulation time 13849321 ps
CPU time 0.64 seconds
Started May 30 02:53:37 PM PDT 24
Finished May 30 02:53:40 PM PDT 24
Peak memory 195952 kb
Host smart-44b8fa0e-9862-4d0c-b6c2-bc7731ec89fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569564301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3569564301
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.3931580957
Short name T470
Test name
Test status
Simulation time 3013340333 ps
CPU time 13.08 seconds
Started May 30 02:53:24 PM PDT 24
Finished May 30 02:53:39 PM PDT 24
Peak memory 216460 kb
Host smart-c9d3f5b7-6743-4e82-b98d-08ca10fcf713
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3931580957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3931580957
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1214593600
Short name T449
Test name
Test status
Simulation time 16161128345 ps
CPU time 56.05 seconds
Started May 30 02:53:23 PM PDT 24
Finished May 30 02:54:21 PM PDT 24
Peak memory 200132 kb
Host smart-8db7d6fd-876f-4417-8aaf-8f70d19d5166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214593600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1214593600
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1482817370
Short name T322
Test name
Test status
Simulation time 5875780144 ps
CPU time 824.22 seconds
Started May 30 02:53:21 PM PDT 24
Finished May 30 03:07:07 PM PDT 24
Peak memory 729368 kb
Host smart-0ed7154c-a928-43a0-8bf2-e4785bde50db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1482817370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1482817370
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1740584302
Short name T217
Test name
Test status
Simulation time 12480546428 ps
CPU time 163.66 seconds
Started May 30 02:53:22 PM PDT 24
Finished May 30 02:56:07 PM PDT 24
Peak memory 200092 kb
Host smart-ca6b754c-7f6d-4db1-a12e-02ace95bbda7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740584302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1740584302
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.4074395906
Short name T358
Test name
Test status
Simulation time 13094906751 ps
CPU time 55.05 seconds
Started May 30 02:53:21 PM PDT 24
Finished May 30 02:54:18 PM PDT 24
Peak memory 200188 kb
Host smart-a909059e-2187-41d5-85f6-17557a7326c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074395906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.4074395906
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2336371769
Short name T298
Test name
Test status
Simulation time 90811519 ps
CPU time 1.62 seconds
Started May 30 02:53:24 PM PDT 24
Finished May 30 02:53:27 PM PDT 24
Peak memory 200056 kb
Host smart-fb92eb5c-a5af-465f-94fe-81c73f116273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336371769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2336371769
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.1179734
Short name T437
Test name
Test status
Simulation time 3902502265 ps
CPU time 22.27 seconds
Started May 30 02:53:39 PM PDT 24
Finished May 30 02:54:03 PM PDT 24
Peak memory 199836 kb
Host smart-34ae7d5b-cb71-410b-a06f-a4868aa1198f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179734 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.1179734
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.4014994059
Short name T255
Test name
Test status
Simulation time 35046797 ps
CPU time 1.48 seconds
Started May 30 02:53:35 PM PDT 24
Finished May 30 02:53:38 PM PDT 24
Peak memory 200040 kb
Host smart-ca826635-54ba-4054-8706-4a464f43ed8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014994059 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.4014994059
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.1984320559
Short name T320
Test name
Test status
Simulation time 34793149270 ps
CPU time 473.34 seconds
Started May 30 02:53:40 PM PDT 24
Finished May 30 03:01:35 PM PDT 24
Peak memory 200068 kb
Host smart-1a59c425-96c1-41b7-92d3-d2bdfe6286f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984320559 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.1984320559
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.4245845647
Short name T164
Test name
Test status
Simulation time 6511458007 ps
CPU time 24 seconds
Started May 30 02:53:39 PM PDT 24
Finished May 30 02:54:05 PM PDT 24
Peak memory 200140 kb
Host smart-e98602fb-262a-4ef6-a937-d0c090be78cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245845647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.4245845647
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3480318971
Short name T248
Test name
Test status
Simulation time 40933596 ps
CPU time 0.6 seconds
Started May 30 02:53:34 PM PDT 24
Finished May 30 02:53:36 PM PDT 24
Peak memory 196676 kb
Host smart-63564faf-9d39-4f8f-8127-06954f00a667
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480318971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3480318971
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.1538779352
Short name T405
Test name
Test status
Simulation time 19074498231 ps
CPU time 62.62 seconds
Started May 30 02:53:37 PM PDT 24
Finished May 30 02:54:42 PM PDT 24
Peak memory 230744 kb
Host smart-31216759-47a1-4239-af7f-a87c1c012549
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1538779352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.1538779352
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.1820146224
Short name T174
Test name
Test status
Simulation time 4137465254 ps
CPU time 43.17 seconds
Started May 30 02:53:37 PM PDT 24
Finished May 30 02:54:23 PM PDT 24
Peak memory 200076 kb
Host smart-9e1e8239-ca7c-4936-ac00-3eab6b2f73fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820146224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.1820146224
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3943000264
Short name T339
Test name
Test status
Simulation time 19070985 ps
CPU time 0.75 seconds
Started May 30 02:53:35 PM PDT 24
Finished May 30 02:53:37 PM PDT 24
Peak memory 198148 kb
Host smart-8ba80fb4-7060-4147-858b-4f9c605ee775
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3943000264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3943000264
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.967735441
Short name T166
Test name
Test status
Simulation time 15903279200 ps
CPU time 116.2 seconds
Started May 30 02:53:36 PM PDT 24
Finished May 30 02:55:34 PM PDT 24
Peak memory 200068 kb
Host smart-9bb9f85d-8b4a-452b-97bb-9d1cccaf1ad6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967735441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.967735441
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1828450190
Short name T249
Test name
Test status
Simulation time 3537295812 ps
CPU time 25.44 seconds
Started May 30 02:53:35 PM PDT 24
Finished May 30 02:54:02 PM PDT 24
Peak memory 200168 kb
Host smart-2e1ac7f5-a4c0-4c4e-bac1-80095d889653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828450190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1828450190
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.764309842
Short name T139
Test name
Test status
Simulation time 640077228 ps
CPU time 4.03 seconds
Started May 30 02:53:35 PM PDT 24
Finished May 30 02:53:41 PM PDT 24
Peak memory 200028 kb
Host smart-868eeb71-015b-4058-bd4e-38b13767281d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764309842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.764309842
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2064890696
Short name T48
Test name
Test status
Simulation time 131059581602 ps
CPU time 2908.93 seconds
Started May 30 02:53:35 PM PDT 24
Finished May 30 03:42:06 PM PDT 24
Peak memory 795508 kb
Host smart-85a509e2-63d9-45c9-a5e8-4cdc2af723bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064890696 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2064890696
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.3739333111
Short name T590
Test name
Test status
Simulation time 78603601 ps
CPU time 1.38 seconds
Started May 30 02:53:38 PM PDT 24
Finished May 30 02:53:41 PM PDT 24
Peak memory 200072 kb
Host smart-408bb744-2639-4639-94c4-04ef65dbb602
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739333111 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.3739333111
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.3129866219
Short name T140
Test name
Test status
Simulation time 8058162688 ps
CPU time 458.33 seconds
Started May 30 02:53:36 PM PDT 24
Finished May 30 03:01:16 PM PDT 24
Peak memory 200024 kb
Host smart-e4d08110-c6ca-4647-b202-34d0a71a09a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129866219 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.3129866219
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3438684435
Short name T323
Test name
Test status
Simulation time 11630364030 ps
CPU time 62.75 seconds
Started May 30 02:53:37 PM PDT 24
Finished May 30 02:54:42 PM PDT 24
Peak memory 200056 kb
Host smart-41edf9a7-f7b2-49ea-958b-3a33c89827bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438684435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3438684435
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1081655
Short name T219
Test name
Test status
Simulation time 32015243 ps
CPU time 0.58 seconds
Started May 30 02:53:40 PM PDT 24
Finished May 30 02:53:42 PM PDT 24
Peak memory 195708 kb
Host smart-e81dcc43-0d7c-4fd2-94cd-ab6cfa518d8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1081655
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.497435135
Short name T490
Test name
Test status
Simulation time 412516078 ps
CPU time 5.9 seconds
Started May 30 02:53:36 PM PDT 24
Finished May 30 02:53:44 PM PDT 24
Peak memory 200004 kb
Host smart-76182466-ab48-453d-a309-8982ef8e9e2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=497435135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.497435135
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.4083219039
Short name T582
Test name
Test status
Simulation time 4516952540 ps
CPU time 63.87 seconds
Started May 30 02:53:40 PM PDT 24
Finished May 30 02:54:46 PM PDT 24
Peak memory 200092 kb
Host smart-a5957e68-402a-44ef-83fd-bcafa12780d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083219039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.4083219039
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3418940753
Short name T503
Test name
Test status
Simulation time 12228555126 ps
CPU time 688.24 seconds
Started May 30 02:53:35 PM PDT 24
Finished May 30 03:05:04 PM PDT 24
Peak memory 465408 kb
Host smart-13f8e9a8-3ad9-4a11-9149-ddf37cc57fa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3418940753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3418940753
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3986361082
Short name T311
Test name
Test status
Simulation time 4170083378 ps
CPU time 62.55 seconds
Started May 30 02:53:36 PM PDT 24
Finished May 30 02:54:41 PM PDT 24
Peak memory 200064 kb
Host smart-fadad5aa-1b08-492c-9064-11ecde63f262
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986361082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3986361082
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2329485137
Short name T289
Test name
Test status
Simulation time 6657027679 ps
CPU time 101.7 seconds
Started May 30 02:53:37 PM PDT 24
Finished May 30 02:55:21 PM PDT 24
Peak memory 200104 kb
Host smart-d2798592-6d1b-4278-a873-64ed9794e7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329485137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2329485137
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.753293426
Short name T183
Test name
Test status
Simulation time 518288892 ps
CPU time 6.09 seconds
Started May 30 02:53:35 PM PDT 24
Finished May 30 02:53:43 PM PDT 24
Peak memory 200076 kb
Host smart-a5735ed0-1b0c-4a72-9bd1-f242f927cb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753293426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.753293426
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.2869506629
Short name T272
Test name
Test status
Simulation time 31615254 ps
CPU time 1.11 seconds
Started May 30 02:53:35 PM PDT 24
Finished May 30 02:53:38 PM PDT 24
Peak memory 199932 kb
Host smart-1505f48e-22b2-49c9-9615-5a33f7620392
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869506629 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.2869506629
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.2160349658
Short name T381
Test name
Test status
Simulation time 430458999038 ps
CPU time 505.03 seconds
Started May 30 02:53:36 PM PDT 24
Finished May 30 03:02:03 PM PDT 24
Peak memory 200096 kb
Host smart-c6716c47-f5cb-42a8-b3cf-660f5ceb5f23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160349658 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.2160349658
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3936791898
Short name T432
Test name
Test status
Simulation time 1905123610 ps
CPU time 99.92 seconds
Started May 30 02:53:39 PM PDT 24
Finished May 30 02:55:21 PM PDT 24
Peak memory 200064 kb
Host smart-a36e0c82-5970-4413-aeea-97531087e992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936791898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3936791898
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.2265254314
Short name T263
Test name
Test status
Simulation time 14148721 ps
CPU time 0.6 seconds
Started May 30 02:50:08 PM PDT 24
Finished May 30 02:50:10 PM PDT 24
Peak memory 195700 kb
Host smart-1782facc-8981-4b1b-b563-7242a3148942
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265254314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.2265254314
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.3116014809
Short name T418
Test name
Test status
Simulation time 952014656 ps
CPU time 32.06 seconds
Started May 30 02:49:57 PM PDT 24
Finished May 30 02:50:31 PM PDT 24
Peak memory 227636 kb
Host smart-6d34d14f-0635-48ec-a822-0f9c88ea120c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3116014809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3116014809
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.4116224194
Short name T534
Test name
Test status
Simulation time 577488459 ps
CPU time 5.39 seconds
Started May 30 02:49:58 PM PDT 24
Finished May 30 02:50:05 PM PDT 24
Peak memory 199964 kb
Host smart-a8bb1861-f614-4add-a44e-6f8e91c51325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116224194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.4116224194
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2800236265
Short name T285
Test name
Test status
Simulation time 8458370821 ps
CPU time 1214.76 seconds
Started May 30 02:49:54 PM PDT 24
Finished May 30 03:10:10 PM PDT 24
Peak memory 760480 kb
Host smart-dde2f3d2-4493-44fa-99d0-e211f6982968
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2800236265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2800236265
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1454994524
Short name T160
Test name
Test status
Simulation time 2407441446 ps
CPU time 128.08 seconds
Started May 30 02:49:57 PM PDT 24
Finished May 30 02:52:07 PM PDT 24
Peak memory 200048 kb
Host smart-61c8cbb5-8209-47bc-a706-ac4df5436ab3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454994524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1454994524
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3671285737
Short name T247
Test name
Test status
Simulation time 14826834993 ps
CPU time 76.56 seconds
Started May 30 02:49:54 PM PDT 24
Finished May 30 02:51:12 PM PDT 24
Peak memory 200072 kb
Host smart-28848196-5b26-48f5-be96-99eb7f472d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671285737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3671285737
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3079154339
Short name T515
Test name
Test status
Simulation time 437227926 ps
CPU time 7.51 seconds
Started May 30 02:49:55 PM PDT 24
Finished May 30 02:50:04 PM PDT 24
Peak memory 200020 kb
Host smart-0c1e4310-ce47-46fd-81cd-12861e40fabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079154339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3079154339
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.2058734870
Short name T274
Test name
Test status
Simulation time 122002771044 ps
CPU time 1026 seconds
Started May 30 02:49:55 PM PDT 24
Finished May 30 03:07:03 PM PDT 24
Peak memory 720676 kb
Host smart-903618fc-2423-4d09-95b0-e45a0ae74228
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058734870 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.2058734870
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.2062003219
Short name T566
Test name
Test status
Simulation time 97709197 ps
CPU time 1.05 seconds
Started May 30 02:49:57 PM PDT 24
Finished May 30 02:50:00 PM PDT 24
Peak memory 199924 kb
Host smart-bc68fdfe-6b4f-4604-b773-0a04519dfc51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062003219 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.2062003219
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.1999963781
Short name T149
Test name
Test status
Simulation time 7571824784 ps
CPU time 465.08 seconds
Started May 30 02:49:55 PM PDT 24
Finished May 30 02:57:41 PM PDT 24
Peak memory 200068 kb
Host smart-4506c241-6ccc-4559-b154-9e1ce8b29577
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999963781 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.1999963781
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.1262833002
Short name T536
Test name
Test status
Simulation time 291524441 ps
CPU time 3.17 seconds
Started May 30 02:49:55 PM PDT 24
Finished May 30 02:49:59 PM PDT 24
Peak memory 199884 kb
Host smart-d9ac14f5-6f05-45b5-8471-edf19cde51a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262833002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.1262833002
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/56.hmac_stress_all_with_rand_reset.1441337441
Short name T10
Test name
Test status
Simulation time 174758069839 ps
CPU time 2727.71 seconds
Started May 30 02:53:39 PM PDT 24
Finished May 30 03:39:09 PM PDT 24
Peak memory 370304 kb
Host smart-5dc0bed2-c0f8-4b2c-a31d-563da040b410
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1441337441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.hmac_stress_all_with_rand_reset.1441337441
Directory /workspace/56.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_alert_test.933385420
Short name T24
Test name
Test status
Simulation time 14809204 ps
CPU time 0.57 seconds
Started May 30 02:50:10 PM PDT 24
Finished May 30 02:50:12 PM PDT 24
Peak memory 194932 kb
Host smart-633dca61-c576-460c-87c3-dcfe4edc029c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933385420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.933385420
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3316409803
Short name T496
Test name
Test status
Simulation time 2508652587 ps
CPU time 31.15 seconds
Started May 30 02:50:11 PM PDT 24
Finished May 30 02:50:44 PM PDT 24
Peak memory 208316 kb
Host smart-c465f196-3f3d-4cdd-9898-4907e3d8078d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3316409803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3316409803
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.2816264867
Short name T482
Test name
Test status
Simulation time 7915110409 ps
CPU time 37.83 seconds
Started May 30 02:50:11 PM PDT 24
Finished May 30 02:50:50 PM PDT 24
Peak memory 200100 kb
Host smart-383d8fb2-a990-4639-9f0b-8542a4759233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816264867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2816264867
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1469339418
Short name T548
Test name
Test status
Simulation time 3349138887 ps
CPU time 745.45 seconds
Started May 30 02:50:08 PM PDT 24
Finished May 30 03:02:35 PM PDT 24
Peak memory 637180 kb
Host smart-4b6965a3-14a9-4b43-a4f6-f8ebf759196f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1469339418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1469339418
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1129913542
Short name T307
Test name
Test status
Simulation time 9020379244 ps
CPU time 114.53 seconds
Started May 30 02:50:09 PM PDT 24
Finished May 30 02:52:05 PM PDT 24
Peak memory 200128 kb
Host smart-41a04cd4-a3be-419f-8ac6-6b3f921f9a78
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129913542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1129913542
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.15688155
Short name T210
Test name
Test status
Simulation time 13958698407 ps
CPU time 44.21 seconds
Started May 30 02:50:08 PM PDT 24
Finished May 30 02:50:53 PM PDT 24
Peak memory 200104 kb
Host smart-8fc45bfc-881d-4327-b055-da37564eea66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15688155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.15688155
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3915264368
Short name T422
Test name
Test status
Simulation time 216881237 ps
CPU time 3.67 seconds
Started May 30 02:50:10 PM PDT 24
Finished May 30 02:50:15 PM PDT 24
Peak memory 200092 kb
Host smart-37e360a6-d415-4547-b05e-07f5fba9b3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915264368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3915264368
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.3208117820
Short name T126
Test name
Test status
Simulation time 23750255593 ps
CPU time 1575.63 seconds
Started May 30 02:50:10 PM PDT 24
Finished May 30 03:16:28 PM PDT 24
Peak memory 804724 kb
Host smart-1ffcf136-399c-4a73-87f3-d30a87089137
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208117820 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3208117820
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.3247119290
Short name T321
Test name
Test status
Simulation time 110944944 ps
CPU time 1.07 seconds
Started May 30 02:50:10 PM PDT 24
Finished May 30 02:50:13 PM PDT 24
Peak memory 200060 kb
Host smart-7acbc97e-5abe-45f5-a8d9-a2ed218dc01c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247119290 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.3247119290
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.495236254
Short name T91
Test name
Test status
Simulation time 8468600141 ps
CPU time 499.14 seconds
Started May 30 02:50:11 PM PDT 24
Finished May 30 02:58:32 PM PDT 24
Peak memory 200100 kb
Host smart-9dde8801-402b-4b59-97bc-5f5f78f8823f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495236254 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.495236254
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2917195489
Short name T466
Test name
Test status
Simulation time 8573021938 ps
CPU time 67.33 seconds
Started May 30 02:50:11 PM PDT 24
Finished May 30 02:51:21 PM PDT 24
Peak memory 200068 kb
Host smart-a86bb8ca-c719-46c7-abbd-aae0a997fd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917195489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2917195489
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3069722201
Short name T584
Test name
Test status
Simulation time 23528986 ps
CPU time 0.59 seconds
Started May 30 02:50:11 PM PDT 24
Finished May 30 02:50:14 PM PDT 24
Peak memory 196004 kb
Host smart-cd3389c2-12d4-4b06-b507-dd96b484e1ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069722201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3069722201
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1617605327
Short name T445
Test name
Test status
Simulation time 8172175965 ps
CPU time 55.24 seconds
Started May 30 02:50:09 PM PDT 24
Finished May 30 02:51:06 PM PDT 24
Peak memory 241836 kb
Host smart-d05d5c34-2f01-4039-95e7-5e9262d319e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1617605327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1617605327
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3243951841
Short name T6
Test name
Test status
Simulation time 1401743074 ps
CPU time 18.74 seconds
Started May 30 02:50:10 PM PDT 24
Finished May 30 02:50:30 PM PDT 24
Peak memory 199960 kb
Host smart-bf0e673a-6d3f-4954-a38e-ba0c2617dd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243951841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3243951841
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2003272872
Short name T380
Test name
Test status
Simulation time 3220021715 ps
CPU time 711.98 seconds
Started May 30 02:50:09 PM PDT 24
Finished May 30 03:02:03 PM PDT 24
Peak memory 714008 kb
Host smart-01cda49f-0c58-4cca-a595-6f08b4854f8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2003272872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2003272872
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2230419036
Short name T547
Test name
Test status
Simulation time 7180431964 ps
CPU time 102.94 seconds
Started May 30 02:50:11 PM PDT 24
Finished May 30 02:51:56 PM PDT 24
Peak memory 200072 kb
Host smart-31c37f9b-ef48-4c43-b34b-1ea191473444
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230419036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2230419036
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2851847108
Short name T182
Test name
Test status
Simulation time 3126099176 ps
CPU time 93.15 seconds
Started May 30 02:50:11 PM PDT 24
Finished May 30 02:51:46 PM PDT 24
Peak memory 200112 kb
Host smart-8763f387-cc6d-4f31-93ee-cde4894d5553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851847108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2851847108
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.222537735
Short name T399
Test name
Test status
Simulation time 175402545 ps
CPU time 2.66 seconds
Started May 30 02:50:12 PM PDT 24
Finished May 30 02:50:16 PM PDT 24
Peak memory 200080 kb
Host smart-1a44ad72-3a86-4779-b90d-26be4079a9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222537735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.222537735
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.3414577583
Short name T21
Test name
Test status
Simulation time 31044061275 ps
CPU time 958.62 seconds
Started May 30 02:50:11 PM PDT 24
Finished May 30 03:06:12 PM PDT 24
Peak memory 739816 kb
Host smart-3438124c-fd08-4185-ac7c-530f57b0009b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414577583 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.3414577583
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.250483353
Short name T578
Test name
Test status
Simulation time 539653802 ps
CPU time 1.45 seconds
Started May 30 02:50:08 PM PDT 24
Finished May 30 02:50:12 PM PDT 24
Peak memory 200000 kb
Host smart-1c6db4d9-8bdc-4ebe-a78b-8e1336fa342c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250483353 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.hmac_test_hmac_vectors.250483353
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.1456012907
Short name T372
Test name
Test status
Simulation time 160526973180 ps
CPU time 586.5 seconds
Started May 30 02:50:09 PM PDT 24
Finished May 30 02:59:57 PM PDT 24
Peak memory 200008 kb
Host smart-16e002f4-da2c-4144-9562-87ac2bb97cfd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456012907 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.1456012907
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.3882383595
Short name T69
Test name
Test status
Simulation time 30002318570 ps
CPU time 86.77 seconds
Started May 30 02:50:11 PM PDT 24
Finished May 30 02:51:40 PM PDT 24
Peak memory 200044 kb
Host smart-525d9808-8783-4e6f-8e9e-68dd271577be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882383595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3882383595
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2069678521
Short name T524
Test name
Test status
Simulation time 22231170 ps
CPU time 0.63 seconds
Started May 30 02:50:08 PM PDT 24
Finished May 30 02:50:10 PM PDT 24
Peak memory 195992 kb
Host smart-dc257dc0-e444-4864-bf9d-461e8be3ffef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069678521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2069678521
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1236555417
Short name T87
Test name
Test status
Simulation time 38757077 ps
CPU time 2.17 seconds
Started May 30 02:50:10 PM PDT 24
Finished May 30 02:50:14 PM PDT 24
Peak memory 208192 kb
Host smart-157f048a-99b9-4ef3-bd99-7dad18f05bfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1236555417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1236555417
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2898155565
Short name T271
Test name
Test status
Simulation time 5827531192 ps
CPU time 16.72 seconds
Started May 30 02:50:10 PM PDT 24
Finished May 30 02:50:29 PM PDT 24
Peak memory 200112 kb
Host smart-5f847098-d08c-4a59-b807-fcc36d5faee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898155565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2898155565
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.798618425
Short name T119
Test name
Test status
Simulation time 4293425076 ps
CPU time 1110.8 seconds
Started May 30 02:50:12 PM PDT 24
Finished May 30 03:08:45 PM PDT 24
Peak memory 707984 kb
Host smart-05bc65b7-7d58-4277-835c-9e7109bdc5cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=798618425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.798618425
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.2117344057
Short name T389
Test name
Test status
Simulation time 10728704624 ps
CPU time 147.85 seconds
Started May 30 02:50:08 PM PDT 24
Finished May 30 02:52:38 PM PDT 24
Peak memory 200084 kb
Host smart-5f544453-2fe9-46dc-ba48-b34d941c3eff
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117344057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2117344057
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3664818406
Short name T504
Test name
Test status
Simulation time 374071231 ps
CPU time 20.55 seconds
Started May 30 02:50:11 PM PDT 24
Finished May 30 02:50:34 PM PDT 24
Peak memory 200024 kb
Host smart-9b6d7bb0-7302-49ba-8477-85c721675fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664818406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3664818406
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.2180603030
Short name T344
Test name
Test status
Simulation time 140468924 ps
CPU time 1.36 seconds
Started May 30 02:50:07 PM PDT 24
Finished May 30 02:50:10 PM PDT 24
Peak memory 200024 kb
Host smart-37079e8f-3487-47e1-952e-899eb774facc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180603030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.2180603030
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.3485994257
Short name T337
Test name
Test status
Simulation time 23797750970 ps
CPU time 1676.6 seconds
Started May 30 02:50:08 PM PDT 24
Finished May 30 03:18:07 PM PDT 24
Peak memory 679084 kb
Host smart-be566b20-eaef-4efc-94ed-2c9dc6fb76c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485994257 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3485994257
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.3762757060
Short name T316
Test name
Test status
Simulation time 260439688 ps
CPU time 1.11 seconds
Started May 30 02:50:10 PM PDT 24
Finished May 30 02:50:13 PM PDT 24
Peak memory 199932 kb
Host smart-a5c09f34-0e9d-4360-b151-123eefc913c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762757060 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.3762757060
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.3529964394
Short name T177
Test name
Test status
Simulation time 169354894163 ps
CPU time 525.41 seconds
Started May 30 02:50:11 PM PDT 24
Finished May 30 02:58:58 PM PDT 24
Peak memory 200064 kb
Host smart-73ed4b7b-2193-4b06-9553-ca48dc212ef7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529964394 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.3529964394
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.4234856125
Short name T407
Test name
Test status
Simulation time 431473015 ps
CPU time 6.42 seconds
Started May 30 02:50:10 PM PDT 24
Finished May 30 02:50:18 PM PDT 24
Peak memory 199956 kb
Host smart-7510b1c4-cda4-4c5a-89a3-29e6bdb56ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234856125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.4234856125
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3412366764
Short name T186
Test name
Test status
Simulation time 16787834 ps
CPU time 0.59 seconds
Started May 30 02:50:20 PM PDT 24
Finished May 30 02:50:22 PM PDT 24
Peak memory 195936 kb
Host smart-ef9ece9c-0986-45ed-86f5-839a32c2a641
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412366764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3412366764
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1004922587
Short name T279
Test name
Test status
Simulation time 26196278 ps
CPU time 1.74 seconds
Started May 30 02:50:09 PM PDT 24
Finished May 30 02:50:13 PM PDT 24
Peak memory 199892 kb
Host smart-9f9cf4e8-5569-4881-a390-2a6f9e4fd7b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1004922587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1004922587
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.1349768270
Short name T282
Test name
Test status
Simulation time 619158152 ps
CPU time 32.38 seconds
Started May 30 02:50:10 PM PDT 24
Finished May 30 02:50:44 PM PDT 24
Peak memory 200024 kb
Host smart-1dc34d8a-60b5-4ec8-a137-bc2eadd8435e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349768270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.1349768270
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.4020058679
Short name T209
Test name
Test status
Simulation time 8791370588 ps
CPU time 1359.24 seconds
Started May 30 02:50:10 PM PDT 24
Finished May 30 03:12:51 PM PDT 24
Peak memory 794068 kb
Host smart-2f5bdcec-ed64-47b5-9672-723ff7b51bfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4020058679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.4020058679
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.867874496
Short name T400
Test name
Test status
Simulation time 2215179926 ps
CPU time 114.1 seconds
Started May 30 02:50:07 PM PDT 24
Finished May 30 02:52:03 PM PDT 24
Peak memory 200080 kb
Host smart-4363bc93-3be5-4520-8be6-08e94fd99e2e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867874496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.867874496
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.2384167384
Short name T448
Test name
Test status
Simulation time 1477322793 ps
CPU time 88.59 seconds
Started May 30 02:50:11 PM PDT 24
Finished May 30 02:51:41 PM PDT 24
Peak memory 200020 kb
Host smart-080d56c0-f5a9-4e21-a2b9-f5b3e7ae5bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384167384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2384167384
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2090135449
Short name T539
Test name
Test status
Simulation time 356965924 ps
CPU time 2.56 seconds
Started May 30 02:50:10 PM PDT 24
Finished May 30 02:50:14 PM PDT 24
Peak memory 200044 kb
Host smart-f0f5faca-d6e0-4e15-b7fa-4dbba187c167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090135449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2090135449
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1601995118
Short name T383
Test name
Test status
Simulation time 53977656766 ps
CPU time 2497.76 seconds
Started May 30 02:50:22 PM PDT 24
Finished May 30 03:32:02 PM PDT 24
Peak memory 785540 kb
Host smart-f776f3ca-4424-4c67-b744-c2d6505f4194
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601995118 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1601995118
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.546375061
Short name T395
Test name
Test status
Simulation time 48711097 ps
CPU time 1.22 seconds
Started May 30 02:50:12 PM PDT 24
Finished May 30 02:50:15 PM PDT 24
Peak memory 200036 kb
Host smart-869da8a0-d925-45fb-b563-67a67b5b5652
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546375061 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.hmac_test_hmac_vectors.546375061
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.4099584483
Short name T94
Test name
Test status
Simulation time 52034477170 ps
CPU time 494.24 seconds
Started May 30 02:50:07 PM PDT 24
Finished May 30 02:58:23 PM PDT 24
Peak memory 200072 kb
Host smart-a6e18a48-2387-4b64-b940-c060af5830b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099584483 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.4099584483
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.41303299
Short name T487
Test name
Test status
Simulation time 17989611035 ps
CPU time 79.13 seconds
Started May 30 02:50:08 PM PDT 24
Finished May 30 02:51:30 PM PDT 24
Peak memory 200052 kb
Host smart-3c5c81b5-c8e7-4155-9b58-655a3b174597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41303299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.41303299
Directory /workspace/9.hmac_wipe_secret/latest
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