Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14487987	1			T1	1141		T3	7426		T4	91
all_values[1]	14487987	1			T1	1141		T3	7426		T4	91
all_values[2]	14487987	1			T1	1141		T3	7426		T4	91

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132806

1

T1

221

T5

5

T6

3

auto[1]

43331155

1

T1

3202

T3

22278

T4

273

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36150189

1

T1

2507

T3

19703

T4

216

auto[1]

7313772

1

T1

916

T3

2575

T4

57

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	39594	1			T8	372		T49	8		T88	25
all_values[0]	auto[0]	auto[1]	317	1			T49	2		T88	2		T104	2
all_values[0]	auto[1]	auto[0]	14410797	1			T1	1139		T3	7412		T4	87
all_values[0]	auto[1]	auto[1]	37279	1			T1	2		T3	14		T4	4
all_values[1]	auto[0]	auto[0]	52965	1			T6	3		T9	2		T8	2423
all_values[1]	auto[0]	auto[1]	176	1			T27	5		T42	4		T103	4
all_values[1]	auto[1]	auto[0]	14434619	1			T1	1141		T3	7426		T4	91
all_values[1]	auto[1]	auto[1]	227	1			T27	4		T120	4		T42	9
all_values[2]	auto[0]	auto[0]	17246	1			T1	221		T5	5		T8	4
all_values[2]	auto[0]	auto[1]	22508	1			T8	2094		T10	316		T34	179
all_values[2]	auto[1]	auto[0]	7194968	1			T1	6		T3	4865		T4	38
all_values[2]	auto[1]	auto[1]	7253265	1			T1	914		T3	2561		T4	53