Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6692569

1

T1

229

T3

751

T4

33

auto[1]

2487315

1

T1

906

T3

6644

T5

59

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2468584

1

T1

617

T3

2299

T5

61

auto[1]

6711300

1

T1

518

T3

5096

T4

33

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5684166

1

T1

626

T3

4924

T5

54

auto[1]

3495718

1

T1

509

T3

2471

T4

33

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	7336916	1			T1	1108		T3	7058		T4	31
fifo_depth[1]	312885	1			T1	12		T3	174		T4	2
fifo_depth[2]	253066	1			T1	9		T3	100		T5	5
fifo_depth[3]	197521	1			T1	5		T3	47		T5	5
fifo_depth[4]	162742	1			T1	1		T3	11		T5	1
fifo_depth[5]	136118	1			T3	4		T5	3		T6	50
fifo_depth[6]	126411	1			T3	1		T5	3		T6	56
fifo_depth[7]	109199	1			T5	3		T6	61		T7	1304

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1842968

1

T1

27

T3

337

T4

2

auto[1]

7336916

1

T1

1108

T3

7058

T4

31

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9166399

1

T1

1135

T3

7395

T4

33

auto[1]

13485

1

T8

815

T19

1

T27

151

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

87794

1

T1

27

T9

364

T8

2951

auto[0]

auto[0]

auto[0]

auto[1]

84486

1

T3

56

T8

3193

T10

331

auto[0]

auto[0]

auto[1]

auto[0]

874350

1

T7

16234

T9

176

T8

3903

auto[0]

auto[0]

auto[1]

auto[1]

91419

1

T3

139

T8

2291

T10

27

auto[0]

auto[1]

auto[0]

auto[0]

174706

1

T3

26

T5

8

T9

258

auto[0]

auto[1]

auto[0]

auto[1]

181786

1

T3

73

T6

618

T8

3541

auto[0]

auto[1]

auto[1]

auto[0]

188749

1

T4

2

T5

12

T8

3372

auto[0]

auto[1]

auto[1]

auto[1]

159678

1

T3

43

T5

13

T9

71

auto[1]

auto[0]

auto[0]

auto[0]

263110

1

T1

193

T5

1

T9

307

auto[1]

auto[0]

auto[0]

auto[1]

269837

1

T1

397

T3

943

T5

17

auto[1]

auto[0]

auto[1]

auto[0]

3725349

1

T1

9

T3

354

T5

17

auto[1]

auto[0]

auto[1]

auto[1]

287821

1

T3

3432

T5

19

T8

3254

auto[1]

auto[1]

auto[0]

auto[0]

702516

1

T3

291

T5

28

T6

893

auto[1]

auto[1]

auto[0]

auto[1]

704349

1

T3

910

T5

7

T6

898

auto[1]

auto[1]

auto[1]

auto[0]

675995

1

T3

80

T4

31

T5

2

auto[1]

auto[1]

auto[1]

auto[1]

707939

1

T1

509

T3

1048

T5

3

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

348388

1

T1

220

T5

1

T9

671

auto[0]

auto[0]

auto[0]

auto[1]

352719

1

T1

397

T3

999

T5

17

auto[0]

auto[0]

auto[1]

auto[0]

4598406

1

T1

9

T3

354

T5

17

auto[0]

auto[0]

auto[1]

auto[1]

377502

1

T3

3571

T5

19

T8

5545

auto[0]

auto[1]

auto[0]

auto[0]

875892

1

T3

317

T5

36

T6

893

auto[0]

auto[1]

auto[0]

auto[1]

883444

1

T3

983

T5

7

T6

1516

auto[0]

auto[1]

auto[1]

auto[0]

863613

1

T3

80

T4

33

T5

14

auto[0]

auto[1]

auto[1]

auto[1]

866435

1

T1

509

T3

1091

T5

16

auto[1]

auto[0]

auto[0]

auto[0]

2516

1

T8

90

T120

20

T41

1

auto[1]

auto[0]

auto[0]

auto[1]

1604

1

T8

5

T120

42

T42

264

auto[1]

auto[0]

auto[1]

auto[0]

1293

1

T8

152

T41

1

T42

51

auto[1]

auto[0]

auto[1]

auto[1]

1738

1

T42

68

T130

4

T43

1

auto[1]

auto[1]

auto[0]

auto[0]

1330

1

T8

210

T120

22

T42

158

auto[1]

auto[1]

auto[0]

auto[1]

2691

1

T8

58

T27

151

T120

10

auto[1]

auto[1]

auto[1]

auto[0]

1131

1

T8

300

T19

1

T42

33

auto[1]

auto[1]

auto[1]

auto[1]

1182

1

T42

391

T130

78

T131

8

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	263110	1			T1	193		T5	1		T9	307
fifo_depth[0]	auto[0]	auto[0]	auto[1]	269837	1			T1	397		T3	943		T5	17
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3725349	1			T1	9		T3	354		T5	17
fifo_depth[0]	auto[0]	auto[1]	auto[1]	287821	1			T3	3432		T5	19		T8	3254
fifo_depth[0]	auto[1]	auto[0]	auto[0]	702516	1			T3	291		T5	28		T6	893
fifo_depth[0]	auto[1]	auto[0]	auto[1]	704349	1			T3	910		T5	7		T6	898
fifo_depth[0]	auto[1]	auto[1]	auto[0]	675995	1			T3	80		T4	31		T5	2
fifo_depth[0]	auto[1]	auto[1]	auto[1]	707939	1			T1	509		T3	1048		T5	3
fifo_depth[1]	auto[0]	auto[0]	auto[0]	8565	1			T1	12		T9	46		T8	123
fifo_depth[1]	auto[0]	auto[0]	auto[1]	8190	1			T3	30		T8	230		T10	112
fifo_depth[1]	auto[0]	auto[1]	auto[0]	210477	1			T7	2519		T9	14		T8	140
fifo_depth[1]	auto[0]	auto[1]	auto[1]	9709	1			T3	77		T8	213		T10	14
fifo_depth[1]	auto[1]	auto[0]	auto[0]	18080	1			T3	20		T5	1		T9	33
fifo_depth[1]	auto[1]	auto[0]	auto[1]	19417	1			T3	35		T6	62		T8	252
fifo_depth[1]	auto[1]	auto[1]	auto[0]	20072	1			T4	2		T5	2		T8	179
fifo_depth[1]	auto[1]	auto[1]	auto[1]	18375	1			T3	12		T5	2		T9	9
fifo_depth[2]	auto[0]	auto[0]	auto[0]	7528	1			T1	9		T9	43		T8	133
fifo_depth[2]	auto[0]	auto[0]	auto[1]	7211	1			T3	17		T8	203		T10	100
fifo_depth[2]	auto[0]	auto[1]	auto[0]	160069	1			T7	2517		T9	11		T8	165
fifo_depth[2]	auto[0]	auto[1]	auto[1]	8771	1			T3	40		T8	241		T10	7
fifo_depth[2]	auto[1]	auto[0]	auto[0]	16296	1			T3	5		T5	1		T9	36
fifo_depth[2]	auto[1]	auto[0]	auto[1]	17728	1			T3	24		T6	53		T8	300
fifo_depth[2]	auto[1]	auto[1]	auto[0]	18813	1			T5	2		T8	184		T38	4
fifo_depth[2]	auto[1]	auto[1]	auto[1]	16650	1			T3	14		T5	2		T9	10
fifo_depth[3]	auto[0]	auto[0]	auto[0]	5708	1			T1	5		T9	46		T8	140
fifo_depth[3]	auto[0]	auto[0]	auto[1]	5612	1			T3	7		T8	220		T10	68
fifo_depth[3]	auto[0]	auto[1]	auto[0]	119320	1			T7	2202		T9	11		T8	165
fifo_depth[3]	auto[0]	auto[1]	auto[1]	6740	1			T3	15		T8	245		T10	3
fifo_depth[3]	auto[1]	auto[0]	auto[0]	14144	1			T3	1		T5	1		T9	28
fifo_depth[3]	auto[1]	auto[0]	auto[1]	15155	1			T3	11		T6	60		T8	255
fifo_depth[3]	auto[1]	auto[1]	auto[0]	16492	1			T5	2		T8	183		T38	3
fifo_depth[3]	auto[1]	auto[1]	auto[1]	14350	1			T3	13		T5	2		T9	10
fifo_depth[4]	auto[0]	auto[0]	auto[0]	5755	1			T1	1		T9	41		T8	185
fifo_depth[4]	auto[0]	auto[0]	auto[1]	5399	1			T3	1		T8	222		T10	27
fifo_depth[4]	auto[0]	auto[1]	auto[0]	87481	1			T7	1856		T9	15		T8	198
fifo_depth[4]	auto[0]	auto[1]	auto[1]	6729	1			T3	4		T8	234		T10	3
fifo_depth[4]	auto[1]	auto[0]	auto[0]	13479	1			T5	1		T9	23		T8	151
fifo_depth[4]	auto[1]	auto[0]	auto[1]	14232	1			T3	3		T6	49		T8	280
fifo_depth[4]	auto[1]	auto[1]	auto[0]	16206	1			T8	166		T38	3		T10	2
fifo_depth[4]	auto[1]	auto[1]	auto[1]	13461	1			T3	3		T9	9		T8	169
fifo_depth[5]	auto[0]	auto[0]	auto[0]	4568	1			T9	39		T8	163		T47	3
fifo_depth[5]	auto[0]	auto[0]	auto[1]	4337	1			T3	1		T8	242		T10	17
fifo_depth[5]	auto[0]	auto[1]	auto[0]	69885	1			T7	1711		T9	13		T8	168
fifo_depth[5]	auto[0]	auto[1]	auto[1]	5245	1			T3	2		T8	219		T46	2
fifo_depth[5]	auto[1]	auto[0]	auto[0]	12176	1			T9	30		T8	167		T10	1
fifo_depth[5]	auto[1]	auto[0]	auto[1]	13087	1			T6	50		T8	336		T10	8
fifo_depth[5]	auto[1]	auto[1]	auto[0]	14649	1			T8	178		T38	1		T10	3
fifo_depth[5]	auto[1]	auto[1]	auto[1]	12171	1			T3	1		T5	3		T9	7
fifo_depth[6]	auto[0]	auto[0]	auto[0]	4684	1			T9	30		T8	123		T47	1
fifo_depth[6]	auto[0]	auto[0]	auto[1]	4585	1			T8	218		T10	5		T46	35
fifo_depth[6]	auto[0]	auto[1]	auto[0]	59869	1			T7	1561		T9	19		T8	170
fifo_depth[6]	auto[0]	auto[1]	auto[1]	5524	1			T3	1		T8	210		T46	2
fifo_depth[6]	auto[1]	auto[0]	auto[0]	12262	1			T5	1		T9	28		T8	156
fifo_depth[6]	auto[1]	auto[0]	auto[1]	12956	1			T6	56		T8	249		T10	4
fifo_depth[6]	auto[1]	auto[1]	auto[0]	14490	1			T5	1		T8	167		T38	4
fifo_depth[6]	auto[1]	auto[1]	auto[1]	12041	1			T5	1		T9	11		T8	147
fifo_depth[7]	auto[0]	auto[0]	auto[0]	4328	1			T9	31		T8	136		T47	1
fifo_depth[7]	auto[0]	auto[0]	auto[1]	3979	1			T8	186		T46	18		T47	2
fifo_depth[7]	auto[0]	auto[1]	auto[0]	47197	1			T7	1304		T9	15		T8	176
fifo_depth[7]	auto[0]	auto[1]	auto[1]	4692	1			T8	150		T46	2		T24	2
fifo_depth[7]	auto[1]	auto[0]	auto[0]	11673	1			T5	1		T9	31		T8	158
fifo_depth[7]	auto[1]	auto[0]	auto[1]	12369	1			T6	61		T8	266		T23	95
fifo_depth[7]	auto[1]	auto[1]	auto[0]	13614	1			T5	1		T8	190		T38	5
fifo_depth[7]	auto[1]	auto[1]	auto[1]	11347	1			T5	1		T9	6		T8	115