Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	14487987	1			T1	1141		T3	7426		T4	91
all_pins[1]	14487987	1			T1	1141		T3	7426		T4	91
all_pins[2]	14487987	1			T1	1141		T3	7426		T4	91

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	36172600	1			T1	2507		T3	19702		T4	216
values[0x1]	7291361	1			T1	916		T3	2576		T4	57
transitions[0x0=>0x1]	7291211	1			T1	916		T3	2576		T4	57
transitions[0x1=>0x0]	7291221	1			T1	916		T3	2576		T4	57

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	14450132	1			T1	1139		T3	7411		T4	87
all_pins[0]	values[0x1]	37855	1			T1	2		T3	15		T4	4
all_pins[0]	transitions[0x0=>0x1]	37776	1			T1	2		T3	15		T4	4
all_pins[0]	transitions[0x1=>0x0]	7253196	1			T1	914		T3	2561		T4	53
all_pins[1]	values[0x0]	14487746	1			T1	1141		T3	7426		T4	91
all_pins[1]	values[0x1]	241	1			T8	1		T27	4		T120	5
all_pins[1]	transitions[0x0=>0x1]	202	1			T8	1		T27	3		T120	5
all_pins[1]	transitions[0x1=>0x0]	37816	1			T1	2		T3	15		T4	4
all_pins[2]	values[0x0]	7234722	1			T1	227		T3	4865		T4	38
all_pins[2]	values[0x1]	7253265	1			T1	914		T3	2561		T4	53
all_pins[2]	transitions[0x0=>0x1]	7253233	1			T1	914		T3	2561		T4	53
all_pins[2]	transitions[0x1=>0x0]	209	1			T8	1		T27	3		T120	5