Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 788 1 T17 8 T27 20 T42 17
all_values[1] 788 1 T17 8 T27 20 T42 17
all_values[2] 788 1 T17 8 T27 20 T42 17


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1279 1 T17 10 T27 30 T42 31
auto[1] 1085 1 T17 14 T27 30 T42 20


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 846 1 T17 16 T27 22 T42 16
auto[1] 1518 1 T17 8 T27 38 T42 35


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1336 1 T17 19 T27 32 T42 25
auto[1] 1028 1 T17 5 T27 28 T42 26


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 169 1 T17 5 T27 2 T42 3
all_values[0] auto[0] auto[0] auto[1] 78 1 T27 2 T42 1 T103 2
all_values[0] auto[0] auto[1] auto[0] 124 1 T17 1 T27 3 T42 2
all_values[0] auto[0] auto[1] auto[1] 82 1 T27 2 T42 3 T114 3
all_values[0] auto[1] auto[0] auto[1] 175 1 T27 8 T42 4 T103 1
all_values[0] auto[1] auto[1] auto[1] 160 1 T17 2 T27 3 T42 4
all_values[1] auto[0] auto[0] auto[0] 145 1 T17 2 T27 1 T42 5
all_values[1] auto[0] auto[0] auto[1] 93 1 T27 2 T42 3 T103 2
all_values[1] auto[0] auto[1] auto[0] 125 1 T17 6 T27 5 T42 1
all_values[1] auto[0] auto[1] auto[1] 90 1 T27 3 T42 1 T103 1
all_values[1] auto[1] auto[0] auto[1] 184 1 T27 6 T42 4 T103 3
all_values[1] auto[1] auto[1] auto[1] 151 1 T27 3 T42 3 T103 2
all_values[2] auto[0] auto[0] auto[0] 158 1 T27 5 T42 4 T103 2
all_values[2] auto[0] auto[0] auto[1] 75 1 T17 1 T27 1 T42 1
all_values[2] auto[0] auto[1] auto[0] 125 1 T17 2 T27 6 T42 1
all_values[2] auto[0] auto[1] auto[1] 72 1 T17 2 T103 1 T121 3
all_values[2] auto[1] auto[0] auto[1] 202 1 T17 2 T27 3 T42 6
all_values[2] auto[1] auto[1] auto[1] 156 1 T17 1 T27 5 T42 5


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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