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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.30 94.82 92.44 100.00 76.92 89.38 99.49 72.04


Total test records in report: 726
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T542 /workspace/coverage/default/11.hmac_error.1463064936 Jun 02 12:36:28 PM PDT 24 Jun 02 12:38:21 PM PDT 24 26367038437 ps
T543 /workspace/coverage/default/35.hmac_smoke.2780860666 Jun 02 12:37:26 PM PDT 24 Jun 02 12:37:28 PM PDT 24 58365316 ps
T117 /workspace/coverage/default/17.hmac_stress_all.2090736957 Jun 02 12:36:56 PM PDT 24 Jun 02 01:06:49 PM PDT 24 90879607938 ps
T544 /workspace/coverage/default/29.hmac_datapath_stress.1927570238 Jun 02 12:37:05 PM PDT 24 Jun 02 12:44:57 PM PDT 24 1930091611 ps
T72 /workspace/coverage/default/9.hmac_stress_all.1686328202 Jun 02 12:36:31 PM PDT 24 Jun 02 12:56:45 PM PDT 24 124587021209 ps
T545 /workspace/coverage/default/30.hmac_smoke.4115533387 Jun 02 12:36:46 PM PDT 24 Jun 02 12:36:47 PM PDT 24 11871659 ps
T546 /workspace/coverage/default/4.hmac_datapath_stress.3146886009 Jun 02 12:36:15 PM PDT 24 Jun 02 12:46:43 PM PDT 24 2567055402 ps
T547 /workspace/coverage/default/42.hmac_alert_test.3196809978 Jun 02 12:37:29 PM PDT 24 Jun 02 12:37:31 PM PDT 24 30433299 ps
T548 /workspace/coverage/default/41.hmac_error.3011748025 Jun 02 12:37:23 PM PDT 24 Jun 02 12:39:31 PM PDT 24 18592575869 ps
T549 /workspace/coverage/default/43.hmac_test_sha_vectors.2161801812 Jun 02 12:37:13 PM PDT 24 Jun 02 12:45:37 PM PDT 24 37142199808 ps
T550 /workspace/coverage/default/45.hmac_alert_test.2724376472 Jun 02 12:37:33 PM PDT 24 Jun 02 12:37:35 PM PDT 24 13268902 ps
T551 /workspace/coverage/default/33.hmac_long_msg.3942361671 Jun 02 12:37:00 PM PDT 24 Jun 02 12:38:52 PM PDT 24 23394316501 ps
T552 /workspace/coverage/default/6.hmac_test_sha_vectors.3532813962 Jun 02 12:36:36 PM PDT 24 Jun 02 12:45:37 PM PDT 24 41188970504 ps
T553 /workspace/coverage/default/39.hmac_long_msg.2644987723 Jun 02 12:38:22 PM PDT 24 Jun 02 12:39:18 PM PDT 24 15668324936 ps
T554 /workspace/coverage/default/34.hmac_wipe_secret.4277369025 Jun 02 12:37:05 PM PDT 24 Jun 02 12:38:28 PM PDT 24 3216075959 ps
T555 /workspace/coverage/default/9.hmac_test_sha_vectors.3239492530 Jun 02 12:36:21 PM PDT 24 Jun 02 12:42:49 PM PDT 24 28257601224 ps
T556 /workspace/coverage/default/22.hmac_wipe_secret.3021512992 Jun 02 12:37:09 PM PDT 24 Jun 02 12:37:50 PM PDT 24 4088780429 ps
T12 /workspace/coverage/default/80.hmac_stress_all_with_rand_reset.2424339288 Jun 02 12:37:26 PM PDT 24 Jun 02 12:53:40 PM PDT 24 37429942416 ps
T73 /workspace/coverage/default/16.hmac_stress_all.3432480827 Jun 02 12:36:26 PM PDT 24 Jun 02 01:21:59 PM PDT 24 119050039383 ps
T557 /workspace/coverage/default/46.hmac_stress_all.3526413450 Jun 02 12:37:15 PM PDT 24 Jun 02 01:55:43 PM PDT 24 131058878195 ps
T558 /workspace/coverage/default/49.hmac_test_sha_vectors.4242770911 Jun 02 12:37:15 PM PDT 24 Jun 02 12:46:06 PM PDT 24 255083309800 ps
T559 /workspace/coverage/default/18.hmac_back_pressure.2977939135 Jun 02 12:36:51 PM PDT 24 Jun 02 12:37:08 PM PDT 24 651079965 ps
T560 /workspace/coverage/default/34.hmac_test_sha_vectors.3937252568 Jun 02 12:37:08 PM PDT 24 Jun 02 12:44:59 PM PDT 24 129403824966 ps
T561 /workspace/coverage/default/16.hmac_alert_test.112491440 Jun 02 12:36:40 PM PDT 24 Jun 02 12:36:41 PM PDT 24 115337799 ps
T562 /workspace/coverage/default/30.hmac_wipe_secret.3721001963 Jun 02 12:37:19 PM PDT 24 Jun 02 12:37:39 PM PDT 24 1278967619 ps
T563 /workspace/coverage/default/24.hmac_test_hmac_vectors.1783473379 Jun 02 12:36:45 PM PDT 24 Jun 02 12:36:47 PM PDT 24 55994237 ps
T564 /workspace/coverage/default/2.hmac_test_hmac_vectors.1746489695 Jun 02 12:36:22 PM PDT 24 Jun 02 12:36:24 PM PDT 24 207015008 ps
T565 /workspace/coverage/default/36.hmac_back_pressure.284027425 Jun 02 12:36:51 PM PDT 24 Jun 02 12:37:56 PM PDT 24 4280434311 ps
T566 /workspace/coverage/default/29.hmac_stress_all.1778212252 Jun 02 12:36:56 PM PDT 24 Jun 02 01:11:30 PM PDT 24 29026658848 ps
T567 /workspace/coverage/default/21.hmac_test_hmac_vectors.1905683010 Jun 02 12:36:42 PM PDT 24 Jun 02 12:36:44 PM PDT 24 342795414 ps
T568 /workspace/coverage/default/7.hmac_stress_all.620019518 Jun 02 12:36:32 PM PDT 24 Jun 02 01:28:32 PM PDT 24 28601468592 ps
T569 /workspace/coverage/default/40.hmac_alert_test.680957891 Jun 02 12:37:13 PM PDT 24 Jun 02 12:37:14 PM PDT 24 53992858 ps
T570 /workspace/coverage/default/1.hmac_long_msg.876338662 Jun 02 12:23:35 PM PDT 24 Jun 02 12:23:52 PM PDT 24 1194620665 ps
T571 /workspace/coverage/default/38.hmac_wipe_secret.2838665376 Jun 02 12:38:23 PM PDT 24 Jun 02 12:38:55 PM PDT 24 1791262822 ps
T572 /workspace/coverage/default/49.hmac_long_msg.446731402 Jun 02 12:37:42 PM PDT 24 Jun 02 12:39:16 PM PDT 24 7345493527 ps
T573 /workspace/coverage/default/48.hmac_burst_wr.3562461472 Jun 02 12:37:20 PM PDT 24 Jun 02 12:38:00 PM PDT 24 2805287289 ps
T574 /workspace/coverage/default/10.hmac_stress_all.38616673 Jun 02 12:36:27 PM PDT 24 Jun 02 01:00:48 PM PDT 24 21411677097 ps
T575 /workspace/coverage/default/4.hmac_stress_all.551096812 Jun 02 12:36:10 PM PDT 24 Jun 02 12:51:06 PM PDT 24 22695101835 ps
T576 /workspace/coverage/default/2.hmac_smoke.1331152726 Jun 02 12:36:01 PM PDT 24 Jun 02 12:36:05 PM PDT 24 334153048 ps
T577 /workspace/coverage/default/22.hmac_smoke.2289544963 Jun 02 12:36:58 PM PDT 24 Jun 02 12:37:04 PM PDT 24 166195201 ps
T578 /workspace/coverage/default/44.hmac_error.2594033978 Jun 02 12:37:27 PM PDT 24 Jun 02 12:38:39 PM PDT 24 22472000041 ps
T579 /workspace/coverage/default/40.hmac_error.985413903 Jun 02 12:37:21 PM PDT 24 Jun 02 12:37:51 PM PDT 24 3986792946 ps
T580 /workspace/coverage/default/7.hmac_burst_wr.4029623270 Jun 02 12:36:35 PM PDT 24 Jun 02 12:36:54 PM PDT 24 3894481655 ps
T581 /workspace/coverage/default/24.hmac_stress_all.850303191 Jun 02 12:36:35 PM PDT 24 Jun 02 01:03:43 PM PDT 24 124158529703 ps
T582 /workspace/coverage/default/42.hmac_datapath_stress.1057500026 Jun 02 12:37:13 PM PDT 24 Jun 02 12:50:13 PM PDT 24 5960841991 ps
T583 /workspace/coverage/default/24.hmac_smoke.1519960114 Jun 02 12:36:55 PM PDT 24 Jun 02 12:36:57 PM PDT 24 124955962 ps
T584 /workspace/coverage/default/17.hmac_back_pressure.2344759484 Jun 02 12:36:44 PM PDT 24 Jun 02 12:37:24 PM PDT 24 821169998 ps
T585 /workspace/coverage/default/3.hmac_alert_test.33866676 Jun 02 12:36:11 PM PDT 24 Jun 02 12:36:12 PM PDT 24 40655277 ps
T586 /workspace/coverage/default/25.hmac_error.3665383942 Jun 02 12:36:55 PM PDT 24 Jun 02 12:38:39 PM PDT 24 6334127311 ps
T587 /workspace/coverage/default/21.hmac_alert_test.1579243208 Jun 02 12:36:42 PM PDT 24 Jun 02 12:36:43 PM PDT 24 108155817 ps
T588 /workspace/coverage/default/35.hmac_test_hmac_vectors.30729908 Jun 02 12:37:03 PM PDT 24 Jun 02 12:37:05 PM PDT 24 108890608 ps
T74 /workspace/coverage/default/27.hmac_stress_all.3981739712 Jun 02 12:36:52 PM PDT 24 Jun 02 01:12:08 PM PDT 24 266438832201 ps
T589 /workspace/coverage/default/31.hmac_test_sha_vectors.3574840171 Jun 02 12:37:05 PM PDT 24 Jun 02 12:44:33 PM PDT 24 23618808393 ps
T590 /workspace/coverage/default/26.hmac_test_hmac_vectors.165012005 Jun 02 12:36:55 PM PDT 24 Jun 02 12:36:57 PM PDT 24 152195053 ps
T591 /workspace/coverage/default/49.hmac_back_pressure.2855298545 Jun 02 12:37:30 PM PDT 24 Jun 02 12:37:59 PM PDT 24 1085904145 ps
T592 /workspace/coverage/default/0.hmac_back_pressure.1897528291 Jun 02 12:25:07 PM PDT 24 Jun 02 12:25:21 PM PDT 24 838341943 ps
T593 /workspace/coverage/default/31.hmac_datapath_stress.1337992516 Jun 02 12:37:02 PM PDT 24 Jun 02 12:48:11 PM PDT 24 5542539714 ps
T594 /workspace/coverage/default/30.hmac_stress_all.3284751820 Jun 02 12:37:10 PM PDT 24 Jun 02 01:14:44 PM PDT 24 12846801914 ps
T595 /workspace/coverage/default/25.hmac_back_pressure.4173265616 Jun 02 12:36:57 PM PDT 24 Jun 02 12:36:59 PM PDT 24 54604746 ps
T596 /workspace/coverage/default/3.hmac_datapath_stress.3378196107 Jun 02 12:36:04 PM PDT 24 Jun 02 12:49:08 PM PDT 24 2481922044 ps
T75 /workspace/coverage/default/41.hmac_stress_all.2006709119 Jun 02 12:37:08 PM PDT 24 Jun 02 12:59:58 PM PDT 24 160809782587 ps
T54 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.4187830133 Jun 02 01:09:03 PM PDT 24 Jun 02 01:09:04 PM PDT 24 37859256 ps
T597 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3543573545 Jun 02 01:09:54 PM PDT 24 Jun 02 01:09:55 PM PDT 24 13349859 ps
T55 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3617995241 Jun 02 01:09:27 PM PDT 24 Jun 02 01:09:29 PM PDT 24 17997022 ps
T76 /workspace/coverage/cover_reg_top/46.hmac_intr_test.475394765 Jun 02 01:09:52 PM PDT 24 Jun 02 01:09:53 PM PDT 24 52098901 ps
T598 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3773287515 Jun 02 01:09:47 PM PDT 24 Jun 02 01:09:48 PM PDT 24 46136532 ps
T56 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3044546763 Jun 02 01:09:22 PM PDT 24 Jun 02 01:09:23 PM PDT 24 17821945 ps
T50 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1951143274 Jun 02 01:09:08 PM PDT 24 Jun 02 01:09:11 PM PDT 24 297263872 ps
T77 /workspace/coverage/cover_reg_top/21.hmac_intr_test.330279075 Jun 02 01:09:45 PM PDT 24 Jun 02 01:09:46 PM PDT 24 93803133 ps
T599 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3695017372 Jun 02 01:09:10 PM PDT 24 Jun 02 01:09:11 PM PDT 24 52767179 ps
T59 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2926957708 Jun 02 01:09:45 PM PDT 24 Jun 02 01:09:48 PM PDT 24 323581433 ps
T60 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3649667651 Jun 02 01:08:49 PM PDT 24 Jun 02 01:08:54 PM PDT 24 1425513181 ps
T86 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3726398168 Jun 02 01:08:32 PM PDT 24 Jun 02 01:08:35 PM PDT 24 49020525 ps
T600 /workspace/coverage/cover_reg_top/20.hmac_intr_test.3827036606 Jun 02 01:09:44 PM PDT 24 Jun 02 01:09:45 PM PDT 24 34502180 ps
T51 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1728960592 Jun 02 01:09:28 PM PDT 24 Jun 02 01:09:32 PM PDT 24 700389445 ps
T601 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1562129606 Jun 02 01:09:38 PM PDT 24 Jun 02 01:09:40 PM PDT 24 196364584 ps
T602 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3456814272 Jun 02 01:09:14 PM PDT 24 Jun 02 01:09:18 PM PDT 24 219770985 ps
T603 /workspace/coverage/cover_reg_top/38.hmac_intr_test.3310329955 Jun 02 01:09:55 PM PDT 24 Jun 02 01:09:56 PM PDT 24 20735862 ps
T604 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2178185400 Jun 02 01:09:15 PM PDT 24 Jun 02 01:09:16 PM PDT 24 115635840 ps
T605 /workspace/coverage/cover_reg_top/3.hmac_intr_test.3313736847 Jun 02 01:08:49 PM PDT 24 Jun 02 01:08:50 PM PDT 24 43706965 ps
T606 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.703714723 Jun 02 01:08:40 PM PDT 24 Jun 02 01:08:42 PM PDT 24 136747256 ps
T98 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2582597518 Jun 02 01:08:48 PM PDT 24 Jun 02 01:08:54 PM PDT 24 113043200 ps
T607 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2950969812 Jun 02 01:08:47 PM PDT 24 Jun 02 01:08:49 PM PDT 24 24221871 ps
T608 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3181585942 Jun 02 01:09:11 PM PDT 24 Jun 02 01:09:13 PM PDT 24 110555568 ps
T89 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.518981164 Jun 02 01:09:09 PM PDT 24 Jun 02 01:09:10 PM PDT 24 47136532 ps
T52 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2182676399 Jun 02 01:09:45 PM PDT 24 Jun 02 01:09:49 PM PDT 24 1060614467 ps
T609 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1880769623 Jun 02 01:09:47 PM PDT 24 Jun 02 01:09:48 PM PDT 24 52900134 ps
T122 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2417025895 Jun 02 01:09:09 PM PDT 24 Jun 02 01:09:14 PM PDT 24 229694415 ps
T610 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.4124016061 Jun 02 01:09:04 PM PDT 24 Jun 02 01:09:06 PM PDT 24 500345267 ps
T611 /workspace/coverage/cover_reg_top/6.hmac_intr_test.708070651 Jun 02 01:09:09 PM PDT 24 Jun 02 01:09:10 PM PDT 24 19105213 ps
T612 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2369676601 Jun 02 01:08:55 PM PDT 24 Jun 02 01:08:58 PM PDT 24 193728971 ps
T90 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.378503972 Jun 02 01:09:46 PM PDT 24 Jun 02 01:09:47 PM PDT 24 63455080 ps
T613 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2651011012 Jun 02 01:08:48 PM PDT 24 Jun 02 01:08:51 PM PDT 24 39030295 ps
T614 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1800152497 Jun 02 01:09:15 PM PDT 24 Jun 02 01:09:16 PM PDT 24 169116170 ps
T615 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2910669732 Jun 02 01:09:52 PM PDT 24 Jun 02 01:09:53 PM PDT 24 14067733 ps
T123 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.4135507871 Jun 02 01:09:08 PM PDT 24 Jun 02 01:09:13 PM PDT 24 1109326917 ps
T128 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2835230684 Jun 02 01:09:29 PM PDT 24 Jun 02 01:09:33 PM PDT 24 125473820 ps
T616 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.727458295 Jun 02 01:08:48 PM PDT 24 Jun 02 01:08:52 PM PDT 24 170615044 ps
T617 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1145736861 Jun 02 01:09:29 PM PDT 24 Jun 02 01:09:30 PM PDT 24 100379982 ps
T91 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.187974898 Jun 02 01:09:38 PM PDT 24 Jun 02 01:09:39 PM PDT 24 50747870 ps
T618 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.792563737 Jun 02 01:09:23 PM PDT 24 Jun 02 01:09:26 PM PDT 24 173578787 ps
T619 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3421053891 Jun 02 01:09:07 PM PDT 24 Jun 02 01:09:12 PM PDT 24 186733755 ps
T620 /workspace/coverage/cover_reg_top/9.hmac_intr_test.1819887899 Jun 02 01:09:15 PM PDT 24 Jun 02 01:09:16 PM PDT 24 13036916 ps
T621 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1194436118 Jun 02 01:08:48 PM PDT 24 Jun 02 01:08:49 PM PDT 24 27891831 ps
T622 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.708951972 Jun 02 01:09:31 PM PDT 24 Jun 02 01:09:32 PM PDT 24 38799142 ps
T92 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.105001757 Jun 02 01:08:53 PM PDT 24 Jun 02 01:08:55 PM PDT 24 51241515 ps
T623 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1882279173 Jun 02 01:08:48 PM PDT 24 Jun 02 01:08:49 PM PDT 24 20887220 ps
T624 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3479046406 Jun 02 01:09:38 PM PDT 24 Jun 02 01:09:39 PM PDT 24 29990518 ps
T625 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3603524872 Jun 02 01:09:51 PM PDT 24 Jun 02 01:09:52 PM PDT 24 16991093 ps
T626 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3792036794 Jun 02 01:08:49 PM PDT 24 Jun 02 01:08:51 PM PDT 24 22186464 ps
T124 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3230073420 Jun 02 01:09:03 PM PDT 24 Jun 02 01:09:05 PM PDT 24 885814542 ps
T93 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3407252556 Jun 02 01:08:49 PM PDT 24 Jun 02 01:09:06 PM PDT 24 5437219605 ps
T627 /workspace/coverage/cover_reg_top/30.hmac_intr_test.2856562802 Jun 02 01:09:57 PM PDT 24 Jun 02 01:09:58 PM PDT 24 17561563 ps
T94 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3778968611 Jun 02 01:09:28 PM PDT 24 Jun 02 01:09:30 PM PDT 24 15858826 ps
T628 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3517148299 Jun 02 01:09:47 PM PDT 24 Jun 02 01:09:50 PM PDT 24 46873556 ps
T95 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1977886748 Jun 02 01:09:38 PM PDT 24 Jun 02 01:09:39 PM PDT 24 28166447 ps
T629 /workspace/coverage/cover_reg_top/35.hmac_intr_test.3967624870 Jun 02 01:09:53 PM PDT 24 Jun 02 01:09:54 PM PDT 24 14285070 ps
T58 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2576470695 Jun 02 01:08:48 PM PDT 24 Jun 02 01:08:50 PM PDT 24 91426295 ps
T96 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3273931660 Jun 02 01:09:49 PM PDT 24 Jun 02 01:09:51 PM PDT 24 40627694 ps
T630 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1484581077 Jun 02 01:09:02 PM PDT 24 Jun 02 01:09:05 PM PDT 24 192527095 ps
T631 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.866793891 Jun 02 01:09:09 PM PDT 24 Jun 02 01:09:13 PM PDT 24 408895434 ps
T632 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1886070807 Jun 02 01:09:29 PM PDT 24 Jun 02 01:09:32 PM PDT 24 369044724 ps
T633 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3462558406 Jun 02 01:09:28 PM PDT 24 Jun 02 01:09:31 PM PDT 24 187250944 ps
T634 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.124020896 Jun 02 01:09:37 PM PDT 24 Jun 02 01:09:40 PM PDT 24 88714968 ps
T635 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3339425824 Jun 02 01:09:15 PM PDT 24 Jun 02 01:09:16 PM PDT 24 20835497 ps
T636 /workspace/coverage/cover_reg_top/10.hmac_intr_test.3616485495 Jun 02 01:09:15 PM PDT 24 Jun 02 01:09:16 PM PDT 24 44330169 ps
T97 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2520958867 Jun 02 01:09:29 PM PDT 24 Jun 02 01:09:30 PM PDT 24 18055838 ps
T637 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2069096771 Jun 02 01:09:29 PM PDT 24 Jun 02 01:09:32 PM PDT 24 86204641 ps
T638 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3287808620 Jun 02 01:09:56 PM PDT 24 Jun 02 01:09:57 PM PDT 24 42432052 ps
T639 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2808682319 Jun 02 01:09:51 PM PDT 24 Jun 02 01:09:52 PM PDT 24 54679853 ps
T640 /workspace/coverage/cover_reg_top/49.hmac_intr_test.237779088 Jun 02 01:09:56 PM PDT 24 Jun 02 01:09:57 PM PDT 24 64599091 ps
T641 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3559196734 Jun 02 01:09:15 PM PDT 24 Jun 02 01:09:18 PM PDT 24 47973751 ps
T642 /workspace/coverage/cover_reg_top/44.hmac_intr_test.1217353085 Jun 02 01:09:53 PM PDT 24 Jun 02 01:09:54 PM PDT 24 55017164 ps
T643 /workspace/coverage/cover_reg_top/40.hmac_intr_test.2905474488 Jun 02 01:09:53 PM PDT 24 Jun 02 01:09:54 PM PDT 24 86471978 ps
T644 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2703286703 Jun 02 01:09:51 PM PDT 24 Jun 02 01:16:25 PM PDT 24 96552525397 ps
T645 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3512101425 Jun 02 01:08:55 PM PDT 24 Jun 02 01:08:58 PM PDT 24 106252671 ps
T125 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.943123235 Jun 02 01:08:55 PM PDT 24 Jun 02 01:09:00 PM PDT 24 328957867 ps
T646 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3025998618 Jun 02 01:09:27 PM PDT 24 Jun 02 01:09:32 PM PDT 24 84255830 ps
T647 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2643797472 Jun 02 01:09:29 PM PDT 24 Jun 02 01:09:30 PM PDT 24 22566977 ps
T99 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.186125447 Jun 02 01:08:48 PM PDT 24 Jun 02 01:08:57 PM PDT 24 158555150 ps
T648 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2618493201 Jun 02 01:08:33 PM PDT 24 Jun 02 01:08:37 PM PDT 24 249298821 ps
T127 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.493304761 Jun 02 01:09:29 PM PDT 24 Jun 02 01:09:33 PM PDT 24 234012112 ps
T649 /workspace/coverage/cover_reg_top/29.hmac_intr_test.1354790365 Jun 02 01:09:53 PM PDT 24 Jun 02 01:09:54 PM PDT 24 46490685 ps
T101 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.4054457591 Jun 02 01:08:41 PM PDT 24 Jun 02 01:08:42 PM PDT 24 19546822 ps
T650 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3572965134 Jun 02 01:08:55 PM PDT 24 Jun 02 01:08:57 PM PDT 24 140212973 ps
T651 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.584402732 Jun 02 01:09:28 PM PDT 24 Jun 02 01:09:31 PM PDT 24 65552430 ps
T652 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1013755643 Jun 02 01:09:37 PM PDT 24 Jun 02 01:09:40 PM PDT 24 590034239 ps
T653 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3695370086 Jun 02 01:09:39 PM PDT 24 Jun 02 01:09:41 PM PDT 24 108652984 ps
T654 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3105775518 Jun 02 01:09:02 PM PDT 24 Jun 02 01:09:03 PM PDT 24 13002411 ps
T655 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2036452652 Jun 02 01:08:53 PM PDT 24 Jun 02 01:08:59 PM PDT 24 416085275 ps
T656 /workspace/coverage/cover_reg_top/14.hmac_intr_test.2284080156 Jun 02 01:09:30 PM PDT 24 Jun 02 01:09:30 PM PDT 24 13386781 ps
T657 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2490245249 Jun 02 01:09:29 PM PDT 24 Jun 02 01:09:31 PM PDT 24 158492503 ps
T658 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.199833168 Jun 02 01:09:29 PM PDT 24 Jun 02 01:09:32 PM PDT 24 351216546 ps
T659 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3999217034 Jun 02 01:09:21 PM PDT 24 Jun 02 01:09:24 PM PDT 24 164622518 ps
T660 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.224752702 Jun 02 01:09:15 PM PDT 24 Jun 02 01:09:18 PM PDT 24 46055274 ps
T661 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1813845200 Jun 02 01:09:28 PM PDT 24 Jun 02 01:09:32 PM PDT 24 80645183 ps
T662 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1947958520 Jun 02 01:09:57 PM PDT 24 Jun 02 01:09:57 PM PDT 24 20995806 ps
T663 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2170318024 Jun 02 01:09:10 PM PDT 24 Jun 02 01:09:15 PM PDT 24 814830993 ps
T664 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2038210397 Jun 02 01:09:02 PM PDT 24 Jun 02 01:09:04 PM PDT 24 81252604 ps
T100 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2347196790 Jun 02 01:08:49 PM PDT 24 Jun 02 01:09:06 PM PDT 24 13644310834 ps
T665 /workspace/coverage/cover_reg_top/47.hmac_intr_test.4045285605 Jun 02 01:09:55 PM PDT 24 Jun 02 01:09:56 PM PDT 24 43939786 ps
T666 /workspace/coverage/cover_reg_top/41.hmac_intr_test.3541027304 Jun 02 01:09:53 PM PDT 24 Jun 02 01:09:54 PM PDT 24 53664216 ps
T667 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1549881666 Jun 02 01:09:30 PM PDT 24 Jun 02 01:09:31 PM PDT 24 179420527 ps
T668 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3000335231 Jun 02 01:08:48 PM PDT 24 Jun 02 01:08:57 PM PDT 24 764110343 ps
T669 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3876575607 Jun 02 01:08:50 PM PDT 24 Jun 02 01:08:52 PM PDT 24 174708552 ps
T670 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1278516884 Jun 02 01:09:27 PM PDT 24 Jun 02 01:09:28 PM PDT 24 14361944 ps
T129 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.4119477100 Jun 02 01:09:36 PM PDT 24 Jun 02 01:09:41 PM PDT 24 169070180 ps
T671 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2518892940 Jun 02 01:09:01 PM PDT 24 Jun 02 01:09:02 PM PDT 24 17680777 ps
T672 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2935328175 Jun 02 01:08:50 PM PDT 24 Jun 02 01:08:54 PM PDT 24 115882220 ps
T673 /workspace/coverage/cover_reg_top/24.hmac_intr_test.2457597333 Jun 02 01:09:46 PM PDT 24 Jun 02 01:09:47 PM PDT 24 20162796 ps
T674 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.165536342 Jun 02 01:08:50 PM PDT 24 Jun 02 01:08:51 PM PDT 24 41184964 ps
T675 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.907053185 Jun 02 01:09:27 PM PDT 24 Jun 02 01:09:30 PM PDT 24 105777719 ps
T676 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2170728854 Jun 02 01:09:52 PM PDT 24 Jun 02 01:09:53 PM PDT 24 88742025 ps
T677 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1316126320 Jun 02 01:08:47 PM PDT 24 Jun 02 01:08:48 PM PDT 24 95735425 ps
T678 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.4192570316 Jun 02 01:09:46 PM PDT 24 Jun 02 01:09:50 PM PDT 24 181638470 ps
T679 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2984742948 Jun 02 01:09:45 PM PDT 24 Jun 02 01:09:48 PM PDT 24 184737750 ps
T680 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3585400418 Jun 02 01:08:49 PM PDT 24 Jun 02 01:08:54 PM PDT 24 430269275 ps
T681 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.4278271431 Jun 02 01:08:49 PM PDT 24 Jun 02 01:08:50 PM PDT 24 19748154 ps
T682 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.756265445 Jun 02 01:09:09 PM PDT 24 Jun 02 01:09:10 PM PDT 24 40591577 ps
T683 /workspace/coverage/cover_reg_top/11.hmac_intr_test.76407201 Jun 02 01:09:22 PM PDT 24 Jun 02 01:09:23 PM PDT 24 18205849 ps
T684 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3710556305 Jun 02 01:09:37 PM PDT 24 Jun 02 01:09:40 PM PDT 24 148344383 ps
T57 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1019497738 Jun 02 01:08:48 PM PDT 24 Jun 02 01:08:52 PM PDT 24 302980813 ps
T53 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3710362960 Jun 02 01:09:09 PM PDT 24 Jun 02 01:09:11 PM PDT 24 53524304 ps
T685 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1622312261 Jun 02 01:09:46 PM PDT 24 Jun 02 01:09:50 PM PDT 24 61125708 ps
T686 /workspace/coverage/cover_reg_top/26.hmac_intr_test.2705424327 Jun 02 01:09:54 PM PDT 24 Jun 02 01:09:55 PM PDT 24 36106562 ps
T687 /workspace/coverage/cover_reg_top/23.hmac_intr_test.1300665580 Jun 02 01:09:50 PM PDT 24 Jun 02 01:09:51 PM PDT 24 41836378 ps
T688 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1069333238 Jun 02 01:08:58 PM PDT 24 Jun 02 01:08:59 PM PDT 24 27248752 ps
T689 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3552987764 Jun 02 01:08:50 PM PDT 24 Jun 02 01:08:52 PM PDT 24 28546132 ps
T690 /workspace/coverage/cover_reg_top/7.hmac_intr_test.4271427912 Jun 02 01:09:11 PM PDT 24 Jun 02 01:09:12 PM PDT 24 113381511 ps
T691 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1432203672 Jun 02 01:09:09 PM PDT 24 Jun 02 01:09:10 PM PDT 24 19366873 ps
T692 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1738774961 Jun 02 01:09:08 PM PDT 24 Jun 02 01:09:11 PM PDT 24 243696337 ps
T693 /workspace/coverage/cover_reg_top/19.hmac_intr_test.3015829182 Jun 02 01:09:44 PM PDT 24 Jun 02 01:09:45 PM PDT 24 33022627 ps
T694 /workspace/coverage/cover_reg_top/4.hmac_intr_test.1658481511 Jun 02 01:08:54 PM PDT 24 Jun 02 01:08:55 PM PDT 24 40129957 ps
T695 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1850810367 Jun 02 01:09:47 PM PDT 24 Jun 02 01:09:49 PM PDT 24 79795015 ps
T696 /workspace/coverage/cover_reg_top/2.hmac_intr_test.3813658550 Jun 02 01:08:48 PM PDT 24 Jun 02 01:08:49 PM PDT 24 11993079 ps
T697 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1830137930 Jun 02 01:09:22 PM PDT 24 Jun 02 01:09:24 PM PDT 24 78598938 ps
T698 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.917591773 Jun 02 01:09:37 PM PDT 24 Jun 02 01:09:40 PM PDT 24 173615432 ps
T699 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2504506609 Jun 02 01:08:49 PM PDT 24 Jun 02 01:08:51 PM PDT 24 208460358 ps
T126 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2039108612 Jun 02 01:09:14 PM PDT 24 Jun 02 01:09:19 PM PDT 24 234777996 ps
T700 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1513999624 Jun 02 01:08:50 PM PDT 24 Jun 02 01:08:52 PM PDT 24 1825489868 ps
T701 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2279540367 Jun 02 01:09:09 PM PDT 24 Jun 02 01:09:11 PM PDT 24 90810731 ps
T702 /workspace/coverage/cover_reg_top/0.hmac_intr_test.3680107326 Jun 02 01:08:31 PM PDT 24 Jun 02 01:08:32 PM PDT 24 55460188 ps
T703 /workspace/coverage/cover_reg_top/31.hmac_intr_test.1450382751 Jun 02 01:09:55 PM PDT 24 Jun 02 01:09:56 PM PDT 24 11836048 ps
T704 /workspace/coverage/cover_reg_top/22.hmac_intr_test.2981940024 Jun 02 01:09:46 PM PDT 24 Jun 02 01:09:47 PM PDT 24 12135546 ps
T705 /workspace/coverage/cover_reg_top/17.hmac_intr_test.1778841253 Jun 02 01:09:38 PM PDT 24 Jun 02 01:09:38 PM PDT 24 15315049 ps
T706 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1456765299 Jun 02 01:09:55 PM PDT 24 Jun 02 01:09:56 PM PDT 24 16879804 ps
T707 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3043771130 Jun 02 01:09:09 PM PDT 24 Jun 02 01:09:12 PM PDT 24 176687710 ps
T708 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3119442575 Jun 02 01:08:56 PM PDT 24 Jun 02 01:08:57 PM PDT 24 25333499 ps
T709 /workspace/coverage/cover_reg_top/1.hmac_intr_test.868033058 Jun 02 01:08:48 PM PDT 24 Jun 02 01:08:49 PM PDT 24 15642177 ps
T710 /workspace/coverage/cover_reg_top/45.hmac_intr_test.3347145252 Jun 02 01:09:53 PM PDT 24 Jun 02 01:09:54 PM PDT 24 21288066 ps
T711 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1425138191 Jun 02 01:09:10 PM PDT 24 Jun 02 01:09:12 PM PDT 24 93297203 ps
T712 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.622614556 Jun 02 01:09:39 PM PDT 24 Jun 02 01:09:42 PM PDT 24 93122517 ps
T713 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1628108857 Jun 02 01:09:38 PM PDT 24 Jun 02 01:09:40 PM PDT 24 304393020 ps
T714 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2347851108 Jun 02 01:09:54 PM PDT 24 Jun 02 01:09:55 PM PDT 24 26429319 ps
T715 /workspace/coverage/cover_reg_top/13.hmac_intr_test.219797263 Jun 02 01:09:27 PM PDT 24 Jun 02 01:09:28 PM PDT 24 14366169 ps
T716 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3327722894 Jun 02 01:09:52 PM PDT 24 Jun 02 01:09:53 PM PDT 24 18011947 ps
T717 /workspace/coverage/cover_reg_top/8.hmac_intr_test.2840885871 Jun 02 01:09:10 PM PDT 24 Jun 02 01:09:11 PM PDT 24 31346507 ps
T718 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3758107068 Jun 02 01:08:56 PM PDT 24 Jun 02 01:09:07 PM PDT 24 758972021 ps
T719 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.67587284 Jun 02 01:09:28 PM PDT 24 Jun 02 01:09:34 PM PDT 24 857090395 ps
T720 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3751798338 Jun 02 01:09:10 PM PDT 24 Jun 02 01:09:13 PM PDT 24 159047618 ps
T721 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.4111969067 Jun 02 01:08:48 PM PDT 24 Jun 02 01:08:51 PM PDT 24 170687277 ps
T722 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3813632361 Jun 02 01:08:49 PM PDT 24 Jun 02 01:08:51 PM PDT 24 398047424 ps
T723 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3208951440 Jun 02 01:09:07 PM PDT 24 Jun 02 01:09:09 PM PDT 24 121500338 ps
T724 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1803021254 Jun 02 01:09:30 PM PDT 24 Jun 02 01:09:32 PM PDT 24 84676830 ps
T725 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2801714998 Jun 02 01:09:28 PM PDT 24 Jun 02 01:09:29 PM PDT 24 39553984 ps
T726 /workspace/coverage/cover_reg_top/48.hmac_intr_test.2006336844 Jun 02 01:09:54 PM PDT 24 Jun 02 01:09:55 PM PDT 24 44233974 ps

Test location /workspace/coverage/default/7.hmac_long_msg.87914971
Short name T3
Test name
Test status
Simulation time 3477483987 ps
CPU time 55.01 seconds
Started Jun 02 12:36:39 PM PDT 24
Finished Jun 02 12:37:34 PM PDT 24
Peak memory 200016 kb
Host smart-7bbab055-b230-40a3-8185-8060b4c5cb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87914971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.87914971
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/80.hmac_stress_all_with_rand_reset.2424339288
Short name T12
Test name
Test status
Simulation time 37429942416 ps
CPU time 973.25 seconds
Started Jun 02 12:37:26 PM PDT 24
Finished Jun 02 12:53:40 PM PDT 24
Peak memory 444592 kb
Host smart-58ea6e38-0dcb-45a4-9387-ff726fbc901b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2424339288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.hmac_stress_all_with_rand_reset.2424339288
Directory /workspace/80.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_stress_all.70397764
Short name T8
Test name
Test status
Simulation time 50088187642 ps
CPU time 887.37 seconds
Started Jun 02 12:36:09 PM PDT 24
Finished Jun 02 12:50:57 PM PDT 24
Peak memory 522556 kb
Host smart-2e406e3b-d81d-4b0b-96f2-9fd82b733b84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70397764 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.70397764
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.754299702
Short name T25
Test name
Test status
Simulation time 123663226 ps
CPU time 0.9 seconds
Started Jun 02 12:36:22 PM PDT 24
Finished Jun 02 12:36:23 PM PDT 24
Peak memory 218300 kb
Host smart-1783f85b-e13b-46d4-9fbf-8b8e857bb8dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754299702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.754299702
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/28.hmac_stress_all.1310410564
Short name T42
Test name
Test status
Simulation time 109865264783 ps
CPU time 2869.28 seconds
Started Jun 02 12:36:35 PM PDT 24
Finished Jun 02 01:24:25 PM PDT 24
Peak memory 808904 kb
Host smart-c5c48345-dafe-47b8-a031-a6a760ef3c7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310410564 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.1310410564
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1951143274
Short name T50
Test name
Test status
Simulation time 297263872 ps
CPU time 2.94 seconds
Started Jun 02 01:09:08 PM PDT 24
Finished Jun 02 01:09:11 PM PDT 24
Peak memory 199316 kb
Host smart-9105d513-e8b9-4d79-9d96-9f74ec62f18c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951143274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1951143274
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/63.hmac_stress_all_with_rand_reset.2201034803
Short name T13
Test name
Test status
Simulation time 55088283634 ps
CPU time 1142.5 seconds
Started Jun 02 12:37:38 PM PDT 24
Finished Jun 02 12:56:41 PM PDT 24
Peak memory 264908 kb
Host smart-dc95273d-be19-4a2b-a168-3e3f319452af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2201034803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.hmac_stress_all_with_rand_reset.2201034803
Directory /workspace/63.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.hmac_stress_all_with_rand_reset.2651602246
Short name T14
Test name
Test status
Simulation time 56870355745 ps
CPU time 2199.16 seconds
Started Jun 02 12:37:48 PM PDT 24
Finished Jun 02 01:14:28 PM PDT 24
Peak memory 834548 kb
Host smart-d25f11b1-e4c4-4f95-996b-96939ae3feb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2651602246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.hmac_stress_all_with_rand_reset.2651602246
Directory /workspace/87.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3044546763
Short name T56
Test name
Test status
Simulation time 17821945 ps
CPU time 0.71 seconds
Started Jun 02 01:09:22 PM PDT 24
Finished Jun 02 01:09:23 PM PDT 24
Peak memory 196768 kb
Host smart-d4e8ab5d-0967-4a4d-8449-66a93a5ac7fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044546763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3044546763
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2933594299
Short name T105
Test name
Test status
Simulation time 10424238803 ps
CPU time 1043.85 seconds
Started Jun 02 12:36:46 PM PDT 24
Finished Jun 02 12:54:11 PM PDT 24
Peak memory 717748 kb
Host smart-b77610e4-c9d6-4aef-87cc-0064cdc3a4a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2933594299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2933594299
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2811082786
Short name T2
Test name
Test status
Simulation time 14387248 ps
CPU time 0.57 seconds
Started Jun 02 12:36:29 PM PDT 24
Finished Jun 02 12:36:30 PM PDT 24
Peak memory 195408 kb
Host smart-c38fd01d-a813-408b-85ba-49f975dfec7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811082786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2811082786
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2417025895
Short name T122
Test name
Test status
Simulation time 229694415 ps
CPU time 4.34 seconds
Started Jun 02 01:09:09 PM PDT 24
Finished Jun 02 01:09:14 PM PDT 24
Peak memory 199368 kb
Host smart-95812bf6-76e5-4aea-9cb2-3c38541c26cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417025895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.2417025895
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1575474914
Short name T110
Test name
Test status
Simulation time 21939029382 ps
CPU time 60.68 seconds
Started Jun 02 12:36:34 PM PDT 24
Finished Jun 02 12:37:35 PM PDT 24
Peak memory 199948 kb
Host smart-fa98a1ab-eb77-4105-99db-883681de137e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575474914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1575474914
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2876317834
Short name T108
Test name
Test status
Simulation time 2176588076 ps
CPU time 56.61 seconds
Started Jun 02 12:36:14 PM PDT 24
Finished Jun 02 12:37:11 PM PDT 24
Peak memory 199220 kb
Host smart-a1b517eb-bcd6-4afe-9463-682823b29d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876317834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2876317834
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_stress_all.3531612888
Short name T116
Test name
Test status
Simulation time 142322467112 ps
CPU time 4630.85 seconds
Started Jun 02 12:37:01 PM PDT 24
Finished Jun 02 01:54:12 PM PDT 24
Peak memory 856412 kb
Host smart-97d8db87-56c4-4f1e-9997-89bd1093fd03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531612888 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.3531612888
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.4201485779
Short name T112
Test name
Test status
Simulation time 3182682858 ps
CPU time 46.33 seconds
Started Jun 02 12:37:10 PM PDT 24
Finished Jun 02 12:37:57 PM PDT 24
Peak memory 199964 kb
Host smart-82e40897-a520-493e-a547-bda474f3e38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201485779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.4201485779
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2039108612
Short name T126
Test name
Test status
Simulation time 234777996 ps
CPU time 4.44 seconds
Started Jun 02 01:09:14 PM PDT 24
Finished Jun 02 01:09:19 PM PDT 24
Peak memory 199344 kb
Host smart-9b1ed224-86ca-4c60-86fb-1b72862fb6d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039108612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2039108612
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1728960592
Short name T51
Test name
Test status
Simulation time 700389445 ps
CPU time 3.28 seconds
Started Jun 02 01:09:28 PM PDT 24
Finished Jun 02 01:09:32 PM PDT 24
Peak memory 199332 kb
Host smart-9dbbac73-3bd3-4330-b52a-f98afdbd801e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728960592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1728960592
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2090736957
Short name T117
Test name
Test status
Simulation time 90879607938 ps
CPU time 1791.11 seconds
Started Jun 02 12:36:56 PM PDT 24
Finished Jun 02 01:06:49 PM PDT 24
Peak memory 797828 kb
Host smart-89a14a0e-b463-463b-8ec3-be832e6b2b3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090736957 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2090736957
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2576470695
Short name T58
Test name
Test status
Simulation time 91426295 ps
CPU time 1.65 seconds
Started Jun 02 01:08:48 PM PDT 24
Finished Jun 02 01:08:50 PM PDT 24
Peak memory 199272 kb
Host smart-e446a3f8-2a01-4435-b4d2-9b425bd9f000
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576470695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2576470695
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1019497738
Short name T57
Test name
Test status
Simulation time 302980813 ps
CPU time 3.15 seconds
Started Jun 02 01:08:48 PM PDT 24
Finished Jun 02 01:08:52 PM PDT 24
Peak memory 199300 kb
Host smart-c2afab89-b98a-4576-b15a-ab87a04df456
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019497738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.1019497738
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3710362960
Short name T53
Test name
Test status
Simulation time 53524304 ps
CPU time 1.67 seconds
Started Jun 02 01:09:09 PM PDT 24
Finished Jun 02 01:09:11 PM PDT 24
Peak memory 199356 kb
Host smart-9f63922a-ceab-44ab-bad3-5639402e7698
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710362960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3710362960
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.727458295
Short name T616
Test name
Test status
Simulation time 170615044 ps
CPU time 2.96 seconds
Started Jun 02 01:08:48 PM PDT 24
Finished Jun 02 01:08:52 PM PDT 24
Peak memory 198020 kb
Host smart-1046b47f-592d-44db-8227-46864fd1be03
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727458295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.727458295
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3407252556
Short name T93
Test name
Test status
Simulation time 5437219605 ps
CPU time 16.4 seconds
Started Jun 02 01:08:49 PM PDT 24
Finished Jun 02 01:09:06 PM PDT 24
Peak memory 199252 kb
Host smart-6f5b1849-536a-409e-b77f-16f1b622663d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407252556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3407252556
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.703714723
Short name T606
Test name
Test status
Simulation time 136747256 ps
CPU time 1.07 seconds
Started Jun 02 01:08:40 PM PDT 24
Finished Jun 02 01:08:42 PM PDT 24
Peak memory 199076 kb
Host smart-51457ab4-23a5-4ffa-b316-89f0d499a0e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703714723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.703714723
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2950969812
Short name T607
Test name
Test status
Simulation time 24221871 ps
CPU time 1.41 seconds
Started Jun 02 01:08:47 PM PDT 24
Finished Jun 02 01:08:49 PM PDT 24
Peak memory 199392 kb
Host smart-7d0a486c-40c0-41c6-8f31-0b7b677bb37b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950969812 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2950969812
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.4054457591
Short name T101
Test name
Test status
Simulation time 19546822 ps
CPU time 0.74 seconds
Started Jun 02 01:08:41 PM PDT 24
Finished Jun 02 01:08:42 PM PDT 24
Peak memory 196832 kb
Host smart-12a37641-4b67-4205-a69e-dcd6dc09c40e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054457591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.4054457591
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.3680107326
Short name T702
Test name
Test status
Simulation time 55460188 ps
CPU time 0.6 seconds
Started Jun 02 01:08:31 PM PDT 24
Finished Jun 02 01:08:32 PM PDT 24
Peak memory 194212 kb
Host smart-c4e0e5dd-c93f-4a15-a874-15a630017b72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680107326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3680107326
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.4111969067
Short name T721
Test name
Test status
Simulation time 170687277 ps
CPU time 1.99 seconds
Started Jun 02 01:08:48 PM PDT 24
Finished Jun 02 01:08:51 PM PDT 24
Peak memory 198588 kb
Host smart-c77aa58c-f4b3-4b02-ad5a-8b16fd5c664c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111969067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.4111969067
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3726398168
Short name T86
Test name
Test status
Simulation time 49020525 ps
CPU time 2.54 seconds
Started Jun 02 01:08:32 PM PDT 24
Finished Jun 02 01:08:35 PM PDT 24
Peak memory 199292 kb
Host smart-4a116c78-f96f-4cbe-8995-d91e37fc7191
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726398168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.3726398168
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2618493201
Short name T648
Test name
Test status
Simulation time 249298821 ps
CPU time 4.11 seconds
Started Jun 02 01:08:33 PM PDT 24
Finished Jun 02 01:08:37 PM PDT 24
Peak memory 199312 kb
Host smart-e3cf5f31-cbff-414f-9bcf-fda46a65f0ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618493201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2618493201
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3000335231
Short name T668
Test name
Test status
Simulation time 764110343 ps
CPU time 8.87 seconds
Started Jun 02 01:08:48 PM PDT 24
Finished Jun 02 01:08:57 PM PDT 24
Peak memory 198812 kb
Host smart-b634198a-4e16-4c6f-a4bb-e2991f7503c1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000335231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3000335231
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3585400418
Short name T680
Test name
Test status
Simulation time 430269275 ps
CPU time 5.15 seconds
Started Jun 02 01:08:49 PM PDT 24
Finished Jun 02 01:08:54 PM PDT 24
Peak memory 198112 kb
Host smart-3949004c-6614-4234-afea-c0c6df56863e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585400418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3585400418
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1194436118
Short name T621
Test name
Test status
Simulation time 27891831 ps
CPU time 0.88 seconds
Started Jun 02 01:08:48 PM PDT 24
Finished Jun 02 01:08:49 PM PDT 24
Peak memory 198324 kb
Host smart-54a60b26-9502-422c-9778-25b8fe40d5d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194436118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1194436118
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2651011012
Short name T613
Test name
Test status
Simulation time 39030295 ps
CPU time 2.32 seconds
Started Jun 02 01:08:48 PM PDT 24
Finished Jun 02 01:08:51 PM PDT 24
Peak memory 207560 kb
Host smart-de9c93ba-4205-4221-9cd4-a0362ab05f06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651011012 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2651011012
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2504506609
Short name T699
Test name
Test status
Simulation time 208460358 ps
CPU time 0.71 seconds
Started Jun 02 01:08:49 PM PDT 24
Finished Jun 02 01:08:51 PM PDT 24
Peak memory 196728 kb
Host smart-a4ad597e-5928-41b4-9912-742f0dce0385
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504506609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2504506609
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.868033058
Short name T709
Test name
Test status
Simulation time 15642177 ps
CPU time 0.59 seconds
Started Jun 02 01:08:48 PM PDT 24
Finished Jun 02 01:08:49 PM PDT 24
Peak memory 194052 kb
Host smart-7f4000b7-62ea-4c8d-ae2a-8c19d3a3d21e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868033058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.868033058
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1513999624
Short name T700
Test name
Test status
Simulation time 1825489868 ps
CPU time 2.33 seconds
Started Jun 02 01:08:50 PM PDT 24
Finished Jun 02 01:08:52 PM PDT 24
Peak memory 199280 kb
Host smart-faa40500-d0ea-46cb-9247-acdc47d14a45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513999624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.1513999624
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3552987764
Short name T689
Test name
Test status
Simulation time 28546132 ps
CPU time 1.6 seconds
Started Jun 02 01:08:50 PM PDT 24
Finished Jun 02 01:08:52 PM PDT 24
Peak memory 199368 kb
Host smart-b8238c73-60e6-43ff-a7a0-07a4698cded4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552987764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3552987764
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1830137930
Short name T697
Test name
Test status
Simulation time 78598938 ps
CPU time 1.2 seconds
Started Jun 02 01:09:22 PM PDT 24
Finished Jun 02 01:09:24 PM PDT 24
Peak memory 199192 kb
Host smart-9923e1a7-94d4-4060-85c0-383ba961505d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830137930 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.1830137930
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1800152497
Short name T614
Test name
Test status
Simulation time 169116170 ps
CPU time 0.71 seconds
Started Jun 02 01:09:15 PM PDT 24
Finished Jun 02 01:09:16 PM PDT 24
Peak memory 196832 kb
Host smart-e98a8b36-0555-48fa-bb2e-830900e64cc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800152497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1800152497
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3616485495
Short name T636
Test name
Test status
Simulation time 44330169 ps
CPU time 0.61 seconds
Started Jun 02 01:09:15 PM PDT 24
Finished Jun 02 01:09:16 PM PDT 24
Peak memory 194080 kb
Host smart-70c43d1e-f612-4768-85d2-f88def56178f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616485495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3616485495
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3559196734
Short name T641
Test name
Test status
Simulation time 47973751 ps
CPU time 2.27 seconds
Started Jun 02 01:09:15 PM PDT 24
Finished Jun 02 01:09:18 PM PDT 24
Peak memory 199284 kb
Host smart-9066578e-c024-4dbb-a8e1-76e6a4e860dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559196734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.3559196734
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3456814272
Short name T602
Test name
Test status
Simulation time 219770985 ps
CPU time 3.2 seconds
Started Jun 02 01:09:14 PM PDT 24
Finished Jun 02 01:09:18 PM PDT 24
Peak memory 199292 kb
Host smart-3fdc83fa-32c6-429e-9056-3d1b4c4734ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456814272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3456814272
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.584402732
Short name T651
Test name
Test status
Simulation time 65552430 ps
CPU time 2.05 seconds
Started Jun 02 01:09:28 PM PDT 24
Finished Jun 02 01:09:31 PM PDT 24
Peak memory 199320 kb
Host smart-43000c9b-bec6-4f41-b340-bbce5065ceec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584402732 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.584402732
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.76407201
Short name T683
Test name
Test status
Simulation time 18205849 ps
CPU time 0.64 seconds
Started Jun 02 01:09:22 PM PDT 24
Finished Jun 02 01:09:23 PM PDT 24
Peak memory 194128 kb
Host smart-7a64f3a5-04c4-44f9-bb96-731fe35121c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76407201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.76407201
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2069096771
Short name T637
Test name
Test status
Simulation time 86204641 ps
CPU time 2.08 seconds
Started Jun 02 01:09:29 PM PDT 24
Finished Jun 02 01:09:32 PM PDT 24
Peak memory 199288 kb
Host smart-7e697b96-b86c-48bf-be90-a53e7776465e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069096771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2069096771
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.792563737
Short name T618
Test name
Test status
Simulation time 173578787 ps
CPU time 2.39 seconds
Started Jun 02 01:09:23 PM PDT 24
Finished Jun 02 01:09:26 PM PDT 24
Peak memory 199436 kb
Host smart-4c6baad6-4910-4e0d-bbdb-5735e8c8f3a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792563737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.792563737
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3999217034
Short name T659
Test name
Test status
Simulation time 164622518 ps
CPU time 2.78 seconds
Started Jun 02 01:09:21 PM PDT 24
Finished Jun 02 01:09:24 PM PDT 24
Peak memory 199328 kb
Host smart-f8d45dd5-6a94-4278-9a6d-f551da709956
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999217034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3999217034
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.199833168
Short name T658
Test name
Test status
Simulation time 351216546 ps
CPU time 2.43 seconds
Started Jun 02 01:09:29 PM PDT 24
Finished Jun 02 01:09:32 PM PDT 24
Peak memory 199592 kb
Host smart-348a3bd1-af7e-4799-8441-0432d5573051
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199833168 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.199833168
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1549881666
Short name T667
Test name
Test status
Simulation time 179420527 ps
CPU time 0.81 seconds
Started Jun 02 01:09:30 PM PDT 24
Finished Jun 02 01:09:31 PM PDT 24
Peak memory 198492 kb
Host smart-6a439700-3d0d-4768-93f3-e1d7ec1a9169
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549881666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1549881666
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1278516884
Short name T670
Test name
Test status
Simulation time 14361944 ps
CPU time 0.59 seconds
Started Jun 02 01:09:27 PM PDT 24
Finished Jun 02 01:09:28 PM PDT 24
Peak memory 194044 kb
Host smart-ff10938d-b4b5-4ffa-9fd4-d75219308580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278516884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1278516884
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1145736861
Short name T617
Test name
Test status
Simulation time 100379982 ps
CPU time 1.11 seconds
Started Jun 02 01:09:29 PM PDT 24
Finished Jun 02 01:09:30 PM PDT 24
Peak memory 197708 kb
Host smart-c7c6b30b-2674-49b5-ab50-ac0fd11c8977
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145736861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1145736861
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.67587284
Short name T719
Test name
Test status
Simulation time 857090395 ps
CPU time 4.99 seconds
Started Jun 02 01:09:28 PM PDT 24
Finished Jun 02 01:09:34 PM PDT 24
Peak memory 199360 kb
Host smart-882614f5-f5ec-4c64-af38-33ee01f8b9a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67587284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.67587284
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.708951972
Short name T622
Test name
Test status
Simulation time 38799142 ps
CPU time 1.33 seconds
Started Jun 02 01:09:31 PM PDT 24
Finished Jun 02 01:09:32 PM PDT 24
Peak memory 199384 kb
Host smart-2d291ca1-c7d3-4850-a493-a5549347da00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708951972 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.708951972
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3617995241
Short name T55
Test name
Test status
Simulation time 17997022 ps
CPU time 0.74 seconds
Started Jun 02 01:09:27 PM PDT 24
Finished Jun 02 01:09:29 PM PDT 24
Peak memory 196940 kb
Host smart-34478013-53a2-4192-94d3-8e524e79ec13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617995241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3617995241
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.219797263
Short name T715
Test name
Test status
Simulation time 14366169 ps
CPU time 0.58 seconds
Started Jun 02 01:09:27 PM PDT 24
Finished Jun 02 01:09:28 PM PDT 24
Peak memory 194160 kb
Host smart-5ef0cceb-a4ce-4ce6-9edf-a3173a27cca0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219797263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.219797263
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2490245249
Short name T657
Test name
Test status
Simulation time 158492503 ps
CPU time 1.84 seconds
Started Jun 02 01:09:29 PM PDT 24
Finished Jun 02 01:09:31 PM PDT 24
Peak memory 199156 kb
Host smart-ea62a45d-d111-479e-b6b0-3ff9cedf5e89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490245249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2490245249
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1813845200
Short name T661
Test name
Test status
Simulation time 80645183 ps
CPU time 4.01 seconds
Started Jun 02 01:09:28 PM PDT 24
Finished Jun 02 01:09:32 PM PDT 24
Peak memory 199272 kb
Host smart-d1b6efd8-9c1b-4b03-a83e-40405d731124
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813845200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1813845200
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2835230684
Short name T128
Test name
Test status
Simulation time 125473820 ps
CPU time 4.03 seconds
Started Jun 02 01:09:29 PM PDT 24
Finished Jun 02 01:09:33 PM PDT 24
Peak memory 199336 kb
Host smart-60043b31-26ac-4b7a-924b-4ef9ac350b58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835230684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2835230684
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1803021254
Short name T724
Test name
Test status
Simulation time 84676830 ps
CPU time 2.59 seconds
Started Jun 02 01:09:30 PM PDT 24
Finished Jun 02 01:09:32 PM PDT 24
Peak memory 199392 kb
Host smart-520d52f7-bb2f-4da6-b592-0a8f536035b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803021254 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1803021254
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3778968611
Short name T94
Test name
Test status
Simulation time 15858826 ps
CPU time 0.71 seconds
Started Jun 02 01:09:28 PM PDT 24
Finished Jun 02 01:09:30 PM PDT 24
Peak memory 196768 kb
Host smart-5e05acf6-e593-4b69-8fbd-e1ba6754415b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778968611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3778968611
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.2284080156
Short name T656
Test name
Test status
Simulation time 13386781 ps
CPU time 0.58 seconds
Started Jun 02 01:09:30 PM PDT 24
Finished Jun 02 01:09:30 PM PDT 24
Peak memory 194100 kb
Host smart-eb22d394-bf94-405b-97cf-fc171324047c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284080156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2284080156
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2801714998
Short name T725
Test name
Test status
Simulation time 39553984 ps
CPU time 1.16 seconds
Started Jun 02 01:09:28 PM PDT 24
Finished Jun 02 01:09:29 PM PDT 24
Peak memory 198984 kb
Host smart-a5517d8e-f215-4dc9-92b3-2afc60ac9fd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801714998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2801714998
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3462558406
Short name T633
Test name
Test status
Simulation time 187250944 ps
CPU time 2.27 seconds
Started Jun 02 01:09:28 PM PDT 24
Finished Jun 02 01:09:31 PM PDT 24
Peak memory 199372 kb
Host smart-adda215a-61b9-44aa-be07-26580284d63a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462558406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3462558406
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1886070807
Short name T632
Test name
Test status
Simulation time 369044724 ps
CPU time 2.86 seconds
Started Jun 02 01:09:29 PM PDT 24
Finished Jun 02 01:09:32 PM PDT 24
Peak memory 199324 kb
Host smart-180433fd-5e5c-4f94-9c40-d45e8446596f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886070807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1886070807
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1628108857
Short name T713
Test name
Test status
Simulation time 304393020 ps
CPU time 1.84 seconds
Started Jun 02 01:09:38 PM PDT 24
Finished Jun 02 01:09:40 PM PDT 24
Peak memory 199412 kb
Host smart-c760ffc7-ddfd-4f44-b5d4-844cb75202ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628108857 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1628108857
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2520958867
Short name T97
Test name
Test status
Simulation time 18055838 ps
CPU time 0.71 seconds
Started Jun 02 01:09:29 PM PDT 24
Finished Jun 02 01:09:30 PM PDT 24
Peak memory 197020 kb
Host smart-9045120c-6e03-42c3-8904-37855db935d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520958867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2520958867
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2643797472
Short name T647
Test name
Test status
Simulation time 22566977 ps
CPU time 0.57 seconds
Started Jun 02 01:09:29 PM PDT 24
Finished Jun 02 01:09:30 PM PDT 24
Peak memory 194056 kb
Host smart-8d313a5c-5cd3-43fe-8f42-dceb62e620bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643797472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2643797472
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.907053185
Short name T675
Test name
Test status
Simulation time 105777719 ps
CPU time 1.87 seconds
Started Jun 02 01:09:27 PM PDT 24
Finished Jun 02 01:09:30 PM PDT 24
Peak memory 199368 kb
Host smart-c6ae2667-a057-453d-b36f-5b2421dd1a2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907053185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr
_outstanding.907053185
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3025998618
Short name T646
Test name
Test status
Simulation time 84255830 ps
CPU time 4.52 seconds
Started Jun 02 01:09:27 PM PDT 24
Finished Jun 02 01:09:32 PM PDT 24
Peak memory 199348 kb
Host smart-9d2ea90d-5eef-4f5f-ad9f-fc6084b14434
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025998618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3025998618
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.493304761
Short name T127
Test name
Test status
Simulation time 234012112 ps
CPU time 4.47 seconds
Started Jun 02 01:09:29 PM PDT 24
Finished Jun 02 01:09:33 PM PDT 24
Peak memory 199344 kb
Host smart-d2606336-5a3a-40a1-b5dc-6f8f135080fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493304761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.493304761
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.622614556
Short name T712
Test name
Test status
Simulation time 93122517 ps
CPU time 2.38 seconds
Started Jun 02 01:09:39 PM PDT 24
Finished Jun 02 01:09:42 PM PDT 24
Peak memory 199396 kb
Host smart-e36218ac-fa26-48f0-9856-dee7d2e06caa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622614556 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.622614556
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.187974898
Short name T91
Test name
Test status
Simulation time 50747870 ps
CPU time 0.81 seconds
Started Jun 02 01:09:38 PM PDT 24
Finished Jun 02 01:09:39 PM PDT 24
Peak memory 199040 kb
Host smart-929167cd-a003-4e25-850f-04196b574689
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187974898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.187974898
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3479046406
Short name T624
Test name
Test status
Simulation time 29990518 ps
CPU time 0.57 seconds
Started Jun 02 01:09:38 PM PDT 24
Finished Jun 02 01:09:39 PM PDT 24
Peak memory 194112 kb
Host smart-ad9043ae-e18e-43b2-b672-4b5486b8eb2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479046406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3479046406
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.124020896
Short name T634
Test name
Test status
Simulation time 88714968 ps
CPU time 2 seconds
Started Jun 02 01:09:37 PM PDT 24
Finished Jun 02 01:09:40 PM PDT 24
Peak memory 199372 kb
Host smart-3772146a-6d94-426a-936b-861e2a9a50d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124020896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr
_outstanding.124020896
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3710556305
Short name T684
Test name
Test status
Simulation time 148344383 ps
CPU time 3.06 seconds
Started Jun 02 01:09:37 PM PDT 24
Finished Jun 02 01:09:40 PM PDT 24
Peak memory 199428 kb
Host smart-c9ac88a5-84c1-41d3-b3ed-1f9a34dc2bcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710556305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3710556305
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3695370086
Short name T653
Test name
Test status
Simulation time 108652984 ps
CPU time 1.88 seconds
Started Jun 02 01:09:39 PM PDT 24
Finished Jun 02 01:09:41 PM PDT 24
Peak memory 199384 kb
Host smart-e3ad5a2d-a041-40a6-9f37-43b4c9ae3376
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695370086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3695370086
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1562129606
Short name T601
Test name
Test status
Simulation time 196364584 ps
CPU time 1.28 seconds
Started Jun 02 01:09:38 PM PDT 24
Finished Jun 02 01:09:40 PM PDT 24
Peak memory 199120 kb
Host smart-fa56611c-15f4-4004-af78-3aa375ef0723
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562129606 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1562129606
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1977886748
Short name T95
Test name
Test status
Simulation time 28166447 ps
CPU time 0.94 seconds
Started Jun 02 01:09:38 PM PDT 24
Finished Jun 02 01:09:39 PM PDT 24
Peak memory 198992 kb
Host smart-dfd645d7-6eb6-431e-8bad-7be972283ba1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977886748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1977886748
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1778841253
Short name T705
Test name
Test status
Simulation time 15315049 ps
CPU time 0.59 seconds
Started Jun 02 01:09:38 PM PDT 24
Finished Jun 02 01:09:38 PM PDT 24
Peak memory 194116 kb
Host smart-cd74b4ca-4099-4a29-a4d4-10aaf082643c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778841253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1778841253
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.917591773
Short name T698
Test name
Test status
Simulation time 173615432 ps
CPU time 2.08 seconds
Started Jun 02 01:09:37 PM PDT 24
Finished Jun 02 01:09:40 PM PDT 24
Peak memory 199256 kb
Host smart-67637130-b831-4606-a3c5-6c736b878acb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917591773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr
_outstanding.917591773
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1013755643
Short name T652
Test name
Test status
Simulation time 590034239 ps
CPU time 2.87 seconds
Started Jun 02 01:09:37 PM PDT 24
Finished Jun 02 01:09:40 PM PDT 24
Peak memory 199332 kb
Host smart-43b97a18-5f02-46d5-b5c1-e1613bcd3105
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013755643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1013755643
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.4119477100
Short name T129
Test name
Test status
Simulation time 169070180 ps
CPU time 4.23 seconds
Started Jun 02 01:09:36 PM PDT 24
Finished Jun 02 01:09:41 PM PDT 24
Peak memory 199352 kb
Host smart-20f1ad5a-fee3-4dbf-a0b9-92b20e1c8859
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119477100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.4119477100
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2984742948
Short name T679
Test name
Test status
Simulation time 184737750 ps
CPU time 2.95 seconds
Started Jun 02 01:09:45 PM PDT 24
Finished Jun 02 01:09:48 PM PDT 24
Peak memory 199452 kb
Host smart-8239ffd8-703d-4c93-a06c-b8bcef33684a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984742948 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2984742948
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3273931660
Short name T96
Test name
Test status
Simulation time 40627694 ps
CPU time 0.89 seconds
Started Jun 02 01:09:49 PM PDT 24
Finished Jun 02 01:09:51 PM PDT 24
Peak memory 198428 kb
Host smart-f3656a3f-5357-47cf-8fe9-c1bfcc263dab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273931660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3273931660
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1880769623
Short name T609
Test name
Test status
Simulation time 52900134 ps
CPU time 0.58 seconds
Started Jun 02 01:09:47 PM PDT 24
Finished Jun 02 01:09:48 PM PDT 24
Peak memory 194108 kb
Host smart-736add34-2251-4460-b05c-34959eb15e06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880769623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1880769623
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1850810367
Short name T695
Test name
Test status
Simulation time 79795015 ps
CPU time 1.14 seconds
Started Jun 02 01:09:47 PM PDT 24
Finished Jun 02 01:09:49 PM PDT 24
Peak memory 199088 kb
Host smart-2e2a839b-bd5f-495a-bbe7-058841047897
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850810367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.1850810367
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2926957708
Short name T59
Test name
Test status
Simulation time 323581433 ps
CPU time 3.31 seconds
Started Jun 02 01:09:45 PM PDT 24
Finished Jun 02 01:09:48 PM PDT 24
Peak memory 199376 kb
Host smart-2a23943d-53a3-42f0-a85a-7a2bd27212b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926957708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2926957708
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2182676399
Short name T52
Test name
Test status
Simulation time 1060614467 ps
CPU time 3.03 seconds
Started Jun 02 01:09:45 PM PDT 24
Finished Jun 02 01:09:49 PM PDT 24
Peak memory 199348 kb
Host smart-f861bd05-5d2d-4d65-bc9f-5dc9598f3772
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182676399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2182676399
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2703286703
Short name T644
Test name
Test status
Simulation time 96552525397 ps
CPU time 393.71 seconds
Started Jun 02 01:09:51 PM PDT 24
Finished Jun 02 01:16:25 PM PDT 24
Peak memory 215848 kb
Host smart-8e2783b6-7810-452b-b45f-6c64d97a5df3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703286703 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.2703286703
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.378503972
Short name T90
Test name
Test status
Simulation time 63455080 ps
CPU time 0.91 seconds
Started Jun 02 01:09:46 PM PDT 24
Finished Jun 02 01:09:47 PM PDT 24
Peak memory 198688 kb
Host smart-13a36e0a-50e1-42fb-be47-4f896281ef3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378503972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.378503972
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.3015829182
Short name T693
Test name
Test status
Simulation time 33022627 ps
CPU time 0.6 seconds
Started Jun 02 01:09:44 PM PDT 24
Finished Jun 02 01:09:45 PM PDT 24
Peak memory 194084 kb
Host smart-0e773834-e910-415c-bf65-b03a3a51347d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015829182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3015829182
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3517148299
Short name T628
Test name
Test status
Simulation time 46873556 ps
CPU time 2.28 seconds
Started Jun 02 01:09:47 PM PDT 24
Finished Jun 02 01:09:50 PM PDT 24
Peak memory 199132 kb
Host smart-c472b98a-9007-49a4-bd24-efa5da3ecb75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517148299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3517148299
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1622312261
Short name T685
Test name
Test status
Simulation time 61125708 ps
CPU time 3.31 seconds
Started Jun 02 01:09:46 PM PDT 24
Finished Jun 02 01:09:50 PM PDT 24
Peak memory 199408 kb
Host smart-cb64b9d4-8649-4927-8026-a923465a0768
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622312261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1622312261
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.4192570316
Short name T678
Test name
Test status
Simulation time 181638470 ps
CPU time 2.92 seconds
Started Jun 02 01:09:46 PM PDT 24
Finished Jun 02 01:09:50 PM PDT 24
Peak memory 199364 kb
Host smart-a8f02e2c-6aac-4a5d-9192-0c34ed171994
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192570316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.4192570316
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.186125447
Short name T99
Test name
Test status
Simulation time 158555150 ps
CPU time 7.88 seconds
Started Jun 02 01:08:48 PM PDT 24
Finished Jun 02 01:08:57 PM PDT 24
Peak memory 199276 kb
Host smart-d58c6d98-01b1-496a-9fb7-a1f9afc8d2d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186125447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.186125447
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2582597518
Short name T98
Test name
Test status
Simulation time 113043200 ps
CPU time 5.28 seconds
Started Jun 02 01:08:48 PM PDT 24
Finished Jun 02 01:08:54 PM PDT 24
Peak memory 199232 kb
Host smart-9e8dc4fd-1079-4d4f-9351-47c08463b4fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582597518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2582597518
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.4278271431
Short name T681
Test name
Test status
Simulation time 19748154 ps
CPU time 0.86 seconds
Started Jun 02 01:08:49 PM PDT 24
Finished Jun 02 01:08:50 PM PDT 24
Peak memory 198592 kb
Host smart-65c71c57-ca37-457d-9b15-c2fef9a8a0ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278271431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.4278271431
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3792036794
Short name T626
Test name
Test status
Simulation time 22186464 ps
CPU time 1.41 seconds
Started Jun 02 01:08:49 PM PDT 24
Finished Jun 02 01:08:51 PM PDT 24
Peak memory 199400 kb
Host smart-c42e7928-c413-4134-b55c-b4b240c617ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792036794 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3792036794
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1882279173
Short name T623
Test name
Test status
Simulation time 20887220 ps
CPU time 0.69 seconds
Started Jun 02 01:08:48 PM PDT 24
Finished Jun 02 01:08:49 PM PDT 24
Peak memory 197224 kb
Host smart-b18dbd18-c539-4309-90b7-ac966c31c936
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882279173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1882279173
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.3813658550
Short name T696
Test name
Test status
Simulation time 11993079 ps
CPU time 0.63 seconds
Started Jun 02 01:08:48 PM PDT 24
Finished Jun 02 01:08:49 PM PDT 24
Peak memory 194112 kb
Host smart-57bc2b1e-dc25-4454-90ff-137f80bf03c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813658550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3813658550
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3876575607
Short name T669
Test name
Test status
Simulation time 174708552 ps
CPU time 1.7 seconds
Started Jun 02 01:08:50 PM PDT 24
Finished Jun 02 01:08:52 PM PDT 24
Peak memory 199280 kb
Host smart-df427884-9c02-44bf-a61b-a44868b4f4ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876575607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3876575607
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3649667651
Short name T60
Test name
Test status
Simulation time 1425513181 ps
CPU time 4.22 seconds
Started Jun 02 01:08:49 PM PDT 24
Finished Jun 02 01:08:54 PM PDT 24
Peak memory 199364 kb
Host smart-71d89003-58c5-4c0d-a7dc-4c9df3e2b5b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649667651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3649667651
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.3827036606
Short name T600
Test name
Test status
Simulation time 34502180 ps
CPU time 0.58 seconds
Started Jun 02 01:09:44 PM PDT 24
Finished Jun 02 01:09:45 PM PDT 24
Peak memory 194116 kb
Host smart-8b7d5f4a-196c-4d30-bf9a-88f4f65948ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827036606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3827036606
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.330279075
Short name T77
Test name
Test status
Simulation time 93803133 ps
CPU time 0.63 seconds
Started Jun 02 01:09:45 PM PDT 24
Finished Jun 02 01:09:46 PM PDT 24
Peak memory 194264 kb
Host smart-1174194d-afb9-47e1-92bd-53129859bb0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330279075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.330279075
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.2981940024
Short name T704
Test name
Test status
Simulation time 12135546 ps
CPU time 0.62 seconds
Started Jun 02 01:09:46 PM PDT 24
Finished Jun 02 01:09:47 PM PDT 24
Peak memory 194160 kb
Host smart-956e38fe-b525-46fe-84db-97fefdbc338b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981940024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.2981940024
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1300665580
Short name T687
Test name
Test status
Simulation time 41836378 ps
CPU time 0.59 seconds
Started Jun 02 01:09:50 PM PDT 24
Finished Jun 02 01:09:51 PM PDT 24
Peak memory 194080 kb
Host smart-99b2b1bd-63b3-4a2f-a8f8-d73405492488
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300665580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1300665580
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2457597333
Short name T673
Test name
Test status
Simulation time 20162796 ps
CPU time 0.61 seconds
Started Jun 02 01:09:46 PM PDT 24
Finished Jun 02 01:09:47 PM PDT 24
Peak memory 194108 kb
Host smart-580c2c14-00d1-44c0-9817-b689c08ad640
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457597333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2457597333
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3773287515
Short name T598
Test name
Test status
Simulation time 46136532 ps
CPU time 0.59 seconds
Started Jun 02 01:09:47 PM PDT 24
Finished Jun 02 01:09:48 PM PDT 24
Peak memory 194160 kb
Host smart-af488925-4dd9-453c-8db3-64b04b6cb85b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773287515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3773287515
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.2705424327
Short name T686
Test name
Test status
Simulation time 36106562 ps
CPU time 0.57 seconds
Started Jun 02 01:09:54 PM PDT 24
Finished Jun 02 01:09:55 PM PDT 24
Peak memory 194008 kb
Host smart-cc25da12-3551-4efa-94d8-f299a9792988
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705424327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2705424327
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1456765299
Short name T706
Test name
Test status
Simulation time 16879804 ps
CPU time 0.6 seconds
Started Jun 02 01:09:55 PM PDT 24
Finished Jun 02 01:09:56 PM PDT 24
Peak memory 194176 kb
Host smart-28995a22-12d7-45ce-a684-6fdeb173d824
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456765299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1456765299
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2910669732
Short name T615
Test name
Test status
Simulation time 14067733 ps
CPU time 0.61 seconds
Started Jun 02 01:09:52 PM PDT 24
Finished Jun 02 01:09:53 PM PDT 24
Peak memory 194044 kb
Host smart-e73a9cbe-f9bc-4fd3-bdc0-a8eb8a4e6e06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910669732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2910669732
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1354790365
Short name T649
Test name
Test status
Simulation time 46490685 ps
CPU time 0.6 seconds
Started Jun 02 01:09:53 PM PDT 24
Finished Jun 02 01:09:54 PM PDT 24
Peak memory 194328 kb
Host smart-1bb6370d-b286-4904-a0ca-ecdccb72d27c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354790365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1354790365
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2369676601
Short name T612
Test name
Test status
Simulation time 193728971 ps
CPU time 3.32 seconds
Started Jun 02 01:08:55 PM PDT 24
Finished Jun 02 01:08:58 PM PDT 24
Peak memory 199280 kb
Host smart-96c3e1aa-016d-4c6f-98f5-0e5b6e914646
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369676601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2369676601
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2347196790
Short name T100
Test name
Test status
Simulation time 13644310834 ps
CPU time 16.03 seconds
Started Jun 02 01:08:49 PM PDT 24
Finished Jun 02 01:09:06 PM PDT 24
Peak memory 198668 kb
Host smart-ea4e169f-bf4d-4141-b2b3-b0d2df84832c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347196790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2347196790
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.165536342
Short name T674
Test name
Test status
Simulation time 41184964 ps
CPU time 0.76 seconds
Started Jun 02 01:08:50 PM PDT 24
Finished Jun 02 01:08:51 PM PDT 24
Peak memory 197200 kb
Host smart-e701750a-3088-4fa2-ad85-acb5540872f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165536342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.165536342
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3512101425
Short name T645
Test name
Test status
Simulation time 106252671 ps
CPU time 2.98 seconds
Started Jun 02 01:08:55 PM PDT 24
Finished Jun 02 01:08:58 PM PDT 24
Peak memory 207620 kb
Host smart-5df3cf86-2e51-4c52-8662-7958e57d4387
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512101425 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.3512101425
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1316126320
Short name T677
Test name
Test status
Simulation time 95735425 ps
CPU time 0.83 seconds
Started Jun 02 01:08:47 PM PDT 24
Finished Jun 02 01:08:48 PM PDT 24
Peak memory 198328 kb
Host smart-256d1505-7fe3-4a8e-9bd5-847f02969fcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316126320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1316126320
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3313736847
Short name T605
Test name
Test status
Simulation time 43706965 ps
CPU time 0.61 seconds
Started Jun 02 01:08:49 PM PDT 24
Finished Jun 02 01:08:50 PM PDT 24
Peak memory 194268 kb
Host smart-ab1a1b26-4019-42c9-a49d-35c1e4833b65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313736847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3313736847
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3119442575
Short name T708
Test name
Test status
Simulation time 25333499 ps
CPU time 1.12 seconds
Started Jun 02 01:08:56 PM PDT 24
Finished Jun 02 01:08:57 PM PDT 24
Peak memory 199356 kb
Host smart-48163e17-c843-4fbc-af58-c5db20dc0987
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119442575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3119442575
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2935328175
Short name T672
Test name
Test status
Simulation time 115882220 ps
CPU time 2.96 seconds
Started Jun 02 01:08:50 PM PDT 24
Finished Jun 02 01:08:54 PM PDT 24
Peak memory 199376 kb
Host smart-306f770c-6177-43f3-bd08-03b2d2804a86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935328175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2935328175
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3813632361
Short name T722
Test name
Test status
Simulation time 398047424 ps
CPU time 2.02 seconds
Started Jun 02 01:08:49 PM PDT 24
Finished Jun 02 01:08:51 PM PDT 24
Peak memory 199364 kb
Host smart-14536655-2271-43f4-9c3f-3c0d0443bc69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813632361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.3813632361
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.2856562802
Short name T627
Test name
Test status
Simulation time 17561563 ps
CPU time 0.63 seconds
Started Jun 02 01:09:57 PM PDT 24
Finished Jun 02 01:09:58 PM PDT 24
Peak memory 194128 kb
Host smart-e7cef105-1d53-4955-a6a7-730ee059a9c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856562802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2856562802
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1450382751
Short name T703
Test name
Test status
Simulation time 11836048 ps
CPU time 0.59 seconds
Started Jun 02 01:09:55 PM PDT 24
Finished Jun 02 01:09:56 PM PDT 24
Peak memory 194104 kb
Host smart-c8a7c7e6-f8bd-4484-8f41-bc73c41df77e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450382751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1450382751
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3603524872
Short name T625
Test name
Test status
Simulation time 16991093 ps
CPU time 0.61 seconds
Started Jun 02 01:09:51 PM PDT 24
Finished Jun 02 01:09:52 PM PDT 24
Peak memory 194116 kb
Host smart-2c332ad4-8056-42a7-9733-e20c184631fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603524872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3603524872
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3327722894
Short name T716
Test name
Test status
Simulation time 18011947 ps
CPU time 0.62 seconds
Started Jun 02 01:09:52 PM PDT 24
Finished Jun 02 01:09:53 PM PDT 24
Peak memory 194056 kb
Host smart-02f58c76-f79b-4bfe-92d0-7dd9a8780f43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327722894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3327722894
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3287808620
Short name T638
Test name
Test status
Simulation time 42432052 ps
CPU time 0.6 seconds
Started Jun 02 01:09:56 PM PDT 24
Finished Jun 02 01:09:57 PM PDT 24
Peak memory 194188 kb
Host smart-c45442d8-3de7-4e06-9f75-0a94c0f47579
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287808620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3287808620
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.3967624870
Short name T629
Test name
Test status
Simulation time 14285070 ps
CPU time 0.59 seconds
Started Jun 02 01:09:53 PM PDT 24
Finished Jun 02 01:09:54 PM PDT 24
Peak memory 194064 kb
Host smart-b23b73e7-5180-45d3-8649-9cb106b12f85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967624870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3967624870
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2808682319
Short name T639
Test name
Test status
Simulation time 54679853 ps
CPU time 0.56 seconds
Started Jun 02 01:09:51 PM PDT 24
Finished Jun 02 01:09:52 PM PDT 24
Peak memory 194424 kb
Host smart-a46742a5-0e23-4f89-92b9-5a5361489510
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808682319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2808682319
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2347851108
Short name T714
Test name
Test status
Simulation time 26429319 ps
CPU time 0.56 seconds
Started Jun 02 01:09:54 PM PDT 24
Finished Jun 02 01:09:55 PM PDT 24
Peak memory 194104 kb
Host smart-1f19ebd0-3339-4407-a35a-b62ea831905e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347851108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2347851108
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.3310329955
Short name T603
Test name
Test status
Simulation time 20735862 ps
CPU time 0.6 seconds
Started Jun 02 01:09:55 PM PDT 24
Finished Jun 02 01:09:56 PM PDT 24
Peak memory 194088 kb
Host smart-72d7431f-245b-4d9c-9d43-8e2dd21fc44c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310329955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3310329955
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1947958520
Short name T662
Test name
Test status
Simulation time 20995806 ps
CPU time 0.62 seconds
Started Jun 02 01:09:57 PM PDT 24
Finished Jun 02 01:09:57 PM PDT 24
Peak memory 194140 kb
Host smart-2d4fcd6a-bd02-4cf8-8e16-5a718de2b261
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947958520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1947958520
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2036452652
Short name T655
Test name
Test status
Simulation time 416085275 ps
CPU time 5.04 seconds
Started Jun 02 01:08:53 PM PDT 24
Finished Jun 02 01:08:59 PM PDT 24
Peak memory 199224 kb
Host smart-de81c1ad-1308-4d35-8433-60984789b133
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036452652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2036452652
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3758107068
Short name T718
Test name
Test status
Simulation time 758972021 ps
CPU time 11.2 seconds
Started Jun 02 01:08:56 PM PDT 24
Finished Jun 02 01:09:07 PM PDT 24
Peak memory 198312 kb
Host smart-ead1a43e-e3de-425c-addd-b7d56e83ecdd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758107068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3758107068
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.105001757
Short name T92
Test name
Test status
Simulation time 51241515 ps
CPU time 0.84 seconds
Started Jun 02 01:08:53 PM PDT 24
Finished Jun 02 01:08:55 PM PDT 24
Peak memory 198144 kb
Host smart-5aea1e50-900f-4eb3-9548-d4daa7768f9c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105001757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.105001757
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.4187830133
Short name T54
Test name
Test status
Simulation time 37859256 ps
CPU time 1.16 seconds
Started Jun 02 01:09:03 PM PDT 24
Finished Jun 02 01:09:04 PM PDT 24
Peak memory 199200 kb
Host smart-c56a4e2b-7a44-4084-a17e-4c2ac2db2d21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187830133 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.4187830133
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1069333238
Short name T688
Test name
Test status
Simulation time 27248752 ps
CPU time 0.82 seconds
Started Jun 02 01:08:58 PM PDT 24
Finished Jun 02 01:08:59 PM PDT 24
Peak memory 198496 kb
Host smart-c4f415b7-9921-4402-9483-cbcdc2b5dffb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069333238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1069333238
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.1658481511
Short name T694
Test name
Test status
Simulation time 40129957 ps
CPU time 0.64 seconds
Started Jun 02 01:08:54 PM PDT 24
Finished Jun 02 01:08:55 PM PDT 24
Peak memory 194160 kb
Host smart-9fb7e57c-4eb7-43ae-aab8-7a12b710dfd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658481511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1658481511
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2038210397
Short name T664
Test name
Test status
Simulation time 81252604 ps
CPU time 1.79 seconds
Started Jun 02 01:09:02 PM PDT 24
Finished Jun 02 01:09:04 PM PDT 24
Peak memory 199320 kb
Host smart-27a34a25-39ed-4e3d-b0bb-77b8b795dc60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038210397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.2038210397
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3572965134
Short name T650
Test name
Test status
Simulation time 140212973 ps
CPU time 2.39 seconds
Started Jun 02 01:08:55 PM PDT 24
Finished Jun 02 01:08:57 PM PDT 24
Peak memory 199296 kb
Host smart-fbbd6293-3fde-4577-9e32-0ea614ca5c5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572965134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3572965134
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.943123235
Short name T125
Test name
Test status
Simulation time 328957867 ps
CPU time 4.51 seconds
Started Jun 02 01:08:55 PM PDT 24
Finished Jun 02 01:09:00 PM PDT 24
Peak memory 199392 kb
Host smart-e477325d-fbca-4a8b-ae22-450deeea0a4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943123235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.943123235
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.2905474488
Short name T643
Test name
Test status
Simulation time 86471978 ps
CPU time 0.57 seconds
Started Jun 02 01:09:53 PM PDT 24
Finished Jun 02 01:09:54 PM PDT 24
Peak memory 194188 kb
Host smart-93320f76-409e-4374-b8de-105ad966e968
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905474488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2905474488
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.3541027304
Short name T666
Test name
Test status
Simulation time 53664216 ps
CPU time 0.56 seconds
Started Jun 02 01:09:53 PM PDT 24
Finished Jun 02 01:09:54 PM PDT 24
Peak memory 194168 kb
Host smart-78faba21-55ef-4652-8436-845d438f0929
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541027304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3541027304
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3543573545
Short name T597
Test name
Test status
Simulation time 13349859 ps
CPU time 0.58 seconds
Started Jun 02 01:09:54 PM PDT 24
Finished Jun 02 01:09:55 PM PDT 24
Peak memory 194112 kb
Host smart-4fab23ab-ce63-4121-b0ee-d6985a45fdd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543573545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3543573545
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2170728854
Short name T676
Test name
Test status
Simulation time 88742025 ps
CPU time 0.57 seconds
Started Jun 02 01:09:52 PM PDT 24
Finished Jun 02 01:09:53 PM PDT 24
Peak memory 194116 kb
Host smart-298a9899-a2ef-4c85-b321-c3fc6a929bfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170728854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2170728854
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.1217353085
Short name T642
Test name
Test status
Simulation time 55017164 ps
CPU time 0.61 seconds
Started Jun 02 01:09:53 PM PDT 24
Finished Jun 02 01:09:54 PM PDT 24
Peak memory 194060 kb
Host smart-72953875-b94a-462f-b56f-1137fc5261a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217353085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.1217353085
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3347145252
Short name T710
Test name
Test status
Simulation time 21288066 ps
CPU time 0.57 seconds
Started Jun 02 01:09:53 PM PDT 24
Finished Jun 02 01:09:54 PM PDT 24
Peak memory 194112 kb
Host smart-eca692f9-858b-4c92-98c3-b77fdcf548df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347145252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3347145252
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.475394765
Short name T76
Test name
Test status
Simulation time 52098901 ps
CPU time 0.62 seconds
Started Jun 02 01:09:52 PM PDT 24
Finished Jun 02 01:09:53 PM PDT 24
Peak memory 194196 kb
Host smart-d30210bf-fa0e-4731-9e0d-9f6b77ab771b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475394765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.475394765
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.4045285605
Short name T665
Test name
Test status
Simulation time 43939786 ps
CPU time 0.61 seconds
Started Jun 02 01:09:55 PM PDT 24
Finished Jun 02 01:09:56 PM PDT 24
Peak memory 194204 kb
Host smart-e9c8315e-cce7-44ce-b542-3660b2e9f348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045285605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.4045285605
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2006336844
Short name T726
Test name
Test status
Simulation time 44233974 ps
CPU time 0.61 seconds
Started Jun 02 01:09:54 PM PDT 24
Finished Jun 02 01:09:55 PM PDT 24
Peak memory 194188 kb
Host smart-d64b5a75-128a-4809-b14b-a45836f74c78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006336844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2006336844
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.237779088
Short name T640
Test name
Test status
Simulation time 64599091 ps
CPU time 0.6 seconds
Started Jun 02 01:09:56 PM PDT 24
Finished Jun 02 01:09:57 PM PDT 24
Peak memory 194076 kb
Host smart-c6c032d2-f1fd-4f1b-b342-7b346836107f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237779088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.237779088
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3421053891
Short name T619
Test name
Test status
Simulation time 186733755 ps
CPU time 4.07 seconds
Started Jun 02 01:09:07 PM PDT 24
Finished Jun 02 01:09:12 PM PDT 24
Peak memory 207560 kb
Host smart-e35445da-9d39-4b1d-b74d-e83136820ce8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421053891 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3421053891
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2518892940
Short name T671
Test name
Test status
Simulation time 17680777 ps
CPU time 0.72 seconds
Started Jun 02 01:09:01 PM PDT 24
Finished Jun 02 01:09:02 PM PDT 24
Peak memory 196968 kb
Host smart-a13a338f-3a22-4595-8093-34ddc9f5abfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518892940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2518892940
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3105775518
Short name T654
Test name
Test status
Simulation time 13002411 ps
CPU time 0.6 seconds
Started Jun 02 01:09:02 PM PDT 24
Finished Jun 02 01:09:03 PM PDT 24
Peak memory 194108 kb
Host smart-0aa59a5f-9f6c-4dd3-8f87-524389f42629
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105775518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3105775518
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.4124016061
Short name T610
Test name
Test status
Simulation time 500345267 ps
CPU time 1.84 seconds
Started Jun 02 01:09:04 PM PDT 24
Finished Jun 02 01:09:06 PM PDT 24
Peak memory 199296 kb
Host smart-0738b4a2-abc8-4ae8-92db-143844de319d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124016061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.4124016061
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1484581077
Short name T630
Test name
Test status
Simulation time 192527095 ps
CPU time 2.17 seconds
Started Jun 02 01:09:02 PM PDT 24
Finished Jun 02 01:09:05 PM PDT 24
Peak memory 199376 kb
Host smart-88c89c29-e71e-49ea-94d9-d0e97fcdbba6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484581077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1484581077
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3230073420
Short name T124
Test name
Test status
Simulation time 885814542 ps
CPU time 1.91 seconds
Started Jun 02 01:09:03 PM PDT 24
Finished Jun 02 01:09:05 PM PDT 24
Peak memory 199528 kb
Host smart-9de35c27-0fe6-4a83-bdf5-a44ee98fdc61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230073420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3230073420
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1738774961
Short name T692
Test name
Test status
Simulation time 243696337 ps
CPU time 1.88 seconds
Started Jun 02 01:09:08 PM PDT 24
Finished Jun 02 01:09:11 PM PDT 24
Peak memory 199396 kb
Host smart-1fd278cc-eb1f-4e16-8b59-ec22f0e515b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738774961 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1738774961
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.756265445
Short name T682
Test name
Test status
Simulation time 40591577 ps
CPU time 0.81 seconds
Started Jun 02 01:09:09 PM PDT 24
Finished Jun 02 01:09:10 PM PDT 24
Peak memory 198508 kb
Host smart-893b27ca-430e-47b7-97f1-ab357c12d21c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756265445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.756265445
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.708070651
Short name T611
Test name
Test status
Simulation time 19105213 ps
CPU time 0.63 seconds
Started Jun 02 01:09:09 PM PDT 24
Finished Jun 02 01:09:10 PM PDT 24
Peak memory 194184 kb
Host smart-fa882897-5699-4be3-b252-fac369b1e19d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708070651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.708070651
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1425138191
Short name T711
Test name
Test status
Simulation time 93297203 ps
CPU time 2.32 seconds
Started Jun 02 01:09:10 PM PDT 24
Finished Jun 02 01:09:12 PM PDT 24
Peak memory 199292 kb
Host smart-4092835a-ca31-4c88-9e1d-b9a2cc63c508
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425138191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1425138191
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.866793891
Short name T631
Test name
Test status
Simulation time 408895434 ps
CPU time 4.5 seconds
Started Jun 02 01:09:09 PM PDT 24
Finished Jun 02 01:09:13 PM PDT 24
Peak memory 199408 kb
Host smart-6b72216c-d285-4e1b-a158-3cbb27baf503
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866793891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.866793891
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3208951440
Short name T723
Test name
Test status
Simulation time 121500338 ps
CPU time 2.02 seconds
Started Jun 02 01:09:07 PM PDT 24
Finished Jun 02 01:09:09 PM PDT 24
Peak memory 199336 kb
Host smart-81d6b2ae-a3d0-4ff5-b048-b74ed2fa97ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208951440 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.3208951440
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1432203672
Short name T691
Test name
Test status
Simulation time 19366873 ps
CPU time 0.96 seconds
Started Jun 02 01:09:09 PM PDT 24
Finished Jun 02 01:09:10 PM PDT 24
Peak memory 198976 kb
Host smart-fba010cb-bfb9-495e-a7d5-09495e647a89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432203672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.1432203672
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.4271427912
Short name T690
Test name
Test status
Simulation time 113381511 ps
CPU time 0.59 seconds
Started Jun 02 01:09:11 PM PDT 24
Finished Jun 02 01:09:12 PM PDT 24
Peak memory 194080 kb
Host smart-293ac83a-2f42-41b2-b211-7e53b5b37528
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271427912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.4271427912
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3695017372
Short name T599
Test name
Test status
Simulation time 52767179 ps
CPU time 1.17 seconds
Started Jun 02 01:09:10 PM PDT 24
Finished Jun 02 01:09:11 PM PDT 24
Peak memory 197800 kb
Host smart-7a4780da-e090-446c-b9e8-619406421ae0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695017372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3695017372
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3751798338
Short name T720
Test name
Test status
Simulation time 159047618 ps
CPU time 3.23 seconds
Started Jun 02 01:09:10 PM PDT 24
Finished Jun 02 01:09:13 PM PDT 24
Peak memory 199380 kb
Host smart-e9d8a81a-dc67-4022-aadb-ad98532e2cdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751798338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3751798338
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3043771130
Short name T707
Test name
Test status
Simulation time 176687710 ps
CPU time 2.16 seconds
Started Jun 02 01:09:09 PM PDT 24
Finished Jun 02 01:09:12 PM PDT 24
Peak memory 199336 kb
Host smart-9f6eb68d-9b20-4dbe-a35e-f3fe955ccfa7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043771130 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3043771130
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.518981164
Short name T89
Test name
Test status
Simulation time 47136532 ps
CPU time 0.86 seconds
Started Jun 02 01:09:09 PM PDT 24
Finished Jun 02 01:09:10 PM PDT 24
Peak memory 199052 kb
Host smart-7c2e9bc2-6038-446c-845e-41d5f477c0a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518981164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.518981164
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.2840885871
Short name T717
Test name
Test status
Simulation time 31346507 ps
CPU time 0.6 seconds
Started Jun 02 01:09:10 PM PDT 24
Finished Jun 02 01:09:11 PM PDT 24
Peak memory 194132 kb
Host smart-a154272b-1ccb-4946-bd4d-c54160d1c0c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840885871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2840885871
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2279540367
Short name T701
Test name
Test status
Simulation time 90810731 ps
CPU time 2.18 seconds
Started Jun 02 01:09:09 PM PDT 24
Finished Jun 02 01:09:11 PM PDT 24
Peak memory 199328 kb
Host smart-08897bfb-52bd-4f59-95d6-0a530cfe3925
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279540367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.2279540367
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3181585942
Short name T608
Test name
Test status
Simulation time 110555568 ps
CPU time 1.47 seconds
Started Jun 02 01:09:11 PM PDT 24
Finished Jun 02 01:09:13 PM PDT 24
Peak memory 199360 kb
Host smart-7a4f5ce4-e7b7-4370-b8cf-cfc586f61861
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181585942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3181585942
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2178185400
Short name T604
Test name
Test status
Simulation time 115635840 ps
CPU time 1.37 seconds
Started Jun 02 01:09:15 PM PDT 24
Finished Jun 02 01:09:16 PM PDT 24
Peak memory 199356 kb
Host smart-bbe47264-d26d-4fd5-8c3d-3c3cfb9c8976
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178185400 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2178185400
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3339425824
Short name T635
Test name
Test status
Simulation time 20835497 ps
CPU time 0.89 seconds
Started Jun 02 01:09:15 PM PDT 24
Finished Jun 02 01:09:16 PM PDT 24
Peak memory 199032 kb
Host smart-322330d5-cfaf-4b1c-afec-5e27f74eea8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339425824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3339425824
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1819887899
Short name T620
Test name
Test status
Simulation time 13036916 ps
CPU time 0.58 seconds
Started Jun 02 01:09:15 PM PDT 24
Finished Jun 02 01:09:16 PM PDT 24
Peak memory 194016 kb
Host smart-dd42b929-b13c-4410-8d85-c32321c7c430
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819887899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1819887899
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.224752702
Short name T660
Test name
Test status
Simulation time 46055274 ps
CPU time 2.16 seconds
Started Jun 02 01:09:15 PM PDT 24
Finished Jun 02 01:09:18 PM PDT 24
Peak memory 199080 kb
Host smart-4c6958f1-2ec1-4adc-8445-3609b3f77c1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224752702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.224752702
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2170318024
Short name T663
Test name
Test status
Simulation time 814830993 ps
CPU time 4.22 seconds
Started Jun 02 01:09:10 PM PDT 24
Finished Jun 02 01:09:15 PM PDT 24
Peak memory 199368 kb
Host smart-6221fdc3-32e0-4767-9239-5d6f9d30f5c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170318024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2170318024
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.4135507871
Short name T123
Test name
Test status
Simulation time 1109326917 ps
CPU time 4.39 seconds
Started Jun 02 01:09:08 PM PDT 24
Finished Jun 02 01:09:13 PM PDT 24
Peak memory 199324 kb
Host smart-d11465c7-4e9a-4b57-87a3-5e144347730f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135507871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.4135507871
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2731423405
Short name T191
Test name
Test status
Simulation time 12946066 ps
CPU time 0.63 seconds
Started Jun 02 12:20:37 PM PDT 24
Finished Jun 02 12:20:38 PM PDT 24
Peak memory 195068 kb
Host smart-368a8389-e966-4188-95a1-d02ed5d3eba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731423405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2731423405
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.1897528291
Short name T592
Test name
Test status
Simulation time 838341943 ps
CPU time 13.59 seconds
Started Jun 02 12:25:07 PM PDT 24
Finished Jun 02 12:25:21 PM PDT 24
Peak memory 198988 kb
Host smart-4fbb0dc1-8388-41cc-a61c-c7400878cc0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1897528291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.1897528291
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.61983311
Short name T119
Test name
Test status
Simulation time 15470758041 ps
CPU time 66.52 seconds
Started Jun 02 12:25:18 PM PDT 24
Finished Jun 02 12:26:27 PM PDT 24
Peak memory 198952 kb
Host smart-b1f9e199-7dc8-4250-a6ba-d9efb4cea2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61983311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.61983311
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.3192941528
Short name T353
Test name
Test status
Simulation time 14471022883 ps
CPU time 752.28 seconds
Started Jun 02 12:22:19 PM PDT 24
Finished Jun 02 12:34:52 PM PDT 24
Peak memory 742560 kb
Host smart-02869449-4213-4826-ae8e-ee5c7d83ad8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3192941528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3192941528
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.3826673644
Short name T319
Test name
Test status
Simulation time 8828576148 ps
CPU time 116.84 seconds
Started Jun 02 12:25:19 PM PDT 24
Finished Jun 02 12:27:17 PM PDT 24
Peak memory 198944 kb
Host smart-ad8249d5-5299-46a2-a997-77096211f406
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826673644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.3826673644
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3546428903
Short name T281
Test name
Test status
Simulation time 10706680806 ps
CPU time 36.5 seconds
Started Jun 02 12:20:58 PM PDT 24
Finished Jun 02 12:21:35 PM PDT 24
Peak memory 199968 kb
Host smart-3b211b98-bfb1-4be3-9497-e4045159747f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546428903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3546428903
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2740541287
Short name T30
Test name
Test status
Simulation time 88474046 ps
CPU time 1.1 seconds
Started Jun 02 12:22:01 PM PDT 24
Finished Jun 02 12:22:02 PM PDT 24
Peak memory 219364 kb
Host smart-cf7ec1c2-12ce-467c-bbeb-accab886874c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740541287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2740541287
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.2173184424
Short name T396
Test name
Test status
Simulation time 236105631 ps
CPU time 4.56 seconds
Started Jun 02 12:24:27 PM PDT 24
Finished Jun 02 12:24:32 PM PDT 24
Peak memory 199592 kb
Host smart-ff914a96-5d16-42a8-b415-92995a3c34ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173184424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2173184424
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3359489578
Short name T371
Test name
Test status
Simulation time 332441638064 ps
CPU time 3198.9 seconds
Started Jun 02 12:25:18 PM PDT 24
Finished Jun 02 01:18:40 PM PDT 24
Peak memory 724860 kb
Host smart-c59e6592-b6ad-41a7-8aa6-f493af0c22b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359489578 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3359489578
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.4133327543
Short name T48
Test name
Test status
Simulation time 63393739 ps
CPU time 1.35 seconds
Started Jun 02 12:24:34 PM PDT 24
Finished Jun 02 12:24:36 PM PDT 24
Peak memory 199808 kb
Host smart-47c762dc-2a73-4ff5-abb4-76a9d15202f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133327543 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.4133327543
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.2484450656
Short name T168
Test name
Test status
Simulation time 12110979468 ps
CPU time 442.93 seconds
Started Jun 02 12:25:08 PM PDT 24
Finished Jun 02 12:32:32 PM PDT 24
Peak memory 199688 kb
Host smart-e48b9341-39d5-4344-9fe5-46767dfed1a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484450656 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.2484450656
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.255469234
Short name T424
Test name
Test status
Simulation time 3575994925 ps
CPU time 24.21 seconds
Started Jun 02 12:24:29 PM PDT 24
Finished Jun 02 12:24:54 PM PDT 24
Peak memory 199580 kb
Host smart-f8f60f6b-189f-45ed-86a9-8f22147a8947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255469234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.255469234
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.814824043
Short name T65
Test name
Test status
Simulation time 13596950 ps
CPU time 0.56 seconds
Started Jun 02 12:36:14 PM PDT 24
Finished Jun 02 12:36:16 PM PDT 24
Peak memory 195512 kb
Host smart-45f3abbd-e897-41d1-89e0-1635d7b8a6a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814824043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.814824043
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3248682837
Short name T377
Test name
Test status
Simulation time 386766948 ps
CPU time 17.66 seconds
Started Jun 02 12:24:47 PM PDT 24
Finished Jun 02 12:25:05 PM PDT 24
Peak memory 215596 kb
Host smart-656d5df9-3a32-4357-82dc-1cddbfde73c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3248682837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3248682837
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3663632248
Short name T200
Test name
Test status
Simulation time 10553861685 ps
CPU time 45.35 seconds
Started Jun 02 12:24:10 PM PDT 24
Finished Jun 02 12:24:56 PM PDT 24
Peak memory 199220 kb
Host smart-c8e5a3c3-850a-4f03-8088-b8396e1bc576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663632248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3663632248
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3437128906
Short name T394
Test name
Test status
Simulation time 552295208 ps
CPU time 119.44 seconds
Started Jun 02 12:20:57 PM PDT 24
Finished Jun 02 12:22:57 PM PDT 24
Peak memory 450432 kb
Host smart-2ec33412-7fab-43e0-b9b3-11cfb9428282
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3437128906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3437128906
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3855013132
Short name T446
Test name
Test status
Simulation time 1979531262 ps
CPU time 108.98 seconds
Started Jun 02 12:36:03 PM PDT 24
Finished Jun 02 12:37:52 PM PDT 24
Peak memory 199900 kb
Host smart-67ca62c9-148e-4051-bea1-ee0fc3412c06
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855013132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3855013132
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.876338662
Short name T570
Test name
Test status
Simulation time 1194620665 ps
CPU time 17.15 seconds
Started Jun 02 12:23:35 PM PDT 24
Finished Jun 02 12:23:52 PM PDT 24
Peak memory 199932 kb
Host smart-3ffd626b-2386-406a-ada2-b29fc8f2fb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876338662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.876338662
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1677354126
Short name T31
Test name
Test status
Simulation time 61994477 ps
CPU time 0.76 seconds
Started Jun 02 12:36:10 PM PDT 24
Finished Jun 02 12:36:12 PM PDT 24
Peak memory 218280 kb
Host smart-f171c999-a0e9-487b-9fad-05ff3d00986f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677354126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1677354126
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.1116678289
Short name T375
Test name
Test status
Simulation time 46176449 ps
CPU time 0.65 seconds
Started Jun 02 12:25:08 PM PDT 24
Finished Jun 02 12:25:09 PM PDT 24
Peak memory 196088 kb
Host smart-183be025-1927-41e2-b045-969196307325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116678289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1116678289
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.3433498162
Short name T189
Test name
Test status
Simulation time 208294448 ps
CPU time 1.33 seconds
Started Jun 02 12:36:15 PM PDT 24
Finished Jun 02 12:36:18 PM PDT 24
Peak memory 199140 kb
Host smart-2684ddf6-c504-45c0-8813-070a85669f33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433498162 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.3433498162
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.3321830493
Short name T178
Test name
Test status
Simulation time 52424126994 ps
CPU time 433.33 seconds
Started Jun 02 12:36:05 PM PDT 24
Finished Jun 02 12:43:19 PM PDT 24
Peak memory 199916 kb
Host smart-4e1b054a-15cf-4b6f-8f87-10c75367a2f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321830493 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.3321830493
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1834752839
Short name T228
Test name
Test status
Simulation time 4130027949 ps
CPU time 72.69 seconds
Started Jun 02 12:36:14 PM PDT 24
Finished Jun 02 12:37:27 PM PDT 24
Peak memory 200244 kb
Host smart-2ba69cea-4fd7-486f-b607-64ab7491418c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834752839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1834752839
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.1285590212
Short name T323
Test name
Test status
Simulation time 34045247 ps
CPU time 0.63 seconds
Started Jun 02 12:36:38 PM PDT 24
Finished Jun 02 12:36:44 PM PDT 24
Peak memory 195776 kb
Host smart-c3557bb1-5c95-4057-a5bc-f7a076962fd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285590212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1285590212
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.4028735613
Short name T318
Test name
Test status
Simulation time 5774567756 ps
CPU time 72.91 seconds
Started Jun 02 12:36:42 PM PDT 24
Finished Jun 02 12:37:55 PM PDT 24
Peak memory 232624 kb
Host smart-97121164-36c8-4662-ba3c-5ab38488154c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4028735613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.4028735613
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.3380625153
Short name T118
Test name
Test status
Simulation time 30810268245 ps
CPU time 44.65 seconds
Started Jun 02 12:36:13 PM PDT 24
Finished Jun 02 12:36:58 PM PDT 24
Peak memory 199964 kb
Host smart-0c160a17-765c-40b5-810e-0b683400f089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380625153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3380625153
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.3826916839
Short name T499
Test name
Test status
Simulation time 5263542174 ps
CPU time 460.36 seconds
Started Jun 02 12:36:21 PM PDT 24
Finished Jun 02 12:44:02 PM PDT 24
Peak memory 690804 kb
Host smart-6cb101d8-b882-485d-b699-0fce89880035
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3826916839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.3826916839
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.871080743
Short name T379
Test name
Test status
Simulation time 63277810238 ps
CPU time 123.39 seconds
Started Jun 02 12:36:39 PM PDT 24
Finished Jun 02 12:38:43 PM PDT 24
Peak memory 199944 kb
Host smart-a198bb1d-07db-4374-b38b-e1e230ecc078
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871080743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.871080743
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.1109499416
Short name T467
Test name
Test status
Simulation time 5411707599 ps
CPU time 82.4 seconds
Started Jun 02 12:36:29 PM PDT 24
Finished Jun 02 12:37:51 PM PDT 24
Peak memory 200028 kb
Host smart-8f9725be-9cdc-457e-8e0c-9f71dac5031f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109499416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1109499416
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1139258385
Short name T455
Test name
Test status
Simulation time 93347036 ps
CPU time 2.97 seconds
Started Jun 02 12:36:31 PM PDT 24
Finished Jun 02 12:36:34 PM PDT 24
Peak memory 199868 kb
Host smart-f06e409e-6f21-429f-b4da-07ea91ef23f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139258385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1139258385
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.38616673
Short name T574
Test name
Test status
Simulation time 21411677097 ps
CPU time 1460.62 seconds
Started Jun 02 12:36:27 PM PDT 24
Finished Jun 02 01:00:48 PM PDT 24
Peak memory 681456 kb
Host smart-680c1f4b-f57a-4c20-91ee-f7a76cefcfdf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38616673 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.38616673
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.1010073560
Short name T223
Test name
Test status
Simulation time 31460227 ps
CPU time 1.1 seconds
Started Jun 02 12:36:30 PM PDT 24
Finished Jun 02 12:36:31 PM PDT 24
Peak memory 199944 kb
Host smart-4b594cc6-997d-41c5-ab53-38f171b2e17c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010073560 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.1010073560
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.1332983753
Short name T408
Test name
Test status
Simulation time 38023640759 ps
CPU time 488.98 seconds
Started Jun 02 12:36:39 PM PDT 24
Finished Jun 02 12:44:49 PM PDT 24
Peak memory 199908 kb
Host smart-aa2861ee-d16d-4611-be37-f9545312e36a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332983753 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.1332983753
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.4229286471
Short name T160
Test name
Test status
Simulation time 13256376932 ps
CPU time 47.88 seconds
Started Jun 02 12:36:33 PM PDT 24
Finished Jun 02 12:37:22 PM PDT 24
Peak memory 200004 kb
Host smart-95f1bffe-269c-4e53-9b55-be9c3bf9a54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229286471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.4229286471
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2819095717
Short name T363
Test name
Test status
Simulation time 22842365 ps
CPU time 0.59 seconds
Started Jun 02 12:36:38 PM PDT 24
Finished Jun 02 12:36:39 PM PDT 24
Peak memory 196464 kb
Host smart-6c0e4f79-7cf4-438d-8f6c-4ccd1689305f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819095717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2819095717
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1863541489
Short name T18
Test name
Test status
Simulation time 788584665 ps
CPU time 13.4 seconds
Started Jun 02 12:36:48 PM PDT 24
Finished Jun 02 12:37:02 PM PDT 24
Peak memory 225032 kb
Host smart-2a4afc8e-8a2a-4c02-950f-6e476336dfa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1863541489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1863541489
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.1662462350
Short name T259
Test name
Test status
Simulation time 3573808189 ps
CPU time 15.06 seconds
Started Jun 02 12:36:43 PM PDT 24
Finished Jun 02 12:36:58 PM PDT 24
Peak memory 200016 kb
Host smart-3275aeb7-9a0e-4557-a3a6-5c34a0956cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662462350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1662462350
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1246484911
Short name T243
Test name
Test status
Simulation time 3006162321 ps
CPU time 875.75 seconds
Started Jun 02 12:36:31 PM PDT 24
Finished Jun 02 12:51:07 PM PDT 24
Peak memory 727112 kb
Host smart-e8cd8b39-011e-450f-ac0a-bd1fa7b81e86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1246484911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1246484911
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1463064936
Short name T542
Test name
Test status
Simulation time 26367038437 ps
CPU time 111.68 seconds
Started Jun 02 12:36:28 PM PDT 24
Finished Jun 02 12:38:21 PM PDT 24
Peak memory 200044 kb
Host smart-f65fa133-12d6-41dc-b881-f1cdd3668870
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463064936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1463064936
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2129381196
Short name T320
Test name
Test status
Simulation time 15709701020 ps
CPU time 70.09 seconds
Started Jun 02 12:36:44 PM PDT 24
Finished Jun 02 12:37:55 PM PDT 24
Peak memory 199968 kb
Host smart-4fc4a70d-2dae-4ddb-b16f-7fe20683ccba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129381196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2129381196
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.417704675
Short name T425
Test name
Test status
Simulation time 666049106 ps
CPU time 5.84 seconds
Started Jun 02 12:36:36 PM PDT 24
Finished Jun 02 12:36:43 PM PDT 24
Peak memory 199968 kb
Host smart-73fe62c7-2f73-44fe-810d-b856a64ac206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417704675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.417704675
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.1425779117
Short name T280
Test name
Test status
Simulation time 46545758559 ps
CPU time 1688.79 seconds
Started Jun 02 12:36:23 PM PDT 24
Finished Jun 02 01:04:32 PM PDT 24
Peak memory 705636 kb
Host smart-68383637-f27f-43cf-ae4c-b1f5ea0f2acc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425779117 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1425779117
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.1847418721
Short name T391
Test name
Test status
Simulation time 33806069 ps
CPU time 1.34 seconds
Started Jun 02 12:36:42 PM PDT 24
Finished Jun 02 12:36:44 PM PDT 24
Peak memory 199616 kb
Host smart-0b213c42-f64a-4ed0-99b4-fbf26b890212
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847418721 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.1847418721
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.1916601548
Short name T7
Test name
Test status
Simulation time 10517292893 ps
CPU time 385.58 seconds
Started Jun 02 12:36:43 PM PDT 24
Finished Jun 02 12:43:09 PM PDT 24
Peak memory 199908 kb
Host smart-14cd6da0-7c73-4c3b-bdef-4d7d008b7935
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916601548 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.1916601548
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.3847393578
Short name T1
Test name
Test status
Simulation time 443159865 ps
CPU time 8.68 seconds
Started Jun 02 12:36:28 PM PDT 24
Finished Jun 02 12:36:37 PM PDT 24
Peak memory 199916 kb
Host smart-e9b66859-87bd-48a9-a80a-efec15e107de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847393578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3847393578
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.2996933464
Short name T531
Test name
Test status
Simulation time 1687563749 ps
CPU time 41.24 seconds
Started Jun 02 12:36:28 PM PDT 24
Finished Jun 02 12:37:10 PM PDT 24
Peak memory 224536 kb
Host smart-7a450ccb-cfe2-4684-8187-2629e597a9d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2996933464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.2996933464
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1999002354
Short name T445
Test name
Test status
Simulation time 9856319655 ps
CPU time 38.34 seconds
Started Jun 02 12:36:33 PM PDT 24
Finished Jun 02 12:37:12 PM PDT 24
Peak memory 200008 kb
Host smart-5fbcca0b-4628-41e0-9071-a49590c1d2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999002354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1999002354
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.2714643956
Short name T518
Test name
Test status
Simulation time 12243146040 ps
CPU time 277.77 seconds
Started Jun 02 12:36:25 PM PDT 24
Finished Jun 02 12:41:04 PM PDT 24
Peak memory 382832 kb
Host smart-0210984a-b2f1-417b-83fe-b104f599c838
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2714643956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2714643956
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2365771893
Short name T456
Test name
Test status
Simulation time 84448404247 ps
CPU time 126.36 seconds
Started Jun 02 12:36:34 PM PDT 24
Finished Jun 02 12:38:40 PM PDT 24
Peak memory 199956 kb
Host smart-2f5c416b-1765-4c0d-af2b-64eecc871285
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365771893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2365771893
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1583716840
Short name T301
Test name
Test status
Simulation time 1445851568 ps
CPU time 40.92 seconds
Started Jun 02 12:36:29 PM PDT 24
Finished Jun 02 12:37:10 PM PDT 24
Peak memory 199860 kb
Host smart-4c90e357-4ee5-4764-b206-8f33c30f2dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583716840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1583716840
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1231549996
Short name T240
Test name
Test status
Simulation time 137730899 ps
CPU time 2.77 seconds
Started Jun 02 12:36:34 PM PDT 24
Finished Jun 02 12:36:37 PM PDT 24
Peak memory 199928 kb
Host smart-29372681-107b-40ad-a511-055ff9b20610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231549996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1231549996
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.2616215759
Short name T182
Test name
Test status
Simulation time 52457289776 ps
CPU time 737.08 seconds
Started Jun 02 12:36:31 PM PDT 24
Finished Jun 02 12:48:48 PM PDT 24
Peak memory 208172 kb
Host smart-7a087294-72d6-49fd-a777-8895595f077a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616215759 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2616215759
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.2479712930
Short name T183
Test name
Test status
Simulation time 57063946 ps
CPU time 1.12 seconds
Started Jun 02 12:36:32 PM PDT 24
Finished Jun 02 12:36:34 PM PDT 24
Peak memory 199980 kb
Host smart-273a4261-a7fa-4bbe-9b97-537aa6b51b29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479712930 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.2479712930
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.1846456084
Short name T145
Test name
Test status
Simulation time 8573115716 ps
CPU time 458.13 seconds
Started Jun 02 12:36:28 PM PDT 24
Finished Jun 02 12:44:07 PM PDT 24
Peak memory 199916 kb
Host smart-7c98f56d-5887-4bb0-b192-62c605a4d792
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846456084 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.1846456084
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3491907253
Short name T354
Test name
Test status
Simulation time 10498426929 ps
CPU time 50.05 seconds
Started Jun 02 12:36:53 PM PDT 24
Finished Jun 02 12:37:44 PM PDT 24
Peak memory 200008 kb
Host smart-00dddf68-d66d-469d-928f-9e7e1e985920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491907253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3491907253
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3408195489
Short name T278
Test name
Test status
Simulation time 11431553 ps
CPU time 0.6 seconds
Started Jun 02 12:36:37 PM PDT 24
Finished Jun 02 12:36:38 PM PDT 24
Peak memory 195756 kb
Host smart-2d3a880a-5096-4f88-959b-53be1d77701a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408195489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3408195489
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1060555497
Short name T45
Test name
Test status
Simulation time 2901630679 ps
CPU time 49.08 seconds
Started Jun 02 12:36:32 PM PDT 24
Finished Jun 02 12:37:21 PM PDT 24
Peak memory 227616 kb
Host smart-88926755-ad26-4b92-91b3-aac20ffaacb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1060555497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1060555497
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.172689151
Short name T331
Test name
Test status
Simulation time 3429813734 ps
CPU time 66.47 seconds
Started Jun 02 12:36:28 PM PDT 24
Finished Jun 02 12:37:35 PM PDT 24
Peak memory 200020 kb
Host smart-29a82cea-84a9-49e7-8b37-9fb358e9567a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172689151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.172689151
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.3221509953
Short name T247
Test name
Test status
Simulation time 8792298620 ps
CPU time 417.17 seconds
Started Jun 02 12:36:32 PM PDT 24
Finished Jun 02 12:43:30 PM PDT 24
Peak memory 515728 kb
Host smart-fdbf350b-a970-4065-9c0d-310d58c74d97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3221509953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.3221509953
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.1057681134
Short name T401
Test name
Test status
Simulation time 4240222661 ps
CPU time 55.28 seconds
Started Jun 02 12:36:46 PM PDT 24
Finished Jun 02 12:37:42 PM PDT 24
Peak memory 199980 kb
Host smart-3ac2ba15-bed4-4d2b-8aaa-0c4fa5d4c3bc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057681134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1057681134
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2670078466
Short name T414
Test name
Test status
Simulation time 8091118337 ps
CPU time 75.85 seconds
Started Jun 02 12:36:23 PM PDT 24
Finished Jun 02 12:37:40 PM PDT 24
Peak memory 199968 kb
Host smart-49931d96-97d5-4819-969e-c4176fd7fd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670078466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2670078466
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.565966916
Short name T311
Test name
Test status
Simulation time 67129005 ps
CPU time 0.96 seconds
Started Jun 02 12:36:33 PM PDT 24
Finished Jun 02 12:36:35 PM PDT 24
Peak memory 198988 kb
Host smart-14d63679-eace-4b9a-b5f7-e64b3f8990eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565966916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.565966916
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.3813576615
Short name T528
Test name
Test status
Simulation time 580167811918 ps
CPU time 3814.28 seconds
Started Jun 02 12:36:49 PM PDT 24
Finished Jun 02 01:40:25 PM PDT 24
Peak memory 814940 kb
Host smart-d9731040-b639-4e89-b38d-65d30e0ceaf8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813576615 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3813576615
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.3648177055
Short name T486
Test name
Test status
Simulation time 155696758 ps
CPU time 1.2 seconds
Started Jun 02 12:36:32 PM PDT 24
Finished Jun 02 12:36:34 PM PDT 24
Peak memory 199944 kb
Host smart-aaf5081a-e0c3-43a1-9d6e-6d8aa9ba1c79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648177055 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.3648177055
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.115798542
Short name T368
Test name
Test status
Simulation time 100862464321 ps
CPU time 463.03 seconds
Started Jun 02 12:36:42 PM PDT 24
Finished Jun 02 12:44:26 PM PDT 24
Peak memory 199928 kb
Host smart-e46392fa-a890-4e14-bba4-2ea41d95ffed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115798542 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.115798542
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.274563053
Short name T218
Test name
Test status
Simulation time 32240517662 ps
CPU time 99.87 seconds
Started Jun 02 12:36:43 PM PDT 24
Finished Jun 02 12:38:24 PM PDT 24
Peak memory 199924 kb
Host smart-c23423c6-e350-4c9c-83b8-51db0aecc7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274563053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.274563053
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/136.hmac_stress_all_with_rand_reset.1404845484
Short name T26
Test name
Test status
Simulation time 151725980111 ps
CPU time 4841.16 seconds
Started Jun 02 12:37:41 PM PDT 24
Finished Jun 02 01:58:23 PM PDT 24
Peak memory 772160 kb
Host smart-9b712457-150c-42b0-b7ff-99c1151bd8fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1404845484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.hmac_stress_all_with_rand_reset.1404845484
Directory /workspace/136.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2868641048
Short name T403
Test name
Test status
Simulation time 64746083 ps
CPU time 0.56 seconds
Started Jun 02 12:36:37 PM PDT 24
Finished Jun 02 12:36:38 PM PDT 24
Peak memory 196528 kb
Host smart-4ebe3468-3929-4676-8550-d841d60b6fdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868641048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2868641048
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1685470456
Short name T275
Test name
Test status
Simulation time 662264831 ps
CPU time 28.78 seconds
Started Jun 02 12:36:42 PM PDT 24
Finished Jun 02 12:37:11 PM PDT 24
Peak memory 208092 kb
Host smart-5c0d60e1-afff-4813-9ea0-4a1067dc1672
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1685470456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1685470456
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2795941328
Short name T469
Test name
Test status
Simulation time 1907561213 ps
CPU time 29.87 seconds
Started Jun 02 12:36:42 PM PDT 24
Finished Jun 02 12:37:13 PM PDT 24
Peak memory 199948 kb
Host smart-9f46e29f-8ae8-4ec6-abce-4b5f3470bf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795941328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2795941328
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.640247730
Short name T367
Test name
Test status
Simulation time 4445711839 ps
CPU time 370.51 seconds
Started Jun 02 12:36:35 PM PDT 24
Finished Jun 02 12:42:46 PM PDT 24
Peak memory 644736 kb
Host smart-689b493e-8d84-49b7-829a-60753bc9a902
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=640247730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.640247730
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.2249105949
Short name T447
Test name
Test status
Simulation time 714279231 ps
CPU time 3.34 seconds
Started Jun 02 12:36:48 PM PDT 24
Finished Jun 02 12:36:52 PM PDT 24
Peak memory 199828 kb
Host smart-fcc0e8eb-8569-49ac-86e2-1dfe6acf1a8e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249105949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.2249105949
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.3542317213
Short name T406
Test name
Test status
Simulation time 1896226964 ps
CPU time 98.08 seconds
Started Jun 02 12:36:45 PM PDT 24
Finished Jun 02 12:38:24 PM PDT 24
Peak memory 199864 kb
Host smart-7f773ee4-bdc2-445f-afbc-a14ae129427f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542317213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3542317213
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.2707337662
Short name T366
Test name
Test status
Simulation time 409601371 ps
CPU time 4.02 seconds
Started Jun 02 12:36:30 PM PDT 24
Finished Jun 02 12:36:35 PM PDT 24
Peak memory 199920 kb
Host smart-784ab2d8-5c6e-4b3d-88aa-72dcff44948f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707337662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2707337662
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.3357279930
Short name T255
Test name
Test status
Simulation time 18904004586 ps
CPU time 1053.38 seconds
Started Jun 02 12:36:37 PM PDT 24
Finished Jun 02 12:54:14 PM PDT 24
Peak memory 200236 kb
Host smart-cb1315db-bfad-4b5d-b844-9d1c264b7606
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357279930 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3357279930
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.1034511998
Short name T534
Test name
Test status
Simulation time 223956196 ps
CPU time 1.1 seconds
Started Jun 02 12:36:36 PM PDT 24
Finished Jun 02 12:36:38 PM PDT 24
Peak memory 199924 kb
Host smart-1276fdb2-ef0c-4d5c-9951-12d9b2ca8f1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034511998 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.1034511998
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.3663172207
Short name T190
Test name
Test status
Simulation time 37346205803 ps
CPU time 468.67 seconds
Started Jun 02 12:36:30 PM PDT 24
Finished Jun 02 12:44:19 PM PDT 24
Peak memory 199932 kb
Host smart-01a7aabf-0b76-44be-b8f9-ab3600b0b56b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663172207 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.3663172207
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3463372966
Short name T199
Test name
Test status
Simulation time 3017307914 ps
CPU time 17.09 seconds
Started Jun 02 12:36:45 PM PDT 24
Finished Jun 02 12:37:03 PM PDT 24
Peak memory 200004 kb
Host smart-2b341a68-0312-43f7-a624-8f0addad1852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463372966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3463372966
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.2711273981
Short name T22
Test name
Test status
Simulation time 12767190 ps
CPU time 0.57 seconds
Started Jun 02 12:36:30 PM PDT 24
Finished Jun 02 12:36:31 PM PDT 24
Peak memory 195496 kb
Host smart-ac60d0b4-6754-4492-9f29-d1d01a809441
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711273981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2711273981
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1740623199
Short name T462
Test name
Test status
Simulation time 451955512 ps
CPU time 5.47 seconds
Started Jun 02 12:36:30 PM PDT 24
Finished Jun 02 12:36:36 PM PDT 24
Peak memory 199900 kb
Host smart-8bdd366c-16b5-475b-96a1-3a4868c29787
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1740623199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1740623199
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3743372951
Short name T107
Test name
Test status
Simulation time 4111089393 ps
CPU time 1223.35 seconds
Started Jun 02 12:36:40 PM PDT 24
Finished Jun 02 12:57:04 PM PDT 24
Peak memory 756088 kb
Host smart-08d27898-9be4-4dfd-9839-9782d1d5e866
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3743372951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3743372951
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.19004311
Short name T385
Test name
Test status
Simulation time 10540777805 ps
CPU time 143.27 seconds
Started Jun 02 12:36:51 PM PDT 24
Finished Jun 02 12:39:14 PM PDT 24
Peak memory 199940 kb
Host smart-e2ca9d47-0b0e-4234-acbd-c0e947f9398f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19004311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.19004311
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2261610803
Short name T303
Test name
Test status
Simulation time 22109794060 ps
CPU time 40.03 seconds
Started Jun 02 12:36:27 PM PDT 24
Finished Jun 02 12:37:07 PM PDT 24
Peak memory 199992 kb
Host smart-c30ecd6a-b36f-4343-be61-62aa05642540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261610803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2261610803
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2984082161
Short name T81
Test name
Test status
Simulation time 2709125328 ps
CPU time 10.13 seconds
Started Jun 02 12:36:40 PM PDT 24
Finished Jun 02 12:36:51 PM PDT 24
Peak memory 199988 kb
Host smart-b647af62-e6ad-468d-b16f-3e949e3a7f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984082161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2984082161
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.2719077416
Short name T230
Test name
Test status
Simulation time 11840307318 ps
CPU time 663.89 seconds
Started Jun 02 12:36:36 PM PDT 24
Finished Jun 02 12:47:41 PM PDT 24
Peak memory 224560 kb
Host smart-117164bc-fa02-4987-a088-05bc43d6a8cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719077416 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2719077416
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.373017481
Short name T175
Test name
Test status
Simulation time 246579077 ps
CPU time 1.2 seconds
Started Jun 02 12:36:35 PM PDT 24
Finished Jun 02 12:36:36 PM PDT 24
Peak memory 199896 kb
Host smart-b79695a9-923d-4436-a441-b7add8e8d9be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373017481 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_test_hmac_vectors.373017481
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.2161039708
Short name T334
Test name
Test status
Simulation time 55070596519 ps
CPU time 537.9 seconds
Started Jun 02 12:36:39 PM PDT 24
Finished Jun 02 12:45:37 PM PDT 24
Peak memory 199956 kb
Host smart-77b0eebc-5b93-497b-b105-f1681f8a8a4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161039708 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.2161039708
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.971364384
Short name T9
Test name
Test status
Simulation time 1174962149 ps
CPU time 11.1 seconds
Started Jun 02 12:36:32 PM PDT 24
Finished Jun 02 12:36:44 PM PDT 24
Peak memory 199896 kb
Host smart-56303f1f-1c76-4347-880b-fa983f371377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971364384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.971364384
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.112491440
Short name T561
Test name
Test status
Simulation time 115337799 ps
CPU time 0.56 seconds
Started Jun 02 12:36:40 PM PDT 24
Finished Jun 02 12:36:41 PM PDT 24
Peak memory 195112 kb
Host smart-86b98b3b-4c38-4f0c-83c0-142024864c8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112491440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.112491440
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.4182822850
Short name T273
Test name
Test status
Simulation time 2257995889 ps
CPU time 33.24 seconds
Started Jun 02 12:36:54 PM PDT 24
Finished Jun 02 12:37:28 PM PDT 24
Peak memory 228112 kb
Host smart-55278b19-1eed-493d-97f3-36c9bede8893
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4182822850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.4182822850
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1319066235
Short name T451
Test name
Test status
Simulation time 888684828 ps
CPU time 48.76 seconds
Started Jun 02 12:36:41 PM PDT 24
Finished Jun 02 12:37:30 PM PDT 24
Peak memory 199912 kb
Host smart-3fb773de-6616-4790-bc83-847fcc547419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319066235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1319066235
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.26854917
Short name T276
Test name
Test status
Simulation time 871830825 ps
CPU time 211.75 seconds
Started Jun 02 12:36:54 PM PDT 24
Finished Jun 02 12:40:27 PM PDT 24
Peak memory 637580 kb
Host smart-cad51c99-04b2-42e2-be34-50a247cfca9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=26854917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.26854917
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.3952339724
Short name T426
Test name
Test status
Simulation time 899936928 ps
CPU time 49.27 seconds
Started Jun 02 12:36:55 PM PDT 24
Finished Jun 02 12:37:45 PM PDT 24
Peak memory 199896 kb
Host smart-c47676dd-ca64-441f-b540-2f35ecc5e29b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952339724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3952339724
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.4060748171
Short name T444
Test name
Test status
Simulation time 2223117522 ps
CPU time 4.13 seconds
Started Jun 02 12:36:16 PM PDT 24
Finished Jun 02 12:36:25 PM PDT 24
Peak memory 199972 kb
Host smart-5db15005-fbf6-4174-a869-4df73454697c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060748171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.4060748171
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.1344039994
Short name T238
Test name
Test status
Simulation time 333842661 ps
CPU time 4.99 seconds
Started Jun 02 12:36:41 PM PDT 24
Finished Jun 02 12:36:47 PM PDT 24
Peak memory 199976 kb
Host smart-89962e31-9dff-4a96-8f18-198a186e47f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344039994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1344039994
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3432480827
Short name T73
Test name
Test status
Simulation time 119050039383 ps
CPU time 2731.77 seconds
Started Jun 02 12:36:26 PM PDT 24
Finished Jun 02 01:21:59 PM PDT 24
Peak memory 800424 kb
Host smart-d14c0dec-fd5b-454d-a904-f35b8a8fec16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432480827 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3432480827
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.3616834010
Short name T4
Test name
Test status
Simulation time 78710042 ps
CPU time 1.44 seconds
Started Jun 02 12:36:41 PM PDT 24
Finished Jun 02 12:36:43 PM PDT 24
Peak memory 199924 kb
Host smart-531607da-263f-4396-82d5-37e78f7c3e70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616834010 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.3616834010
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.985511150
Short name T194
Test name
Test status
Simulation time 39537408988 ps
CPU time 499.5 seconds
Started Jun 02 12:36:38 PM PDT 24
Finished Jun 02 12:44:58 PM PDT 24
Peak memory 199936 kb
Host smart-31c79830-dd1c-48ea-80ee-cbf45c3f132a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985511150 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.985511150
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1011530608
Short name T340
Test name
Test status
Simulation time 219680568 ps
CPU time 3.82 seconds
Started Jun 02 12:36:40 PM PDT 24
Finished Jun 02 12:36:44 PM PDT 24
Peak memory 199892 kb
Host smart-5f7f3e40-216f-4ebb-9280-4940b813fc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011530608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1011530608
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.754063168
Short name T415
Test name
Test status
Simulation time 17927298 ps
CPU time 0.58 seconds
Started Jun 02 12:36:40 PM PDT 24
Finished Jun 02 12:36:41 PM PDT 24
Peak memory 194780 kb
Host smart-7bdb1421-ac1b-4a5b-965b-57df920a1f14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754063168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.754063168
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2344759484
Short name T584
Test name
Test status
Simulation time 821169998 ps
CPU time 38.93 seconds
Started Jun 02 12:36:44 PM PDT 24
Finished Jun 02 12:37:24 PM PDT 24
Peak memory 219416 kb
Host smart-6df4dcca-9274-43cd-8077-c4f16268ee0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2344759484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2344759484
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.943331655
Short name T321
Test name
Test status
Simulation time 2055209838 ps
CPU time 19.9 seconds
Started Jun 02 12:37:01 PM PDT 24
Finished Jun 02 12:37:22 PM PDT 24
Peak memory 199844 kb
Host smart-465fd42c-cb82-44ff-a152-cbe00685d45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943331655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.943331655
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2915147127
Short name T369
Test name
Test status
Simulation time 1633456079 ps
CPU time 368.64 seconds
Started Jun 02 12:36:46 PM PDT 24
Finished Jun 02 12:42:55 PM PDT 24
Peak memory 491488 kb
Host smart-fc25240d-57f2-4f9b-a071-b2c86ba57edd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2915147127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2915147127
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1780429507
Short name T497
Test name
Test status
Simulation time 4568174575 ps
CPU time 26.04 seconds
Started Jun 02 12:36:37 PM PDT 24
Finished Jun 02 12:37:04 PM PDT 24
Peak memory 199892 kb
Host smart-39f6ccda-7052-4428-9f57-a30f22215ec0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780429507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1780429507
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.1610071845
Short name T302
Test name
Test status
Simulation time 27206572611 ps
CPU time 106.07 seconds
Started Jun 02 12:36:40 PM PDT 24
Finished Jun 02 12:38:26 PM PDT 24
Peak memory 199976 kb
Host smart-551f9d89-e5d6-4bcb-8647-de3ee45f1be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610071845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1610071845
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3933991063
Short name T258
Test name
Test status
Simulation time 286054202 ps
CPU time 1.5 seconds
Started Jun 02 12:36:30 PM PDT 24
Finished Jun 02 12:36:32 PM PDT 24
Peak memory 199844 kb
Host smart-81fd16e5-255d-48d5-a28e-c6f49be7b7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933991063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3933991063
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.1355002109
Short name T438
Test name
Test status
Simulation time 46184240 ps
CPU time 1.25 seconds
Started Jun 02 12:36:53 PM PDT 24
Finished Jun 02 12:36:55 PM PDT 24
Peak memory 199952 kb
Host smart-74bc9f8a-9d37-433d-b4c9-7479bcdc19fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355002109 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.1355002109
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.1138460634
Short name T268
Test name
Test status
Simulation time 35424701390 ps
CPU time 514.37 seconds
Started Jun 02 12:36:40 PM PDT 24
Finished Jun 02 12:45:15 PM PDT 24
Peak memory 199924 kb
Host smart-390eba2d-529c-4b1d-83f7-2fb2dd09909e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138460634 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.1138460634
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3906587073
Short name T404
Test name
Test status
Simulation time 1376711761 ps
CPU time 15.99 seconds
Started Jun 02 12:36:51 PM PDT 24
Finished Jun 02 12:37:07 PM PDT 24
Peak memory 199884 kb
Host smart-29d729c9-0af5-42a1-b9e1-46b8efa16f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906587073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3906587073
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3320194400
Short name T203
Test name
Test status
Simulation time 25686317 ps
CPU time 0.54 seconds
Started Jun 02 12:36:56 PM PDT 24
Finished Jun 02 12:36:57 PM PDT 24
Peak memory 194652 kb
Host smart-d65c1473-b3a8-4db2-8973-1195f7cb7b70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320194400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3320194400
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2977939135
Short name T559
Test name
Test status
Simulation time 651079965 ps
CPU time 15.91 seconds
Started Jun 02 12:36:51 PM PDT 24
Finished Jun 02 12:37:08 PM PDT 24
Peak memory 212376 kb
Host smart-b517c08a-ab8b-4749-8bcd-6572fbc9d69a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2977939135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2977939135
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1538872881
Short name T409
Test name
Test status
Simulation time 640131262 ps
CPU time 8.48 seconds
Started Jun 02 12:36:53 PM PDT 24
Finished Jun 02 12:37:02 PM PDT 24
Peak memory 199804 kb
Host smart-101e4b7a-42a6-4e0a-b0a5-9a8b39cd0cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538872881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1538872881
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2452235624
Short name T484
Test name
Test status
Simulation time 7887530846 ps
CPU time 525.75 seconds
Started Jun 02 12:36:49 PM PDT 24
Finished Jun 02 12:45:35 PM PDT 24
Peak memory 732804 kb
Host smart-2c9e562c-96b9-4289-a6ba-68392472589b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2452235624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2452235624
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.2771829762
Short name T67
Test name
Test status
Simulation time 5826930463 ps
CPU time 103.16 seconds
Started Jun 02 12:36:36 PM PDT 24
Finished Jun 02 12:38:20 PM PDT 24
Peak memory 199956 kb
Host smart-3484ff27-ef32-48f8-954c-50ad52871a25
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771829762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2771829762
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.4238876518
Short name T343
Test name
Test status
Simulation time 1406284549 ps
CPU time 26.96 seconds
Started Jun 02 12:36:41 PM PDT 24
Finished Jun 02 12:37:09 PM PDT 24
Peak memory 199900 kb
Host smart-6e0feb5c-5b12-47e1-b8b4-2e0521236c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238876518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.4238876518
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.878328926
Short name T283
Test name
Test status
Simulation time 52945739 ps
CPU time 1.89 seconds
Started Jun 02 12:36:45 PM PDT 24
Finished Jun 02 12:36:47 PM PDT 24
Peak memory 199964 kb
Host smart-f534798a-ab32-4c76-94fa-392e659755be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878328926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.878328926
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3782022257
Short name T400
Test name
Test status
Simulation time 21107840483 ps
CPU time 201.77 seconds
Started Jun 02 12:36:56 PM PDT 24
Finished Jun 02 12:40:18 PM PDT 24
Peak memory 208248 kb
Host smart-d2b2ed87-3c3a-4064-9029-a1c9b95edeee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782022257 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3782022257
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.3295964718
Short name T288
Test name
Test status
Simulation time 30112157 ps
CPU time 1.06 seconds
Started Jun 02 12:36:47 PM PDT 24
Finished Jun 02 12:36:48 PM PDT 24
Peak memory 200012 kb
Host smart-b9ddf009-5a70-421f-a891-fe944e85c093
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295964718 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.3295964718
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.3655834117
Short name T538
Test name
Test status
Simulation time 28156427819 ps
CPU time 517.98 seconds
Started Jun 02 12:36:54 PM PDT 24
Finished Jun 02 12:45:33 PM PDT 24
Peak memory 199932 kb
Host smart-0a9f2350-aa9b-425a-92d9-eda8bcd74a63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655834117 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.3655834117
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2995661909
Short name T474
Test name
Test status
Simulation time 13504012555 ps
CPU time 96.83 seconds
Started Jun 02 12:36:54 PM PDT 24
Finished Jun 02 12:38:32 PM PDT 24
Peak memory 199992 kb
Host smart-690560e1-605e-4f66-9244-8e76f9e34a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995661909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2995661909
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.413585095
Short name T150
Test name
Test status
Simulation time 13560658 ps
CPU time 0.58 seconds
Started Jun 02 12:36:29 PM PDT 24
Finished Jun 02 12:36:30 PM PDT 24
Peak memory 195816 kb
Host smart-195a945f-debe-4444-8f0b-3ba64da2dd1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413585095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.413585095
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.1761361415
Short name T493
Test name
Test status
Simulation time 375957010 ps
CPU time 15.07 seconds
Started Jun 02 12:36:49 PM PDT 24
Finished Jun 02 12:37:05 PM PDT 24
Peak memory 208104 kb
Host smart-6f47601d-6b46-47b1-b0c3-e5375fbf2b38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1761361415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.1761361415
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2103095078
Short name T480
Test name
Test status
Simulation time 6155247441 ps
CPU time 61.7 seconds
Started Jun 02 12:36:40 PM PDT 24
Finished Jun 02 12:37:43 PM PDT 24
Peak memory 200032 kb
Host smart-f2d3ab81-33aa-48e0-a5b2-f1a818651f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103095078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2103095078
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2747575707
Short name T246
Test name
Test status
Simulation time 807893579 ps
CPU time 84.17 seconds
Started Jun 02 12:36:39 PM PDT 24
Finished Jun 02 12:38:04 PM PDT 24
Peak memory 417696 kb
Host smart-dec4c489-6934-482d-9338-5fd6ab1e7074
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2747575707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2747575707
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3258200174
Short name T166
Test name
Test status
Simulation time 8216302253 ps
CPU time 191.62 seconds
Started Jun 02 12:36:40 PM PDT 24
Finished Jun 02 12:39:52 PM PDT 24
Peak memory 200240 kb
Host smart-2984d929-c661-4d7a-9f84-1edc7f109078
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258200174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3258200174
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.260260610
Short name T252
Test name
Test status
Simulation time 906051337 ps
CPU time 53.03 seconds
Started Jun 02 12:36:40 PM PDT 24
Finished Jun 02 12:37:33 PM PDT 24
Peak memory 200172 kb
Host smart-b3a40665-5286-4b08-bae5-0c3c695d2d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260260610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.260260610
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1002753117
Short name T85
Test name
Test status
Simulation time 225906655 ps
CPU time 4 seconds
Started Jun 02 12:36:53 PM PDT 24
Finished Jun 02 12:36:58 PM PDT 24
Peak memory 199984 kb
Host smart-dab1a434-dd27-42df-970d-11033da7ade3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002753117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1002753117
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.3044326431
Short name T71
Test name
Test status
Simulation time 131035598417 ps
CPU time 3859.26 seconds
Started Jun 02 12:36:38 PM PDT 24
Finished Jun 02 01:40:58 PM PDT 24
Peak memory 784524 kb
Host smart-67da062c-0df0-4e31-b730-7693317fb818
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044326431 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3044326431
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.927516629
Short name T437
Test name
Test status
Simulation time 250273227 ps
CPU time 1.4 seconds
Started Jun 02 12:36:37 PM PDT 24
Finished Jun 02 12:36:39 PM PDT 24
Peak memory 199952 kb
Host smart-41e58b91-add2-4771-90ab-a66bcbaae6ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927516629 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_hmac_vectors.927516629
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.4093699310
Short name T529
Test name
Test status
Simulation time 28573505626 ps
CPU time 499.71 seconds
Started Jun 02 12:36:55 PM PDT 24
Finished Jun 02 12:45:15 PM PDT 24
Peak memory 199920 kb
Host smart-84452ce2-ea5b-43c3-867b-7e8d77e00099
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093699310 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.4093699310
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.767048041
Short name T515
Test name
Test status
Simulation time 27082844761 ps
CPU time 86.55 seconds
Started Jun 02 12:36:55 PM PDT 24
Finished Jun 02 12:38:22 PM PDT 24
Peak memory 199984 kb
Host smart-fafaeed5-3bcc-4106-b6dc-f03d4e0e194c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767048041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.767048041
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/192.hmac_stress_all_with_rand_reset.2051751069
Short name T11
Test name
Test status
Simulation time 15248783615 ps
CPU time 820.52 seconds
Started Jun 02 12:37:52 PM PDT 24
Finished Jun 02 12:51:33 PM PDT 24
Peak memory 475620 kb
Host smart-e635d02d-9c49-4c43-b350-8e923efaaf24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2051751069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.hmac_stress_all_with_rand_reset.2051751069
Directory /workspace/192.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.4076259536
Short name T289
Test name
Test status
Simulation time 19853652 ps
CPU time 0.6 seconds
Started Jun 02 12:36:12 PM PDT 24
Finished Jun 02 12:36:13 PM PDT 24
Peak memory 195792 kb
Host smart-1b672f2a-2fb9-4590-bac3-3261519d3442
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076259536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.4076259536
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.2043101064
Short name T521
Test name
Test status
Simulation time 2500568815 ps
CPU time 27.4 seconds
Started Jun 02 12:36:37 PM PDT 24
Finished Jun 02 12:37:05 PM PDT 24
Peak memory 213292 kb
Host smart-9ac15107-ccc9-4882-b5d8-adb223f029fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2043101064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.2043101064
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2223329182
Short name T237
Test name
Test status
Simulation time 3536840772 ps
CPU time 46.83 seconds
Started Jun 02 12:36:36 PM PDT 24
Finished Jun 02 12:37:24 PM PDT 24
Peak memory 199992 kb
Host smart-2fad12b8-5fbd-4b93-8f19-d7a6cb4925f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223329182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2223329182
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.2828529383
Short name T226
Test name
Test status
Simulation time 33174394260 ps
CPU time 526.12 seconds
Started Jun 02 12:36:17 PM PDT 24
Finished Jun 02 12:45:03 PM PDT 24
Peak memory 681556 kb
Host smart-03532002-e2d1-4858-8b83-0a1746edda5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2828529383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2828529383
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.112736548
Short name T383
Test name
Test status
Simulation time 9154678080 ps
CPU time 37.69 seconds
Started Jun 02 12:36:05 PM PDT 24
Finished Jun 02 12:36:43 PM PDT 24
Peak memory 200004 kb
Host smart-a6837de4-c2fd-4dd1-b58e-1dce435561a2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112736548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.112736548
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.485685734
Short name T374
Test name
Test status
Simulation time 7932392507 ps
CPU time 72.39 seconds
Started Jun 02 12:36:16 PM PDT 24
Finished Jun 02 12:37:28 PM PDT 24
Peak memory 199956 kb
Host smart-9b18ca45-53f7-46f0-a724-9a7f533bbc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485685734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.485685734
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_smoke.1331152726
Short name T576
Test name
Test status
Simulation time 334153048 ps
CPU time 2.99 seconds
Started Jun 02 12:36:01 PM PDT 24
Finished Jun 02 12:36:05 PM PDT 24
Peak memory 199912 kb
Host smart-b648a8f9-77b1-43fa-a2e4-e54fabce0961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331152726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1331152726
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.300460579
Short name T416
Test name
Test status
Simulation time 48919834373 ps
CPU time 1551.7 seconds
Started Jun 02 12:36:24 PM PDT 24
Finished Jun 02 01:02:17 PM PDT 24
Peak memory 200012 kb
Host smart-062061f6-5571-402e-bed7-82c4bf425ec7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300460579 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.300460579
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.1746489695
Short name T564
Test name
Test status
Simulation time 207015008 ps
CPU time 1.34 seconds
Started Jun 02 12:36:22 PM PDT 24
Finished Jun 02 12:36:24 PM PDT 24
Peak memory 199872 kb
Host smart-51614317-2a4e-44b3-bacd-6d7f1c1cd68e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746489695 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.1746489695
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.3160074945
Short name T244
Test name
Test status
Simulation time 80496312009 ps
CPU time 481.72 seconds
Started Jun 02 12:36:10 PM PDT 24
Finished Jun 02 12:44:12 PM PDT 24
Peak memory 199920 kb
Host smart-9a0e6504-c736-4c7b-b212-21e38179e78b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160074945 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.3160074945
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.4029234249
Short name T413
Test name
Test status
Simulation time 24681765150 ps
CPU time 93.92 seconds
Started Jun 02 12:36:23 PM PDT 24
Finished Jun 02 12:37:57 PM PDT 24
Peak memory 199988 kb
Host smart-4e1ecc39-596d-43a0-ade5-e16bda4eb4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029234249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.4029234249
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1756075322
Short name T398
Test name
Test status
Simulation time 50770333 ps
CPU time 0.61 seconds
Started Jun 02 12:36:57 PM PDT 24
Finished Jun 02 12:36:59 PM PDT 24
Peak memory 195804 kb
Host smart-965145a0-298c-4030-8aac-b231694be4b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756075322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1756075322
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1229585991
Short name T40
Test name
Test status
Simulation time 757353272 ps
CPU time 17.73 seconds
Started Jun 02 12:36:32 PM PDT 24
Finished Jun 02 12:36:50 PM PDT 24
Peak memory 215940 kb
Host smart-41f3f63f-fa8b-42b4-843b-e010af1fa88f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1229585991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1229585991
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2010906424
Short name T46
Test name
Test status
Simulation time 5823545327 ps
CPU time 30.26 seconds
Started Jun 02 12:36:58 PM PDT 24
Finished Jun 02 12:37:29 PM PDT 24
Peak memory 199964 kb
Host smart-4a615d18-17ff-4017-9347-591f929f3293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010906424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2010906424
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3478774124
Short name T36
Test name
Test status
Simulation time 16657156048 ps
CPU time 541.75 seconds
Started Jun 02 12:36:52 PM PDT 24
Finished Jun 02 12:45:55 PM PDT 24
Peak memory 719084 kb
Host smart-32a1203f-dc99-497a-99f1-77c58a8b8ed7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3478774124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3478774124
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.602762804
Short name T192
Test name
Test status
Simulation time 34645649201 ps
CPU time 55.01 seconds
Started Jun 02 12:36:39 PM PDT 24
Finished Jun 02 12:37:34 PM PDT 24
Peak memory 199944 kb
Host smart-90b2ee1b-f40f-4602-b0b7-bbc451457ab7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602762804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.602762804
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1846507554
Short name T407
Test name
Test status
Simulation time 7925484199 ps
CPU time 76.22 seconds
Started Jun 02 12:37:05 PM PDT 24
Finished Jun 02 12:38:22 PM PDT 24
Peak memory 199968 kb
Host smart-96202102-cd04-4d74-b069-9caa67e3bf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846507554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1846507554
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1556903
Short name T540
Test name
Test status
Simulation time 672194948 ps
CPU time 8.58 seconds
Started Jun 02 12:37:03 PM PDT 24
Finished Jun 02 12:37:12 PM PDT 24
Peak memory 199936 kb
Host smart-b3c3dd67-1977-4b8a-8c1e-5ea2ed979508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1556903
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.212093174
Short name T299
Test name
Test status
Simulation time 122740103890 ps
CPU time 1941.85 seconds
Started Jun 02 12:36:46 PM PDT 24
Finished Jun 02 01:09:09 PM PDT 24
Peak memory 684092 kb
Host smart-b8d97e04-e705-42c7-a7e7-f4292de02e97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212093174 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.212093174
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.988019276
Short name T197
Test name
Test status
Simulation time 125578514 ps
CPU time 1.39 seconds
Started Jun 02 12:36:47 PM PDT 24
Finished Jun 02 12:36:49 PM PDT 24
Peak memory 199900 kb
Host smart-c4d9ea0a-f217-4cca-809d-804ce6b5e9cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988019276 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_hmac_vectors.988019276
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.1143996693
Short name T297
Test name
Test status
Simulation time 24421431618 ps
CPU time 448.64 seconds
Started Jun 02 12:36:40 PM PDT 24
Finished Jun 02 12:44:10 PM PDT 24
Peak memory 199972 kb
Host smart-51c57916-7398-412e-8ebd-342ccb255eb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143996693 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.1143996693
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.1767227082
Short name T172
Test name
Test status
Simulation time 240250004 ps
CPU time 4.01 seconds
Started Jun 02 12:36:51 PM PDT 24
Finished Jun 02 12:36:56 PM PDT 24
Peak memory 199812 kb
Host smart-bca6e3cf-e2b3-4634-809e-4daafe645332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767227082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1767227082
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1579243208
Short name T587
Test name
Test status
Simulation time 108155817 ps
CPU time 0.6 seconds
Started Jun 02 12:36:42 PM PDT 24
Finished Jun 02 12:36:43 PM PDT 24
Peak memory 195428 kb
Host smart-7fc9b121-8c5b-49a6-952f-f9f22e00b991
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579243208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1579243208
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.4110187368
Short name T253
Test name
Test status
Simulation time 2212339017 ps
CPU time 20.08 seconds
Started Jun 02 12:37:01 PM PDT 24
Finished Jun 02 12:37:21 PM PDT 24
Peak memory 215908 kb
Host smart-82732513-8357-4fe7-a70b-5ea3562eec3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4110187368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.4110187368
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3816262016
Short name T478
Test name
Test status
Simulation time 1910508341 ps
CPU time 13.3 seconds
Started Jun 02 12:36:41 PM PDT 24
Finished Jun 02 12:36:55 PM PDT 24
Peak memory 199880 kb
Host smart-0b20d657-3c8c-4592-a270-20fa075be427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816262016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3816262016
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.542201345
Short name T386
Test name
Test status
Simulation time 6112001877 ps
CPU time 407.65 seconds
Started Jun 02 12:36:45 PM PDT 24
Finished Jun 02 12:43:34 PM PDT 24
Peak memory 624392 kb
Host smart-42e5166b-48d2-4060-b187-b32fdcee1549
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=542201345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.542201345
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3847946108
Short name T376
Test name
Test status
Simulation time 535802018 ps
CPU time 31.69 seconds
Started Jun 02 12:36:55 PM PDT 24
Finished Jun 02 12:37:27 PM PDT 24
Peak memory 199816 kb
Host smart-c54390b1-3ec1-4743-97d2-88a0706e319b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847946108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3847946108
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.424596573
Short name T393
Test name
Test status
Simulation time 4155649458 ps
CPU time 76.99 seconds
Started Jun 02 12:36:53 PM PDT 24
Finished Jun 02 12:38:11 PM PDT 24
Peak memory 200020 kb
Host smart-80480ea3-05f1-434f-a2f1-fb6afc62f7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424596573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.424596573
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.1454353633
Short name T49
Test name
Test status
Simulation time 239379547 ps
CPU time 3.76 seconds
Started Jun 02 12:36:47 PM PDT 24
Finished Jun 02 12:36:51 PM PDT 24
Peak memory 199928 kb
Host smart-7a8188b0-1ba9-4f54-bdfd-edd0142c7062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454353633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.1454353633
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3849972900
Short name T418
Test name
Test status
Simulation time 223786478395 ps
CPU time 906.15 seconds
Started Jun 02 12:36:56 PM PDT 24
Finished Jun 02 12:52:03 PM PDT 24
Peak memory 224564 kb
Host smart-38611954-af24-4e47-be93-a5a011140fd6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849972900 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3849972900
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.1905683010
Short name T567
Test name
Test status
Simulation time 342795414 ps
CPU time 1.36 seconds
Started Jun 02 12:36:42 PM PDT 24
Finished Jun 02 12:36:44 PM PDT 24
Peak memory 199936 kb
Host smart-290c7e4c-9716-47da-9e5f-008e10711842
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905683010 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.1905683010
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.2947458081
Short name T167
Test name
Test status
Simulation time 128903983527 ps
CPU time 503.86 seconds
Started Jun 02 12:36:50 PM PDT 24
Finished Jun 02 12:45:14 PM PDT 24
Peak memory 199932 kb
Host smart-5e999e13-2add-4290-9110-bbb0928add42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947458081 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.2947458081
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.600995453
Short name T225
Test name
Test status
Simulation time 7296508826 ps
CPU time 84.59 seconds
Started Jun 02 12:36:46 PM PDT 24
Finished Jun 02 12:38:11 PM PDT 24
Peak memory 199972 kb
Host smart-83052f8f-c999-487e-85ff-e8ae5e96db14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600995453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.600995453
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3343126877
Short name T83
Test name
Test status
Simulation time 45304725 ps
CPU time 0.58 seconds
Started Jun 02 12:36:55 PM PDT 24
Finished Jun 02 12:36:56 PM PDT 24
Peak memory 195796 kb
Host smart-5ae2ab12-8c07-4caa-ba4d-0398c1989122
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343126877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3343126877
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2293809726
Short name T234
Test name
Test status
Simulation time 867195604 ps
CPU time 19.42 seconds
Started Jun 02 12:36:55 PM PDT 24
Finished Jun 02 12:37:15 PM PDT 24
Peak memory 208116 kb
Host smart-9c72220f-f1dd-42a8-a915-97bc69393270
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2293809726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2293809726
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.3231395053
Short name T62
Test name
Test status
Simulation time 13679103080 ps
CPU time 28.49 seconds
Started Jun 02 12:36:56 PM PDT 24
Finished Jun 02 12:37:25 PM PDT 24
Peak memory 200036 kb
Host smart-15164585-28e9-4a6a-b319-55086a428148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231395053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.3231395053
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1324854940
Short name T433
Test name
Test status
Simulation time 1448794418 ps
CPU time 135.46 seconds
Started Jun 02 12:36:54 PM PDT 24
Finished Jun 02 12:39:10 PM PDT 24
Peak memory 617524 kb
Host smart-0fff6418-e1de-45e5-8e60-6e2ea4c4ddc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1324854940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1324854940
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2848122639
Short name T305
Test name
Test status
Simulation time 6332685802 ps
CPU time 96.61 seconds
Started Jun 02 12:37:09 PM PDT 24
Finished Jun 02 12:38:51 PM PDT 24
Peak memory 199952 kb
Host smart-79b468b5-a58e-4160-8184-f2f56f110630
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848122639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2848122639
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2030582654
Short name T269
Test name
Test status
Simulation time 4142610978 ps
CPU time 57.26 seconds
Started Jun 02 12:36:54 PM PDT 24
Finished Jun 02 12:37:51 PM PDT 24
Peak memory 199984 kb
Host smart-a3cbdfcc-3148-40c1-99be-7fcb4c20de6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030582654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2030582654
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2289544963
Short name T577
Test name
Test status
Simulation time 166195201 ps
CPU time 5.37 seconds
Started Jun 02 12:36:58 PM PDT 24
Finished Jun 02 12:37:04 PM PDT 24
Peak memory 199976 kb
Host smart-d53d0800-716b-40e6-9230-da36b6f4cc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289544963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2289544963
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.4182186637
Short name T27
Test name
Test status
Simulation time 2815416730 ps
CPU time 76.14 seconds
Started Jun 02 12:36:57 PM PDT 24
Finished Jun 02 12:38:14 PM PDT 24
Peak memory 199968 kb
Host smart-dcf903aa-686b-4bae-9d6b-6aac97dc0f26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182186637 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.4182186637
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.491417190
Short name T217
Test name
Test status
Simulation time 64608864 ps
CPU time 1.32 seconds
Started Jun 02 12:36:58 PM PDT 24
Finished Jun 02 12:37:00 PM PDT 24
Peak memory 199856 kb
Host smart-f16d4c98-541b-427c-9f73-52a4c0bd346a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491417190 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_hmac_vectors.491417190
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.3509870303
Short name T87
Test name
Test status
Simulation time 139982379197 ps
CPU time 484.7 seconds
Started Jun 02 12:36:39 PM PDT 24
Finished Jun 02 12:44:45 PM PDT 24
Peak memory 199920 kb
Host smart-5a3e3d44-1c84-467f-bd29-773721d448ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509870303 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.3509870303
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.3021512992
Short name T556
Test name
Test status
Simulation time 4088780429 ps
CPU time 40.28 seconds
Started Jun 02 12:37:09 PM PDT 24
Finished Jun 02 12:37:50 PM PDT 24
Peak memory 199932 kb
Host smart-66df28ab-b121-4dfc-84b3-6432d1d5643d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021512992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3021512992
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.3157118349
Short name T453
Test name
Test status
Simulation time 58297236 ps
CPU time 0.6 seconds
Started Jun 02 12:36:52 PM PDT 24
Finished Jun 02 12:36:53 PM PDT 24
Peak memory 196536 kb
Host smart-6563676e-060b-4fd1-b350-19ea76f7e528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157118349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3157118349
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.723766091
Short name T339
Test name
Test status
Simulation time 1198618374 ps
CPU time 59.14 seconds
Started Jun 02 12:36:50 PM PDT 24
Finished Jun 02 12:37:50 PM PDT 24
Peak memory 240752 kb
Host smart-e8195bff-0206-4cd7-b283-4e7c95fb2475
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=723766091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.723766091
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.414630427
Short name T481
Test name
Test status
Simulation time 1655205772 ps
CPU time 44.85 seconds
Started Jun 02 12:37:09 PM PDT 24
Finished Jun 02 12:37:54 PM PDT 24
Peak memory 200288 kb
Host smart-65ab7e94-27d1-4b01-bdf0-0b7b76017aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414630427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.414630427
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2058112130
Short name T359
Test name
Test status
Simulation time 1295201611 ps
CPU time 24.92 seconds
Started Jun 02 12:36:55 PM PDT 24
Finished Jun 02 12:37:20 PM PDT 24
Peak memory 256512 kb
Host smart-9ed38c95-941b-49c8-ae7d-3b8d3bd3b26b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2058112130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2058112130
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.4202838091
Short name T364
Test name
Test status
Simulation time 16008056783 ps
CPU time 74.97 seconds
Started Jun 02 12:36:45 PM PDT 24
Finished Jun 02 12:38:01 PM PDT 24
Peak memory 200008 kb
Host smart-2f2e8dad-5b7e-4787-995f-0c8b6954bacb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202838091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.4202838091
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1944076119
Short name T519
Test name
Test status
Simulation time 3388723376 ps
CPU time 7.6 seconds
Started Jun 02 12:36:56 PM PDT 24
Finished Jun 02 12:37:05 PM PDT 24
Peak memory 199984 kb
Host smart-7e71789d-57e3-451e-9018-5ea273a825a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944076119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1944076119
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.807943170
Short name T279
Test name
Test status
Simulation time 67865714 ps
CPU time 1.55 seconds
Started Jun 02 12:36:59 PM PDT 24
Finished Jun 02 12:37:01 PM PDT 24
Peak memory 199968 kb
Host smart-a1f0f6c3-ddd3-40fe-aa73-1e3eafd854ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807943170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.807943170
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.2766367255
Short name T24
Test name
Test status
Simulation time 26479426849 ps
CPU time 137.81 seconds
Started Jun 02 12:36:56 PM PDT 24
Finished Jun 02 12:39:15 PM PDT 24
Peak memory 199960 kb
Host smart-ce9bc613-5537-41b2-a1d6-c6284113c48f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766367255 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.2766367255
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.2855491539
Short name T196
Test name
Test status
Simulation time 57154949 ps
CPU time 1.15 seconds
Started Jun 02 12:36:57 PM PDT 24
Finished Jun 02 12:36:59 PM PDT 24
Peak memory 199920 kb
Host smart-3751e14b-cbbf-4fda-8079-be41d6603b39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855491539 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.2855491539
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.1650849624
Short name T537
Test name
Test status
Simulation time 114429551143 ps
CPU time 463.79 seconds
Started Jun 02 12:36:40 PM PDT 24
Finished Jun 02 12:44:25 PM PDT 24
Peak memory 199860 kb
Host smart-1f236690-03a7-44d5-bd2d-db78c723911f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650849624 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.1650849624
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.442663630
Short name T34
Test name
Test status
Simulation time 2448603960 ps
CPU time 22.56 seconds
Started Jun 02 12:37:01 PM PDT 24
Finished Jun 02 12:37:24 PM PDT 24
Peak memory 199916 kb
Host smart-82083729-e445-48d0-8d7c-b80df117511a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442663630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.442663630
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3719341472
Short name T212
Test name
Test status
Simulation time 12280926 ps
CPU time 0.58 seconds
Started Jun 02 12:36:40 PM PDT 24
Finished Jun 02 12:36:41 PM PDT 24
Peak memory 195772 kb
Host smart-80684e3e-baa1-4883-9ea5-9396d2b7a3b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719341472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3719341472
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2399914133
Short name T327
Test name
Test status
Simulation time 395523439 ps
CPU time 23.51 seconds
Started Jun 02 12:36:48 PM PDT 24
Finished Jun 02 12:37:12 PM PDT 24
Peak memory 229616 kb
Host smart-d6166c0e-5780-4081-b1eb-7ba85ae4cb42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2399914133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2399914133
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1090164169
Short name T513
Test name
Test status
Simulation time 5359520631 ps
CPU time 21.69 seconds
Started Jun 02 12:36:47 PM PDT 24
Finished Jun 02 12:37:09 PM PDT 24
Peak memory 199928 kb
Host smart-482c76ea-e984-4a95-8210-512136ac9e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090164169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1090164169
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.294513855
Short name T106
Test name
Test status
Simulation time 3459926797 ps
CPU time 883.29 seconds
Started Jun 02 12:36:42 PM PDT 24
Finished Jun 02 12:51:26 PM PDT 24
Peak memory 730920 kb
Host smart-88f558bc-4fcb-4c71-8bb4-038ebce75416
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=294513855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.294513855
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2464264938
Short name T512
Test name
Test status
Simulation time 797249128 ps
CPU time 41.99 seconds
Started Jun 02 12:37:01 PM PDT 24
Finished Jun 02 12:37:44 PM PDT 24
Peak memory 199916 kb
Host smart-84dd611a-f88d-497d-9e9f-1359f17141ba
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464264938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2464264938
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.4213962845
Short name T202
Test name
Test status
Simulation time 1036392384 ps
CPU time 10.16 seconds
Started Jun 02 12:36:40 PM PDT 24
Finished Jun 02 12:36:51 PM PDT 24
Peak memory 199388 kb
Host smart-fd63c961-e034-4e7e-9730-49a07decfe12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213962845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.4213962845
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1519960114
Short name T583
Test name
Test status
Simulation time 124955962 ps
CPU time 1.19 seconds
Started Jun 02 12:36:55 PM PDT 24
Finished Jun 02 12:36:57 PM PDT 24
Peak memory 199920 kb
Host smart-682975c9-4949-44ae-b969-3c7e3f1bc84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519960114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1519960114
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.850303191
Short name T581
Test name
Test status
Simulation time 124158529703 ps
CPU time 1627.91 seconds
Started Jun 02 12:36:35 PM PDT 24
Finished Jun 02 01:03:43 PM PDT 24
Peak memory 672028 kb
Host smart-4f1836a9-d028-440c-bd0d-8546464097da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850303191 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.850303191
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.1783473379
Short name T563
Test name
Test status
Simulation time 55994237 ps
CPU time 1.05 seconds
Started Jun 02 12:36:45 PM PDT 24
Finished Jun 02 12:36:47 PM PDT 24
Peak memory 199752 kb
Host smart-3e9c9086-81c6-4db6-90d6-ea3f6ddd2735
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783473379 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.1783473379
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.897964611
Short name T337
Test name
Test status
Simulation time 46079596679 ps
CPU time 495.97 seconds
Started Jun 02 12:36:42 PM PDT 24
Finished Jun 02 12:44:59 PM PDT 24
Peak memory 199168 kb
Host smart-e4fa3f8f-e038-48b6-930c-98e045c2f8ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897964611 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.897964611
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.1123761762
Short name T221
Test name
Test status
Simulation time 3074325185 ps
CPU time 59 seconds
Started Jun 02 12:36:44 PM PDT 24
Finished Jun 02 12:37:44 PM PDT 24
Peak memory 200328 kb
Host smart-33c3c0ce-8b4b-4ee9-a42b-5504cb6f9823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123761762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1123761762
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.740009797
Short name T170
Test name
Test status
Simulation time 11081469 ps
CPU time 0.57 seconds
Started Jun 02 12:36:49 PM PDT 24
Finished Jun 02 12:36:50 PM PDT 24
Peak memory 195508 kb
Host smart-bb25ac74-f3a0-48cc-95e3-69f78933dbfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740009797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.740009797
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.4173265616
Short name T595
Test name
Test status
Simulation time 54604746 ps
CPU time 1.38 seconds
Started Jun 02 12:36:57 PM PDT 24
Finished Jun 02 12:36:59 PM PDT 24
Peak memory 199868 kb
Host smart-8c2b8dc5-de7b-4005-ac37-03cc0280e306
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4173265616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.4173265616
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.257043699
Short name T274
Test name
Test status
Simulation time 1472465912 ps
CPU time 77.09 seconds
Started Jun 02 12:36:31 PM PDT 24
Finished Jun 02 12:37:49 PM PDT 24
Peak memory 199924 kb
Host smart-478b654c-cd3d-4ca1-9458-6061e66a4dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257043699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.257043699
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.3212329726
Short name T304
Test name
Test status
Simulation time 2131737061 ps
CPU time 591.34 seconds
Started Jun 02 12:37:02 PM PDT 24
Finished Jun 02 12:46:54 PM PDT 24
Peak memory 650632 kb
Host smart-28b111fd-5c90-4a69-a857-21c2afa8d90e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3212329726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3212329726
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3665383942
Short name T586
Test name
Test status
Simulation time 6334127311 ps
CPU time 103.45 seconds
Started Jun 02 12:36:55 PM PDT 24
Finished Jun 02 12:38:39 PM PDT 24
Peak memory 200004 kb
Host smart-0d159398-a201-4772-a830-6af5c505819c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665383942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3665383942
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2663137467
Short name T241
Test name
Test status
Simulation time 9586603571 ps
CPU time 75.87 seconds
Started Jun 02 12:36:41 PM PDT 24
Finished Jun 02 12:37:58 PM PDT 24
Peak memory 199932 kb
Host smart-622d13e9-f258-46b7-a111-209eab19241f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663137467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2663137467
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2411331399
Short name T187
Test name
Test status
Simulation time 125673435 ps
CPU time 2.3 seconds
Started Jun 02 12:36:48 PM PDT 24
Finished Jun 02 12:36:51 PM PDT 24
Peak memory 199864 kb
Host smart-aa098168-ef1a-4e74-bdd1-d2b44ce1f19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411331399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2411331399
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.465271905
Short name T136
Test name
Test status
Simulation time 1117986857 ps
CPU time 234.9 seconds
Started Jun 02 12:37:05 PM PDT 24
Finished Jun 02 12:41:00 PM PDT 24
Peak memory 651052 kb
Host smart-0e9a3e74-91a2-4bea-bec7-7400566de39c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465271905 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.465271905
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.3711507037
Short name T487
Test name
Test status
Simulation time 90974171 ps
CPU time 1.11 seconds
Started Jun 02 12:36:43 PM PDT 24
Finished Jun 02 12:36:45 PM PDT 24
Peak memory 199500 kb
Host smart-3338a9c8-a27a-41b1-83e0-3218abaf5ec8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711507037 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.3711507037
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.4286567346
Short name T153
Test name
Test status
Simulation time 68630641933 ps
CPU time 484.45 seconds
Started Jun 02 12:36:54 PM PDT 24
Finished Jun 02 12:44:59 PM PDT 24
Peak memory 199976 kb
Host smart-2837f261-aaa9-4aab-bd7c-92c1fc758a8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286567346 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.4286567346
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1895061860
Short name T104
Test name
Test status
Simulation time 10707774979 ps
CPU time 62.94 seconds
Started Jun 02 12:36:58 PM PDT 24
Finished Jun 02 12:38:02 PM PDT 24
Peak memory 199952 kb
Host smart-d788d2f3-4c0b-4995-8f1e-f09a59e312ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895061860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1895061860
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.3375763419
Short name T21
Test name
Test status
Simulation time 18655918 ps
CPU time 0.59 seconds
Started Jun 02 12:37:00 PM PDT 24
Finished Jun 02 12:37:01 PM PDT 24
Peak memory 194780 kb
Host smart-f9ad7ab5-7a5e-4b13-b3e5-cfca44b16dad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375763419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3375763419
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2333439879
Short name T466
Test name
Test status
Simulation time 2196398150 ps
CPU time 37 seconds
Started Jun 02 12:36:56 PM PDT 24
Finished Jun 02 12:37:34 PM PDT 24
Peak memory 226556 kb
Host smart-c6840dfe-856c-4c96-8b78-d778a69ab14a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2333439879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2333439879
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.3202808838
Short name T159
Test name
Test status
Simulation time 3330994244 ps
CPU time 19.05 seconds
Started Jun 02 12:37:03 PM PDT 24
Finished Jun 02 12:37:22 PM PDT 24
Peak memory 200044 kb
Host smart-e3942397-9a32-4e6d-9993-035cb5c7fadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202808838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.3202808838
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1829049441
Short name T501
Test name
Test status
Simulation time 10801016664 ps
CPU time 456.25 seconds
Started Jun 02 12:37:06 PM PDT 24
Finished Jun 02 12:44:43 PM PDT 24
Peak memory 685796 kb
Host smart-6e0246fc-9eb2-4e78-878d-9324b5b072dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1829049441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1829049441
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3483709937
Short name T472
Test name
Test status
Simulation time 27091642943 ps
CPU time 45.12 seconds
Started Jun 02 12:37:14 PM PDT 24
Finished Jun 02 12:37:59 PM PDT 24
Peak memory 199964 kb
Host smart-e38e8680-6187-447c-bcea-4f333008ae0b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483709937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3483709937
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1814464869
Short name T284
Test name
Test status
Simulation time 5199792879 ps
CPU time 79.75 seconds
Started Jun 02 12:36:44 PM PDT 24
Finished Jun 02 12:38:04 PM PDT 24
Peak memory 200032 kb
Host smart-fcfa66a1-edae-46c7-96f9-d90bed33419d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814464869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1814464869
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.657591504
Short name T5
Test name
Test status
Simulation time 205677066 ps
CPU time 3.41 seconds
Started Jun 02 12:36:41 PM PDT 24
Finished Jun 02 12:36:45 PM PDT 24
Peak memory 199888 kb
Host smart-50fee80b-fe75-4002-8485-75a571efafc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657591504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.657591504
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.912299028
Short name T70
Test name
Test status
Simulation time 202969681775 ps
CPU time 1661.32 seconds
Started Jun 02 12:37:10 PM PDT 24
Finished Jun 02 01:04:53 PM PDT 24
Peak memory 796576 kb
Host smart-26256900-4615-4278-b110-6dd2c25b1bdf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912299028 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.912299028
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.165012005
Short name T590
Test name
Test status
Simulation time 152195053 ps
CPU time 1.3 seconds
Started Jun 02 12:36:55 PM PDT 24
Finished Jun 02 12:36:57 PM PDT 24
Peak memory 199912 kb
Host smart-1f83224b-245d-4bbb-a74a-e19a926b7d36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165012005 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_hmac_vectors.165012005
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.1547603970
Short name T242
Test name
Test status
Simulation time 8384601594 ps
CPU time 471.19 seconds
Started Jun 02 12:36:54 PM PDT 24
Finished Jun 02 12:44:45 PM PDT 24
Peak memory 199900 kb
Host smart-644920ea-b937-4bea-80dd-48be8c4f1c68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547603970 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.1547603970
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2855362589
Short name T198
Test name
Test status
Simulation time 967570157 ps
CPU time 19.41 seconds
Started Jun 02 12:36:57 PM PDT 24
Finished Jun 02 12:37:17 PM PDT 24
Peak memory 200288 kb
Host smart-624ce8bc-f9c8-4df7-b706-833f95ed5d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855362589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2855362589
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.3267964206
Short name T236
Test name
Test status
Simulation time 51393885 ps
CPU time 0.57 seconds
Started Jun 02 12:37:13 PM PDT 24
Finished Jun 02 12:37:14 PM PDT 24
Peak memory 195800 kb
Host smart-8c06f7e3-ee4d-4708-804e-f0788b2358b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267964206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3267964206
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2679746674
Short name T500
Test name
Test status
Simulation time 314125167 ps
CPU time 13.54 seconds
Started Jun 02 12:36:56 PM PDT 24
Finished Jun 02 12:37:11 PM PDT 24
Peak memory 208160 kb
Host smart-8f4e63e8-be03-4675-b013-d1c165ba446b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2679746674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2679746674
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.2555518351
Short name T229
Test name
Test status
Simulation time 10589829912 ps
CPU time 50.91 seconds
Started Jun 02 12:37:00 PM PDT 24
Finished Jun 02 12:37:52 PM PDT 24
Peak memory 199940 kb
Host smart-e52dbc31-ec9d-48bd-a1c8-60bed9fdaef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555518351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2555518351
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1096762369
Short name T482
Test name
Test status
Simulation time 12703702625 ps
CPU time 819.77 seconds
Started Jun 02 12:37:01 PM PDT 24
Finished Jun 02 12:50:41 PM PDT 24
Peak memory 715264 kb
Host smart-fa85481d-b115-4427-aeb2-0098ac73a6d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1096762369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1096762369
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.4117090144
Short name T435
Test name
Test status
Simulation time 4696057664 ps
CPU time 89.2 seconds
Started Jun 02 12:37:05 PM PDT 24
Finished Jun 02 12:38:45 PM PDT 24
Peak memory 199936 kb
Host smart-d5586caf-ae73-467f-998f-6b63cc2e5d8b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117090144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.4117090144
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.4170777820
Short name T219
Test name
Test status
Simulation time 5649553619 ps
CPU time 114.21 seconds
Started Jun 02 12:36:35 PM PDT 24
Finished Jun 02 12:38:30 PM PDT 24
Peak memory 200032 kb
Host smart-3ee76403-2f16-4c3e-9bd4-ce44fc0d81c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170777820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.4170777820
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.3238928192
Short name T468
Test name
Test status
Simulation time 1532200259 ps
CPU time 7.83 seconds
Started Jun 02 12:37:09 PM PDT 24
Finished Jun 02 12:37:22 PM PDT 24
Peak memory 199932 kb
Host smart-e0e3d6d2-67e5-4431-82c1-03c68de7dd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238928192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3238928192
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3981739712
Short name T74
Test name
Test status
Simulation time 266438832201 ps
CPU time 2115.11 seconds
Started Jun 02 12:36:52 PM PDT 24
Finished Jun 02 01:12:08 PM PDT 24
Peak memory 446732 kb
Host smart-29bc63a5-6269-41f0-9eef-b6347d39689b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981739712 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3981739712
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.3897208955
Short name T421
Test name
Test status
Simulation time 53478359 ps
CPU time 1.12 seconds
Started Jun 02 12:36:42 PM PDT 24
Finished Jun 02 12:36:44 PM PDT 24
Peak memory 199720 kb
Host smart-5a5e8e1a-6222-4bc6-b639-012415414a66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897208955 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.3897208955
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.3977203595
Short name T439
Test name
Test status
Simulation time 77806445227 ps
CPU time 526.86 seconds
Started Jun 02 12:37:00 PM PDT 24
Finished Jun 02 12:45:47 PM PDT 24
Peak memory 199912 kb
Host smart-ad6424b3-cd23-4dd0-a245-ec878d56e69b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977203595 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.3977203595
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.824375485
Short name T64
Test name
Test status
Simulation time 2151848570 ps
CPU time 41.3 seconds
Started Jun 02 12:37:05 PM PDT 24
Finished Jun 02 12:37:46 PM PDT 24
Peak memory 200044 kb
Host smart-10abc4ae-0f3e-43b9-9247-1071c61aeb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824375485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.824375485
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1643367366
Short name T373
Test name
Test status
Simulation time 12281964 ps
CPU time 0.64 seconds
Started Jun 02 12:37:09 PM PDT 24
Finished Jun 02 12:37:10 PM PDT 24
Peak memory 195804 kb
Host smart-fba869ec-a21f-412b-82aa-33a00cf98915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643367366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1643367366
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1216133740
Short name T344
Test name
Test status
Simulation time 1691332446 ps
CPU time 52.66 seconds
Started Jun 02 12:37:06 PM PDT 24
Finished Jun 02 12:37:59 PM PDT 24
Peak memory 232716 kb
Host smart-45477ac1-68a7-407c-9263-337f9332e2f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1216133740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1216133740
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3150216513
Short name T332
Test name
Test status
Simulation time 592770533 ps
CPU time 5.47 seconds
Started Jun 02 12:37:02 PM PDT 24
Finished Jun 02 12:37:08 PM PDT 24
Peak memory 200240 kb
Host smart-73d25f5e-b7a2-4a42-9f1b-fd0ccf2fa565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150216513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3150216513
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.2330680505
Short name T317
Test name
Test status
Simulation time 3634501504 ps
CPU time 473.9 seconds
Started Jun 02 12:36:54 PM PDT 24
Finished Jun 02 12:44:49 PM PDT 24
Peak memory 642428 kb
Host smart-8bd6afb9-91e2-4c50-91e8-cc0489cc0df5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2330680505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2330680505
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3747583769
Short name T503
Test name
Test status
Simulation time 21137821280 ps
CPU time 151.61 seconds
Started Jun 02 12:36:45 PM PDT 24
Finished Jun 02 12:39:17 PM PDT 24
Peak memory 200004 kb
Host smart-62329fe3-2c54-4342-a490-7fa76d62979a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747583769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3747583769
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2546977112
Short name T402
Test name
Test status
Simulation time 251959230 ps
CPU time 4.04 seconds
Started Jun 02 12:37:26 PM PDT 24
Finished Jun 02 12:37:31 PM PDT 24
Peak memory 199976 kb
Host smart-0ce39931-cbc7-44aa-9394-d4cf876dda3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546977112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2546977112
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1297762895
Short name T502
Test name
Test status
Simulation time 896969964 ps
CPU time 5.16 seconds
Started Jun 02 12:37:12 PM PDT 24
Finished Jun 02 12:37:18 PM PDT 24
Peak memory 199984 kb
Host smart-a2ecf68f-d176-4ed1-a0be-5556d1e6ec6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297762895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1297762895
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.629163665
Short name T184
Test name
Test status
Simulation time 68264344 ps
CPU time 1.03 seconds
Started Jun 02 12:37:08 PM PDT 24
Finished Jun 02 12:37:09 PM PDT 24
Peak memory 199720 kb
Host smart-47591e1d-d7a7-45e1-8044-875b846130b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629163665 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_hmac_vectors.629163665
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.1767119066
Short name T533
Test name
Test status
Simulation time 67975414831 ps
CPU time 511.62 seconds
Started Jun 02 12:36:41 PM PDT 24
Finished Jun 02 12:45:13 PM PDT 24
Peak memory 199916 kb
Host smart-ec264a84-3e1a-4bc4-9a22-a83063a7d16f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767119066 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.1767119066
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.1201628424
Short name T135
Test name
Test status
Simulation time 9998381061 ps
CPU time 97.96 seconds
Started Jun 02 12:36:56 PM PDT 24
Finished Jun 02 12:38:35 PM PDT 24
Peak memory 199928 kb
Host smart-acc26d6e-be77-42fb-b6b5-33367a81d972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201628424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.1201628424
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1132036601
Short name T137
Test name
Test status
Simulation time 24954943 ps
CPU time 0.57 seconds
Started Jun 02 12:37:15 PM PDT 24
Finished Jun 02 12:37:16 PM PDT 24
Peak memory 194772 kb
Host smart-9ff80ad6-455e-45de-b444-b891a558c368
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132036601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1132036601
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2999807722
Short name T39
Test name
Test status
Simulation time 259131623 ps
CPU time 1.33 seconds
Started Jun 02 12:37:07 PM PDT 24
Finished Jun 02 12:37:09 PM PDT 24
Peak memory 199864 kb
Host smart-17a82e8d-b27b-4487-bfc5-482e55502b76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2999807722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2999807722
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.68923541
Short name T131
Test name
Test status
Simulation time 1228784710 ps
CPU time 64.33 seconds
Started Jun 02 12:36:59 PM PDT 24
Finished Jun 02 12:38:05 PM PDT 24
Peak memory 199212 kb
Host smart-327f6a4b-4750-457b-b875-1ce3517ff526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68923541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.68923541
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1927570238
Short name T544
Test name
Test status
Simulation time 1930091611 ps
CPU time 471.96 seconds
Started Jun 02 12:37:05 PM PDT 24
Finished Jun 02 12:44:57 PM PDT 24
Peak memory 695364 kb
Host smart-d18133c0-d4e4-4eb3-b040-256f579e8585
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1927570238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1927570238
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.1587959438
Short name T293
Test name
Test status
Simulation time 2459981988 ps
CPU time 130.6 seconds
Started Jun 02 12:37:07 PM PDT 24
Finished Jun 02 12:39:18 PM PDT 24
Peak memory 199960 kb
Host smart-36b01722-8049-4d08-9c33-130d795bcbd9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587959438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1587959438
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.831027248
Short name T431
Test name
Test status
Simulation time 4163752512 ps
CPU time 48.74 seconds
Started Jun 02 12:37:11 PM PDT 24
Finished Jun 02 12:38:01 PM PDT 24
Peak memory 200032 kb
Host smart-7cd2af98-e018-48db-accf-e11ea894b478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831027248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.831027248
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.3415211887
Short name T186
Test name
Test status
Simulation time 56106303 ps
CPU time 1.43 seconds
Started Jun 02 12:36:54 PM PDT 24
Finished Jun 02 12:36:56 PM PDT 24
Peak memory 199924 kb
Host smart-8abb3e1f-f3fc-42c2-bc44-729fe7c87b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415211887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.3415211887
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.1778212252
Short name T566
Test name
Test status
Simulation time 29026658848 ps
CPU time 2072.67 seconds
Started Jun 02 12:36:56 PM PDT 24
Finished Jun 02 01:11:30 PM PDT 24
Peak memory 721880 kb
Host smart-3c18d12f-4f9e-4426-aebc-352e1e2aca55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778212252 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1778212252
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.1487994996
Short name T161
Test name
Test status
Simulation time 226771682 ps
CPU time 1.41 seconds
Started Jun 02 12:36:46 PM PDT 24
Finished Jun 02 12:36:53 PM PDT 24
Peak memory 199888 kb
Host smart-4af9c8d7-a8b6-4929-9bec-b6180ce8f923
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487994996 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.1487994996
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.3727154163
Short name T539
Test name
Test status
Simulation time 28956459451 ps
CPU time 461.53 seconds
Started Jun 02 12:36:59 PM PDT 24
Finished Jun 02 12:44:41 PM PDT 24
Peak memory 199896 kb
Host smart-0802a031-9356-40e3-bd54-e459477d7e10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727154163 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.3727154163
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1874808574
Short name T68
Test name
Test status
Simulation time 2326433819 ps
CPU time 84.96 seconds
Started Jun 02 12:37:05 PM PDT 24
Finished Jun 02 12:38:30 PM PDT 24
Peak memory 199936 kb
Host smart-b529eaf1-3336-43c4-9e39-5818decd185b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874808574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1874808574
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.33866676
Short name T585
Test name
Test status
Simulation time 40655277 ps
CPU time 0.59 seconds
Started Jun 02 12:36:11 PM PDT 24
Finished Jun 02 12:36:12 PM PDT 24
Peak memory 195816 kb
Host smart-e3dbdfdf-d4aa-4c43-83ad-b42b4c94a13b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33866676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.33866676
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.1468407428
Short name T220
Test name
Test status
Simulation time 1393729331 ps
CPU time 15.67 seconds
Started Jun 02 12:36:13 PM PDT 24
Finished Jun 02 12:36:29 PM PDT 24
Peak memory 215268 kb
Host smart-873ad691-8f38-4f89-9d28-476e159676b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1468407428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1468407428
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1355000825
Short name T171
Test name
Test status
Simulation time 114041514 ps
CPU time 1.69 seconds
Started Jun 02 12:36:58 PM PDT 24
Finished Jun 02 12:37:01 PM PDT 24
Peak memory 199576 kb
Host smart-c6f63c8c-68e1-41ad-a66e-a3b0ba4f9871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355000825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1355000825
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3378196107
Short name T596
Test name
Test status
Simulation time 2481922044 ps
CPU time 783.57 seconds
Started Jun 02 12:36:04 PM PDT 24
Finished Jun 02 12:49:08 PM PDT 24
Peak memory 756640 kb
Host smart-f4334300-e883-4b75-a213-645e3d84e7f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3378196107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3378196107
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1189152297
Short name T360
Test name
Test status
Simulation time 52427878079 ps
CPU time 108.86 seconds
Started Jun 02 12:36:37 PM PDT 24
Finished Jun 02 12:38:27 PM PDT 24
Peak memory 199928 kb
Host smart-a0ba6aab-6bda-406d-91d2-c6feaae53772
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189152297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1189152297
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3753822662
Short name T355
Test name
Test status
Simulation time 10537898521 ps
CPU time 43.26 seconds
Started Jun 02 12:36:38 PM PDT 24
Finished Jun 02 12:37:21 PM PDT 24
Peak memory 199924 kb
Host smart-e20256c0-8750-4111-878c-e66a187e2452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753822662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3753822662
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2435030711
Short name T29
Test name
Test status
Simulation time 244796210 ps
CPU time 0.91 seconds
Started Jun 02 12:36:24 PM PDT 24
Finished Jun 02 12:36:26 PM PDT 24
Peak memory 218360 kb
Host smart-f2d54871-60d9-4523-928f-04a4edfa806f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435030711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2435030711
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3254717586
Short name T149
Test name
Test status
Simulation time 147275068 ps
CPU time 2.47 seconds
Started Jun 02 12:36:17 PM PDT 24
Finished Jun 02 12:36:20 PM PDT 24
Peak memory 199896 kb
Host smart-0ac739d2-0fe4-4c4d-a283-facd6a01342e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254717586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3254717586
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3897335060
Short name T378
Test name
Test status
Simulation time 8467328690 ps
CPU time 469.73 seconds
Started Jun 02 12:36:13 PM PDT 24
Finished Jun 02 12:44:03 PM PDT 24
Peak memory 216332 kb
Host smart-2706c933-42ae-4681-b8ff-5ce97b6f41b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897335060 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3897335060
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.1582560924
Short name T315
Test name
Test status
Simulation time 32656968 ps
CPU time 1.42 seconds
Started Jun 02 12:36:16 PM PDT 24
Finished Jun 02 12:36:18 PM PDT 24
Peak memory 199924 kb
Host smart-de5308c5-896c-4bf1-9029-2e193d8afbf9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582560924 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.1582560924
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.1890423205
Short name T443
Test name
Test status
Simulation time 52504524945 ps
CPU time 475.48 seconds
Started Jun 02 12:36:32 PM PDT 24
Finished Jun 02 12:44:28 PM PDT 24
Peak memory 199972 kb
Host smart-c75a926f-7e1d-4b55-a53e-f7a62ae4958f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890423205 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.1890423205
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3840407367
Short name T422
Test name
Test status
Simulation time 119292250 ps
CPU time 2.62 seconds
Started Jun 02 12:36:07 PM PDT 24
Finished Jun 02 12:36:10 PM PDT 24
Peak memory 199940 kb
Host smart-7e337451-14cf-45e0-9ba3-7607aad3c31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840407367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3840407367
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.198312417
Short name T155
Test name
Test status
Simulation time 15313697 ps
CPU time 0.62 seconds
Started Jun 02 12:37:05 PM PDT 24
Finished Jun 02 12:37:06 PM PDT 24
Peak memory 195768 kb
Host smart-7fb0c00e-6beb-425d-b7b6-570f379e6f77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198312417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.198312417
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.3787750980
Short name T411
Test name
Test status
Simulation time 8124162351 ps
CPU time 49.68 seconds
Started Jun 02 12:37:10 PM PDT 24
Finished Jun 02 12:38:00 PM PDT 24
Peak memory 216008 kb
Host smart-be78b94f-5f68-4df7-a57e-029bc7bc2ffb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3787750980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3787750980
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.2438589489
Short name T307
Test name
Test status
Simulation time 5127304564 ps
CPU time 20.68 seconds
Started Jun 02 12:37:02 PM PDT 24
Finished Jun 02 12:37:24 PM PDT 24
Peak memory 199652 kb
Host smart-32bf1783-7232-49b6-a36f-9b3142f0592a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438589489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.2438589489
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.4139951249
Short name T115
Test name
Test status
Simulation time 3064352924 ps
CPU time 323.23 seconds
Started Jun 02 12:36:56 PM PDT 24
Finished Jun 02 12:42:20 PM PDT 24
Peak memory 641436 kb
Host smart-094d4d3c-71af-4491-a96e-7c785a6de13c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4139951249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.4139951249
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3746021912
Short name T282
Test name
Test status
Simulation time 8678165952 ps
CPU time 162.59 seconds
Started Jun 02 12:36:57 PM PDT 24
Finished Jun 02 12:39:41 PM PDT 24
Peak memory 199932 kb
Host smart-7be5540e-c963-4cd1-a30b-68b70cfdd1cd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746021912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3746021912
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.360105311
Short name T260
Test name
Test status
Simulation time 1056473975 ps
CPU time 55.07 seconds
Started Jun 02 12:36:42 PM PDT 24
Finished Jun 02 12:37:38 PM PDT 24
Peak memory 199944 kb
Host smart-0a9b0f81-85bb-408e-b517-7e54f95e3ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360105311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.360105311
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.4115533387
Short name T545
Test name
Test status
Simulation time 11871659 ps
CPU time 0.65 seconds
Started Jun 02 12:36:46 PM PDT 24
Finished Jun 02 12:36:47 PM PDT 24
Peak memory 196324 kb
Host smart-9e92de1b-40ee-45ab-9427-11d33e7f2ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115533387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.4115533387
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.3284751820
Short name T594
Test name
Test status
Simulation time 12846801914 ps
CPU time 2253.1 seconds
Started Jun 02 12:37:10 PM PDT 24
Finished Jun 02 01:14:44 PM PDT 24
Peak memory 809380 kb
Host smart-84837776-fd78-42dd-975f-75eba820bc75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284751820 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.3284751820
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.3763876829
Short name T338
Test name
Test status
Simulation time 31081079 ps
CPU time 1.11 seconds
Started Jun 02 12:37:05 PM PDT 24
Finished Jun 02 12:37:07 PM PDT 24
Peak memory 199916 kb
Host smart-8b49001e-e960-4807-a57f-1ce5ec09f0a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763876829 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.3763876829
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.1652929355
Short name T419
Test name
Test status
Simulation time 158297327398 ps
CPU time 552.98 seconds
Started Jun 02 12:37:02 PM PDT 24
Finished Jun 02 12:46:16 PM PDT 24
Peak memory 199900 kb
Host smart-0020d26a-14d4-45cc-848e-f6e3ea00808a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652929355 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.1652929355
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3721001963
Short name T562
Test name
Test status
Simulation time 1278967619 ps
CPU time 18.86 seconds
Started Jun 02 12:37:19 PM PDT 24
Finished Jun 02 12:37:39 PM PDT 24
Peak memory 199884 kb
Host smart-e1b9a2aa-3bb4-4700-80d4-a8505b91f00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721001963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3721001963
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2187414167
Short name T450
Test name
Test status
Simulation time 33738824 ps
CPU time 0.58 seconds
Started Jun 02 12:37:07 PM PDT 24
Finished Jun 02 12:37:08 PM PDT 24
Peak memory 194780 kb
Host smart-e3bdeda2-4e0c-4e98-b879-7faef970397a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187414167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2187414167
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2885287748
Short name T109
Test name
Test status
Simulation time 649776354 ps
CPU time 29.45 seconds
Started Jun 02 12:36:59 PM PDT 24
Finished Jun 02 12:37:29 PM PDT 24
Peak memory 208096 kb
Host smart-9b469386-e880-4752-b3eb-c3b437701dba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2885287748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2885287748
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1589064646
Short name T120
Test name
Test status
Simulation time 1322718433 ps
CPU time 33.36 seconds
Started Jun 02 12:37:11 PM PDT 24
Finished Jun 02 12:37:45 PM PDT 24
Peak memory 199948 kb
Host smart-018c9fc1-5e5e-4cb7-88f8-a6f266ddb8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589064646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1589064646
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1337992516
Short name T593
Test name
Test status
Simulation time 5542539714 ps
CPU time 668.09 seconds
Started Jun 02 12:37:02 PM PDT 24
Finished Jun 02 12:48:11 PM PDT 24
Peak memory 705360 kb
Host smart-b43e2711-406a-4822-a420-821568b288f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1337992516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1337992516
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.2192244952
Short name T164
Test name
Test status
Simulation time 11319755100 ps
CPU time 156.8 seconds
Started Jun 02 12:36:56 PM PDT 24
Finished Jun 02 12:39:34 PM PDT 24
Peak memory 200008 kb
Host smart-b56db31b-f445-4aae-98d1-7c9a1362dd79
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192244952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2192244952
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3066783615
Short name T66
Test name
Test status
Simulation time 23590048302 ps
CPU time 82.47 seconds
Started Jun 02 12:36:59 PM PDT 24
Finished Jun 02 12:38:22 PM PDT 24
Peak memory 199988 kb
Host smart-cc47e5ed-077c-46a9-a4d4-f02752265548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066783615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3066783615
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3315048756
Short name T312
Test name
Test status
Simulation time 168934011 ps
CPU time 6.11 seconds
Started Jun 02 12:37:06 PM PDT 24
Finished Jun 02 12:37:18 PM PDT 24
Peak memory 199976 kb
Host smart-53941eb8-db91-48d6-bc72-e9f8ee90ddc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315048756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3315048756
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.651907290
Short name T210
Test name
Test status
Simulation time 133852239742 ps
CPU time 3287.4 seconds
Started Jun 02 12:37:24 PM PDT 24
Finished Jun 02 01:32:12 PM PDT 24
Peak memory 771376 kb
Host smart-d6acc1d9-9753-4131-a635-1549247ca632
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651907290 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.651907290
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.1754487504
Short name T38
Test name
Test status
Simulation time 30408180 ps
CPU time 0.99 seconds
Started Jun 02 12:36:52 PM PDT 24
Finished Jun 02 12:36:53 PM PDT 24
Peak memory 199708 kb
Host smart-4b65f100-769a-4d09-b2ea-270760f4eed3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754487504 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.1754487504
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.3574840171
Short name T589
Test name
Test status
Simulation time 23618808393 ps
CPU time 447.43 seconds
Started Jun 02 12:37:05 PM PDT 24
Finished Jun 02 12:44:33 PM PDT 24
Peak memory 199948 kb
Host smart-941e1e14-e1b6-408d-9b2f-35897d03cb81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574840171 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.3574840171
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.4090090691
Short name T176
Test name
Test status
Simulation time 873409014 ps
CPU time 4.18 seconds
Started Jun 02 12:36:55 PM PDT 24
Finished Jun 02 12:36:59 PM PDT 24
Peak memory 199828 kb
Host smart-29e7fa25-e1be-4a3e-bd16-0b94dc7e3a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090090691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.4090090691
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.638258951
Short name T139
Test name
Test status
Simulation time 47764522 ps
CPU time 0.63 seconds
Started Jun 02 12:37:00 PM PDT 24
Finished Jun 02 12:37:01 PM PDT 24
Peak memory 196528 kb
Host smart-a5c5dfd8-f58a-41c5-8f51-60de92de512b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638258951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.638258951
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2674866741
Short name T470
Test name
Test status
Simulation time 2371998619 ps
CPU time 28.04 seconds
Started Jun 02 12:37:15 PM PDT 24
Finished Jun 02 12:37:43 PM PDT 24
Peak memory 216384 kb
Host smart-f0173376-19ec-4ddb-bad2-2fd8cc355f1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2674866741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2674866741
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.986612847
Short name T245
Test name
Test status
Simulation time 17862009316 ps
CPU time 74.62 seconds
Started Jun 02 12:36:50 PM PDT 24
Finished Jun 02 12:38:06 PM PDT 24
Peak memory 199984 kb
Host smart-30cd8ab7-5caf-46a3-a195-549faea65886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986612847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.986612847
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.1674113862
Short name T412
Test name
Test status
Simulation time 2470604902 ps
CPU time 353.55 seconds
Started Jun 02 12:36:50 PM PDT 24
Finished Jun 02 12:42:43 PM PDT 24
Peak memory 676516 kb
Host smart-973e852e-88bf-4560-b6a1-2fe8a368016a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1674113862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1674113862
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.324012354
Short name T316
Test name
Test status
Simulation time 3571923328 ps
CPU time 207.2 seconds
Started Jun 02 12:37:13 PM PDT 24
Finished Jun 02 12:40:40 PM PDT 24
Peak memory 199312 kb
Host smart-80667010-573d-473b-a37f-cd92a97467bb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324012354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.324012354
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2965851584
Short name T140
Test name
Test status
Simulation time 5537099549 ps
CPU time 80.71 seconds
Started Jun 02 12:37:09 PM PDT 24
Finished Jun 02 12:38:30 PM PDT 24
Peak memory 200004 kb
Host smart-bf4da3c6-1854-4f52-9ce7-8bf3a87406c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965851584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2965851584
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.846319997
Short name T232
Test name
Test status
Simulation time 3964810739 ps
CPU time 12.42 seconds
Started Jun 02 12:37:24 PM PDT 24
Finished Jun 02 12:37:37 PM PDT 24
Peak memory 199952 kb
Host smart-5253eac9-6abc-49d4-a4b8-e999b782108b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846319997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.846319997
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.3726053039
Short name T325
Test name
Test status
Simulation time 62647429 ps
CPU time 1.26 seconds
Started Jun 02 12:37:08 PM PDT 24
Finished Jun 02 12:37:15 PM PDT 24
Peak memory 199940 kb
Host smart-54629af1-91b7-4922-baaa-5ec2c1a1f55a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726053039 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.3726053039
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.2488885409
Short name T440
Test name
Test status
Simulation time 30004798668 ps
CPU time 381.23 seconds
Started Jun 02 12:37:16 PM PDT 24
Finished Jun 02 12:43:37 PM PDT 24
Peak memory 199968 kb
Host smart-3ebede9a-7136-4cfc-ac3a-6cd80d1f2d2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488885409 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.2488885409
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.2157402754
Short name T342
Test name
Test status
Simulation time 843060527 ps
CPU time 30.59 seconds
Started Jun 02 12:37:16 PM PDT 24
Finished Jun 02 12:37:47 PM PDT 24
Peak memory 199904 kb
Host smart-c7a3e52a-7772-4bb8-a229-51ab269e7557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157402754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.2157402754
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.924726221
Short name T522
Test name
Test status
Simulation time 28859066 ps
CPU time 0.59 seconds
Started Jun 02 12:37:10 PM PDT 24
Finished Jun 02 12:37:12 PM PDT 24
Peak memory 195804 kb
Host smart-1651d7e0-48e0-44e1-b26a-7243e2a93ba3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924726221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.924726221
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.53328746
Short name T267
Test name
Test status
Simulation time 822823848 ps
CPU time 21.29 seconds
Started Jun 02 12:36:57 PM PDT 24
Finished Jun 02 12:37:19 PM PDT 24
Peak memory 216268 kb
Host smart-b920a59b-b12d-48db-9871-4f458acff2fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=53328746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.53328746
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3159261565
Short name T491
Test name
Test status
Simulation time 8881124011 ps
CPU time 42.24 seconds
Started Jun 02 12:37:06 PM PDT 24
Finished Jun 02 12:37:49 PM PDT 24
Peak memory 199936 kb
Host smart-cdb50b24-5c55-470e-925a-ada010578818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159261565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3159261565
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.3796167879
Short name T6
Test name
Test status
Simulation time 575677991 ps
CPU time 42.36 seconds
Started Jun 02 12:36:57 PM PDT 24
Finished Jun 02 12:37:41 PM PDT 24
Peak memory 312008 kb
Host smart-08899afb-a7de-4a2e-ad4b-1d0a89ecd5cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3796167879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3796167879
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.947453905
Short name T485
Test name
Test status
Simulation time 95363780294 ps
CPU time 217.63 seconds
Started Jun 02 12:37:11 PM PDT 24
Finished Jun 02 12:40:50 PM PDT 24
Peak memory 199936 kb
Host smart-70060e9a-8fd9-482e-98f9-acdb973c05bc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947453905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.947453905
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3942361671
Short name T551
Test name
Test status
Simulation time 23394316501 ps
CPU time 110.89 seconds
Started Jun 02 12:37:00 PM PDT 24
Finished Jun 02 12:38:52 PM PDT 24
Peak memory 200044 kb
Host smart-517dd66a-001d-4b70-971b-c3045382e10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942361671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3942361671
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.2387563636
Short name T174
Test name
Test status
Simulation time 197970842 ps
CPU time 2.19 seconds
Started Jun 02 12:37:16 PM PDT 24
Finished Jun 02 12:37:19 PM PDT 24
Peak memory 199900 kb
Host smart-8be71feb-bef0-4d85-a3dc-a7bd31d67b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387563636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2387563636
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2978413126
Short name T103
Test name
Test status
Simulation time 56319280613 ps
CPU time 1320.07 seconds
Started Jun 02 12:37:21 PM PDT 24
Finished Jun 02 12:59:21 PM PDT 24
Peak memory 656284 kb
Host smart-5199adad-2cde-480c-a9eb-c45cbc31d561
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978413126 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2978413126
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.3720489081
Short name T147
Test name
Test status
Simulation time 222587900 ps
CPU time 1.1 seconds
Started Jun 02 12:37:28 PM PDT 24
Finished Jun 02 12:37:29 PM PDT 24
Peak memory 200204 kb
Host smart-ce0f472d-777e-4aec-87fa-3c776623cbc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720489081 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.3720489081
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.1108505595
Short name T516
Test name
Test status
Simulation time 61389419028 ps
CPU time 513.59 seconds
Started Jun 02 12:37:01 PM PDT 24
Finished Jun 02 12:45:35 PM PDT 24
Peak memory 199920 kb
Host smart-b048b14e-bbdc-467f-a9cc-6ec0dda4c4f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108505595 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.1108505595
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_alert_test.1841812252
Short name T163
Test name
Test status
Simulation time 33763342 ps
CPU time 0.59 seconds
Started Jun 02 12:36:48 PM PDT 24
Finished Jun 02 12:36:49 PM PDT 24
Peak memory 195744 kb
Host smart-305bc21d-f69d-41d3-8983-3e64dfd758eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841812252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1841812252
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3358355284
Short name T395
Test name
Test status
Simulation time 372706107 ps
CPU time 3.39 seconds
Started Jun 02 12:37:02 PM PDT 24
Finished Jun 02 12:37:06 PM PDT 24
Peak memory 199580 kb
Host smart-a60efe3c-76fa-4f1f-9b08-a69c31bf970e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3358355284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3358355284
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.789507508
Short name T298
Test name
Test status
Simulation time 442992221 ps
CPU time 25.85 seconds
Started Jun 02 12:37:13 PM PDT 24
Finished Jun 02 12:37:39 PM PDT 24
Peak memory 199272 kb
Host smart-3d354124-ff5c-4f4d-8dce-5b9c1893874f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789507508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.789507508
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.877568792
Short name T169
Test name
Test status
Simulation time 9542253770 ps
CPU time 320.31 seconds
Started Jun 02 12:37:03 PM PDT 24
Finished Jun 02 12:42:24 PM PDT 24
Peak memory 627348 kb
Host smart-3372a724-3469-40ed-adc2-ff5d7b698225
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=877568792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.877568792
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.3502355024
Short name T517
Test name
Test status
Simulation time 54169055803 ps
CPU time 256.02 seconds
Started Jun 02 12:37:11 PM PDT 24
Finished Jun 02 12:41:28 PM PDT 24
Peak memory 199932 kb
Host smart-0b90be3b-5596-4970-9f2f-d01cb41f56d4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502355024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3502355024
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.4132008374
Short name T206
Test name
Test status
Simulation time 3268808208 ps
CPU time 47.45 seconds
Started Jun 02 12:37:10 PM PDT 24
Finished Jun 02 12:37:59 PM PDT 24
Peak memory 199952 kb
Host smart-b5d50f7a-d98b-4d7f-b5ba-fdef72b53e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132008374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.4132008374
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3901763207
Short name T138
Test name
Test status
Simulation time 284085146 ps
CPU time 5.03 seconds
Started Jun 02 12:37:11 PM PDT 24
Finished Jun 02 12:37:17 PM PDT 24
Peak memory 199924 kb
Host smart-499222b6-b822-45cc-b3ee-7969689345a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901763207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3901763207
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.3324879557
Short name T165
Test name
Test status
Simulation time 109028546684 ps
CPU time 1448.84 seconds
Started Jun 02 12:37:10 PM PDT 24
Finished Jun 02 01:01:20 PM PDT 24
Peak memory 231100 kb
Host smart-46232694-e4ea-4e76-bb47-6237f68fe970
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324879557 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.3324879557
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.1950603611
Short name T536
Test name
Test status
Simulation time 83527767 ps
CPU time 1.49 seconds
Started Jun 02 12:37:30 PM PDT 24
Finished Jun 02 12:37:32 PM PDT 24
Peak memory 199992 kb
Host smart-54556a64-0b0f-4185-a4ec-4eb22c99f4f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950603611 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.1950603611
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.3937252568
Short name T560
Test name
Test status
Simulation time 129403824966 ps
CPU time 469.81 seconds
Started Jun 02 12:37:08 PM PDT 24
Finished Jun 02 12:44:59 PM PDT 24
Peak memory 199984 kb
Host smart-51b5c361-d5f5-4ca7-926e-3e066afb9c68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937252568 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.3937252568
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.4277369025
Short name T554
Test name
Test status
Simulation time 3216075959 ps
CPU time 83.39 seconds
Started Jun 02 12:37:05 PM PDT 24
Finished Jun 02 12:38:28 PM PDT 24
Peak memory 199996 kb
Host smart-5a9d4ea3-39a3-4b3c-aa90-2da34d6a1ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277369025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.4277369025
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.4100069106
Short name T257
Test name
Test status
Simulation time 11200710 ps
CPU time 0.57 seconds
Started Jun 02 12:36:46 PM PDT 24
Finished Jun 02 12:36:48 PM PDT 24
Peak memory 196500 kb
Host smart-101f15bc-235f-4c0e-a2c6-142c13910911
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100069106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.4100069106
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.3002678202
Short name T384
Test name
Test status
Simulation time 943711899 ps
CPU time 9.05 seconds
Started Jun 02 12:37:10 PM PDT 24
Finished Jun 02 12:37:20 PM PDT 24
Peak memory 199936 kb
Host smart-ee1d5071-97c4-47e3-84e4-e20c2c42527c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3002678202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3002678202
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2543969569
Short name T47
Test name
Test status
Simulation time 24239299721 ps
CPU time 63.96 seconds
Started Jun 02 12:37:02 PM PDT 24
Finished Jun 02 12:38:06 PM PDT 24
Peak memory 199992 kb
Host smart-1f312f8f-36c0-478a-b5f3-1a666300c3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543969569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2543969569
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2932161958
Short name T296
Test name
Test status
Simulation time 1553800109 ps
CPU time 387.58 seconds
Started Jun 02 12:36:53 PM PDT 24
Finished Jun 02 12:43:21 PM PDT 24
Peak memory 666376 kb
Host smart-23c6cf31-1243-42dc-a173-1253d252cb4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2932161958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2932161958
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.4041593768
Short name T173
Test name
Test status
Simulation time 6381145846 ps
CPU time 92.77 seconds
Started Jun 02 12:37:07 PM PDT 24
Finished Jun 02 12:38:40 PM PDT 24
Peak memory 199960 kb
Host smart-fe25dc3c-8fa7-477c-a137-3cdb4b3f62d2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041593768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.4041593768
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1688492866
Short name T463
Test name
Test status
Simulation time 55170636151 ps
CPU time 119.7 seconds
Started Jun 02 12:36:57 PM PDT 24
Finished Jun 02 12:38:58 PM PDT 24
Peak memory 199992 kb
Host smart-9c5fab1a-24e8-4b57-abc2-cb62a948d5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688492866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1688492866
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2780860666
Short name T543
Test name
Test status
Simulation time 58365316 ps
CPU time 1.33 seconds
Started Jun 02 12:37:26 PM PDT 24
Finished Jun 02 12:37:28 PM PDT 24
Peak memory 200216 kb
Host smart-974672d7-f27c-42a9-8d16-6514c00362ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780860666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2780860666
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.4042339650
Short name T530
Test name
Test status
Simulation time 78365220278 ps
CPU time 1039.45 seconds
Started Jun 02 12:37:10 PM PDT 24
Finished Jun 02 12:54:30 PM PDT 24
Peak memory 666004 kb
Host smart-8918a8bd-3965-414b-b1ea-e1652d92eff8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042339650 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.4042339650
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.30729908
Short name T588
Test name
Test status
Simulation time 108890608 ps
CPU time 1.1 seconds
Started Jun 02 12:37:03 PM PDT 24
Finished Jun 02 12:37:05 PM PDT 24
Peak memory 199680 kb
Host smart-83436b5b-c5cb-4cbd-a51e-13b5a03e2923
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30729908 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.hmac_test_hmac_vectors.30729908
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.168629298
Short name T272
Test name
Test status
Simulation time 7686778901 ps
CPU time 444.57 seconds
Started Jun 02 12:36:58 PM PDT 24
Finished Jun 02 12:44:23 PM PDT 24
Peak memory 200044 kb
Host smart-4048e185-d1b6-4ad0-9610-8002e45425a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168629298 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.168629298
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2005933445
Short name T88
Test name
Test status
Simulation time 3764713607 ps
CPU time 37.35 seconds
Started Jun 02 12:37:02 PM PDT 24
Finished Jun 02 12:37:40 PM PDT 24
Peak memory 199960 kb
Host smart-2c9ea3d7-c2c4-4409-813c-64b3856d5acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005933445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2005933445
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.4076300370
Short name T436
Test name
Test status
Simulation time 36065039 ps
CPU time 0.55 seconds
Started Jun 02 12:37:05 PM PDT 24
Finished Jun 02 12:37:06 PM PDT 24
Peak memory 195556 kb
Host smart-b263be83-3b57-485a-89ac-66d1630a57a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076300370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.4076300370
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.284027425
Short name T565
Test name
Test status
Simulation time 4280434311 ps
CPU time 64.34 seconds
Started Jun 02 12:36:51 PM PDT 24
Finished Jun 02 12:37:56 PM PDT 24
Peak memory 240992 kb
Host smart-1cc45f60-6d93-4447-888f-1b12ca76c86c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=284027425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.284027425
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1357518104
Short name T490
Test name
Test status
Simulation time 272644732 ps
CPU time 15.6 seconds
Started Jun 02 12:36:46 PM PDT 24
Finished Jun 02 12:37:02 PM PDT 24
Peak memory 199848 kb
Host smart-3c56318c-c532-42f0-8829-7ede7ea980f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357518104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1357518104
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3812076591
Short name T179
Test name
Test status
Simulation time 7329284061 ps
CPU time 1029.89 seconds
Started Jun 02 12:37:13 PM PDT 24
Finished Jun 02 12:54:24 PM PDT 24
Peak memory 746140 kb
Host smart-9099f610-1209-4390-ba2a-ba84f76d8471
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3812076591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3812076591
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1182980495
Short name T306
Test name
Test status
Simulation time 288403682 ps
CPU time 4.38 seconds
Started Jun 02 12:37:06 PM PDT 24
Finished Jun 02 12:37:13 PM PDT 24
Peak memory 199828 kb
Host smart-fe374937-c022-4fa6-bc3a-b823800e1c09
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182980495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1182980495
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3783636198
Short name T510
Test name
Test status
Simulation time 123230230 ps
CPU time 2.26 seconds
Started Jun 02 12:37:32 PM PDT 24
Finished Jun 02 12:37:35 PM PDT 24
Peak memory 199868 kb
Host smart-ef0dab32-505b-4810-ae48-09ae9b638733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783636198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3783636198
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2737358552
Short name T464
Test name
Test status
Simulation time 799247753 ps
CPU time 6.79 seconds
Started Jun 02 12:37:19 PM PDT 24
Finished Jun 02 12:37:26 PM PDT 24
Peak memory 199868 kb
Host smart-0d101a15-d6fd-4b73-8215-67beb0bfc0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737358552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2737358552
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.2982575006
Short name T290
Test name
Test status
Simulation time 61713181233 ps
CPU time 2299.16 seconds
Started Jun 02 12:37:10 PM PDT 24
Finished Jun 02 01:15:30 PM PDT 24
Peak memory 756608 kb
Host smart-46d32012-abf1-4fde-b05e-5c55aba411e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982575006 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2982575006
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.3863628994
Short name T399
Test name
Test status
Simulation time 426620140 ps
CPU time 1.21 seconds
Started Jun 02 12:37:00 PM PDT 24
Finished Jun 02 12:37:02 PM PDT 24
Peak memory 198976 kb
Host smart-7d955556-6086-4c16-a267-c66279cae603
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863628994 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.3863628994
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.439703980
Short name T380
Test name
Test status
Simulation time 591214413106 ps
CPU time 489.19 seconds
Started Jun 02 12:37:19 PM PDT 24
Finished Jun 02 12:45:28 PM PDT 24
Peak memory 199660 kb
Host smart-b5c0eb3a-d98d-4dbb-9dba-29eddcbd1d07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439703980 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.439703980
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2062232939
Short name T69
Test name
Test status
Simulation time 350159904 ps
CPU time 10.65 seconds
Started Jun 02 12:37:34 PM PDT 24
Finished Jun 02 12:37:46 PM PDT 24
Peak memory 199892 kb
Host smart-0d23bfb1-dfd9-4d06-bd3e-d246f871ba79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062232939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2062232939
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.2660004517
Short name T449
Test name
Test status
Simulation time 41009073 ps
CPU time 0.57 seconds
Started Jun 02 12:37:16 PM PDT 24
Finished Jun 02 12:37:17 PM PDT 24
Peak memory 194788 kb
Host smart-e92454e5-ba6c-4ab7-9c0a-f5bdc7d87080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660004517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2660004517
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2337445547
Short name T494
Test name
Test status
Simulation time 2259818965 ps
CPU time 50.46 seconds
Started Jun 02 12:37:35 PM PDT 24
Finished Jun 02 12:38:26 PM PDT 24
Peak memory 216140 kb
Host smart-d8b2434a-6ebd-44d0-871b-9abb17cf9e73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2337445547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2337445547
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.2939358397
Short name T428
Test name
Test status
Simulation time 1063241295 ps
CPU time 11.39 seconds
Started Jun 02 12:37:34 PM PDT 24
Finished Jun 02 12:37:46 PM PDT 24
Peak memory 200312 kb
Host smart-c3e51381-d8eb-483e-afb0-9eda9fe5bca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939358397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2939358397
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3881733743
Short name T476
Test name
Test status
Simulation time 2180414422 ps
CPU time 583.94 seconds
Started Jun 02 12:37:06 PM PDT 24
Finished Jun 02 12:46:51 PM PDT 24
Peak memory 660224 kb
Host smart-fe38202d-a107-40be-8e7e-689c8b4f010d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3881733743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3881733743
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1101655298
Short name T208
Test name
Test status
Simulation time 9522825235 ps
CPU time 101.81 seconds
Started Jun 02 12:38:23 PM PDT 24
Finished Jun 02 12:40:05 PM PDT 24
Peak memory 199956 kb
Host smart-c11c61e1-3765-47a2-a71c-bd519b511981
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101655298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1101655298
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3402469545
Short name T35
Test name
Test status
Simulation time 5293616352 ps
CPU time 39.87 seconds
Started Jun 02 12:37:11 PM PDT 24
Finished Jun 02 12:37:52 PM PDT 24
Peak memory 199952 kb
Host smart-657aa010-3473-40fe-90bd-0a8ade254950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402469545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3402469545
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2897755551
Short name T214
Test name
Test status
Simulation time 154461522 ps
CPU time 2.17 seconds
Started Jun 02 12:37:06 PM PDT 24
Finished Jun 02 12:37:08 PM PDT 24
Peak memory 199972 kb
Host smart-0dc9877f-28c8-4234-8304-4b96c89ac143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897755551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2897755551
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.3025003057
Short name T141
Test name
Test status
Simulation time 33804816125 ps
CPU time 597.17 seconds
Started Jun 02 12:37:08 PM PDT 24
Finished Jun 02 12:47:06 PM PDT 24
Peak memory 232044 kb
Host smart-5d24029e-4298-4ab9-b54e-a419ac6b4ad7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025003057 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3025003057
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.3937713498
Short name T454
Test name
Test status
Simulation time 35119834 ps
CPU time 1.31 seconds
Started Jun 02 12:37:03 PM PDT 24
Finished Jun 02 12:37:05 PM PDT 24
Peak memory 199876 kb
Host smart-c38b6a4e-394f-4f84-981f-5f6dcb31f663
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937713498 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.3937713498
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.388256866
Short name T427
Test name
Test status
Simulation time 98134171029 ps
CPU time 503.51 seconds
Started Jun 02 12:37:07 PM PDT 24
Finished Jun 02 12:45:31 PM PDT 24
Peak memory 199928 kb
Host smart-ca2648d4-cbde-4d8a-9213-4bd3dc6850c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388256866 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.388256866
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3942283195
Short name T292
Test name
Test status
Simulation time 1549745545 ps
CPU time 40.87 seconds
Started Jun 02 12:38:23 PM PDT 24
Finished Jun 02 12:39:04 PM PDT 24
Peak memory 199880 kb
Host smart-31256f45-93c9-4952-9297-7f27b919ba20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942283195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3942283195
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.1337786516
Short name T271
Test name
Test status
Simulation time 14454668 ps
CPU time 0.6 seconds
Started Jun 02 12:37:08 PM PDT 24
Finished Jun 02 12:37:09 PM PDT 24
Peak memory 195812 kb
Host smart-a04c153e-7dae-46ea-8d0d-614bd39a8457
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337786516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1337786516
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.39873191
Short name T405
Test name
Test status
Simulation time 1041914645 ps
CPU time 9.07 seconds
Started Jun 02 12:37:06 PM PDT 24
Finished Jun 02 12:37:15 PM PDT 24
Peak memory 231596 kb
Host smart-c0c431af-79bb-4002-aa09-404edb1fc8f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=39873191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.39873191
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3225101210
Short name T504
Test name
Test status
Simulation time 4784235499 ps
CPU time 64.87 seconds
Started Jun 02 12:37:38 PM PDT 24
Finished Jun 02 12:38:44 PM PDT 24
Peak memory 200032 kb
Host smart-8198aaa6-3e9d-45e4-955c-57932683597e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225101210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3225101210
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.443995163
Short name T313
Test name
Test status
Simulation time 569331545 ps
CPU time 99.37 seconds
Started Jun 02 12:37:05 PM PDT 24
Finished Jun 02 12:38:45 PM PDT 24
Peak memory 363476 kb
Host smart-cf2bee4a-e7c5-4043-8c2f-d02b9cc72f5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=443995163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.443995163
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.4206366148
Short name T495
Test name
Test status
Simulation time 6654462950 ps
CPU time 104.58 seconds
Started Jun 02 12:38:23 PM PDT 24
Finished Jun 02 12:40:08 PM PDT 24
Peak memory 199928 kb
Host smart-4496de80-e9bf-4801-a16e-26af00f95647
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206366148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.4206366148
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.2559619643
Short name T205
Test name
Test status
Simulation time 21875261 ps
CPU time 0.76 seconds
Started Jun 02 12:38:06 PM PDT 24
Finished Jun 02 12:38:07 PM PDT 24
Peak memory 196972 kb
Host smart-4c7935f1-59dc-4fe2-a836-e90cc92cf5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559619643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2559619643
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1420433834
Short name T148
Test name
Test status
Simulation time 1508417203 ps
CPU time 6.57 seconds
Started Jun 02 12:37:06 PM PDT 24
Finished Jun 02 12:37:13 PM PDT 24
Peak memory 199924 kb
Host smart-84688080-3216-41f4-b155-56c4fd94c840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420433834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1420433834
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1467562476
Short name T441
Test name
Test status
Simulation time 33707717023 ps
CPU time 115.86 seconds
Started Jun 02 12:37:08 PM PDT 24
Finished Jun 02 12:39:04 PM PDT 24
Peak memory 200016 kb
Host smart-595f37ac-5716-4267-b43f-4957f4a9f022
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467562476 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1467562476
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.1986571024
Short name T133
Test name
Test status
Simulation time 227648546 ps
CPU time 1.24 seconds
Started Jun 02 12:37:05 PM PDT 24
Finished Jun 02 12:37:10 PM PDT 24
Peak memory 199936 kb
Host smart-5fc8afe6-ff33-422d-846a-a2228a75869f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986571024 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.1986571024
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.967713293
Short name T188
Test name
Test status
Simulation time 31027752504 ps
CPU time 445.74 seconds
Started Jun 02 12:37:04 PM PDT 24
Finished Jun 02 12:44:31 PM PDT 24
Peak memory 199936 kb
Host smart-a89772e4-d932-41ac-b9e3-65087e06141a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967713293 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.967713293
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.2838665376
Short name T571
Test name
Test status
Simulation time 1791262822 ps
CPU time 31.25 seconds
Started Jun 02 12:38:23 PM PDT 24
Finished Jun 02 12:38:55 PM PDT 24
Peak memory 199876 kb
Host smart-d89f513b-15a7-4a21-b49f-88cba3e58df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838665376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2838665376
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.3059871701
Short name T397
Test name
Test status
Simulation time 33239460 ps
CPU time 0.61 seconds
Started Jun 02 12:37:10 PM PDT 24
Finished Jun 02 12:37:11 PM PDT 24
Peak memory 194848 kb
Host smart-dd7d4ef6-5f16-46c0-bf89-6225b97c0544
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059871701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3059871701
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.4145456713
Short name T235
Test name
Test status
Simulation time 632758071 ps
CPU time 25.63 seconds
Started Jun 02 12:36:56 PM PDT 24
Finished Jun 02 12:37:22 PM PDT 24
Peak memory 208028 kb
Host smart-6f64369d-9513-4a43-bbab-465bf404762e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4145456713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.4145456713
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3894836977
Short name T341
Test name
Test status
Simulation time 155689937 ps
CPU time 7.99 seconds
Started Jun 02 12:38:23 PM PDT 24
Finished Jun 02 12:38:32 PM PDT 24
Peak memory 199880 kb
Host smart-19eb29c4-5af8-4578-b35c-52da72f6ade4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894836977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3894836977
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3998848166
Short name T310
Test name
Test status
Simulation time 10026120609 ps
CPU time 595.47 seconds
Started Jun 02 12:37:09 PM PDT 24
Finished Jun 02 12:47:05 PM PDT 24
Peak memory 699980 kb
Host smart-104419c6-47e3-43c6-9e4c-bc896bd34151
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3998848166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3998848166
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1249334745
Short name T266
Test name
Test status
Simulation time 845086476 ps
CPU time 44.2 seconds
Started Jun 02 12:37:10 PM PDT 24
Finished Jun 02 12:37:55 PM PDT 24
Peak memory 199828 kb
Host smart-c4e13c2c-6c84-466b-a1a8-e8849da45283
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249334745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1249334745
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.2644987723
Short name T553
Test name
Test status
Simulation time 15668324936 ps
CPU time 55.27 seconds
Started Jun 02 12:38:22 PM PDT 24
Finished Jun 02 12:39:18 PM PDT 24
Peak memory 199988 kb
Host smart-b070dc39-e0cd-40f5-9de9-9228486badbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644987723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.2644987723
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1917098639
Short name T335
Test name
Test status
Simulation time 382029621 ps
CPU time 6.66 seconds
Started Jun 02 12:37:11 PM PDT 24
Finished Jun 02 12:37:19 PM PDT 24
Peak memory 200200 kb
Host smart-1a3e7be6-e13b-4bbe-9660-dc72685fb8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917098639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1917098639
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.2353615110
Short name T121
Test name
Test status
Simulation time 135865911694 ps
CPU time 1042.95 seconds
Started Jun 02 12:37:11 PM PDT 24
Finished Jun 02 12:54:34 PM PDT 24
Peak memory 199968 kb
Host smart-e371b864-336d-460b-9bc3-e9824d56c494
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353615110 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2353615110
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.2892281845
Short name T248
Test name
Test status
Simulation time 152073691 ps
CPU time 1.28 seconds
Started Jun 02 12:37:15 PM PDT 24
Finished Jun 02 12:37:17 PM PDT 24
Peak memory 199992 kb
Host smart-40baf84b-940a-4ab8-ad0d-5058d1a49c06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892281845 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.2892281845
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.1557967910
Short name T475
Test name
Test status
Simulation time 40121854219 ps
CPU time 413.73 seconds
Started Jun 02 12:36:52 PM PDT 24
Finished Jun 02 12:43:46 PM PDT 24
Peak memory 199916 kb
Host smart-e9b409e1-123a-4e97-82c3-dc2bb8eadc9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557967910 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.1557967910
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.886761891
Short name T489
Test name
Test status
Simulation time 2383691233 ps
CPU time 12.5 seconds
Started Jun 02 12:38:23 PM PDT 24
Finished Jun 02 12:38:36 PM PDT 24
Peak memory 199948 kb
Host smart-c301b04e-3859-48b4-8d72-f6051966cf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886761891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.886761891
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.230825977
Short name T162
Test name
Test status
Simulation time 55201695 ps
CPU time 0.56 seconds
Started Jun 02 12:35:53 PM PDT 24
Finished Jun 02 12:35:54 PM PDT 24
Peak memory 195792 kb
Host smart-a2ad1e7f-d0dd-4fee-b371-ffb5c7069db2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230825977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.230825977
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3172253527
Short name T473
Test name
Test status
Simulation time 960139837 ps
CPU time 14.02 seconds
Started Jun 02 12:36:13 PM PDT 24
Finished Jun 02 12:36:27 PM PDT 24
Peak memory 227316 kb
Host smart-970ec168-ce55-49cc-bb9d-9e2c6d586cc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3172253527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3172253527
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3140931867
Short name T130
Test name
Test status
Simulation time 677363909 ps
CPU time 18.82 seconds
Started Jun 02 12:36:38 PM PDT 24
Finished Jun 02 12:36:57 PM PDT 24
Peak memory 199964 kb
Host smart-37ba3c3e-374f-4c0a-9d8a-0b9f3d7a4823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140931867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3140931867
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.3146886009
Short name T546
Test name
Test status
Simulation time 2567055402 ps
CPU time 627.09 seconds
Started Jun 02 12:36:15 PM PDT 24
Finished Jun 02 12:46:43 PM PDT 24
Peak memory 713024 kb
Host smart-9df9bff8-dc97-4e72-a384-efc2a45888fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3146886009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.3146886009
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.343307616
Short name T328
Test name
Test status
Simulation time 2636287074 ps
CPU time 110.5 seconds
Started Jun 02 12:36:15 PM PDT 24
Finished Jun 02 12:38:06 PM PDT 24
Peak memory 199912 kb
Host smart-0ab95ffa-976b-4ef3-8d1d-8cb8b7d77286
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343307616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.343307616
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3252504616
Short name T144
Test name
Test status
Simulation time 514368742 ps
CPU time 9.86 seconds
Started Jun 02 12:36:12 PM PDT 24
Finished Jun 02 12:36:22 PM PDT 24
Peak memory 199888 kb
Host smart-34ede032-a815-4971-85d9-bc12c21eb3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252504616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3252504616
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1129061215
Short name T32
Test name
Test status
Simulation time 251447735 ps
CPU time 0.91 seconds
Started Jun 02 12:36:01 PM PDT 24
Finished Jun 02 12:36:02 PM PDT 24
Peak memory 218348 kb
Host smart-3f9003f1-b3ed-4b7d-a23f-7d63c6d35109
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129061215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1129061215
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.4137610248
Short name T458
Test name
Test status
Simulation time 309753312 ps
CPU time 5.37 seconds
Started Jun 02 12:36:56 PM PDT 24
Finished Jun 02 12:37:02 PM PDT 24
Peak memory 199204 kb
Host smart-d2854b93-5173-4b0c-ab30-6e8d0fa194fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137610248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.4137610248
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.551096812
Short name T575
Test name
Test status
Simulation time 22695101835 ps
CPU time 895.32 seconds
Started Jun 02 12:36:10 PM PDT 24
Finished Jun 02 12:51:06 PM PDT 24
Peak memory 719240 kb
Host smart-d2302b9f-9b92-4ad2-a96e-f3641620e36d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551096812 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.551096812
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.2587189211
Short name T28
Test name
Test status
Simulation time 85024838 ps
CPU time 1.41 seconds
Started Jun 02 12:36:36 PM PDT 24
Finished Jun 02 12:36:38 PM PDT 24
Peak memory 199856 kb
Host smart-3c57a067-1646-4ac8-bee4-c7badc68aa75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587189211 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.2587189211
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.689906716
Short name T181
Test name
Test status
Simulation time 145990174988 ps
CPU time 479.18 seconds
Started Jun 02 12:36:14 PM PDT 24
Finished Jun 02 12:44:13 PM PDT 24
Peak memory 200032 kb
Host smart-e840b328-9527-4a74-af04-918271859a4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689906716 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.689906716
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2207380745
Short name T410
Test name
Test status
Simulation time 1091969293 ps
CPU time 6.16 seconds
Started Jun 02 12:36:15 PM PDT 24
Finished Jun 02 12:36:21 PM PDT 24
Peak memory 199824 kb
Host smart-2ce4c23e-d4d1-4519-babc-93499c78c499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207380745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2207380745
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.680957891
Short name T569
Test name
Test status
Simulation time 53992858 ps
CPU time 0.57 seconds
Started Jun 02 12:37:13 PM PDT 24
Finished Jun 02 12:37:14 PM PDT 24
Peak memory 195424 kb
Host smart-87a6af06-afad-4df0-b891-b4a35a6c4734
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680957891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.680957891
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.810123520
Short name T44
Test name
Test status
Simulation time 3573187326 ps
CPU time 61.93 seconds
Started Jun 02 12:37:14 PM PDT 24
Finished Jun 02 12:38:17 PM PDT 24
Peak memory 230760 kb
Host smart-e1ab030f-7a71-4c01-be14-554b08df96bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=810123520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.810123520
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3688261585
Short name T239
Test name
Test status
Simulation time 627319417 ps
CPU time 9.23 seconds
Started Jun 02 12:37:27 PM PDT 24
Finished Jun 02 12:37:37 PM PDT 24
Peak memory 199992 kb
Host smart-ce4addc7-cc55-46b1-81b6-95e42e234b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688261585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3688261585
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1396804325
Short name T111
Test name
Test status
Simulation time 3722840395 ps
CPU time 954.63 seconds
Started Jun 02 12:37:28 PM PDT 24
Finished Jun 02 12:53:23 PM PDT 24
Peak memory 720956 kb
Host smart-123d46c1-3f0f-4c54-a295-6f8f233f4573
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1396804325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1396804325
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.985413903
Short name T579
Test name
Test status
Simulation time 3986792946 ps
CPU time 29.27 seconds
Started Jun 02 12:37:21 PM PDT 24
Finished Jun 02 12:37:51 PM PDT 24
Peak memory 200008 kb
Host smart-4ba628e6-ffbf-4ab9-a980-2888e457c4e1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985413903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.985413903
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3523048702
Short name T356
Test name
Test status
Simulation time 8129063204 ps
CPU time 54.49 seconds
Started Jun 02 12:37:24 PM PDT 24
Finished Jun 02 12:38:19 PM PDT 24
Peak memory 199948 kb
Host smart-8cf7583a-7977-493e-adc6-c0977fd04232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523048702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3523048702
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.327349711
Short name T350
Test name
Test status
Simulation time 2465210632 ps
CPU time 13.19 seconds
Started Jun 02 12:38:23 PM PDT 24
Finished Jun 02 12:38:36 PM PDT 24
Peak memory 199932 kb
Host smart-f825dc6d-18fd-427a-a185-fdd96c09d1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327349711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.327349711
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2919620248
Short name T541
Test name
Test status
Simulation time 1460489106 ps
CPU time 33.19 seconds
Started Jun 02 12:37:44 PM PDT 24
Finished Jun 02 12:38:17 PM PDT 24
Peak memory 213332 kb
Host smart-0f23ab20-a161-44a7-b41c-9ccc79971938
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919620248 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2919620248
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.3374143564
Short name T300
Test name
Test status
Simulation time 56361422 ps
CPU time 1.09 seconds
Started Jun 02 12:37:10 PM PDT 24
Finished Jun 02 12:37:11 PM PDT 24
Peak memory 200004 kb
Host smart-f1a9757b-ed1b-41d4-bf97-0efa4a0a7943
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374143564 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.3374143564
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.693843289
Short name T452
Test name
Test status
Simulation time 249919371297 ps
CPU time 501.39 seconds
Started Jun 02 12:37:36 PM PDT 24
Finished Jun 02 12:45:58 PM PDT 24
Peak memory 199924 kb
Host smart-43e2f24a-c973-4b37-a212-c97c0d89f26a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693843289 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.693843289
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.61107255
Short name T349
Test name
Test status
Simulation time 5423647564 ps
CPU time 71.16 seconds
Started Jun 02 12:37:06 PM PDT 24
Finished Jun 02 12:38:18 PM PDT 24
Peak memory 199980 kb
Host smart-b8e3ec64-9bc3-4378-b8eb-66368dc465c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61107255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.61107255
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1250066936
Short name T479
Test name
Test status
Simulation time 84078507 ps
CPU time 0.56 seconds
Started Jun 02 12:37:19 PM PDT 24
Finished Jun 02 12:37:20 PM PDT 24
Peak memory 195496 kb
Host smart-12b9eda7-907a-4f18-849a-e048baa8c7bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250066936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1250066936
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.4065188781
Short name T357
Test name
Test status
Simulation time 1967314509 ps
CPU time 30.86 seconds
Started Jun 02 12:37:12 PM PDT 24
Finished Jun 02 12:37:43 PM PDT 24
Peak memory 232724 kb
Host smart-d8b127e9-3d87-4acd-8365-6c0ff46b5e8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4065188781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.4065188781
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3395056600
Short name T261
Test name
Test status
Simulation time 890878888 ps
CPU time 8.3 seconds
Started Jun 02 12:37:33 PM PDT 24
Finished Jun 02 12:37:43 PM PDT 24
Peak memory 199904 kb
Host smart-ac5b37f6-5138-4a47-a6cb-12a85ac02168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395056600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3395056600
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2423081077
Short name T151
Test name
Test status
Simulation time 11313383034 ps
CPU time 675.35 seconds
Started Jun 02 12:37:41 PM PDT 24
Finished Jun 02 12:48:57 PM PDT 24
Peak memory 662964 kb
Host smart-d8a1f062-48e0-4dc4-b913-a132369a0bef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2423081077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2423081077
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3011748025
Short name T548
Test name
Test status
Simulation time 18592575869 ps
CPU time 126.85 seconds
Started Jun 02 12:37:23 PM PDT 24
Finished Jun 02 12:39:31 PM PDT 24
Peak memory 199980 kb
Host smart-83c9a12d-a466-4515-bef3-cc8745eeedee
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011748025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3011748025
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.1164168571
Short name T213
Test name
Test status
Simulation time 2018941349 ps
CPU time 39.47 seconds
Started Jun 02 12:37:04 PM PDT 24
Finished Jun 02 12:37:44 PM PDT 24
Peak memory 199920 kb
Host smart-4d030497-d33d-42fd-ac29-3595287aefab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164168571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.1164168571
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.2629801106
Short name T158
Test name
Test status
Simulation time 233033589 ps
CPU time 4.72 seconds
Started Jun 02 12:37:08 PM PDT 24
Finished Jun 02 12:37:14 PM PDT 24
Peak memory 199916 kb
Host smart-d8930530-e861-4db0-adb2-ce3dded38c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629801106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.2629801106
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.2006709119
Short name T75
Test name
Test status
Simulation time 160809782587 ps
CPU time 1368.82 seconds
Started Jun 02 12:37:08 PM PDT 24
Finished Jun 02 12:59:58 PM PDT 24
Peak memory 647844 kb
Host smart-57f8ec34-5d3d-4409-87a2-8629aef6b028
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006709119 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2006709119
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.3851136263
Short name T285
Test name
Test status
Simulation time 64309508 ps
CPU time 1.22 seconds
Started Jun 02 12:37:03 PM PDT 24
Finished Jun 02 12:37:05 PM PDT 24
Peak memory 199672 kb
Host smart-b6a19555-adec-4875-a622-fa5b04903e14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851136263 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.3851136263
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.3172504605
Short name T461
Test name
Test status
Simulation time 32184560117 ps
CPU time 472.2 seconds
Started Jun 02 12:37:37 PM PDT 24
Finished Jun 02 12:45:30 PM PDT 24
Peak memory 199912 kb
Host smart-abbcc0d2-ac5b-46d2-9238-96e3223a0034
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172504605 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.3172504605
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3634796031
Short name T430
Test name
Test status
Simulation time 1204273738 ps
CPU time 16.18 seconds
Started Jun 02 12:37:11 PM PDT 24
Finished Jun 02 12:37:28 PM PDT 24
Peak memory 199964 kb
Host smart-2dae3c84-e215-487e-b230-3525e94c7085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634796031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3634796031
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3196809978
Short name T547
Test name
Test status
Simulation time 30433299 ps
CPU time 0.6 seconds
Started Jun 02 12:37:29 PM PDT 24
Finished Jun 02 12:37:31 PM PDT 24
Peak memory 195792 kb
Host smart-227fd2f0-957e-43ca-9532-55f547ed2a72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196809978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3196809978
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.3753072236
Short name T488
Test name
Test status
Simulation time 441384156 ps
CPU time 18.54 seconds
Started Jun 02 12:38:23 PM PDT 24
Finished Jun 02 12:38:42 PM PDT 24
Peak memory 208108 kb
Host smart-6d45fd99-5757-496a-8932-1534e1b55077
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3753072236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3753072236
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1049343588
Short name T79
Test name
Test status
Simulation time 12495653706 ps
CPU time 65.66 seconds
Started Jun 02 12:37:10 PM PDT 24
Finished Jun 02 12:38:16 PM PDT 24
Peak memory 199996 kb
Host smart-09fbe868-179b-4d89-a6c8-e2a885772764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049343588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1049343588
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1057500026
Short name T582
Test name
Test status
Simulation time 5960841991 ps
CPU time 778.55 seconds
Started Jun 02 12:37:13 PM PDT 24
Finished Jun 02 12:50:13 PM PDT 24
Peak memory 698376 kb
Host smart-4e23aeda-0ecd-4fef-bcf7-5e6cb746e781
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1057500026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1057500026
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2039124880
Short name T33
Test name
Test status
Simulation time 416757820 ps
CPU time 10.98 seconds
Started Jun 02 12:38:23 PM PDT 24
Finished Jun 02 12:38:35 PM PDT 24
Peak memory 199768 kb
Host smart-c56db4a4-724f-4f95-9dec-108bd9f58fb7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039124880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2039124880
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.4217701441
Short name T382
Test name
Test status
Simulation time 113999661916 ps
CPU time 129.76 seconds
Started Jun 02 12:37:14 PM PDT 24
Finished Jun 02 12:39:24 PM PDT 24
Peak memory 199988 kb
Host smart-a039bbf6-3628-4c40-b6f8-a40cdd7b8fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217701441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.4217701441
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1728440382
Short name T286
Test name
Test status
Simulation time 2048182153 ps
CPU time 12.07 seconds
Started Jun 02 12:37:05 PM PDT 24
Finished Jun 02 12:37:17 PM PDT 24
Peak memory 199900 kb
Host smart-5f8a368c-04d8-4a29-a9cf-cb7627b57ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728440382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1728440382
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.1757119613
Short name T277
Test name
Test status
Simulation time 3563711058 ps
CPU time 110.42 seconds
Started Jun 02 12:37:16 PM PDT 24
Finished Jun 02 12:39:07 PM PDT 24
Peak memory 200036 kb
Host smart-fef7aecb-51cb-4f47-94b8-9eb01251c6a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757119613 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1757119613
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.4046424909
Short name T330
Test name
Test status
Simulation time 31793372 ps
CPU time 1.28 seconds
Started Jun 02 12:37:02 PM PDT 24
Finished Jun 02 12:37:03 PM PDT 24
Peak memory 199908 kb
Host smart-f897ce89-7b62-43a9-9f89-9825240720de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046424909 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.4046424909
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.3724751605
Short name T102
Test name
Test status
Simulation time 80120131901 ps
CPU time 523.93 seconds
Started Jun 02 12:37:32 PM PDT 24
Finished Jun 02 12:46:17 PM PDT 24
Peak memory 199928 kb
Host smart-add8f21e-ca4a-4af4-960f-010c0b9005eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724751605 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.3724751605
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.2965650808
Short name T256
Test name
Test status
Simulation time 782248608 ps
CPU time 42.37 seconds
Started Jun 02 12:37:31 PM PDT 24
Finished Jun 02 12:38:14 PM PDT 24
Peak memory 199948 kb
Host smart-6d86b679-fdb6-4283-9f43-35c176a1e691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965650808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2965650808
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2958761392
Short name T249
Test name
Test status
Simulation time 14051472 ps
CPU time 0.61 seconds
Started Jun 02 12:37:37 PM PDT 24
Finished Jun 02 12:37:39 PM PDT 24
Peak memory 195808 kb
Host smart-132a5b16-7b2a-4c12-92b6-dc81dd281475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958761392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2958761392
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1988062739
Short name T322
Test name
Test status
Simulation time 4230087377 ps
CPU time 45.98 seconds
Started Jun 02 12:37:22 PM PDT 24
Finished Jun 02 12:38:09 PM PDT 24
Peak memory 208476 kb
Host smart-cea47d8e-5540-44f9-8524-7cf99365bdd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1988062739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1988062739
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2112529313
Short name T309
Test name
Test status
Simulation time 112794793 ps
CPU time 5.6 seconds
Started Jun 02 12:37:18 PM PDT 24
Finished Jun 02 12:37:24 PM PDT 24
Peak memory 199924 kb
Host smart-1946e08a-bb18-47e8-9e47-0e9e397713d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112529313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2112529313
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.4152179881
Short name T520
Test name
Test status
Simulation time 7542806353 ps
CPU time 353.51 seconds
Started Jun 02 12:37:31 PM PDT 24
Finished Jun 02 12:43:25 PM PDT 24
Peak memory 684112 kb
Host smart-dc05f611-8be5-4d2e-9726-514c7aed766f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4152179881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.4152179881
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.3279021808
Short name T389
Test name
Test status
Simulation time 1791387804 ps
CPU time 33.93 seconds
Started Jun 02 12:37:12 PM PDT 24
Finished Jun 02 12:37:46 PM PDT 24
Peak memory 199824 kb
Host smart-89695db4-3e0d-42d0-bbf6-6829f044bed0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279021808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3279021808
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.2547628770
Short name T231
Test name
Test status
Simulation time 14653038305 ps
CPU time 114.89 seconds
Started Jun 02 12:37:08 PM PDT 24
Finished Jun 02 12:39:03 PM PDT 24
Peak memory 199940 kb
Host smart-388c5102-67ee-4610-8dc8-dd8bae9d5686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547628770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2547628770
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2006513965
Short name T525
Test name
Test status
Simulation time 54193473 ps
CPU time 1.32 seconds
Started Jun 02 12:37:13 PM PDT 24
Finished Jun 02 12:37:15 PM PDT 24
Peak memory 199652 kb
Host smart-01a24790-8646-4d62-82fb-1d2fec2b4cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006513965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2006513965
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.3624860632
Short name T17
Test name
Test status
Simulation time 434309022409 ps
CPU time 1836.1 seconds
Started Jun 02 12:37:40 PM PDT 24
Finished Jun 02 01:08:17 PM PDT 24
Peak memory 248316 kb
Host smart-f2fb3def-b5bb-4252-9153-7977c5c7a515
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624860632 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3624860632
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.2626694097
Short name T526
Test name
Test status
Simulation time 34213775 ps
CPU time 1.25 seconds
Started Jun 02 12:37:17 PM PDT 24
Finished Jun 02 12:37:19 PM PDT 24
Peak memory 199868 kb
Host smart-3b0476ec-c2de-4d1e-b740-c01e9526b2a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626694097 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.2626694097
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.2161801812
Short name T549
Test name
Test status
Simulation time 37142199808 ps
CPU time 502.97 seconds
Started Jun 02 12:37:13 PM PDT 24
Finished Jun 02 12:45:37 PM PDT 24
Peak memory 199908 kb
Host smart-2834c630-aa0e-4d4e-8393-8da4667cb3b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161801812 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.2161801812
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.43661410
Short name T471
Test name
Test status
Simulation time 133244571 ps
CPU time 7.7 seconds
Started Jun 02 12:37:16 PM PDT 24
Finished Jun 02 12:37:25 PM PDT 24
Peak memory 199924 kb
Host smart-b2323604-4e25-4a95-9082-ea38019fd5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43661410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.43661410
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.364469631
Short name T227
Test name
Test status
Simulation time 28933092 ps
CPU time 0.62 seconds
Started Jun 02 12:37:18 PM PDT 24
Finished Jun 02 12:37:19 PM PDT 24
Peak memory 195804 kb
Host smart-23aed295-aa2e-48f9-a899-0f724c86b6f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364469631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.364469631
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2494745230
Short name T84
Test name
Test status
Simulation time 507636865 ps
CPU time 11.5 seconds
Started Jun 02 12:37:08 PM PDT 24
Finished Jun 02 12:37:20 PM PDT 24
Peak memory 199864 kb
Host smart-f5a359f6-46e6-4fb6-902c-fadf7bb32ecc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2494745230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2494745230
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3956907770
Short name T434
Test name
Test status
Simulation time 5488363183 ps
CPU time 54.09 seconds
Started Jun 02 12:37:13 PM PDT 24
Finished Jun 02 12:38:07 PM PDT 24
Peak memory 199964 kb
Host smart-61e00e97-d5b3-428b-82b4-d594552da82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956907770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3956907770
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.3484413999
Short name T295
Test name
Test status
Simulation time 26447998716 ps
CPU time 769.84 seconds
Started Jun 02 12:37:20 PM PDT 24
Finished Jun 02 12:50:10 PM PDT 24
Peak memory 705068 kb
Host smart-de04eec2-4050-46bf-a3f3-1a52c46a19bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3484413999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3484413999
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.2594033978
Short name T578
Test name
Test status
Simulation time 22472000041 ps
CPU time 71.23 seconds
Started Jun 02 12:37:27 PM PDT 24
Finished Jun 02 12:38:39 PM PDT 24
Peak memory 199908 kb
Host smart-55aa7700-22b4-4417-ae49-76af5d6d2a74
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594033978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.2594033978
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.288483795
Short name T508
Test name
Test status
Simulation time 5654211651 ps
CPU time 87.01 seconds
Started Jun 02 12:37:17 PM PDT 24
Finished Jun 02 12:38:44 PM PDT 24
Peak memory 200024 kb
Host smart-1cf86dab-bf29-458d-9fff-14fa23e3b265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288483795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.288483795
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.1508636886
Short name T224
Test name
Test status
Simulation time 1181254246 ps
CPU time 6.99 seconds
Started Jun 02 12:37:33 PM PDT 24
Finished Jun 02 12:37:41 PM PDT 24
Peak memory 199932 kb
Host smart-6f6c1c94-49b4-412e-b1ed-48995a3afdef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508636886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1508636886
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.1543397898
Short name T532
Test name
Test status
Simulation time 7912184711 ps
CPU time 50.37 seconds
Started Jun 02 12:37:33 PM PDT 24
Finished Jun 02 12:38:25 PM PDT 24
Peak memory 224480 kb
Host smart-7a33e023-0db1-43ba-8eba-ae0086046576
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543397898 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1543397898
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.4006531865
Short name T347
Test name
Test status
Simulation time 133871878 ps
CPU time 1.38 seconds
Started Jun 02 12:37:16 PM PDT 24
Finished Jun 02 12:37:18 PM PDT 24
Peak memory 199944 kb
Host smart-fd70b120-ec72-442e-b194-9dc3cdf1bcbd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006531865 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.4006531865
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.3807855769
Short name T365
Test name
Test status
Simulation time 133346249632 ps
CPU time 510.57 seconds
Started Jun 02 12:37:10 PM PDT 24
Finished Jun 02 12:45:42 PM PDT 24
Peak memory 200348 kb
Host smart-42f3c448-8f05-4d10-ba26-d9d53004728b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807855769 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.3807855769
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.4113608552
Short name T506
Test name
Test status
Simulation time 14215963961 ps
CPU time 37.31 seconds
Started Jun 02 12:37:19 PM PDT 24
Finished Jun 02 12:37:57 PM PDT 24
Peak memory 199904 kb
Host smart-195ce6fd-f5ee-452a-86fa-831b945cfdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113608552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.4113608552
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2724376472
Short name T550
Test name
Test status
Simulation time 13268902 ps
CPU time 0.62 seconds
Started Jun 02 12:37:33 PM PDT 24
Finished Jun 02 12:37:35 PM PDT 24
Peak memory 195796 kb
Host smart-b9b2d144-92ad-4c7b-9b0f-de56431a7fcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724376472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2724376472
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1111632997
Short name T457
Test name
Test status
Simulation time 1206482211 ps
CPU time 19.47 seconds
Started Jun 02 12:37:13 PM PDT 24
Finished Jun 02 12:37:32 PM PDT 24
Peak memory 231952 kb
Host smart-3a049e35-55ff-4529-9fa1-9b870ee1312b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1111632997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1111632997
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2320475355
Short name T211
Test name
Test status
Simulation time 2426111489 ps
CPU time 48.06 seconds
Started Jun 02 12:37:50 PM PDT 24
Finished Jun 02 12:38:39 PM PDT 24
Peak memory 199976 kb
Host smart-78ec3c52-0ddd-48c2-aea9-897af807987c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320475355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2320475355
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1299192119
Short name T152
Test name
Test status
Simulation time 2709411569 ps
CPU time 339.67 seconds
Started Jun 02 12:37:35 PM PDT 24
Finished Jun 02 12:43:15 PM PDT 24
Peak memory 657448 kb
Host smart-8282e773-230b-4fc1-9d81-67df69dd56e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1299192119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1299192119
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1502914125
Short name T509
Test name
Test status
Simulation time 10490778145 ps
CPU time 71.41 seconds
Started Jun 02 12:37:23 PM PDT 24
Finished Jun 02 12:38:35 PM PDT 24
Peak memory 199948 kb
Host smart-139de254-3bde-45dd-a499-73b83f8c9a0b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502914125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1502914125
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.4082903489
Short name T132
Test name
Test status
Simulation time 6926009931 ps
CPU time 64.2 seconds
Started Jun 02 12:37:26 PM PDT 24
Finished Jun 02 12:38:31 PM PDT 24
Peak memory 199960 kb
Host smart-968167b1-2aa6-4200-8797-ca7de5e8a04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082903489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.4082903489
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2673743560
Short name T527
Test name
Test status
Simulation time 760480818 ps
CPU time 5.51 seconds
Started Jun 02 12:37:22 PM PDT 24
Finished Jun 02 12:37:28 PM PDT 24
Peak memory 199932 kb
Host smart-1b21e4f9-b282-4217-92e1-f4adb61cd4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673743560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2673743560
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.4045630784
Short name T250
Test name
Test status
Simulation time 28740563409 ps
CPU time 521.46 seconds
Started Jun 02 12:37:24 PM PDT 24
Finished Jun 02 12:46:06 PM PDT 24
Peak memory 199968 kb
Host smart-b92d71eb-e9f1-4d68-ad35-1097f35ef531
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045630784 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.4045630784
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.2765240662
Short name T207
Test name
Test status
Simulation time 120657594 ps
CPU time 1.34 seconds
Started Jun 02 12:37:17 PM PDT 24
Finished Jun 02 12:37:18 PM PDT 24
Peak memory 199912 kb
Host smart-59e22a5d-4c25-4a25-b3b8-48fc44ef1f23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765240662 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.2765240662
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.1436379489
Short name T80
Test name
Test status
Simulation time 8165289528 ps
CPU time 458.11 seconds
Started Jun 02 12:37:22 PM PDT 24
Finished Jun 02 12:45:01 PM PDT 24
Peak memory 200200 kb
Host smart-494afe76-1dfc-4a01-9d7f-59ba1b160f25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436379489 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.1436379489
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1800954827
Short name T372
Test name
Test status
Simulation time 9567150752 ps
CPU time 35.12 seconds
Started Jun 02 12:37:21 PM PDT 24
Finished Jun 02 12:37:57 PM PDT 24
Peak memory 199952 kb
Host smart-a04dfcd4-ad6c-48a5-a5fc-2dfba91419ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800954827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1800954827
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3084832409
Short name T61
Test name
Test status
Simulation time 42284933 ps
CPU time 0.57 seconds
Started Jun 02 12:37:27 PM PDT 24
Finished Jun 02 12:37:28 PM PDT 24
Peak memory 196508 kb
Host smart-77e3281e-9f43-4f80-96bd-45a7a49d8d2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084832409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3084832409
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.76520253
Short name T448
Test name
Test status
Simulation time 304157925 ps
CPU time 7.44 seconds
Started Jun 02 12:37:37 PM PDT 24
Finished Jun 02 12:37:45 PM PDT 24
Peak memory 208092 kb
Host smart-75e9cc72-bf50-4b4b-b474-e04f80be758c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=76520253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.76520253
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.518806279
Short name T146
Test name
Test status
Simulation time 1810253356 ps
CPU time 35.93 seconds
Started Jun 02 12:37:21 PM PDT 24
Finished Jun 02 12:37:57 PM PDT 24
Peak memory 199904 kb
Host smart-9c3157e0-ad49-4595-ac96-dc6c1af524c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518806279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.518806279
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2335553356
Short name T324
Test name
Test status
Simulation time 15717997727 ps
CPU time 632.93 seconds
Started Jun 02 12:37:27 PM PDT 24
Finished Jun 02 12:48:01 PM PDT 24
Peak memory 675808 kb
Host smart-76f45c30-06bd-4972-8125-86ac277d7fbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2335553356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2335553356
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.1590541601
Short name T193
Test name
Test status
Simulation time 18825819570 ps
CPU time 64.28 seconds
Started Jun 02 12:37:27 PM PDT 24
Finished Jun 02 12:38:32 PM PDT 24
Peak memory 199948 kb
Host smart-0ac56e0a-0631-4482-a7e8-b35a6f1980c1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590541601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1590541601
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1946846993
Short name T156
Test name
Test status
Simulation time 5169804080 ps
CPU time 49.54 seconds
Started Jun 02 12:37:35 PM PDT 24
Finished Jun 02 12:38:25 PM PDT 24
Peak memory 200036 kb
Host smart-c73bcfb5-3c08-414d-9257-fd8500344580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946846993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1946846993
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.1776678784
Short name T314
Test name
Test status
Simulation time 115815834 ps
CPU time 2.2 seconds
Started Jun 02 12:37:21 PM PDT 24
Finished Jun 02 12:37:24 PM PDT 24
Peak memory 200320 kb
Host smart-91c74263-caf1-4ef5-85da-4a0e8ea9201d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776678784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1776678784
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3526413450
Short name T557
Test name
Test status
Simulation time 131058878195 ps
CPU time 4707.53 seconds
Started Jun 02 12:37:15 PM PDT 24
Finished Jun 02 01:55:43 PM PDT 24
Peak memory 872236 kb
Host smart-a3b1d9ef-87c4-4f65-ab8d-2c8913bc1669
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526413450 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3526413450
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.1954413822
Short name T329
Test name
Test status
Simulation time 65145395 ps
CPU time 1.33 seconds
Started Jun 02 12:37:36 PM PDT 24
Finished Jun 02 12:37:38 PM PDT 24
Peak memory 199936 kb
Host smart-8fadb6c8-f626-4519-bb30-c23b631e7ed0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954413822 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.1954413822
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.2337099917
Short name T336
Test name
Test status
Simulation time 212206921385 ps
CPU time 458.36 seconds
Started Jun 02 12:37:33 PM PDT 24
Finished Jun 02 12:45:12 PM PDT 24
Peak memory 199904 kb
Host smart-6fb8a2c5-3b68-4fa2-ba80-4f240bdb1170
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337099917 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.2337099917
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1919621434
Short name T134
Test name
Test status
Simulation time 1821771726 ps
CPU time 37.16 seconds
Started Jun 02 12:37:29 PM PDT 24
Finished Jun 02 12:38:06 PM PDT 24
Peak memory 199884 kb
Host smart-4e681b73-ea56-4049-b61e-1ffe033d52b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919621434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1919621434
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3599221364
Short name T287
Test name
Test status
Simulation time 11375591 ps
CPU time 0.56 seconds
Started Jun 02 12:37:31 PM PDT 24
Finished Jun 02 12:37:33 PM PDT 24
Peak memory 194776 kb
Host smart-b933ebe8-3e84-490a-93f7-03a3bb38d55d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599221364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3599221364
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1089045265
Short name T43
Test name
Test status
Simulation time 4020471763 ps
CPU time 49.1 seconds
Started Jun 02 12:37:27 PM PDT 24
Finished Jun 02 12:38:17 PM PDT 24
Peak memory 236780 kb
Host smart-dce8a23d-a441-40a6-b4a9-c7ba3f5d43f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1089045265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1089045265
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.373459715
Short name T420
Test name
Test status
Simulation time 1784892993 ps
CPU time 22.25 seconds
Started Jun 02 12:37:27 PM PDT 24
Finished Jun 02 12:37:50 PM PDT 24
Peak memory 199940 kb
Host smart-239e843b-6c2a-44e9-82ca-e2237b12073b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373459715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.373459715
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2836901757
Short name T291
Test name
Test status
Simulation time 5172036759 ps
CPU time 486.43 seconds
Started Jun 02 12:37:19 PM PDT 24
Finished Jun 02 12:45:26 PM PDT 24
Peak memory 717488 kb
Host smart-9441b932-c068-4234-abe5-07072561891e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2836901757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2836901757
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.3059984114
Short name T142
Test name
Test status
Simulation time 5907719081 ps
CPU time 100.22 seconds
Started Jun 02 12:37:34 PM PDT 24
Finished Jun 02 12:39:15 PM PDT 24
Peak memory 199932 kb
Host smart-78bbbaaf-17d7-45d2-889f-86141500934d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059984114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3059984114
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1096946261
Short name T333
Test name
Test status
Simulation time 1522661317 ps
CPU time 26.14 seconds
Started Jun 02 12:37:24 PM PDT 24
Finished Jun 02 12:37:51 PM PDT 24
Peak memory 199916 kb
Host smart-db92cc52-eddd-4309-a4ea-dd5abcd6a587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096946261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1096946261
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1583980126
Short name T308
Test name
Test status
Simulation time 193338708 ps
CPU time 6.85 seconds
Started Jun 02 12:37:26 PM PDT 24
Finished Jun 02 12:37:33 PM PDT 24
Peak memory 199924 kb
Host smart-80583747-68bc-49f4-aae2-ceed6ce20db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583980126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1583980126
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.2281447724
Short name T346
Test name
Test status
Simulation time 30480817610 ps
CPU time 161.61 seconds
Started Jun 02 12:37:27 PM PDT 24
Finished Jun 02 12:40:09 PM PDT 24
Peak memory 224564 kb
Host smart-ce1f9c6a-9819-4959-8df8-cc46e9a02c64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281447724 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2281447724
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.3733895031
Short name T264
Test name
Test status
Simulation time 31467934 ps
CPU time 1.32 seconds
Started Jun 02 12:37:23 PM PDT 24
Finished Jun 02 12:37:24 PM PDT 24
Peak memory 199948 kb
Host smart-cfc67761-42f6-444b-95b4-2ab5b728a8dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733895031 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.3733895031
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.1827289265
Short name T177
Test name
Test status
Simulation time 37665819482 ps
CPU time 490.8 seconds
Started Jun 02 12:37:44 PM PDT 24
Finished Jun 02 12:45:56 PM PDT 24
Peak memory 199904 kb
Host smart-e6623aa1-3d86-4637-b73d-bbb7db1f6512
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827289265 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.1827289265
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.517237610
Short name T204
Test name
Test status
Simulation time 1513551097 ps
CPU time 69.44 seconds
Started Jun 02 12:37:20 PM PDT 24
Finished Jun 02 12:38:30 PM PDT 24
Peak memory 199876 kb
Host smart-109520ac-375c-4b65-9d9f-4d0660c7dd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517237610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.517237610
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.910302041
Short name T201
Test name
Test status
Simulation time 113798835 ps
CPU time 0.63 seconds
Started Jun 02 12:37:35 PM PDT 24
Finished Jun 02 12:37:36 PM PDT 24
Peak memory 195812 kb
Host smart-6ee37751-22f0-4f3f-bfc0-d08c49db9865
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910302041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.910302041
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.1506244650
Short name T370
Test name
Test status
Simulation time 4528885364 ps
CPU time 53.69 seconds
Started Jun 02 12:37:15 PM PDT 24
Finished Jun 02 12:38:10 PM PDT 24
Peak memory 216392 kb
Host smart-50481bab-914e-4a29-b6d0-35b3dd8be11e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1506244650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.1506244650
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3562461472
Short name T573
Test name
Test status
Simulation time 2805287289 ps
CPU time 39.47 seconds
Started Jun 02 12:37:20 PM PDT 24
Finished Jun 02 12:38:00 PM PDT 24
Peak memory 200008 kb
Host smart-3e628efc-5a88-4d6a-8490-37f200533c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562461472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3562461472
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.314760800
Short name T63
Test name
Test status
Simulation time 6089115034 ps
CPU time 729.01 seconds
Started Jun 02 12:37:22 PM PDT 24
Finished Jun 02 12:49:31 PM PDT 24
Peak memory 689476 kb
Host smart-d04f1c8b-0e7a-4724-ab96-9ecb116cf9ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=314760800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.314760800
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.366918190
Short name T78
Test name
Test status
Simulation time 502889567 ps
CPU time 9.94 seconds
Started Jun 02 12:37:18 PM PDT 24
Finished Jun 02 12:37:28 PM PDT 24
Peak memory 199828 kb
Host smart-b11c1e72-fa68-46a3-add9-3f05a053a1d0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366918190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.366918190
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.774397309
Short name T459
Test name
Test status
Simulation time 2392363724 ps
CPU time 34.97 seconds
Started Jun 02 12:37:33 PM PDT 24
Finished Jun 02 12:38:09 PM PDT 24
Peak memory 200000 kb
Host smart-1dc72740-eba0-402a-bb71-1b39204f5c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774397309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.774397309
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2770869396
Short name T392
Test name
Test status
Simulation time 681422017 ps
CPU time 7.21 seconds
Started Jun 02 12:37:27 PM PDT 24
Finished Jun 02 12:37:35 PM PDT 24
Peak memory 199860 kb
Host smart-40eb1fac-5ce3-4b82-9631-8b6130c52d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770869396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2770869396
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.3752442511
Short name T429
Test name
Test status
Simulation time 76688603099 ps
CPU time 1921.28 seconds
Started Jun 02 12:37:26 PM PDT 24
Finished Jun 02 01:09:29 PM PDT 24
Peak memory 773728 kb
Host smart-c08e3e5d-6a22-4d4d-81fc-2d6c39b53e73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752442511 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3752442511
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.31095509
Short name T388
Test name
Test status
Simulation time 365774919 ps
CPU time 1.04 seconds
Started Jun 02 12:37:38 PM PDT 24
Finished Jun 02 12:37:39 PM PDT 24
Peak memory 199740 kb
Host smart-ab2539e5-4cc1-446c-8175-73660df685d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31095509 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.hmac_test_hmac_vectors.31095509
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.505848443
Short name T352
Test name
Test status
Simulation time 36600756089 ps
CPU time 510.53 seconds
Started Jun 02 12:37:16 PM PDT 24
Finished Jun 02 12:45:47 PM PDT 24
Peak memory 199948 kb
Host smart-85d5dd30-5a6c-4a46-a9a9-0ea86afe541d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505848443 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.505848443
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2274392713
Short name T157
Test name
Test status
Simulation time 2910683087 ps
CPU time 33.67 seconds
Started Jun 02 12:37:37 PM PDT 24
Finished Jun 02 12:38:12 PM PDT 24
Peak memory 200032 kb
Host smart-1db22801-4dc6-46d5-8375-6a1df72522d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274392713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2274392713
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2761438124
Short name T442
Test name
Test status
Simulation time 15346648 ps
CPU time 0.61 seconds
Started Jun 02 12:37:24 PM PDT 24
Finished Jun 02 12:37:25 PM PDT 24
Peak memory 195816 kb
Host smart-2a1dd272-7e18-4093-adcb-b24fb35a4748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761438124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2761438124
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2855298545
Short name T591
Test name
Test status
Simulation time 1085904145 ps
CPU time 28.61 seconds
Started Jun 02 12:37:30 PM PDT 24
Finished Jun 02 12:37:59 PM PDT 24
Peak memory 222664 kb
Host smart-8f52825f-6ccb-411c-8f3b-9037723e190a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2855298545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2855298545
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3055688151
Short name T254
Test name
Test status
Simulation time 1498564239 ps
CPU time 29.14 seconds
Started Jun 02 12:37:26 PM PDT 24
Finished Jun 02 12:37:56 PM PDT 24
Peak memory 199920 kb
Host smart-93b1eb96-2e9b-475e-9a26-3fde77c174ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055688151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3055688151
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.515052314
Short name T23
Test name
Test status
Simulation time 7543980097 ps
CPU time 428.57 seconds
Started Jun 02 12:37:22 PM PDT 24
Finished Jun 02 12:44:31 PM PDT 24
Peak memory 676488 kb
Host smart-15f2a032-2bb1-44e7-b7bf-b4ad6900ebf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=515052314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.515052314
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.1253261838
Short name T154
Test name
Test status
Simulation time 1045544996 ps
CPU time 12.96 seconds
Started Jun 02 12:37:07 PM PDT 24
Finished Jun 02 12:37:21 PM PDT 24
Peak memory 199936 kb
Host smart-6c860c16-561a-4bfe-a45b-49e3dd282e7a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253261838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1253261838
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.446731402
Short name T572
Test name
Test status
Simulation time 7345493527 ps
CPU time 93.88 seconds
Started Jun 02 12:37:42 PM PDT 24
Finished Jun 02 12:39:16 PM PDT 24
Peak memory 200044 kb
Host smart-26311c98-46c6-4ef9-87ca-1ce2e8cc2e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446731402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.446731402
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2380503198
Short name T265
Test name
Test status
Simulation time 847922860 ps
CPU time 7.8 seconds
Started Jun 02 12:37:16 PM PDT 24
Finished Jun 02 12:37:25 PM PDT 24
Peak memory 199972 kb
Host smart-54bdbfed-3fb2-43f0-8b06-5a68a194038d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380503198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2380503198
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2583121484
Short name T387
Test name
Test status
Simulation time 35393967059 ps
CPU time 894.7 seconds
Started Jun 02 12:37:33 PM PDT 24
Finished Jun 02 12:52:29 PM PDT 24
Peak memory 672144 kb
Host smart-f4a43289-4ab2-4533-b226-2a9390247b52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583121484 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2583121484
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.638274426
Short name T294
Test name
Test status
Simulation time 47975678 ps
CPU time 1.12 seconds
Started Jun 02 12:37:12 PM PDT 24
Finished Jun 02 12:37:14 PM PDT 24
Peak memory 199664 kb
Host smart-d5b2ae84-be5b-43f0-901f-48808aab3701
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638274426 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_hmac_vectors.638274426
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.4242770911
Short name T558
Test name
Test status
Simulation time 255083309800 ps
CPU time 530.85 seconds
Started Jun 02 12:37:15 PM PDT 24
Finished Jun 02 12:46:06 PM PDT 24
Peak memory 199932 kb
Host smart-66610c71-25b7-46bd-8dc8-103c3ffbce2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242770911 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.4242770911
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.2392980792
Short name T262
Test name
Test status
Simulation time 1772920710 ps
CPU time 21.82 seconds
Started Jun 02 12:37:28 PM PDT 24
Finished Jun 02 12:37:50 PM PDT 24
Peak memory 199876 kb
Host smart-0b589552-42de-42cc-9dee-a233e2a9be69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392980792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.2392980792
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.2368901038
Short name T535
Test name
Test status
Simulation time 33590876 ps
CPU time 0.62 seconds
Started Jun 02 12:36:25 PM PDT 24
Finished Jun 02 12:36:26 PM PDT 24
Peak memory 194776 kb
Host smart-6b982ab7-58f4-4a93-9fa1-f4c208863c56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368901038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.2368901038
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.937233365
Short name T20
Test name
Test status
Simulation time 129273360 ps
CPU time 5.06 seconds
Started Jun 02 12:36:11 PM PDT 24
Finished Jun 02 12:36:16 PM PDT 24
Peak memory 199908 kb
Host smart-427e0c6a-518d-4c81-b796-02a52af15bfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=937233365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.937233365
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1833019870
Short name T514
Test name
Test status
Simulation time 11034666325 ps
CPU time 43.62 seconds
Started Jun 02 12:36:17 PM PDT 24
Finished Jun 02 12:37:01 PM PDT 24
Peak memory 199956 kb
Host smart-e07c4369-0914-41fb-876d-1d6a8110ee19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833019870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1833019870
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.476970175
Short name T326
Test name
Test status
Simulation time 448448678 ps
CPU time 27.35 seconds
Started Jun 02 12:36:26 PM PDT 24
Finished Jun 02 12:36:54 PM PDT 24
Peak memory 248224 kb
Host smart-5d122a4e-3d19-420c-bc74-1b3a1a7a4a03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=476970175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.476970175
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1828391898
Short name T143
Test name
Test status
Simulation time 5584077822 ps
CPU time 35.82 seconds
Started Jun 02 12:36:20 PM PDT 24
Finished Jun 02 12:36:56 PM PDT 24
Peak memory 199952 kb
Host smart-22262af9-6b0a-4ad0-9e72-baf0b7fa91ea
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828391898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1828391898
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.310029357
Short name T465
Test name
Test status
Simulation time 6298968010 ps
CPU time 57.46 seconds
Started Jun 02 12:36:17 PM PDT 24
Finished Jun 02 12:37:15 PM PDT 24
Peak memory 200016 kb
Host smart-33150353-961a-4ee3-9091-19e4fe196202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310029357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.310029357
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.195614334
Short name T82
Test name
Test status
Simulation time 329390012 ps
CPU time 5.46 seconds
Started Jun 02 12:37:00 PM PDT 24
Finished Jun 02 12:37:06 PM PDT 24
Peak memory 199820 kb
Host smart-427c4729-08f8-41f3-895e-a5e3eee69be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195614334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.195614334
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.754720409
Short name T233
Test name
Test status
Simulation time 3189411393 ps
CPU time 170.34 seconds
Started Jun 02 12:36:06 PM PDT 24
Finished Jun 02 12:38:57 PM PDT 24
Peak memory 199984 kb
Host smart-751fab5d-af5c-4beb-a70c-20a59110c625
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754720409 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.754720409
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.778642416
Short name T460
Test name
Test status
Simulation time 60897506 ps
CPU time 1.29 seconds
Started Jun 02 12:36:16 PM PDT 24
Finished Jun 02 12:36:18 PM PDT 24
Peak memory 199856 kb
Host smart-60aee2d6-070f-4e88-b334-b7a71a90a80c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778642416 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_hmac_vectors.778642416
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.3742646624
Short name T222
Test name
Test status
Simulation time 40139669349 ps
CPU time 514.71 seconds
Started Jun 02 12:36:20 PM PDT 24
Finished Jun 02 12:44:55 PM PDT 24
Peak memory 199976 kb
Host smart-c0af8909-aa45-47a3-9f82-ddc6616ec18d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742646624 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.3742646624
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.2143104251
Short name T113
Test name
Test status
Simulation time 1083123416 ps
CPU time 54.53 seconds
Started Jun 02 12:36:28 PM PDT 24
Finished Jun 02 12:37:23 PM PDT 24
Peak memory 199876 kb
Host smart-4593c615-1ce4-43e2-8e14-06f50aa88fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143104251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.2143104251
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1714477860
Short name T524
Test name
Test status
Simulation time 40341855 ps
CPU time 0.62 seconds
Started Jun 02 12:36:24 PM PDT 24
Finished Jun 02 12:36:25 PM PDT 24
Peak memory 194756 kb
Host smart-009f762d-d513-4b2f-8cc6-a7569175f2a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714477860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1714477860
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.491312048
Short name T358
Test name
Test status
Simulation time 1372291011 ps
CPU time 17.49 seconds
Started Jun 02 12:36:36 PM PDT 24
Finished Jun 02 12:36:54 PM PDT 24
Peak memory 218208 kb
Host smart-f6df902d-90cd-4ab7-90a2-7c6a44077bf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=491312048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.491312048
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.361731097
Short name T496
Test name
Test status
Simulation time 4101099325 ps
CPU time 56.57 seconds
Started Jun 02 12:36:42 PM PDT 24
Finished Jun 02 12:37:39 PM PDT 24
Peak memory 200372 kb
Host smart-f97004db-2f47-41e5-b0c0-52f28a60804d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361731097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.361731097
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_error.1898854
Short name T16
Test name
Test status
Simulation time 28158416869 ps
CPU time 182.59 seconds
Started Jun 02 12:36:25 PM PDT 24
Finished Jun 02 12:39:28 PM PDT 24
Peak memory 199896 kb
Host smart-e9a6e886-ec28-4fde-9ad1-26c8d7d2dba0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1898854
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3427150287
Short name T423
Test name
Test status
Simulation time 14574908709 ps
CPU time 81.86 seconds
Started Jun 02 12:36:35 PM PDT 24
Finished Jun 02 12:37:57 PM PDT 24
Peak memory 200016 kb
Host smart-18deba2e-dfef-4b61-8872-3c3b6a4a9ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427150287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3427150287
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2314867519
Short name T492
Test name
Test status
Simulation time 2640269665 ps
CPU time 12.51 seconds
Started Jun 02 12:36:19 PM PDT 24
Finished Jun 02 12:36:32 PM PDT 24
Peak memory 199972 kb
Host smart-98f2cb5e-9c5e-425d-8e76-eb152d573f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314867519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2314867519
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.2637986833
Short name T114
Test name
Test status
Simulation time 44707069116 ps
CPU time 1973.63 seconds
Started Jun 02 12:36:22 PM PDT 24
Finished Jun 02 01:09:21 PM PDT 24
Peak memory 749768 kb
Host smart-9eadc901-6685-4229-88ae-e58b66573610
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637986833 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2637986833
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.1938566391
Short name T15
Test name
Test status
Simulation time 87725699213 ps
CPU time 740.07 seconds
Started Jun 02 12:36:36 PM PDT 24
Finished Jun 02 12:49:01 PM PDT 24
Peak memory 216404 kb
Host smart-7518a815-a43e-42fb-8af6-28c21385c010
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1938566391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.1938566391
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.344257137
Short name T185
Test name
Test status
Simulation time 438312523 ps
CPU time 1.31 seconds
Started Jun 02 12:36:19 PM PDT 24
Finished Jun 02 12:36:21 PM PDT 24
Peak memory 199908 kb
Host smart-5c0884f0-dcd9-4a01-9c86-495082d67513
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344257137 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_hmac_vectors.344257137
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.3532813962
Short name T552
Test name
Test status
Simulation time 41188970504 ps
CPU time 540.62 seconds
Started Jun 02 12:36:36 PM PDT 24
Finished Jun 02 12:45:37 PM PDT 24
Peak memory 199972 kb
Host smart-5f2f42e8-df5a-4525-a485-f5557d775b16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532813962 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.3532813962
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1413537236
Short name T209
Test name
Test status
Simulation time 1280536611 ps
CPU time 29.5 seconds
Started Jun 02 12:36:36 PM PDT 24
Finished Jun 02 12:37:06 PM PDT 24
Peak memory 199868 kb
Host smart-04d09d3c-ceda-4334-9480-f904578ea76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413537236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1413537236
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.4032163923
Short name T345
Test name
Test status
Simulation time 19120490 ps
CPU time 0.59 seconds
Started Jun 02 12:36:21 PM PDT 24
Finished Jun 02 12:36:22 PM PDT 24
Peak memory 194840 kb
Host smart-8e2a2f3c-8369-4951-a884-c7f3213e5d99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032163923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.4032163923
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.3035436494
Short name T270
Test name
Test status
Simulation time 1078004358 ps
CPU time 21.07 seconds
Started Jun 02 12:36:24 PM PDT 24
Finished Jun 02 12:36:46 PM PDT 24
Peak memory 207884 kb
Host smart-7917d3ab-d708-4699-9dc6-dbff5ac2774f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3035436494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3035436494
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.4029623270
Short name T580
Test name
Test status
Simulation time 3894481655 ps
CPU time 19 seconds
Started Jun 02 12:36:35 PM PDT 24
Finished Jun 02 12:36:54 PM PDT 24
Peak memory 199972 kb
Host smart-e3642d98-0e0b-48ce-be9a-e5804ec94a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029623270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.4029623270
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.188162140
Short name T417
Test name
Test status
Simulation time 1344345751 ps
CPU time 435.99 seconds
Started Jun 02 12:36:45 PM PDT 24
Finished Jun 02 12:44:06 PM PDT 24
Peak memory 715588 kb
Host smart-ee836536-7500-44ce-bd17-998991ffbd6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=188162140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.188162140
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1502697605
Short name T195
Test name
Test status
Simulation time 6801835492 ps
CPU time 89.36 seconds
Started Jun 02 12:36:28 PM PDT 24
Finished Jun 02 12:37:58 PM PDT 24
Peak memory 199996 kb
Host smart-21c02671-8a0a-4624-be03-6185c836a456
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502697605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1502697605
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_smoke.1008970088
Short name T483
Test name
Test status
Simulation time 152556697 ps
CPU time 2.73 seconds
Started Jun 02 12:36:16 PM PDT 24
Finished Jun 02 12:36:19 PM PDT 24
Peak memory 199968 kb
Host smart-05900335-3cbe-4385-b931-bbb71561682c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008970088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1008970088
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.620019518
Short name T568
Test name
Test status
Simulation time 28601468592 ps
CPU time 3119.09 seconds
Started Jun 02 12:36:32 PM PDT 24
Finished Jun 02 01:28:32 PM PDT 24
Peak memory 823764 kb
Host smart-1be9efa8-1d82-4958-ad23-3230f35a394a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620019518 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.620019518
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.1405607696
Short name T215
Test name
Test status
Simulation time 85861679 ps
CPU time 1.26 seconds
Started Jun 02 12:36:45 PM PDT 24
Finished Jun 02 12:36:47 PM PDT 24
Peak memory 199944 kb
Host smart-572c9b45-39f3-4172-a34f-5e7823eff1e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405607696 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.1405607696
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.1227402552
Short name T348
Test name
Test status
Simulation time 8506384305 ps
CPU time 461.02 seconds
Started Jun 02 12:36:27 PM PDT 24
Finished Jun 02 12:44:08 PM PDT 24
Peak memory 199984 kb
Host smart-968dec64-75b8-4605-bffe-3a41ca6b991d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227402552 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.1227402552
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1998516884
Short name T390
Test name
Test status
Simulation time 25942813565 ps
CPU time 97.39 seconds
Started Jun 02 12:36:24 PM PDT 24
Finished Jun 02 12:38:02 PM PDT 24
Peak memory 199964 kb
Host smart-fd4f8857-f322-4ad4-8220-03b0114eb19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998516884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1998516884
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2550423624
Short name T251
Test name
Test status
Simulation time 16759416 ps
CPU time 0.62 seconds
Started Jun 02 12:36:28 PM PDT 24
Finished Jun 02 12:36:29 PM PDT 24
Peak memory 195552 kb
Host smart-35e6cd0d-b428-4e3f-bfac-8f03dae6b071
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550423624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2550423624
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2994755607
Short name T263
Test name
Test status
Simulation time 1815621768 ps
CPU time 41.72 seconds
Started Jun 02 12:36:40 PM PDT 24
Finished Jun 02 12:37:22 PM PDT 24
Peak memory 230956 kb
Host smart-bb27dc4f-8eb2-464c-bddd-65a7ece604dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2994755607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2994755607
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.1562674028
Short name T351
Test name
Test status
Simulation time 6305692933 ps
CPU time 379.17 seconds
Started Jun 02 12:36:56 PM PDT 24
Finished Jun 02 12:43:15 PM PDT 24
Peak memory 500440 kb
Host smart-7aad7408-4805-40c9-9a0b-710859312a72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1562674028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1562674028
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.849925509
Short name T362
Test name
Test status
Simulation time 1380199929 ps
CPU time 78.25 seconds
Started Jun 02 12:36:21 PM PDT 24
Finished Jun 02 12:37:40 PM PDT 24
Peak memory 199840 kb
Host smart-8d5b1c31-cb5f-442c-a068-07acf7b1cb1a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849925509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.849925509
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.267299332
Short name T10
Test name
Test status
Simulation time 17742902232 ps
CPU time 92.55 seconds
Started Jun 02 12:36:15 PM PDT 24
Finished Jun 02 12:37:49 PM PDT 24
Peak memory 199908 kb
Host smart-3aa046d0-ef2d-4a6a-9f02-41d192aad54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267299332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.267299332
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.915847109
Short name T180
Test name
Test status
Simulation time 66939367 ps
CPU time 2.75 seconds
Started Jun 02 12:36:36 PM PDT 24
Finished Jun 02 12:36:39 PM PDT 24
Peak memory 199924 kb
Host smart-0e9ac64a-5f59-4b94-8e59-3c30143ab9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915847109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.915847109
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2739214813
Short name T511
Test name
Test status
Simulation time 60752668962 ps
CPU time 774.78 seconds
Started Jun 02 12:36:42 PM PDT 24
Finished Jun 02 12:49:38 PM PDT 24
Peak memory 215712 kb
Host smart-48d0d7ec-4647-4589-9447-f6817b77f3c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739214813 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2739214813
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.3153163989
Short name T432
Test name
Test status
Simulation time 184161725 ps
CPU time 1.05 seconds
Started Jun 02 12:36:44 PM PDT 24
Finished Jun 02 12:36:46 PM PDT 24
Peak memory 199728 kb
Host smart-d68d09cd-b992-4078-93b6-bf0b32bd8eaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153163989 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.3153163989
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.3767723109
Short name T381
Test name
Test status
Simulation time 93517233753 ps
CPU time 412.13 seconds
Started Jun 02 12:36:57 PM PDT 24
Finished Jun 02 12:43:50 PM PDT 24
Peak memory 199924 kb
Host smart-b80f24fc-5f7d-41a6-8e72-d34668fe037c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767723109 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.3767723109
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2573142321
Short name T477
Test name
Test status
Simulation time 7779176794 ps
CPU time 109.82 seconds
Started Jun 02 12:36:27 PM PDT 24
Finished Jun 02 12:38:18 PM PDT 24
Peak memory 199864 kb
Host smart-00fcab96-2549-49ad-a6ea-77d5b7a02af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573142321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2573142321
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3000028119
Short name T361
Test name
Test status
Simulation time 42357181 ps
CPU time 0.59 seconds
Started Jun 02 12:36:32 PM PDT 24
Finished Jun 02 12:36:33 PM PDT 24
Peak memory 195496 kb
Host smart-308912ab-270d-4f35-8077-3ae047f40ef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000028119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3000028119
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2474405474
Short name T41
Test name
Test status
Simulation time 2224080913 ps
CPU time 44.44 seconds
Started Jun 02 12:36:26 PM PDT 24
Finished Jun 02 12:37:11 PM PDT 24
Peak memory 227144 kb
Host smart-8de7da68-900a-48c3-aed2-b800b89b6b79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2474405474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2474405474
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.1229692249
Short name T19
Test name
Test status
Simulation time 226019980 ps
CPU time 2.83 seconds
Started Jun 02 12:36:30 PM PDT 24
Finished Jun 02 12:36:33 PM PDT 24
Peak memory 199888 kb
Host smart-ace18e21-1815-43f8-8297-09007ac823eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229692249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.1229692249
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1052200349
Short name T505
Test name
Test status
Simulation time 10018562378 ps
CPU time 320.47 seconds
Started Jun 02 12:36:30 PM PDT 24
Finished Jun 02 12:41:51 PM PDT 24
Peak memory 639516 kb
Host smart-efbc1c30-e7dc-4de1-a1d7-862ceba22a0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1052200349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1052200349
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3252013428
Short name T216
Test name
Test status
Simulation time 1628562633 ps
CPU time 23.44 seconds
Started Jun 02 12:36:34 PM PDT 24
Finished Jun 02 12:36:58 PM PDT 24
Peak memory 199804 kb
Host smart-c0b384d0-831b-4e20-b48d-e04e25b82c1f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252013428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3252013428
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3806266109
Short name T37
Test name
Test status
Simulation time 3214460058 ps
CPU time 47.57 seconds
Started Jun 02 12:36:47 PM PDT 24
Finished Jun 02 12:37:35 PM PDT 24
Peak memory 199988 kb
Host smart-a77b84af-52f7-4ea5-be58-be55d7cd51d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806266109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3806266109
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3987150414
Short name T498
Test name
Test status
Simulation time 1496223833 ps
CPU time 7.06 seconds
Started Jun 02 12:36:28 PM PDT 24
Finished Jun 02 12:36:36 PM PDT 24
Peak memory 199908 kb
Host smart-d0919f0b-5711-4a3a-812d-c7de7f238466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987150414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3987150414
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1686328202
Short name T72
Test name
Test status
Simulation time 124587021209 ps
CPU time 1213.4 seconds
Started Jun 02 12:36:31 PM PDT 24
Finished Jun 02 12:56:45 PM PDT 24
Peak memory 459408 kb
Host smart-873444af-add1-4ea9-afcb-d106c6e7c09a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686328202 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1686328202
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.1146067650
Short name T523
Test name
Test status
Simulation time 30188335 ps
CPU time 1.04 seconds
Started Jun 02 12:36:32 PM PDT 24
Finished Jun 02 12:36:34 PM PDT 24
Peak memory 199680 kb
Host smart-6a3e27ec-bc83-4faa-b2f7-3cfb8e8e2985
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146067650 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.1146067650
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.3239492530
Short name T555
Test name
Test status
Simulation time 28257601224 ps
CPU time 386.25 seconds
Started Jun 02 12:36:21 PM PDT 24
Finished Jun 02 12:42:49 PM PDT 24
Peak memory 199216 kb
Host smart-5aa5a9dd-16a8-4e3d-82a5-cee2b7225c23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239492530 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.3239492530
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.2996715827
Short name T507
Test name
Test status
Simulation time 27374692116 ps
CPU time 70.9 seconds
Started Jun 02 12:36:33 PM PDT 24
Finished Jun 02 12:37:45 PM PDT 24
Peak memory 199996 kb
Host smart-6f0f1616-a890-4c5d-a76e-73dcc7e6358b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996715827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2996715827
Directory /workspace/9.hmac_wipe_secret/latest
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