Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	13720777	1			T1	8590		T2	16033		T3	153273
all_values[1]	13720777	1			T1	8590		T2	16033		T3	153273
all_values[2]	13720777	1			T1	8590		T2	16033		T3	153273

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102237

1

T1

18

T2

2740

T3

934

auto[1]

41060094

1

T1

25752

T2

45359

T3

458885

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34229951

1

T1

22352

T2

38944

T3

390533

auto[1]

6932380

1

T1

3418

T2

9155

T3

69286

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	34980	1			T1	16		T2	2740		T3	458
all_values[0]	auto[0]	auto[1]	359	1			T1	2		T3	3		T4	4
all_values[0]	auto[1]	auto[0]	13650228	1			T1	8549		T2	13275		T3	152378
all_values[0]	auto[1]	auto[1]	35210	1			T1	23		T2	18		T3	434
all_values[1]	auto[0]	auto[0]	37848	1			T3	459		T4	466		T13	70
all_values[1]	auto[0]	auto[1]	165	1			T3	3		T12	1		T20	3
all_values[1]	auto[1]	auto[0]	13682438	1			T1	8590		T2	16033		T3	152811
all_values[1]	auto[1]	auto[1]	326	1			T12	3		T20	4		T82	3
all_values[2]	auto[0]	auto[0]	15700	1			T3	9		T8	35		T12	302
all_values[2]	auto[0]	auto[1]	13185	1			T3	2		T20	4		T10	2
all_values[2]	auto[1]	auto[0]	6808757	1			T1	5197		T2	6896		T3	84418
all_values[2]	auto[1]	auto[1]	6883135	1			T1	3393		T2	9137		T3	68844