Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6340086

1

T1

4537

T2

12014

T3

67312

auto[1]

2479151

1

T1

3963

T2

3575

T3

46587

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2420524

1

T1

2821

T2

10799

T3

41919

auto[1]

6398713

1

T1

5679

T2

4790

T3

71980

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5391892

1

T1

4704

T3

55682

T4

3655

auto[1]

3427345

1

T1

3796

T2

15589

T3

58217

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6978264	1			T1	5996		T2	11830		T3	106107
fifo_depth[1]	299199	1			T1	264		T2	402		T3	3205
fifo_depth[2]	247283	1			T1	270		T2	427		T3	2048
fifo_depth[3]	199172	1			T1	239		T2	415		T3	1109
fifo_depth[4]	165408	1			T1	249		T2	390		T3	753
fifo_depth[5]	140441	1			T1	257		T2	401		T3	240
fifo_depth[6]	128450	1			T1	240		T2	372		T3	193
fifo_depth[7]	111304	1			T1	233		T2	349		T3	65

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1840973

1

T1

2504

T2

3759

T3

7792

auto[1]

6978264

1

T1

5996

T2

11830

T3

106107

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8808023

1

T1

8500

T2

15589

T3

113899

auto[1]

11214

1

T13

109

T12

1

T14

2

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

93374

1

T1

234

T3

389

T4

123

auto[0]

auto[0]

auto[0]

auto[1]

105421

1

T3

300

T8

49

T23

678

auto[0]

auto[0]

auto[1]

auto[0]

891320

1

T1

831

T3

2280

T4

45

auto[0]

auto[0]

auto[1]

auto[1]

88752

1

T1

464

T3

773

T9

12

auto[0]

auto[1]

auto[0]

auto[0]

155430

1

T1

184

T2

1468

T3

942

auto[0]

auto[1]

auto[0]

auto[1]

166218

1

T2

784

T3

867

T4

41

auto[0]

auto[1]

auto[1]

auto[0]

170798

1

T1

250

T2

721

T3

872

auto[0]

auto[1]

auto[1]

auto[1]

169660

1

T1

541

T2

786

T3

1369

auto[1]

auto[0]

auto[0]

auto[0]

262032

1

T1

554

T3

4862

T4

1815

auto[1]

auto[0]

auto[0]

auto[1]

283322

1

T1

517

T3

2906

T4

562

auto[1]

auto[0]

auto[1]

auto[0]

3379591

1

T1

1297

T3

39285

T4

799

auto[1]

auto[0]

auto[1]

auto[1]

288080

1

T1

807

T3

4887

T4

311

auto[1]

auto[1]

auto[0]

auto[0]

680066

1

T1

598

T2

6976

T3

10795

auto[1]

auto[1]

auto[0]

auto[1]

674661

1

T1

734

T2

1571

T3

20858

auto[1]

auto[1]

auto[1]

auto[0]

707475

1

T1

589

T2

2849

T3

7887

auto[1]

auto[1]

auto[1]

auto[1]

703037

1

T1

900

T2

434

T3

14627

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

353028

1

T1

788

T3

5251

T4

1938

auto[0]

auto[0]

auto[0]

auto[1]

386833

1

T1

517

T3

3206

T4

562

auto[0]

auto[0]

auto[1]

auto[0]

4269994

1

T1

2128

T3

41565

T4

844

auto[0]

auto[0]

auto[1]

auto[1]

374375

1

T1

1271

T3

5660

T4

311

auto[0]

auto[1]

auto[0]

auto[0]

834776

1

T1

782

T2

8444

T3

11737

auto[0]

auto[1]

auto[0]

auto[1]

839792

1

T1

734

T2

2355

T3

21725

auto[0]

auto[1]

auto[1]

auto[0]

877340

1

T1

839

T2

3570

T3

8759

auto[0]

auto[1]

auto[1]

auto[1]

871885

1

T1

1441

T2

1220

T3

15996

auto[1]

auto[0]

auto[0]

auto[0]

2378

1

T13

78

T99

11

T15

1

auto[1]

auto[0]

auto[0]

auto[1]

1910

1

T13

2

T14

1

T125

4

auto[1]

auto[0]

auto[1]

auto[0]

917

1

T98

5

T46

355

T108

37

auto[1]

auto[0]

auto[1]

auto[1]

2457

1

T98

35

T41

1

T46

274

auto[1]

auto[1]

auto[0]

auto[0]

720

1

T12

1

T99

97

T41

2

auto[1]

auto[1]

auto[0]

auto[1]

1087

1

T13

29

T14

1

T98

56

auto[1]

auto[1]

auto[1]

auto[0]

933

1

T98

22

T46

4

T108

1

auto[1]

auto[1]

auto[1]

auto[1]

812

1

T98

7

T43

1

T125

22

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	262032	1			T1	554		T3	4862		T4	1815
fifo_depth[0]	auto[0]	auto[0]	auto[1]	283322	1			T1	517		T3	2906		T4	562
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3379591	1			T1	1297		T3	39285		T4	799
fifo_depth[0]	auto[0]	auto[1]	auto[1]	288080	1			T1	807		T3	4887		T4	311
fifo_depth[0]	auto[1]	auto[0]	auto[0]	680066	1			T1	598		T2	6976		T3	10795
fifo_depth[0]	auto[1]	auto[0]	auto[1]	674661	1			T1	734		T2	1571		T3	20858
fifo_depth[0]	auto[1]	auto[1]	auto[0]	707475	1			T1	589		T2	2849		T3	7887
fifo_depth[0]	auto[1]	auto[1]	auto[1]	703037	1			T1	900		T2	434		T3	14627
fifo_depth[1]	auto[0]	auto[0]	auto[0]	7845	1			T1	21		T3	146		T4	66
fifo_depth[1]	auto[0]	auto[0]	auto[1]	9494	1			T3	94		T8	32		T23	78
fifo_depth[1]	auto[0]	auto[1]	auto[0]	199289	1			T1	92		T3	1313		T4	26
fifo_depth[1]	auto[0]	auto[1]	auto[1]	9697	1			T1	59		T3	257		T9	9
fifo_depth[1]	auto[1]	auto[0]	auto[0]	16356	1			T1	19		T2	166		T3	342
fifo_depth[1]	auto[1]	auto[0]	auto[1]	18496	1			T2	83		T3	283		T4	18
fifo_depth[1]	auto[1]	auto[1]	auto[0]	19067	1			T1	20		T2	63		T3	266
fifo_depth[1]	auto[1]	auto[1]	auto[1]	18955	1			T1	53		T2	90		T3	504
fifo_depth[2]	auto[0]	auto[0]	auto[0]	6741	1			T1	19		T3	94		T4	41
fifo_depth[2]	auto[0]	auto[0]	auto[1]	8801	1			T3	55		T8	12		T23	78
fifo_depth[2]	auto[0]	auto[1]	auto[0]	156320	1			T1	100		T3	543		T4	10
fifo_depth[2]	auto[0]	auto[1]	auto[1]	8462	1			T1	47		T3	206		T9	3
fifo_depth[2]	auto[1]	auto[0]	auto[0]	15116	1			T1	20		T2	173		T3	287
fifo_depth[2]	auto[1]	auto[0]	auto[1]	17227	1			T2	100		T3	227		T4	15
fifo_depth[2]	auto[1]	auto[1]	auto[0]	17387	1			T1	24		T2	65		T3	245
fifo_depth[2]	auto[1]	auto[1]	auto[1]	17229	1			T1	60		T2	89		T3	391
fifo_depth[3]	auto[0]	auto[0]	auto[0]	5297	1			T1	22		T3	66		T4	11
fifo_depth[3]	auto[0]	auto[0]	auto[1]	6920	1			T3	24		T8	3		T23	59
fifo_depth[3]	auto[0]	auto[1]	auto[0]	122577	1			T1	88		T3	262		T4	8
fifo_depth[3]	auto[0]	auto[1]	auto[1]	6651	1			T1	41		T3	113		T8	4
fifo_depth[3]	auto[1]	auto[0]	auto[0]	13063	1			T1	14		T2	169		T3	127
fifo_depth[3]	auto[1]	auto[0]	auto[1]	14701	1			T2	104		T3	145		T4	7
fifo_depth[3]	auto[1]	auto[1]	auto[0]	14985	1			T1	23		T2	57		T3	123
fifo_depth[3]	auto[1]	auto[1]	auto[1]	14978	1			T1	51		T2	85		T3	249
fifo_depth[4]	auto[0]	auto[0]	auto[0]	5298	1			T1	21		T3	38		T4	5
fifo_depth[4]	auto[0]	auto[0]	auto[1]	6910	1			T3	41		T8	1		T23	60
fifo_depth[4]	auto[0]	auto[1]	auto[0]	92075	1			T1	94		T3	99		T4	1
fifo_depth[4]	auto[0]	auto[1]	auto[1]	6175	1			T1	42		T3	71		T23	41
fifo_depth[4]	auto[1]	auto[0]	auto[0]	12358	1			T1	18		T2	154		T3	102
fifo_depth[4]	auto[1]	auto[0]	auto[1]	13817	1			T2	90		T3	123		T4	1
fifo_depth[4]	auto[1]	auto[1]	auto[0]	14399	1			T1	22		T2	59		T3	143
fifo_depth[4]	auto[1]	auto[1]	auto[1]	14376	1			T1	52		T2	87		T3	136
fifo_depth[5]	auto[0]	auto[0]	auto[0]	4176	1			T1	27		T3	18		T23	110
fifo_depth[5]	auto[0]	auto[0]	auto[1]	5780	1			T3	20		T8	1		T23	72
fifo_depth[5]	auto[0]	auto[1]	auto[0]	75628	1			T1	94		T3	22		T23	104
fifo_depth[5]	auto[0]	auto[1]	auto[1]	5083	1			T1	53		T3	33		T8	1
fifo_depth[5]	auto[1]	auto[0]	auto[0]	11182	1			T1	15		T2	159		T3	33
fifo_depth[5]	auto[1]	auto[0]	auto[1]	12625	1			T2	85		T3	45		T8	1
fifo_depth[5]	auto[1]	auto[1]	auto[0]	12841	1			T1	17		T2	63		T3	26
fifo_depth[5]	auto[1]	auto[1]	auto[1]	13126	1			T1	51		T2	94		T3	43
fifo_depth[6]	auto[0]	auto[0]	auto[0]	4172	1			T1	24		T3	14		T23	100
fifo_depth[6]	auto[0]	auto[0]	auto[1]	5972	1			T3	22		T23	73		T13	28
fifo_depth[6]	auto[0]	auto[1]	auto[0]	64834	1			T1	84		T3	13		T23	118
fifo_depth[6]	auto[0]	auto[1]	auto[1]	4771	1			T1	40		T3	34		T23	38
fifo_depth[6]	auto[1]	auto[0]	auto[0]	10877	1			T1	17		T2	173		T3	16
fifo_depth[6]	auto[1]	auto[0]	auto[1]	12266	1			T2	67		T3	21		T23	26
fifo_depth[6]	auto[1]	auto[1]	auto[0]	12673	1			T1	23		T2	60		T3	44
fifo_depth[6]	auto[1]	auto[1]	auto[1]	12885	1			T1	52		T2	72		T3	29
fifo_depth[7]	auto[0]	auto[0]	auto[0]	3714	1			T1	26		T3	6		T23	94
fifo_depth[7]	auto[0]	auto[0]	auto[1]	5299	1			T3	13		T23	67		T13	5
fifo_depth[7]	auto[0]	auto[1]	auto[0]	51735	1			T1	72		T3	4		T23	92
fifo_depth[7]	auto[0]	auto[1]	auto[1]	4353	1			T1	47		T3	21		T23	46
fifo_depth[7]	auto[1]	auto[0]	auto[0]	10357	1			T1	15		T2	129		T3	1
fifo_depth[7]	auto[1]	auto[0]	auto[1]	11668	1			T2	74		T3	5		T23	28
fifo_depth[7]	auto[1]	auto[1]	auto[0]	11889	1			T1	25		T2	59		T3	4
fifo_depth[7]	auto[1]	auto[1]	auto[1]	12289	1			T1	48		T2	87		T3	11