Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	13720777	1			T1	8590		T2	16033		T3	153273
all_pins[1]	13720777	1			T1	8590		T2	16033		T3	153273
all_pins[2]	13720777	1			T1	8590		T2	16033		T3	153273

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	34243056	1			T1	22353		T2	38941		T3	390540
values[0x1]	6919275	1			T1	3417		T2	9158		T3	69279
transitions[0x0=>0x1]	6919105	1			T1	3417		T2	9158		T3	69277
transitions[0x1=>0x0]	6919120	1			T1	3417		T2	9158		T3	69277

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	13684981	1			T1	8566		T2	16012		T3	152838
all_pins[0]	values[0x1]	35796	1			T1	24		T2	21		T3	435
all_pins[0]	transitions[0x0=>0x1]	35704	1			T1	24		T2	21		T3	433
all_pins[0]	transitions[0x1=>0x0]	6883058	1			T1	3393		T2	9137		T3	68842
all_pins[1]	values[0x0]	13720433	1			T1	8590		T2	16033		T3	153273
all_pins[1]	values[0x1]	344	1			T12	3		T20	4		T82	3
all_pins[1]	transitions[0x0=>0x1]	299	1			T12	1		T20	1		T82	3
all_pins[1]	transitions[0x1=>0x0]	35751	1			T1	24		T2	21		T3	435
all_pins[2]	values[0x0]	6837642	1			T1	5197		T2	6896		T3	84429
all_pins[2]	values[0x1]	6883135	1			T1	3393		T2	9137		T3	68844
all_pins[2]	transitions[0x0=>0x1]	6883102	1			T1	3393		T2	9137		T3	68844
all_pins[2]	transitions[0x1=>0x0]	311	1			T12	2		T20	3		T82	3