Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 778 1 T3 4 T12 11 T20 21
all_values[1] 778 1 T3 4 T12 11 T20 21
all_values[2] 778 1 T3 4 T12 11 T20 21


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1233 1 T3 11 T12 12 T20 28
auto[1] 1101 1 T3 1 T12 21 T20 35


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 808 1 T3 2 T12 16 T20 22
auto[1] 1526 1 T3 10 T12 17 T20 41


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1292 1 T3 5 T12 23 T20 37
auto[1] 1042 1 T3 7 T12 10 T20 26


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 162 1 T3 1 T12 2 T20 2
all_values[0] auto[0] auto[0] auto[1] 65 1 T3 1 T20 1 T82 2
all_values[0] auto[0] auto[1] auto[0] 120 1 T12 2 T20 1 T82 2
all_values[0] auto[0] auto[1] auto[1] 84 1 T12 3 T20 7 T82 2
all_values[0] auto[1] auto[0] auto[1] 190 1 T3 1 T12 2 T20 4
all_values[0] auto[1] auto[1] auto[1] 157 1 T3 1 T12 2 T20 6
all_values[1] auto[0] auto[0] auto[0] 131 1 T12 2 T20 6 T82 2
all_values[1] auto[0] auto[0] auto[1] 96 1 T3 1 T12 2 T20 3
all_values[1] auto[0] auto[1] auto[0] 115 1 T12 2 T20 4 T82 3
all_values[1] auto[0] auto[1] auto[1] 97 1 T12 1 T20 1 T82 2
all_values[1] auto[1] auto[0] auto[1] 177 1 T3 3 T20 2 T82 7
all_values[1] auto[1] auto[1] auto[1] 162 1 T12 4 T20 5 T82 3
all_values[2] auto[0] auto[0] auto[0] 151 1 T3 1 T12 4 T20 4
all_values[2] auto[0] auto[0] auto[1] 74 1 T3 1 T20 1 T82 4
all_values[2] auto[0] auto[1] auto[0] 129 1 T12 4 T20 5 T82 1
all_values[2] auto[0] auto[1] auto[1] 68 1 T12 1 T20 2 T82 2
all_values[2] auto[1] auto[0] auto[1] 187 1 T3 2 T20 5 T82 5
all_values[2] auto[1] auto[1] auto[1] 169 1 T12 2 T20 4 T82 4


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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