Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
60.78	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	4	16	80.00
Crosses	82	36	46	56.10

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	2	3	60.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	1	6	85.71	100	1	1	0
sha_en	2	1	1	50.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	8	0	8	100.00	100	1	1	0
hmac_dis_x_sha_en	4	2	2	50.00	100	1	1	0
key_x_digest_mismatch	35	17	18	51.43	100	1	1	0
key_length_x_digest_size	35	17	18	51.43	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	2	3	60.00

User Defined Bins for digest_size

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
sha2_invalid	0	1	1
sha2_none	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_512	4034	1			T1	6		T2	3		T3	73
sha2_384	4168	1			T1	9		T2	2		T3	69
sha2_256	24542	1			T1	6		T2	8		T3	263

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26750

1

T1

12

T2

6

T3

293

auto[1]

5994

1

T1

9

T2

7

T3

112

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5845

1

T1

5

T2

7

T3

100

auto[1]

26899

1

T1

16

T2

6

T3

305

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

6573

1

T1

8

T2

13

T3

126

disabled

26171

1

T1

13

T3

279

T4

13

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for key_length

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
key_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	1009	1			T1	3		T3	12		T4	3
key_1024	1775	1			T1	5		T2	1		T3	30
key_512	2303	1			T1	3		T2	7		T3	34
key_384	2327	1			T1	4		T2	1		T3	46
key_256	23109	1			T3	238		T4	5		T9	2
key_128	2221	1			T1	6		T2	4		T3	45

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for sha_en

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
disabled	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

32744

1

T1

21

T2

13

T3

405

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
enabled	auto[0]	auto[0]	1505	1			T1	1		T2	4		T3	29
enabled	auto[0]	auto[1]	1548	1			T1	1		T2	3		T3	33
enabled	auto[1]	auto[0]	1959	1			T1	2		T2	2		T3	34
enabled	auto[1]	auto[1]	1561	1			T1	4		T2	4		T3	30
disabled	auto[0]	auto[0]	1349	1			T1	3		T3	19		T4	5
disabled	auto[0]	auto[1]	1443	1			T3	19		T4	3		T8	3
disabled	auto[1]	auto[0]	21937	1			T1	6		T3	211		T4	5
disabled	auto[1]	auto[1]	1442	1			T1	4		T3	30		T9	2

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	2	2	50.00	2
Automatically Generated Cross Bins	3	2	1	33.33	2
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Element holes

hmac_en	sha_en	COUNT	AT LEAST	NUMBER	STATUS
*	[disabled]	--	--	2

Covered bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

6573

1

T1

8

T2

13

T3

126

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

26171

1

T1

13

T3

279

T4

13

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	17	18	51.43	17
Automatically Generated Cross Bins	34	17	17	50.00	17
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid , sha2_none]	--	--	12

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_512	310	1			T1	2		T3	1		T9	1
key_none	sha2_384	337	1			T1	1		T3	4		T4	1
key_none	sha2_256	362	1			T3	7		T4	2		T8	2
key_1024	sha2_512	699	1			T1	1		T2	1		T3	12
key_1024	sha2_384	766	1			T1	3		T3	14		T8	4
key_512	sha2_512	751	1			T1	1		T2	2		T3	13
key_512	sha2_384	784	1			T2	1		T3	10		T4	1
key_512	sha2_256	768	1			T1	2		T2	4		T3	11
key_384	sha2_512	752	1			T1	1		T3	17		T4	2
key_384	sha2_384	781	1			T1	2		T3	17		T8	2
key_384	sha2_256	794	1			T1	1		T2	1		T3	12
key_256	sha2_512	782	1			T3	12		T4	2		T8	4
key_256	sha2_384	750	1			T3	12		T4	2		T9	2
key_256	sha2_256	21577	1			T3	214		T4	1		T8	3
key_128	sha2_512	740	1			T1	1		T3	18		T4	1
key_128	sha2_384	750	1			T1	3		T2	1		T3	12
key_128	sha2_256	731	1			T1	2		T2	3		T3	15

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

310

1

T1

1

T3

4

T4

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	17	18	51.43	17

Automatically Generated Cross Bins for key_length_x_digest_size

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid , sha2_none]	--	--	12

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_512	310	1			T1	2		T3	1		T9	1
key_none	sha2_384	337	1			T1	1		T3	4		T4	1
key_none	sha2_256	362	1			T3	7		T4	2		T8	2
key_1024	sha2_512	699	1			T1	1		T2	1		T3	12
key_1024	sha2_384	766	1			T1	3		T3	14		T8	4
key_1024	sha2_256	310	1			T1	1		T3	4		T4	1
key_512	sha2_512	751	1			T1	1		T2	2		T3	13
key_512	sha2_384	784	1			T2	1		T3	10		T4	1
key_512	sha2_256	768	1			T1	2		T2	4		T3	11
key_384	sha2_512	752	1			T1	1		T3	17		T4	2
key_384	sha2_384	781	1			T1	2		T3	17		T8	2
key_384	sha2_256	794	1			T1	1		T2	1		T3	12
key_256	sha2_512	782	1			T3	12		T4	2		T8	4
key_256	sha2_384	750	1			T3	12		T4	2		T9	2
key_256	sha2_256	21577	1			T3	214		T4	1		T8	3
key_128	sha2_512	740	1			T1	1		T3	18		T4	1
key_128	sha2_384	750	1			T1	3		T2	1		T3	12
key_128	sha2_256	731	1			T1	2		T2	3		T3	15