Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.87 94.82 92.29 100.00 74.36 89.38 99.49 71.75


Total test records in report: 726
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T540 /workspace/coverage/default/25.hmac_long_msg.884852174 Jun 04 12:28:11 PM PDT 24 Jun 04 12:29:22 PM PDT 24 13095856058 ps
T541 /workspace/coverage/default/40.hmac_back_pressure.2866681579 Jun 04 12:29:01 PM PDT 24 Jun 04 12:29:24 PM PDT 24 309832027 ps
T542 /workspace/coverage/default/42.hmac_stress_all.1272562486 Jun 04 12:29:11 PM PDT 24 Jun 04 01:18:10 PM PDT 24 114132243068 ps
T543 /workspace/coverage/default/20.hmac_test_hmac_vectors.2581576688 Jun 04 12:27:59 PM PDT 24 Jun 04 12:28:03 PM PDT 24 82727753 ps
T544 /workspace/coverage/default/21.hmac_test_hmac_vectors.4239627179 Jun 04 12:28:01 PM PDT 24 Jun 04 12:28:05 PM PDT 24 265866043 ps
T545 /workspace/coverage/default/14.hmac_long_msg.775821373 Jun 04 12:27:48 PM PDT 24 Jun 04 12:29:47 PM PDT 24 7805676317 ps
T112 /workspace/coverage/default/28.hmac_wipe_secret.3352238569 Jun 04 12:28:28 PM PDT 24 Jun 04 12:29:07 PM PDT 24 24497872155 ps
T546 /workspace/coverage/default/18.hmac_long_msg.270275003 Jun 04 12:28:04 PM PDT 24 Jun 04 12:28:30 PM PDT 24 422095102 ps
T547 /workspace/coverage/default/37.hmac_smoke.2238256576 Jun 04 12:28:49 PM PDT 24 Jun 04 12:28:53 PM PDT 24 160852681 ps
T548 /workspace/coverage/default/46.hmac_test_hmac_vectors.254506833 Jun 04 12:29:27 PM PDT 24 Jun 04 12:29:31 PM PDT 24 49313077 ps
T549 /workspace/coverage/default/2.hmac_error.866311973 Jun 04 12:27:15 PM PDT 24 Jun 04 12:28:55 PM PDT 24 11627403838 ps
T550 /workspace/coverage/default/5.hmac_burst_wr.1492388798 Jun 04 12:27:25 PM PDT 24 Jun 04 12:27:59 PM PDT 24 614782358 ps
T551 /workspace/coverage/default/28.hmac_long_msg.1574062192 Jun 04 12:28:33 PM PDT 24 Jun 04 12:28:58 PM PDT 24 4669990530 ps
T552 /workspace/coverage/default/16.hmac_test_hmac_vectors.607293818 Jun 04 12:27:47 PM PDT 24 Jun 04 12:27:50 PM PDT 24 33753107 ps
T553 /workspace/coverage/default/19.hmac_error.1517561618 Jun 04 12:27:57 PM PDT 24 Jun 04 12:29:19 PM PDT 24 4635738638 ps
T554 /workspace/coverage/default/42.hmac_error.2916572853 Jun 04 12:29:09 PM PDT 24 Jun 04 12:29:53 PM PDT 24 3509961872 ps
T555 /workspace/coverage/default/49.hmac_back_pressure.1033435611 Jun 04 12:29:27 PM PDT 24 Jun 04 12:29:47 PM PDT 24 1026340616 ps
T556 /workspace/coverage/default/18.hmac_stress_all.3673555406 Jun 04 12:27:57 PM PDT 24 Jun 04 01:03:46 PM PDT 24 38789816735 ps
T557 /workspace/coverage/default/42.hmac_alert_test.79177004 Jun 04 12:29:13 PM PDT 24 Jun 04 12:29:14 PM PDT 24 16537264 ps
T558 /workspace/coverage/default/3.hmac_test_hmac_vectors.3483886440 Jun 04 12:27:16 PM PDT 24 Jun 04 12:27:20 PM PDT 24 34437770 ps
T110 /workspace/coverage/default/36.hmac_long_msg.470366722 Jun 04 12:28:48 PM PDT 24 Jun 04 12:30:30 PM PDT 24 26887323430 ps
T27 /workspace/coverage/default/4.hmac_sec_cm.1957079876 Jun 04 12:27:26 PM PDT 24 Jun 04 12:27:29 PM PDT 24 37280288 ps
T559 /workspace/coverage/default/43.hmac_wipe_secret.3844651909 Jun 04 12:29:19 PM PDT 24 Jun 04 12:29:33 PM PDT 24 1349167432 ps
T560 /workspace/coverage/default/20.hmac_smoke.857500653 Jun 04 12:27:59 PM PDT 24 Jun 04 12:28:07 PM PDT 24 191086482 ps
T561 /workspace/coverage/default/5.hmac_long_msg.3817562529 Jun 04 12:27:25 PM PDT 24 Jun 04 12:28:38 PM PDT 24 3793185998 ps
T562 /workspace/coverage/default/22.hmac_test_hmac_vectors.1069865971 Jun 04 12:28:09 PM PDT 24 Jun 04 12:28:12 PM PDT 24 119944378 ps
T563 /workspace/coverage/default/47.hmac_test_sha_vectors.1257712694 Jun 04 12:29:29 PM PDT 24 Jun 04 12:35:56 PM PDT 24 18372543847 ps
T564 /workspace/coverage/default/25.hmac_back_pressure.309667035 Jun 04 12:28:15 PM PDT 24 Jun 04 12:28:19 PM PDT 24 101703865 ps
T565 /workspace/coverage/default/48.hmac_test_hmac_vectors.3246286317 Jun 04 12:29:26 PM PDT 24 Jun 04 12:29:29 PM PDT 24 164268117 ps
T566 /workspace/coverage/default/12.hmac_test_sha_vectors.4060462632 Jun 04 12:27:33 PM PDT 24 Jun 04 12:35:10 PM PDT 24 100006542102 ps
T567 /workspace/coverage/default/35.hmac_alert_test.978105401 Jun 04 12:28:50 PM PDT 24 Jun 04 12:28:53 PM PDT 24 32950962 ps
T568 /workspace/coverage/default/4.hmac_alert_test.59558868 Jun 04 12:27:26 PM PDT 24 Jun 04 12:27:28 PM PDT 24 25915202 ps
T569 /workspace/coverage/default/17.hmac_test_hmac_vectors.2145816796 Jun 04 12:27:49 PM PDT 24 Jun 04 12:27:51 PM PDT 24 69092342 ps
T570 /workspace/coverage/default/3.hmac_datapath_stress.3876025684 Jun 04 12:27:16 PM PDT 24 Jun 04 12:35:18 PM PDT 24 6336123434 ps
T571 /workspace/coverage/default/35.hmac_stress_all.705024633 Jun 04 12:28:46 PM PDT 24 Jun 04 12:38:51 PM PDT 24 67772862963 ps
T572 /workspace/coverage/default/46.hmac_test_sha_vectors.170304284 Jun 04 12:29:30 PM PDT 24 Jun 04 12:36:53 PM PDT 24 7888691942 ps
T573 /workspace/coverage/default/3.hmac_wipe_secret.1673893063 Jun 04 12:27:18 PM PDT 24 Jun 04 12:28:10 PM PDT 24 5560857632 ps
T574 /workspace/coverage/default/7.hmac_datapath_stress.170336500 Jun 04 12:27:26 PM PDT 24 Jun 04 12:37:51 PM PDT 24 12860141416 ps
T575 /workspace/coverage/default/18.hmac_back_pressure.2977252244 Jun 04 12:27:59 PM PDT 24 Jun 04 12:28:06 PM PDT 24 304083262 ps
T576 /workspace/coverage/default/39.hmac_datapath_stress.3105279524 Jun 04 12:28:58 PM PDT 24 Jun 04 12:41:19 PM PDT 24 43344156575 ps
T577 /workspace/coverage/default/3.hmac_long_msg.1148617441 Jun 04 12:27:15 PM PDT 24 Jun 04 12:28:17 PM PDT 24 12735320660 ps
T578 /workspace/coverage/default/43.hmac_back_pressure.4048146753 Jun 04 12:29:10 PM PDT 24 Jun 04 12:29:26 PM PDT 24 421237256 ps
T579 /workspace/coverage/default/7.hmac_smoke.845324828 Jun 04 12:27:25 PM PDT 24 Jun 04 12:27:28 PM PDT 24 62679882 ps
T580 /workspace/coverage/default/7.hmac_alert_test.3221897472 Jun 04 12:27:26 PM PDT 24 Jun 04 12:27:28 PM PDT 24 34835567 ps
T581 /workspace/coverage/default/9.hmac_datapath_stress.482283656 Jun 04 12:27:33 PM PDT 24 Jun 04 12:31:38 PM PDT 24 1121401563 ps
T582 /workspace/coverage/default/21.hmac_error.904948464 Jun 04 12:27:58 PM PDT 24 Jun 04 12:30:13 PM PDT 24 2504856777 ps
T103 /workspace/coverage/default/34.hmac_stress_all.1058170345 Jun 04 12:28:51 PM PDT 24 Jun 04 12:49:01 PM PDT 24 80912672969 ps
T28 /workspace/coverage/default/0.hmac_sec_cm.2897299280 Jun 04 12:27:16 PM PDT 24 Jun 04 12:27:19 PM PDT 24 63037166 ps
T583 /workspace/coverage/default/42.hmac_wipe_secret.1196073713 Jun 04 12:29:12 PM PDT 24 Jun 04 12:29:17 PM PDT 24 120651450 ps
T584 /workspace/coverage/default/49.hmac_test_sha_vectors.1938847394 Jun 04 12:29:37 PM PDT 24 Jun 04 12:36:57 PM PDT 24 46663138826 ps
T585 /workspace/coverage/default/42.hmac_datapath_stress.1811958194 Jun 04 12:29:11 PM PDT 24 Jun 04 12:31:40 PM PDT 24 727021118 ps
T586 /workspace/coverage/default/1.hmac_test_sha_vectors.491736784 Jun 04 12:27:15 PM PDT 24 Jun 04 12:35:01 PM PDT 24 169445941305 ps
T587 /workspace/coverage/default/23.hmac_burst_wr.4045005296 Jun 04 12:28:06 PM PDT 24 Jun 04 12:28:38 PM PDT 24 6055274731 ps
T588 /workspace/coverage/default/45.hmac_datapath_stress.1960267970 Jun 04 12:29:29 PM PDT 24 Jun 04 12:40:05 PM PDT 24 3145929439 ps
T589 /workspace/coverage/default/39.hmac_alert_test.942736582 Jun 04 12:28:56 PM PDT 24 Jun 04 12:28:58 PM PDT 24 14535053 ps
T590 /workspace/coverage/default/40.hmac_error.2091994051 Jun 04 12:28:59 PM PDT 24 Jun 04 12:32:41 PM PDT 24 51771887729 ps
T591 /workspace/coverage/default/9.hmac_alert_test.3294317522 Jun 04 12:27:32 PM PDT 24 Jun 04 12:27:33 PM PDT 24 29632425 ps
T592 /workspace/coverage/default/26.hmac_test_sha_vectors.3397539661 Jun 04 12:28:17 PM PDT 24 Jun 04 12:36:37 PM PDT 24 29264861440 ps
T593 /workspace/coverage/default/1.hmac_error.86690754 Jun 04 12:27:19 PM PDT 24 Jun 04 12:29:19 PM PDT 24 17446162916 ps
T594 /workspace/coverage/default/20.hmac_burst_wr.3638081067 Jun 04 12:28:01 PM PDT 24 Jun 04 12:28:07 PM PDT 24 78356626 ps
T595 /workspace/coverage/default/33.hmac_test_sha_vectors.681688160 Jun 04 12:28:42 PM PDT 24 Jun 04 12:37:15 PM PDT 24 125447745610 ps
T79 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2949723989 Jun 04 12:51:43 PM PDT 24 Jun 04 12:51:45 PM PDT 24 56499416 ps
T55 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1359683147 Jun 04 12:51:33 PM PDT 24 Jun 04 12:51:37 PM PDT 24 141973892 ps
T56 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3897238168 Jun 04 12:51:40 PM PDT 24 Jun 04 12:51:43 PM PDT 24 34302469 ps
T57 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1415483027 Jun 04 12:51:33 PM PDT 24 Jun 04 12:51:44 PM PDT 24 456644781 ps
T596 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2230301061 Jun 04 12:51:37 PM PDT 24 Jun 04 12:51:39 PM PDT 24 110074710 ps
T60 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3257541479 Jun 04 12:51:32 PM PDT 24 Jun 04 12:51:36 PM PDT 24 43030746 ps
T597 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3580925871 Jun 04 12:51:46 PM PDT 24 Jun 04 12:51:48 PM PDT 24 25874209 ps
T598 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1729954724 Jun 04 12:51:50 PM PDT 24 Jun 04 12:51:52 PM PDT 24 14718611 ps
T61 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1077797269 Jun 04 12:51:35 PM PDT 24 Jun 04 12:51:38 PM PDT 24 56381287 ps
T599 /workspace/coverage/cover_reg_top/3.hmac_intr_test.4281956923 Jun 04 12:51:33 PM PDT 24 Jun 04 12:51:35 PM PDT 24 98580376 ps
T86 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1442298901 Jun 04 12:51:32 PM PDT 24 Jun 04 12:51:36 PM PDT 24 229324807 ps
T600 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3760163730 Jun 04 12:51:46 PM PDT 24 Jun 04 12:51:48 PM PDT 24 46194393 ps
T62 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2963375654 Jun 04 12:51:55 PM PDT 24 Jun 04 12:51:58 PM PDT 24 256354685 ps
T601 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.390996025 Jun 04 12:51:46 PM PDT 24 Jun 04 12:51:51 PM PDT 24 56071221 ps
T52 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3927719037 Jun 04 12:51:33 PM PDT 24 Jun 04 12:51:39 PM PDT 24 215436927 ps
T602 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.818098183 Jun 04 12:51:40 PM PDT 24 Jun 04 12:51:43 PM PDT 24 29021169 ps
T603 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3541518496 Jun 04 12:51:44 PM PDT 24 Jun 04 12:51:47 PM PDT 24 119924997 ps
T604 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2057463907 Jun 04 12:51:48 PM PDT 24 Jun 04 12:51:50 PM PDT 24 11110916 ps
T87 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3920756009 Jun 04 12:51:46 PM PDT 24 Jun 04 12:51:48 PM PDT 24 42312450 ps
T605 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.179692149 Jun 04 12:51:46 PM PDT 24 Jun 04 12:51:49 PM PDT 24 35742122 ps
T606 /workspace/coverage/cover_reg_top/26.hmac_intr_test.380050596 Jun 04 12:51:50 PM PDT 24 Jun 04 12:51:52 PM PDT 24 17350315 ps
T607 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.517960592 Jun 04 12:51:37 PM PDT 24 Jun 04 12:51:40 PM PDT 24 328353073 ps
T53 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3580951386 Jun 04 12:51:39 PM PDT 24 Jun 04 12:51:42 PM PDT 24 478519339 ps
T608 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1128106560 Jun 04 12:51:39 PM PDT 24 Jun 04 12:51:41 PM PDT 24 15351039 ps
T609 /workspace/coverage/cover_reg_top/9.hmac_intr_test.3543088502 Jun 04 12:51:39 PM PDT 24 Jun 04 12:51:41 PM PDT 24 52286537 ps
T610 /workspace/coverage/cover_reg_top/45.hmac_intr_test.353821473 Jun 04 12:51:46 PM PDT 24 Jun 04 12:51:48 PM PDT 24 22132976 ps
T88 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.981466124 Jun 04 12:51:41 PM PDT 24 Jun 04 12:51:43 PM PDT 24 154637775 ps
T611 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2561918209 Jun 04 12:51:43 PM PDT 24 Jun 04 12:51:45 PM PDT 24 41584709 ps
T612 /workspace/coverage/cover_reg_top/43.hmac_intr_test.11868179 Jun 04 12:51:50 PM PDT 24 Jun 04 12:51:52 PM PDT 24 28923883 ps
T89 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.4275098153 Jun 04 12:51:29 PM PDT 24 Jun 04 12:51:30 PM PDT 24 85586406 ps
T613 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1957946679 Jun 04 12:51:39 PM PDT 24 Jun 04 12:51:43 PM PDT 24 109383989 ps
T614 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3176734917 Jun 04 12:51:36 PM PDT 24 Jun 04 12:51:39 PM PDT 24 235026937 ps
T54 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.695886196 Jun 04 12:51:47 PM PDT 24 Jun 04 12:51:52 PM PDT 24 1199914712 ps
T615 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3594900952 Jun 04 12:51:53 PM PDT 24 Jun 04 12:51:58 PM PDT 24 58876184 ps
T616 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1789351402 Jun 04 12:51:55 PM PDT 24 Jun 04 12:51:57 PM PDT 24 38706054 ps
T617 /workspace/coverage/cover_reg_top/46.hmac_intr_test.455241609 Jun 04 12:51:46 PM PDT 24 Jun 04 12:51:48 PM PDT 24 45372089 ps
T618 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2329196207 Jun 04 12:51:53 PM PDT 24 Jun 04 12:51:55 PM PDT 24 15801159 ps
T90 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3575927569 Jun 04 12:51:33 PM PDT 24 Jun 04 12:51:52 PM PDT 24 9810487271 ps
T619 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.858576896 Jun 04 12:51:31 PM PDT 24 Jun 04 12:51:37 PM PDT 24 117422717 ps
T620 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1810439786 Jun 04 12:51:44 PM PDT 24 Jun 04 12:51:47 PM PDT 24 79044816 ps
T114 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2707171558 Jun 04 12:51:55 PM PDT 24 Jun 04 12:52:00 PM PDT 24 624878240 ps
T621 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.866946496 Jun 04 12:51:55 PM PDT 24 Jun 04 12:51:58 PM PDT 24 151334049 ps
T622 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.467120101 Jun 04 12:51:42 PM PDT 24 Jun 04 12:51:46 PM PDT 24 272985640 ps
T119 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3554527054 Jun 04 12:51:45 PM PDT 24 Jun 04 12:51:49 PM PDT 24 342109641 ps
T623 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2934626165 Jun 04 12:51:34 PM PDT 24 Jun 04 12:51:38 PM PDT 24 121997219 ps
T624 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1006457466 Jun 04 12:51:31 PM PDT 24 Jun 04 12:51:34 PM PDT 24 14978308 ps
T91 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.33308146 Jun 04 12:51:46 PM PDT 24 Jun 04 12:51:49 PM PDT 24 25811758 ps
T625 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2068995675 Jun 04 12:51:39 PM PDT 24 Jun 04 12:51:41 PM PDT 24 18402168 ps
T121 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2339237055 Jun 04 12:51:33 PM PDT 24 Jun 04 12:51:37 PM PDT 24 581364632 ps
T626 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3443748242 Jun 04 12:51:40 PM PDT 24 Jun 04 12:51:44 PM PDT 24 114277697 ps
T627 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.4019874034 Jun 04 12:51:52 PM PDT 24 Jun 04 12:51:57 PM PDT 24 70448073 ps
T628 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3556174287 Jun 04 12:51:44 PM PDT 24 Jun 04 12:51:46 PM PDT 24 19579366 ps
T92 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1559545071 Jun 04 12:51:32 PM PDT 24 Jun 04 12:51:35 PM PDT 24 135527065 ps
T629 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1724031130 Jun 04 12:51:33 PM PDT 24 Jun 04 12:51:37 PM PDT 24 365534372 ps
T115 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.982944008 Jun 04 12:51:32 PM PDT 24 Jun 04 12:51:39 PM PDT 24 297909103 ps
T630 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3995438223 Jun 04 12:51:31 PM PDT 24 Jun 04 12:51:34 PM PDT 24 66165476 ps
T631 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3929845368 Jun 04 12:51:39 PM PDT 24 Jun 04 12:51:42 PM PDT 24 183489983 ps
T93 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1597426887 Jun 04 12:51:32 PM PDT 24 Jun 04 12:51:35 PM PDT 24 15607889 ps
T632 /workspace/coverage/cover_reg_top/6.hmac_intr_test.303967770 Jun 04 12:51:33 PM PDT 24 Jun 04 12:51:36 PM PDT 24 13056147 ps
T633 /workspace/coverage/cover_reg_top/48.hmac_intr_test.2170583474 Jun 04 12:51:46 PM PDT 24 Jun 04 12:51:48 PM PDT 24 20672403 ps
T634 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1551619018 Jun 04 12:51:51 PM PDT 24 Jun 04 12:51:54 PM PDT 24 36008670 ps
T635 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.223760030 Jun 04 12:51:33 PM PDT 24 Jun 04 12:51:37 PM PDT 24 245425805 ps
T636 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3085656311 Jun 04 12:51:45 PM PDT 24 Jun 04 12:51:46 PM PDT 24 18319473 ps
T637 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2674224790 Jun 04 12:51:53 PM PDT 24 Jun 04 12:51:57 PM PDT 24 99156463 ps
T638 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1419215656 Jun 04 12:51:44 PM PDT 24 Jun 04 12:51:46 PM PDT 24 12956129 ps
T639 /workspace/coverage/cover_reg_top/40.hmac_intr_test.3367926413 Jun 04 12:51:44 PM PDT 24 Jun 04 12:51:46 PM PDT 24 16225541 ps
T640 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1647299598 Jun 04 12:51:39 PM PDT 24 Jun 04 12:51:43 PM PDT 24 182834639 ps
T641 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3722300618 Jun 04 12:51:36 PM PDT 24 Jun 04 12:51:38 PM PDT 24 74356574 ps
T642 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3317434886 Jun 04 12:51:55 PM PDT 24 Jun 04 12:51:58 PM PDT 24 203088798 ps
T643 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.458963047 Jun 04 12:51:31 PM PDT 24 Jun 04 12:51:37 PM PDT 24 232163652 ps
T644 /workspace/coverage/cover_reg_top/32.hmac_intr_test.68610511 Jun 04 12:51:40 PM PDT 24 Jun 04 12:51:42 PM PDT 24 12849758 ps
T94 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1622798543 Jun 04 12:51:47 PM PDT 24 Jun 04 12:51:49 PM PDT 24 27499584 ps
T645 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.486257525 Jun 04 12:51:39 PM PDT 24 Jun 04 12:51:41 PM PDT 24 352105004 ps
T646 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2325887358 Jun 04 12:51:50 PM PDT 24 Jun 04 12:51:52 PM PDT 24 12962894 ps
T95 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2427493549 Jun 04 12:51:38 PM PDT 24 Jun 04 12:51:45 PM PDT 24 110059010 ps
T647 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2030957620 Jun 04 12:51:32 PM PDT 24 Jun 04 12:51:37 PM PDT 24 49412457 ps
T648 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.664039359 Jun 04 12:51:33 PM PDT 24 Jun 04 12:51:38 PM PDT 24 98493732 ps
T116 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.171529512 Jun 04 12:51:33 PM PDT 24 Jun 04 12:51:39 PM PDT 24 130341099 ps
T649 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2789975809 Jun 04 12:51:40 PM PDT 24 Jun 04 12:51:42 PM PDT 24 18643857 ps
T650 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.4099126950 Jun 04 12:51:35 PM PDT 24 Jun 04 12:51:41 PM PDT 24 79494415 ps
T651 /workspace/coverage/cover_reg_top/10.hmac_intr_test.3202448452 Jun 04 12:51:55 PM PDT 24 Jun 04 12:51:57 PM PDT 24 15757424 ps
T652 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.508328863 Jun 04 12:51:49 PM PDT 24 Jun 04 12:51:52 PM PDT 24 643612219 ps
T122 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3342502809 Jun 04 12:51:40 PM PDT 24 Jun 04 12:51:46 PM PDT 24 498004985 ps
T96 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2600682383 Jun 04 12:51:33 PM PDT 24 Jun 04 12:51:37 PM PDT 24 69288205 ps
T653 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2365537732 Jun 04 12:51:33 PM PDT 24 Jun 04 12:51:36 PM PDT 24 155330789 ps
T654 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2008095133 Jun 04 12:51:32 PM PDT 24 Jun 04 12:51:36 PM PDT 24 394003898 ps
T655 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2738113981 Jun 04 12:51:32 PM PDT 24 Jun 04 12:51:36 PM PDT 24 36061803 ps
T656 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1525965304 Jun 04 12:51:32 PM PDT 24 Jun 04 12:51:35 PM PDT 24 25276535 ps
T657 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3352281440 Jun 04 12:51:53 PM PDT 24 Jun 04 12:51:55 PM PDT 24 30455895 ps
T658 /workspace/coverage/cover_reg_top/22.hmac_intr_test.2297171783 Jun 04 12:51:55 PM PDT 24 Jun 04 12:51:57 PM PDT 24 49558894 ps
T124 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.854584139 Jun 04 12:51:46 PM PDT 24 Jun 04 12:51:49 PM PDT 24 607765112 ps
T659 /workspace/coverage/cover_reg_top/35.hmac_intr_test.1238554969 Jun 04 12:51:45 PM PDT 24 Jun 04 12:51:47 PM PDT 24 12100444 ps
T123 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.4041249207 Jun 04 12:51:40 PM PDT 24 Jun 04 12:51:45 PM PDT 24 2577658184 ps
T660 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.55418291 Jun 04 12:51:36 PM PDT 24 Jun 04 12:51:39 PM PDT 24 121597625 ps
T661 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.594125660 Jun 04 12:51:53 PM PDT 24 Jun 04 12:51:55 PM PDT 24 17047325 ps
T120 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1094446693 Jun 04 12:51:33 PM PDT 24 Jun 04 12:51:41 PM PDT 24 1106570995 ps
T662 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2372769839 Jun 04 12:51:30 PM PDT 24 Jun 04 12:51:34 PM PDT 24 571850672 ps
T117 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3892964930 Jun 04 12:51:32 PM PDT 24 Jun 04 12:51:36 PM PDT 24 50900463 ps
T663 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1302932806 Jun 04 12:51:46 PM PDT 24 Jun 04 12:51:48 PM PDT 24 14352835 ps
T664 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2241470985 Jun 04 12:51:46 PM PDT 24 Jun 04 12:51:48 PM PDT 24 21554503 ps
T665 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2907860852 Jun 04 12:51:33 PM PDT 24 Jun 04 12:51:36 PM PDT 24 16298354 ps
T666 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.305453201 Jun 04 12:51:30 PM PDT 24 Jun 04 12:51:32 PM PDT 24 46547671 ps
T667 /workspace/coverage/cover_reg_top/47.hmac_intr_test.196963701 Jun 04 12:51:44 PM PDT 24 Jun 04 12:51:46 PM PDT 24 141846768 ps
T668 /workspace/coverage/cover_reg_top/29.hmac_intr_test.832000347 Jun 04 12:51:44 PM PDT 24 Jun 04 12:51:45 PM PDT 24 13778242 ps
T669 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1606315028 Jun 04 12:51:49 PM PDT 24 Jun 04 12:51:54 PM PDT 24 145524697 ps
T670 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.4217141510 Jun 04 12:51:37 PM PDT 24 Jun 04 12:51:44 PM PDT 24 230640762 ps
T671 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.829274609 Jun 04 12:51:45 PM PDT 24 Jun 04 12:51:48 PM PDT 24 43920880 ps
T58 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.4047059625 Jun 04 12:51:29 PM PDT 24 Jun 04 12:51:31 PM PDT 24 52360835 ps
T97 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1606151695 Jun 04 12:51:30 PM PDT 24 Jun 04 12:51:37 PM PDT 24 311550749 ps
T672 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2522034428 Jun 04 12:51:41 PM PDT 24 Jun 04 12:51:44 PM PDT 24 607625189 ps
T673 /workspace/coverage/cover_reg_top/34.hmac_intr_test.4288957094 Jun 04 12:51:58 PM PDT 24 Jun 04 12:52:00 PM PDT 24 11746427 ps
T674 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2953753659 Jun 04 12:51:36 PM PDT 24 Jun 04 12:51:39 PM PDT 24 18118183 ps
T675 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.509412484 Jun 04 12:51:39 PM PDT 24 Jun 04 12:51:44 PM PDT 24 292554720 ps
T676 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1841627545 Jun 04 12:51:32 PM PDT 24 Jun 04 12:51:36 PM PDT 24 248980597 ps
T118 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3297730965 Jun 04 12:51:40 PM PDT 24 Jun 04 12:51:44 PM PDT 24 177028421 ps
T677 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2714730630 Jun 04 12:51:40 PM PDT 24 Jun 04 12:51:43 PM PDT 24 206441236 ps
T678 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1093787658 Jun 04 12:51:29 PM PDT 24 Jun 04 12:51:31 PM PDT 24 23173042 ps
T679 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4040297989 Jun 04 12:51:32 PM PDT 24 Jun 04 12:51:38 PM PDT 24 288886151 ps
T680 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2104681531 Jun 04 12:51:47 PM PDT 24 Jun 04 12:51:50 PM PDT 24 75587167 ps
T681 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1198395895 Jun 04 12:51:43 PM PDT 24 Jun 04 12:51:44 PM PDT 24 13626111 ps
T682 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2247362856 Jun 04 12:51:46 PM PDT 24 Jun 04 12:51:49 PM PDT 24 23050085 ps
T683 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2180878191 Jun 04 12:51:39 PM PDT 24 Jun 04 12:51:41 PM PDT 24 37948679 ps
T684 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1134489211 Jun 04 12:51:46 PM PDT 24 Jun 04 12:51:48 PM PDT 24 42713227 ps
T685 /workspace/coverage/cover_reg_top/18.hmac_intr_test.3490996529 Jun 04 12:51:55 PM PDT 24 Jun 04 12:51:57 PM PDT 24 28193710 ps
T686 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1195884129 Jun 04 12:51:41 PM PDT 24 Jun 04 12:51:43 PM PDT 24 37174694 ps
T687 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2619536741 Jun 04 12:51:31 PM PDT 24 Jun 04 12:51:35 PM PDT 24 248414092 ps
T688 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3660206463 Jun 04 12:51:31 PM PDT 24 Jun 04 12:51:34 PM PDT 24 83196297 ps
T689 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.888551725 Jun 04 12:51:36 PM PDT 24 Jun 04 12:51:38 PM PDT 24 56394361 ps
T690 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2392831343 Jun 04 12:51:44 PM PDT 24 Jun 04 12:51:46 PM PDT 24 15625592 ps
T691 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3099734225 Jun 04 12:51:46 PM PDT 24 Jun 04 12:51:49 PM PDT 24 185557612 ps
T692 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1199987955 Jun 04 12:51:48 PM PDT 24 Jun 04 12:51:50 PM PDT 24 42609745 ps
T693 /workspace/coverage/cover_reg_top/12.hmac_intr_test.4241800285 Jun 04 12:51:47 PM PDT 24 Jun 04 12:51:49 PM PDT 24 12993642 ps
T694 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1753239007 Jun 04 12:51:32 PM PDT 24 Jun 04 12:51:36 PM PDT 24 50941156 ps
T695 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.4234966703 Jun 04 12:51:53 PM PDT 24 Jun 04 12:51:59 PM PDT 24 269536867 ps
T696 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.651725174 Jun 04 12:51:44 PM PDT 24 Jun 04 12:51:46 PM PDT 24 26597958 ps
T697 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.361492210 Jun 04 12:51:31 PM PDT 24 Jun 04 12:51:33 PM PDT 24 31343118 ps
T698 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3804434518 Jun 04 12:51:33 PM PDT 24 Jun 04 12:51:37 PM PDT 24 307377214 ps
T699 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3128447398 Jun 04 12:51:46 PM PDT 24 Jun 04 12:58:48 PM PDT 24 103720436311 ps
T700 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1607278769 Jun 04 12:51:33 PM PDT 24 Jun 04 12:51:37 PM PDT 24 210969890 ps
T701 /workspace/coverage/cover_reg_top/31.hmac_intr_test.4089800031 Jun 04 12:51:47 PM PDT 24 Jun 04 12:51:49 PM PDT 24 12289336 ps
T702 /workspace/coverage/cover_reg_top/23.hmac_intr_test.3867713803 Jun 04 12:51:55 PM PDT 24 Jun 04 12:51:57 PM PDT 24 17133086 ps
T703 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.712095633 Jun 04 12:51:46 PM PDT 24 Jun 04 12:51:51 PM PDT 24 261880740 ps
T704 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.4270940196 Jun 04 12:51:36 PM PDT 24 Jun 04 12:51:39 PM PDT 24 133029807 ps
T705 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3407979039 Jun 04 12:51:41 PM PDT 24 Jun 04 12:54:00 PM PDT 24 88906356942 ps
T706 /workspace/coverage/cover_reg_top/17.hmac_intr_test.4066141929 Jun 04 12:51:46 PM PDT 24 Jun 04 12:51:48 PM PDT 24 13565034 ps
T707 /workspace/coverage/cover_reg_top/11.hmac_intr_test.738967853 Jun 04 12:51:39 PM PDT 24 Jun 04 12:51:41 PM PDT 24 43454484 ps
T708 /workspace/coverage/cover_reg_top/8.hmac_intr_test.4277062451 Jun 04 12:51:36 PM PDT 24 Jun 04 12:51:39 PM PDT 24 18174451 ps
T709 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3654225310 Jun 04 12:51:43 PM PDT 24 Jun 04 12:51:44 PM PDT 24 181353044 ps
T710 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.4176589302 Jun 04 12:51:30 PM PDT 24 Jun 04 12:51:33 PM PDT 24 102998345 ps
T711 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1009724671 Jun 04 12:51:46 PM PDT 24 Jun 04 12:51:49 PM PDT 24 50400223 ps
T712 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3576653521 Jun 04 12:51:40 PM PDT 24 Jun 04 01:05:32 PM PDT 24 84058835448 ps
T713 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.56432881 Jun 04 12:51:31 PM PDT 24 Jun 04 12:51:34 PM PDT 24 100923521 ps
T714 /workspace/coverage/cover_reg_top/7.hmac_intr_test.3471274259 Jun 04 12:51:36 PM PDT 24 Jun 04 12:51:39 PM PDT 24 11277910 ps
T715 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4096859501 Jun 04 12:51:31 PM PDT 24 Jun 04 12:51:49 PM PDT 24 6561854923 ps
T716 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1247923415 Jun 04 12:51:46 PM PDT 24 Jun 04 12:51:48 PM PDT 24 21746890 ps
T717 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3612697084 Jun 04 12:51:36 PM PDT 24 Jun 04 12:51:49 PM PDT 24 2235494789 ps
T718 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.891399275 Jun 04 12:51:34 PM PDT 24 Jun 04 12:51:38 PM PDT 24 33908642 ps
T719 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1077150551 Jun 04 12:51:49 PM PDT 24 Jun 04 12:51:53 PM PDT 24 111347623 ps
T720 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.780977861 Jun 04 12:51:51 PM PDT 24 Jun 04 12:51:54 PM PDT 24 33953038 ps
T721 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1662330663 Jun 04 12:51:47 PM PDT 24 Jun 04 12:51:50 PM PDT 24 43664551 ps
T722 /workspace/coverage/cover_reg_top/28.hmac_intr_test.965827732 Jun 04 12:51:42 PM PDT 24 Jun 04 12:51:44 PM PDT 24 18214762 ps
T723 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2722188983 Jun 04 12:51:37 PM PDT 24 Jun 04 12:51:41 PM PDT 24 86727756 ps
T724 /workspace/coverage/cover_reg_top/2.hmac_intr_test.675369596 Jun 04 12:51:30 PM PDT 24 Jun 04 12:51:32 PM PDT 24 12454168 ps
T725 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1348320151 Jun 04 12:51:49 PM PDT 24 Jun 04 12:51:51 PM PDT 24 26330463 ps
T726 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3533373827 Jun 04 12:51:35 PM PDT 24 Jun 04 12:51:39 PM PDT 24 73262859 ps

Test location /workspace/coverage/default/11.hmac_long_msg.2884977383
Short name T21
Test name
Test status
Simulation time 1513896249 ps
CPU time 20.44 seconds
Started Jun 04 12:27:32 PM PDT 24
Finished Jun 04 12:27:54 PM PDT 24
Peak memory 199836 kb
Host smart-147d2d91-c81f-492a-b964-41f2380efad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884977383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2884977383
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/71.hmac_stress_all_with_rand_reset.3071620110
Short name T7
Test name
Test status
Simulation time 16180867166 ps
CPU time 1151.42 seconds
Started Jun 04 12:29:50 PM PDT 24
Finished Jun 04 12:49:03 PM PDT 24
Peak memory 660788 kb
Host smart-b4bf62a3-0941-43d4-a4ea-e888d3b982eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3071620110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.hmac_stress_all_with_rand_reset.3071620110
Directory /workspace/71.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.hmac_stress_all.874319301
Short name T3
Test name
Test status
Simulation time 243054605984 ps
CPU time 2003.11 seconds
Started Jun 04 12:28:19 PM PDT 24
Finished Jun 04 01:01:43 PM PDT 24
Peak memory 724956 kb
Host smart-9aed801a-1f59-4d54-bac4-fd28762329c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874319301 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.874319301
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3414333679
Short name T46
Test name
Test status
Simulation time 70704383766 ps
CPU time 1795.33 seconds
Started Jun 04 12:27:27 PM PDT 24
Finished Jun 04 12:57:25 PM PDT 24
Peak memory 712724 kb
Host smart-903dd815-3c81-4014-a541-b0708417e35e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414333679 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3414333679
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2897299280
Short name T28
Test name
Test status
Simulation time 63037166 ps
CPU time 0.89 seconds
Started Jun 04 12:27:16 PM PDT 24
Finished Jun 04 12:27:19 PM PDT 24
Peak memory 218484 kb
Host smart-b4f42838-1676-4a93-9f89-a3a39d08986f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897299280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2897299280
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3927719037
Short name T52
Test name
Test status
Simulation time 215436927 ps
CPU time 2.93 seconds
Started Jun 04 12:51:33 PM PDT 24
Finished Jun 04 12:51:39 PM PDT 24
Peak memory 199324 kb
Host smart-5304743e-f845-4fdd-a2e3-361b6c762b48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927719037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.3927719037
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3255435032
Short name T18
Test name
Test status
Simulation time 12791466 ps
CPU time 0.56 seconds
Started Jun 04 12:27:43 PM PDT 24
Finished Jun 04 12:27:44 PM PDT 24
Peak memory 195456 kb
Host smart-8651bec8-3c2d-4f73-ac18-80fc4cd49da9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255435032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3255435032
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.33308146
Short name T91
Test name
Test status
Simulation time 25811758 ps
CPU time 0.8 seconds
Started Jun 04 12:51:46 PM PDT 24
Finished Jun 04 12:51:49 PM PDT 24
Peak memory 198568 kb
Host smart-4737d67f-6105-40dc-b065-1684a6a1e244
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33308146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.33308146
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/default/0.hmac_stress_all.1613597260
Short name T10
Test name
Test status
Simulation time 106682408667 ps
CPU time 4890.19 seconds
Started Jun 04 12:27:16 PM PDT 24
Finished Jun 04 01:48:49 PM PDT 24
Peak memory 848340 kb
Host smart-115d179a-4446-4f2f-93a7-026fb2f985d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613597260 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.1613597260
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2959284363
Short name T13
Test name
Test status
Simulation time 989395446 ps
CPU time 13.33 seconds
Started Jun 04 12:27:32 PM PDT 24
Finished Jun 04 12:27:46 PM PDT 24
Peak memory 199960 kb
Host smart-09d49ac6-ce9b-4772-87fc-93947a79ec63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959284363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2959284363
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.982944008
Short name T115
Test name
Test status
Simulation time 297909103 ps
CPU time 4.29 seconds
Started Jun 04 12:51:32 PM PDT 24
Finished Jun 04 12:51:39 PM PDT 24
Peak memory 199352 kb
Host smart-726f98b6-24ae-42d5-9517-ca1abb0d1936
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982944008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.982944008
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/24.hmac_stress_all.494607948
Short name T73
Test name
Test status
Simulation time 614065160579 ps
CPU time 2684.77 seconds
Started Jun 04 12:28:08 PM PDT 24
Finished Jun 04 01:12:54 PM PDT 24
Peak memory 478120 kb
Host smart-dd4c1a66-99ba-4ae0-ab5d-af886d5d90a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494607948 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.494607948
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3281016628
Short name T102
Test name
Test status
Simulation time 931619366 ps
CPU time 47.06 seconds
Started Jun 04 12:28:38 PM PDT 24
Finished Jun 04 12:29:26 PM PDT 24
Peak memory 200004 kb
Host smart-f23dc5be-a5f7-466d-8060-ce607eff3b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281016628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3281016628
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.695886196
Short name T54
Test name
Test status
Simulation time 1199914712 ps
CPU time 3.23 seconds
Started Jun 04 12:51:47 PM PDT 24
Finished Jun 04 12:51:52 PM PDT 24
Peak memory 199216 kb
Host smart-17c92285-e76e-4e81-bdff-a49256c7bb1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695886196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.695886196
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3297730965
Short name T118
Test name
Test status
Simulation time 177028421 ps
CPU time 2.99 seconds
Started Jun 04 12:51:40 PM PDT 24
Finished Jun 04 12:51:44 PM PDT 24
Peak memory 199372 kb
Host smart-43fd405c-af0c-4fb7-9596-5eb14a08ddff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297730965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3297730965
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/22.hmac_stress_all.492824949
Short name T111
Test name
Test status
Simulation time 128885765502 ps
CPU time 1793.32 seconds
Started Jun 04 12:28:07 PM PDT 24
Finished Jun 04 12:58:02 PM PDT 24
Peak memory 217348 kb
Host smart-78814773-f7ff-4603-870c-e8e149825052
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492824949 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.492824949
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_stress_all.1058170345
Short name T103
Test name
Test status
Simulation time 80912672969 ps
CPU time 1209.21 seconds
Started Jun 04 12:28:51 PM PDT 24
Finished Jun 04 12:49:01 PM PDT 24
Peak memory 199972 kb
Host smart-e3c399a1-640d-4693-9962-b24368caeb87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058170345 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1058170345
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_long_msg.470366722
Short name T110
Test name
Test status
Simulation time 26887323430 ps
CPU time 100.95 seconds
Started Jun 04 12:28:48 PM PDT 24
Finished Jun 04 12:30:30 PM PDT 24
Peak memory 200052 kb
Host smart-abd45466-f09d-4e84-a23d-a8972924cc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470366722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.470366722
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.4047059625
Short name T58
Test name
Test status
Simulation time 52360835 ps
CPU time 1.71 seconds
Started Jun 04 12:51:29 PM PDT 24
Finished Jun 04 12:51:31 PM PDT 24
Peak memory 199364 kb
Host smart-c1ba0e35-46b9-4553-8c48-7805b18a5d13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047059625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.4047059625
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.458963047
Short name T643
Test name
Test status
Simulation time 232163652 ps
CPU time 3.17 seconds
Started Jun 04 12:51:31 PM PDT 24
Finished Jun 04 12:51:37 PM PDT 24
Peak memory 199160 kb
Host smart-a63ce773-e2da-43bb-bd05-771b1db1986f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458963047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.458963047
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3612697084
Short name T717
Test name
Test status
Simulation time 2235494789 ps
CPU time 11.28 seconds
Started Jun 04 12:51:36 PM PDT 24
Finished Jun 04 12:51:49 PM PDT 24
Peak memory 199308 kb
Host smart-2653abea-3098-4c93-b565-8c0ac7f3002e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612697084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3612697084
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3995438223
Short name T630
Test name
Test status
Simulation time 66165476 ps
CPU time 0.75 seconds
Started Jun 04 12:51:31 PM PDT 24
Finished Jun 04 12:51:34 PM PDT 24
Peak memory 197088 kb
Host smart-4e285b07-c51d-4f92-a271-10f6564b0446
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995438223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3995438223
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3533373827
Short name T726
Test name
Test status
Simulation time 73262859 ps
CPU time 1.68 seconds
Started Jun 04 12:51:35 PM PDT 24
Finished Jun 04 12:51:39 PM PDT 24
Peak memory 199372 kb
Host smart-b1efc022-7da3-45e9-9f4a-dbebb33603ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533373827 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.3533373827
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.305453201
Short name T666
Test name
Test status
Simulation time 46547671 ps
CPU time 0.86 seconds
Started Jun 04 12:51:30 PM PDT 24
Finished Jun 04 12:51:32 PM PDT 24
Peak memory 199000 kb
Host smart-9f38b9a2-a838-4ba7-b748-3b03c70ea42f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305453201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.305453201
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2907860852
Short name T665
Test name
Test status
Simulation time 16298354 ps
CPU time 0.57 seconds
Started Jun 04 12:51:33 PM PDT 24
Finished Jun 04 12:51:36 PM PDT 24
Peak memory 194200 kb
Host smart-1c1491c5-391a-464f-add3-ff75c7f7b633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907860852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2907860852
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.55418291
Short name T660
Test name
Test status
Simulation time 121597625 ps
CPU time 1.56 seconds
Started Jun 04 12:51:36 PM PDT 24
Finished Jun 04 12:51:39 PM PDT 24
Peak memory 199372 kb
Host smart-2f441cb1-47a6-4ff5-8ada-0c7b33071440
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55418291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_o
utstanding.55418291
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.664039359
Short name T648
Test name
Test status
Simulation time 98493732 ps
CPU time 1.86 seconds
Started Jun 04 12:51:33 PM PDT 24
Finished Jun 04 12:51:38 PM PDT 24
Peak memory 199472 kb
Host smart-89bb91fd-b8ec-4cad-9b8f-72505168a206
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664039359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.664039359
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1606151695
Short name T97
Test name
Test status
Simulation time 311550749 ps
CPU time 6.25 seconds
Started Jun 04 12:51:30 PM PDT 24
Finished Jun 04 12:51:37 PM PDT 24
Peak memory 199204 kb
Host smart-18fa4781-1c2d-45d4-860c-fba520f846dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606151695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1606151695
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.858576896
Short name T619
Test name
Test status
Simulation time 117422717 ps
CPU time 5.14 seconds
Started Jun 04 12:51:31 PM PDT 24
Finished Jun 04 12:51:37 PM PDT 24
Peak memory 199128 kb
Host smart-92270917-577e-485b-92d7-93954ed2d7a7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858576896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.858576896
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.4275098153
Short name T89
Test name
Test status
Simulation time 85586406 ps
CPU time 0.95 seconds
Started Jun 04 12:51:29 PM PDT 24
Finished Jun 04 12:51:30 PM PDT 24
Peak memory 198928 kb
Host smart-d2b546aa-9e7e-4648-96db-3e0605270e60
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275098153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.4275098153
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2030957620
Short name T647
Test name
Test status
Simulation time 49412457 ps
CPU time 3 seconds
Started Jun 04 12:51:32 PM PDT 24
Finished Jun 04 12:51:37 PM PDT 24
Peak memory 207628 kb
Host smart-4dba53f1-ce44-4d08-9275-ce0905f8f7f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030957620 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2030957620
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.56432881
Short name T713
Test name
Test status
Simulation time 100923521 ps
CPU time 0.82 seconds
Started Jun 04 12:51:31 PM PDT 24
Finished Jun 04 12:51:34 PM PDT 24
Peak memory 198452 kb
Host smart-5c6ae2b5-bbe8-41eb-aefd-da2fda956308
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56432881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.56432881
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1006457466
Short name T624
Test name
Test status
Simulation time 14978308 ps
CPU time 0.61 seconds
Started Jun 04 12:51:31 PM PDT 24
Finished Jun 04 12:51:34 PM PDT 24
Peak memory 194060 kb
Host smart-fbfa5250-64bd-4d2b-8ce8-c9ca4904eb6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006457466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1006457466
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2008095133
Short name T654
Test name
Test status
Simulation time 394003898 ps
CPU time 1.8 seconds
Started Jun 04 12:51:32 PM PDT 24
Finished Jun 04 12:51:36 PM PDT 24
Peak memory 199180 kb
Host smart-0f831223-d6f9-4a6f-98fc-f0cdebb56309
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008095133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2008095133
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2372769839
Short name T662
Test name
Test status
Simulation time 571850672 ps
CPU time 2.34 seconds
Started Jun 04 12:51:30 PM PDT 24
Finished Jun 04 12:51:34 PM PDT 24
Peak memory 199316 kb
Host smart-5a430781-9b32-4053-94e2-a5c4e457ec15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372769839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2372769839
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3407979039
Short name T705
Test name
Test status
Simulation time 88906356942 ps
CPU time 137.93 seconds
Started Jun 04 12:51:41 PM PDT 24
Finished Jun 04 12:54:00 PM PDT 24
Peak memory 207692 kb
Host smart-3ccd658b-8aed-4562-9059-ee74fb7c8811
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407979039 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3407979039
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3202448452
Short name T651
Test name
Test status
Simulation time 15757424 ps
CPU time 0.58 seconds
Started Jun 04 12:51:55 PM PDT 24
Finished Jun 04 12:51:57 PM PDT 24
Peak memory 193888 kb
Host smart-e3c77bc2-3de5-4312-91df-04b0e133a458
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202448452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3202448452
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2522034428
Short name T672
Test name
Test status
Simulation time 607625189 ps
CPU time 2.5 seconds
Started Jun 04 12:51:41 PM PDT 24
Finished Jun 04 12:51:44 PM PDT 24
Peak memory 199352 kb
Host smart-c57ccd48-e54a-4d5b-8997-4bc97628e5ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522034428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2522034428
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3541518496
Short name T603
Test name
Test status
Simulation time 119924997 ps
CPU time 1.66 seconds
Started Jun 04 12:51:44 PM PDT 24
Finished Jun 04 12:51:47 PM PDT 24
Peak memory 199464 kb
Host smart-5bf2fa81-19ac-4977-b639-863d727ad3fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541518496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3541518496
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3576653521
Short name T712
Test name
Test status
Simulation time 84058835448 ps
CPU time 831.52 seconds
Started Jun 04 12:51:40 PM PDT 24
Finished Jun 04 01:05:32 PM PDT 24
Peak memory 215888 kb
Host smart-809a8ada-8103-4ee1-8339-eaac012c7f01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576653521 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.3576653521
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.651725174
Short name T696
Test name
Test status
Simulation time 26597958 ps
CPU time 0.84 seconds
Started Jun 04 12:51:44 PM PDT 24
Finished Jun 04 12:51:46 PM PDT 24
Peak memory 198164 kb
Host smart-42a00c32-05b8-454d-974d-1ab818763215
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651725174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.651725174
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.738967853
Short name T707
Test name
Test status
Simulation time 43454484 ps
CPU time 0.63 seconds
Started Jun 04 12:51:39 PM PDT 24
Finished Jun 04 12:51:41 PM PDT 24
Peak memory 194144 kb
Host smart-bc557132-4a3a-4c38-b0bf-416bef34ff08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738967853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.738967853
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3897238168
Short name T56
Test name
Test status
Simulation time 34302469 ps
CPU time 1.67 seconds
Started Jun 04 12:51:40 PM PDT 24
Finished Jun 04 12:51:43 PM PDT 24
Peak memory 199376 kb
Host smart-6506498e-fccc-4580-a912-f5ed358d71d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897238168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3897238168
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1647299598
Short name T640
Test name
Test status
Simulation time 182834639 ps
CPU time 2.63 seconds
Started Jun 04 12:51:39 PM PDT 24
Finished Jun 04 12:51:43 PM PDT 24
Peak memory 199260 kb
Host smart-d07787af-efd9-438f-9223-3b83a76c4f34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647299598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1647299598
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1195884129
Short name T686
Test name
Test status
Simulation time 37174694 ps
CPU time 1.2 seconds
Started Jun 04 12:51:41 PM PDT 24
Finished Jun 04 12:51:43 PM PDT 24
Peak memory 199180 kb
Host smart-2b79e9b6-7106-4777-bf17-7f5ebc148cc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195884129 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1195884129
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2392831343
Short name T690
Test name
Test status
Simulation time 15625592 ps
CPU time 0.82 seconds
Started Jun 04 12:51:44 PM PDT 24
Finished Jun 04 12:51:46 PM PDT 24
Peak memory 199104 kb
Host smart-f410976a-4fb2-4498-a73b-fff6de9f9304
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392831343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2392831343
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.4241800285
Short name T693
Test name
Test status
Simulation time 12993642 ps
CPU time 0.65 seconds
Started Jun 04 12:51:47 PM PDT 24
Finished Jun 04 12:51:49 PM PDT 24
Peak memory 193964 kb
Host smart-32dc07c0-c73f-4395-80cb-0fb99214a78b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241800285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.4241800285
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1810439786
Short name T620
Test name
Test status
Simulation time 79044816 ps
CPU time 1.71 seconds
Started Jun 04 12:51:44 PM PDT 24
Finished Jun 04 12:51:47 PM PDT 24
Peak memory 199368 kb
Host smart-b73096a0-c387-4fa3-a6ec-e548b9583194
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810439786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1810439786
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.467120101
Short name T622
Test name
Test status
Simulation time 272985640 ps
CPU time 2.65 seconds
Started Jun 04 12:51:42 PM PDT 24
Finished Jun 04 12:51:46 PM PDT 24
Peak memory 199296 kb
Host smart-76ee647d-31f5-45a1-b1cb-ef4dc4e730e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467120101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.467120101
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3554527054
Short name T119
Test name
Test status
Simulation time 342109641 ps
CPU time 2.85 seconds
Started Jun 04 12:51:45 PM PDT 24
Finished Jun 04 12:51:49 PM PDT 24
Peak memory 199412 kb
Host smart-f9cd63d6-301b-4cd3-aba0-530016e00aa6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554527054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3554527054
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2104681531
Short name T680
Test name
Test status
Simulation time 75587167 ps
CPU time 1.17 seconds
Started Jun 04 12:51:47 PM PDT 24
Finished Jun 04 12:51:50 PM PDT 24
Peak memory 199060 kb
Host smart-9c3906f7-7742-4f87-8639-7478fb470e62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104681531 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2104681531
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3556174287
Short name T628
Test name
Test status
Simulation time 19579366 ps
CPU time 0.76 seconds
Started Jun 04 12:51:44 PM PDT 24
Finished Jun 04 12:51:46 PM PDT 24
Peak memory 196920 kb
Host smart-bbafea03-97ea-4a85-9f2c-fae40dbf51ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556174287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3556174287
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2068995675
Short name T625
Test name
Test status
Simulation time 18402168 ps
CPU time 0.65 seconds
Started Jun 04 12:51:39 PM PDT 24
Finished Jun 04 12:51:41 PM PDT 24
Peak memory 194140 kb
Host smart-9e535831-d17b-4506-b8e3-412dd8534de2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068995675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2068995675
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.829274609
Short name T671
Test name
Test status
Simulation time 43920880 ps
CPU time 1.99 seconds
Started Jun 04 12:51:45 PM PDT 24
Finished Jun 04 12:51:48 PM PDT 24
Peak memory 199300 kb
Host smart-577f3d38-4445-418b-976f-0d326b3bf266
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829274609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr
_outstanding.829274609
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1957946679
Short name T613
Test name
Test status
Simulation time 109383989 ps
CPU time 3.06 seconds
Started Jun 04 12:51:39 PM PDT 24
Finished Jun 04 12:51:43 PM PDT 24
Peak memory 199200 kb
Host smart-eb25039f-defa-43f4-828a-5c7b9c9b86bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957946679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1957946679
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.4041249207
Short name T123
Test name
Test status
Simulation time 2577658184 ps
CPU time 3.19 seconds
Started Jun 04 12:51:40 PM PDT 24
Finished Jun 04 12:51:45 PM PDT 24
Peak memory 199424 kb
Host smart-745a6381-ef0c-4c0e-ad0c-87e54a8ca3be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041249207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.4041249207
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.390996025
Short name T601
Test name
Test status
Simulation time 56071221 ps
CPU time 3.38 seconds
Started Jun 04 12:51:46 PM PDT 24
Finished Jun 04 12:51:51 PM PDT 24
Peak memory 207088 kb
Host smart-b7924f93-cadf-4e83-85c4-de9ca29a116f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390996025 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.390996025
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2789975809
Short name T649
Test name
Test status
Simulation time 18643857 ps
CPU time 0.75 seconds
Started Jun 04 12:51:40 PM PDT 24
Finished Jun 04 12:51:42 PM PDT 24
Peak memory 196916 kb
Host smart-a6283806-e5dc-4802-8976-d031b4201d5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789975809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2789975809
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1128106560
Short name T608
Test name
Test status
Simulation time 15351039 ps
CPU time 0.62 seconds
Started Jun 04 12:51:39 PM PDT 24
Finished Jun 04 12:51:41 PM PDT 24
Peak memory 194048 kb
Host smart-46b0bf11-7c67-4967-8fb4-cf9b12bb3201
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128106560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1128106560
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.780977861
Short name T720
Test name
Test status
Simulation time 33953038 ps
CPU time 1.54 seconds
Started Jun 04 12:51:51 PM PDT 24
Finished Jun 04 12:51:54 PM PDT 24
Peak memory 199288 kb
Host smart-ad9dde5a-4118-4936-968e-5fe34ac753e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780977861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr
_outstanding.780977861
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.4019874034
Short name T627
Test name
Test status
Simulation time 70448073 ps
CPU time 3.35 seconds
Started Jun 04 12:51:52 PM PDT 24
Finished Jun 04 12:51:57 PM PDT 24
Peak memory 199396 kb
Host smart-9e397bbd-d89f-4a36-b4cc-06aaf2977614
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019874034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.4019874034
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3342502809
Short name T122
Test name
Test status
Simulation time 498004985 ps
CPU time 4.05 seconds
Started Jun 04 12:51:40 PM PDT 24
Finished Jun 04 12:51:46 PM PDT 24
Peak memory 199220 kb
Host smart-df34ce11-07b7-478c-bd3d-89a3bfdfa5a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342502809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3342502809
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3594900952
Short name T615
Test name
Test status
Simulation time 58876184 ps
CPU time 3.84 seconds
Started Jun 04 12:51:53 PM PDT 24
Finished Jun 04 12:51:58 PM PDT 24
Peak memory 214852 kb
Host smart-823add60-0858-4aa1-99d1-c502118501d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594900952 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.3594900952
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.594125660
Short name T661
Test name
Test status
Simulation time 17047325 ps
CPU time 0.82 seconds
Started Jun 04 12:51:53 PM PDT 24
Finished Jun 04 12:51:55 PM PDT 24
Peak memory 199028 kb
Host smart-a498b510-7f9d-4ead-8f2e-3a3d9dcb0199
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594125660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.594125660
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1302932806
Short name T663
Test name
Test status
Simulation time 14352835 ps
CPU time 0.59 seconds
Started Jun 04 12:51:46 PM PDT 24
Finished Jun 04 12:51:48 PM PDT 24
Peak memory 194176 kb
Host smart-f73d2d81-639a-4b69-b598-9316e05e9afa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302932806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1302932806
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1077150551
Short name T719
Test name
Test status
Simulation time 111347623 ps
CPU time 2.34 seconds
Started Jun 04 12:51:49 PM PDT 24
Finished Jun 04 12:51:53 PM PDT 24
Peak memory 199172 kb
Host smart-c8fd62c8-6a7a-4d31-886d-faf096bc3124
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077150551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.1077150551
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.818098183
Short name T602
Test name
Test status
Simulation time 29021169 ps
CPU time 1.48 seconds
Started Jun 04 12:51:40 PM PDT 24
Finished Jun 04 12:51:43 PM PDT 24
Peak memory 199324 kb
Host smart-620fd73b-4cbf-4c72-9aaa-2bf9fec861ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818098183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.818098183
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.854584139
Short name T124
Test name
Test status
Simulation time 607765112 ps
CPU time 1.94 seconds
Started Jun 04 12:51:46 PM PDT 24
Finished Jun 04 12:51:49 PM PDT 24
Peak memory 199304 kb
Host smart-dff5bba6-0860-41d9-909c-b81d68200040
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854584139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.854584139
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1551619018
Short name T634
Test name
Test status
Simulation time 36008670 ps
CPU time 2.1 seconds
Started Jun 04 12:51:51 PM PDT 24
Finished Jun 04 12:51:54 PM PDT 24
Peak memory 199428 kb
Host smart-7e90b838-491a-4cd3-915d-7ba9ca23e9df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551619018 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.1551619018
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1622798543
Short name T94
Test name
Test status
Simulation time 27499584 ps
CPU time 0.82 seconds
Started Jun 04 12:51:47 PM PDT 24
Finished Jun 04 12:51:49 PM PDT 24
Peak memory 198568 kb
Host smart-ce01f48a-a0d7-47bd-8c52-64d50f04fd44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622798543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1622798543
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3352281440
Short name T657
Test name
Test status
Simulation time 30455895 ps
CPU time 0.6 seconds
Started Jun 04 12:51:53 PM PDT 24
Finished Jun 04 12:51:55 PM PDT 24
Peak memory 194132 kb
Host smart-d57c49df-0cc8-416c-850b-6ec31cd32e93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352281440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3352281440
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2247362856
Short name T682
Test name
Test status
Simulation time 23050085 ps
CPU time 1.1 seconds
Started Jun 04 12:51:46 PM PDT 24
Finished Jun 04 12:51:49 PM PDT 24
Peak memory 199304 kb
Host smart-d2f1a068-b4c9-4e33-90b2-7784e9b31fe2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247362856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.2247362856
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1606315028
Short name T669
Test name
Test status
Simulation time 145524697 ps
CPU time 2.88 seconds
Started Jun 04 12:51:49 PM PDT 24
Finished Jun 04 12:51:54 PM PDT 24
Peak memory 199256 kb
Host smart-d9786798-ba66-4168-b0de-78e419637d9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606315028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1606315028
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3580951386
Short name T53
Test name
Test status
Simulation time 478519339 ps
CPU time 1.93 seconds
Started Jun 04 12:51:39 PM PDT 24
Finished Jun 04 12:51:42 PM PDT 24
Peak memory 199384 kb
Host smart-b3436232-5817-4b14-a0a5-edbe658ccd20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580951386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3580951386
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2674224790
Short name T637
Test name
Test status
Simulation time 99156463 ps
CPU time 2.17 seconds
Started Jun 04 12:51:53 PM PDT 24
Finished Jun 04 12:51:57 PM PDT 24
Peak memory 199428 kb
Host smart-f3151807-da56-4246-9102-f884c855a015
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674224790 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2674224790
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3920756009
Short name T87
Test name
Test status
Simulation time 42312450 ps
CPU time 0.69 seconds
Started Jun 04 12:51:46 PM PDT 24
Finished Jun 04 12:51:48 PM PDT 24
Peak memory 196832 kb
Host smart-1c859ac6-2a91-4288-a85d-e48361c3602a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920756009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3920756009
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.4066141929
Short name T706
Test name
Test status
Simulation time 13565034 ps
CPU time 0.59 seconds
Started Jun 04 12:51:46 PM PDT 24
Finished Jun 04 12:51:48 PM PDT 24
Peak memory 194104 kb
Host smart-c3f9bea0-f9bd-44c9-a1ee-24f8f4e4d121
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066141929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.4066141929
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3317434886
Short name T642
Test name
Test status
Simulation time 203088798 ps
CPU time 1.25 seconds
Started Jun 04 12:51:55 PM PDT 24
Finished Jun 04 12:51:58 PM PDT 24
Peak memory 197724 kb
Host smart-acd677c6-4fe8-4b51-9e5d-6d3446ab9a78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317434886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3317434886
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.866946496
Short name T621
Test name
Test status
Simulation time 151334049 ps
CPU time 1.77 seconds
Started Jun 04 12:51:55 PM PDT 24
Finished Jun 04 12:51:58 PM PDT 24
Peak memory 199340 kb
Host smart-26dead4d-8b54-4c33-a656-8cf00c997b9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866946496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.866946496
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.4234966703
Short name T695
Test name
Test status
Simulation time 269536867 ps
CPU time 4.46 seconds
Started Jun 04 12:51:53 PM PDT 24
Finished Jun 04 12:51:59 PM PDT 24
Peak memory 199368 kb
Host smart-b81ed386-4d72-4821-86d4-a909fa32f6c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234966703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.4234966703
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3443748242
Short name T626
Test name
Test status
Simulation time 114277697 ps
CPU time 3.4 seconds
Started Jun 04 12:51:40 PM PDT 24
Finished Jun 04 12:51:44 PM PDT 24
Peak memory 199384 kb
Host smart-4ca29e96-1bb8-4284-a86d-4fca3676f3c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443748242 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3443748242
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3760163730
Short name T600
Test name
Test status
Simulation time 46194393 ps
CPU time 0.84 seconds
Started Jun 04 12:51:46 PM PDT 24
Finished Jun 04 12:51:48 PM PDT 24
Peak memory 198088 kb
Host smart-351abf85-8444-48d3-befe-4cc68d5dff24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760163730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3760163730
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3490996529
Short name T685
Test name
Test status
Simulation time 28193710 ps
CPU time 0.62 seconds
Started Jun 04 12:51:55 PM PDT 24
Finished Jun 04 12:51:57 PM PDT 24
Peak memory 193940 kb
Host smart-0bb78d78-0f1e-4cb7-8200-d9132bf9b4d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490996529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3490996529
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3099734225
Short name T691
Test name
Test status
Simulation time 185557612 ps
CPU time 2.26 seconds
Started Jun 04 12:51:46 PM PDT 24
Finished Jun 04 12:51:49 PM PDT 24
Peak memory 199136 kb
Host smart-23325ac1-6fe5-4ad8-96f4-60364286c32b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099734225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3099734225
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.712095633
Short name T703
Test name
Test status
Simulation time 261880740 ps
CPU time 3.33 seconds
Started Jun 04 12:51:46 PM PDT 24
Finished Jun 04 12:51:51 PM PDT 24
Peak memory 199316 kb
Host smart-7c2d49e0-5b14-45f8-ba90-ed8da75d9d0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712095633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.712095633
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.508328863
Short name T652
Test name
Test status
Simulation time 643612219 ps
CPU time 1.72 seconds
Started Jun 04 12:51:49 PM PDT 24
Finished Jun 04 12:51:52 PM PDT 24
Peak memory 199204 kb
Host smart-630a3447-55e4-47b1-840f-7238762d201d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508328863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.508328863
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2561918209
Short name T611
Test name
Test status
Simulation time 41584709 ps
CPU time 1.21 seconds
Started Jun 04 12:51:43 PM PDT 24
Finished Jun 04 12:51:45 PM PDT 24
Peak memory 199144 kb
Host smart-ec7c81f9-c4a4-46be-9f93-0067da6994d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561918209 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.2561918209
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2180878191
Short name T683
Test name
Test status
Simulation time 37948679 ps
CPU time 0.67 seconds
Started Jun 04 12:51:39 PM PDT 24
Finished Jun 04 12:51:41 PM PDT 24
Peak memory 196932 kb
Host smart-a89e1757-d128-4b4c-9059-dcfd1ed3227b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180878191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2180878191
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1247923415
Short name T716
Test name
Test status
Simulation time 21746890 ps
CPU time 0.57 seconds
Started Jun 04 12:51:46 PM PDT 24
Finished Jun 04 12:51:48 PM PDT 24
Peak memory 194116 kb
Host smart-c89f34d8-3090-4d82-9fbd-7e993fbb03f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247923415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1247923415
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1009724671
Short name T711
Test name
Test status
Simulation time 50400223 ps
CPU time 2.24 seconds
Started Jun 04 12:51:46 PM PDT 24
Finished Jun 04 12:51:49 PM PDT 24
Peak memory 198796 kb
Host smart-bb0a6771-433b-4c0e-953e-f9c06a2b7dae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009724671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1009724671
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2963375654
Short name T62
Test name
Test status
Simulation time 256354685 ps
CPU time 1.67 seconds
Started Jun 04 12:51:55 PM PDT 24
Finished Jun 04 12:51:58 PM PDT 24
Peak memory 199312 kb
Host smart-22babaf2-a8c8-4f27-a269-1472ec639284
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963375654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2963375654
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2707171558
Short name T114
Test name
Test status
Simulation time 624878240 ps
CPU time 2.97 seconds
Started Jun 04 12:51:55 PM PDT 24
Finished Jun 04 12:52:00 PM PDT 24
Peak memory 199260 kb
Host smart-783b38c6-92f9-498c-803e-40e4e5697f6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707171558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2707171558
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2427493549
Short name T95
Test name
Test status
Simulation time 110059010 ps
CPU time 5.17 seconds
Started Jun 04 12:51:38 PM PDT 24
Finished Jun 04 12:51:45 PM PDT 24
Peak memory 199316 kb
Host smart-5eec4740-dad6-4244-9a48-4bca58213953
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427493549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.2427493549
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4096859501
Short name T715
Test name
Test status
Simulation time 6561854923 ps
CPU time 16.35 seconds
Started Jun 04 12:51:31 PM PDT 24
Finished Jun 04 12:51:49 PM PDT 24
Peak memory 198500 kb
Host smart-8a753eea-3710-4b83-8520-dd96d6c04d03
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096859501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.4096859501
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1442298901
Short name T86
Test name
Test status
Simulation time 229324807 ps
CPU time 0.95 seconds
Started Jun 04 12:51:32 PM PDT 24
Finished Jun 04 12:51:36 PM PDT 24
Peak memory 198060 kb
Host smart-c2f3fc93-322f-4bf9-8f27-870a477f095a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442298901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1442298901
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3660206463
Short name T688
Test name
Test status
Simulation time 83196297 ps
CPU time 1.3 seconds
Started Jun 04 12:51:31 PM PDT 24
Finished Jun 04 12:51:34 PM PDT 24
Peak memory 199400 kb
Host smart-9180cf55-bde7-4eb3-a523-5b6391617b2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660206463 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3660206463
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1559545071
Short name T92
Test name
Test status
Simulation time 135527065 ps
CPU time 0.86 seconds
Started Jun 04 12:51:32 PM PDT 24
Finished Jun 04 12:51:35 PM PDT 24
Peak memory 199096 kb
Host smart-738e6021-903b-4198-a9a0-349f809b1094
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559545071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1559545071
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.675369596
Short name T724
Test name
Test status
Simulation time 12454168 ps
CPU time 0.63 seconds
Started Jun 04 12:51:30 PM PDT 24
Finished Jun 04 12:51:32 PM PDT 24
Peak memory 194132 kb
Host smart-9ee2de35-66ce-4182-8c22-753bd4b456d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675369596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.675369596
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.4176589302
Short name T710
Test name
Test status
Simulation time 102998345 ps
CPU time 1.77 seconds
Started Jun 04 12:51:30 PM PDT 24
Finished Jun 04 12:51:33 PM PDT 24
Peak memory 199048 kb
Host smart-1e355bca-7e99-43dd-aadb-489fcbca2d8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176589302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.4176589302
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1841627545
Short name T676
Test name
Test status
Simulation time 248980597 ps
CPU time 1.42 seconds
Started Jun 04 12:51:32 PM PDT 24
Finished Jun 04 12:51:36 PM PDT 24
Peak memory 199420 kb
Host smart-621bbf7c-1465-4bc0-aefb-ae333549d817
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841627545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1841627545
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.509412484
Short name T675
Test name
Test status
Simulation time 292554720 ps
CPU time 4.5 seconds
Started Jun 04 12:51:39 PM PDT 24
Finished Jun 04 12:51:44 PM PDT 24
Peak memory 199308 kb
Host smart-28379462-3313-43a8-b89b-37f23a9cbc76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509412484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.509412484
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1419215656
Short name T638
Test name
Test status
Simulation time 12956129 ps
CPU time 0.6 seconds
Started Jun 04 12:51:44 PM PDT 24
Finished Jun 04 12:51:46 PM PDT 24
Peak memory 194144 kb
Host smart-5777f1c5-bb7a-4ee2-a463-3f3f3ac71cd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419215656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1419215656
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1789351402
Short name T616
Test name
Test status
Simulation time 38706054 ps
CPU time 0.59 seconds
Started Jun 04 12:51:55 PM PDT 24
Finished Jun 04 12:51:57 PM PDT 24
Peak memory 194112 kb
Host smart-bd2742b9-600d-422f-9b86-e19363a6d288
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789351402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1789351402
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.2297171783
Short name T658
Test name
Test status
Simulation time 49558894 ps
CPU time 0.59 seconds
Started Jun 04 12:51:55 PM PDT 24
Finished Jun 04 12:51:57 PM PDT 24
Peak memory 194112 kb
Host smart-34dcecaf-f99f-4273-b410-aa3e80e4d488
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297171783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.2297171783
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.3867713803
Short name T702
Test name
Test status
Simulation time 17133086 ps
CPU time 0.6 seconds
Started Jun 04 12:51:55 PM PDT 24
Finished Jun 04 12:51:57 PM PDT 24
Peak memory 194028 kb
Host smart-0ee4616d-32eb-4848-ad98-4c3472f31185
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867713803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.3867713803
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1198395895
Short name T681
Test name
Test status
Simulation time 13626111 ps
CPU time 0.57 seconds
Started Jun 04 12:51:43 PM PDT 24
Finished Jun 04 12:51:44 PM PDT 24
Peak memory 194048 kb
Host smart-70fc4b5a-b65a-4646-afd1-5ee0f1a29595
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198395895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1198395895
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3654225310
Short name T709
Test name
Test status
Simulation time 181353044 ps
CPU time 0.62 seconds
Started Jun 04 12:51:43 PM PDT 24
Finished Jun 04 12:51:44 PM PDT 24
Peak memory 194112 kb
Host smart-3a9563d3-38fa-48d3-9bc7-cbe63d2a26f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654225310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3654225310
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.380050596
Short name T606
Test name
Test status
Simulation time 17350315 ps
CPU time 0.6 seconds
Started Jun 04 12:51:50 PM PDT 24
Finished Jun 04 12:51:52 PM PDT 24
Peak memory 194196 kb
Host smart-84c7e18a-33a8-49d9-926f-e4258a571286
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380050596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.380050596
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1348320151
Short name T725
Test name
Test status
Simulation time 26330463 ps
CPU time 0.58 seconds
Started Jun 04 12:51:49 PM PDT 24
Finished Jun 04 12:51:51 PM PDT 24
Peak memory 194128 kb
Host smart-446a9300-2c16-4c49-b4d5-3b61235ea863
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348320151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1348320151
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.965827732
Short name T722
Test name
Test status
Simulation time 18214762 ps
CPU time 0.61 seconds
Started Jun 04 12:51:42 PM PDT 24
Finished Jun 04 12:51:44 PM PDT 24
Peak memory 194116 kb
Host smart-350db1b2-9a51-4244-861f-2514ec1d936c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965827732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.965827732
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.832000347
Short name T668
Test name
Test status
Simulation time 13778242 ps
CPU time 0.58 seconds
Started Jun 04 12:51:44 PM PDT 24
Finished Jun 04 12:51:45 PM PDT 24
Peak memory 194100 kb
Host smart-0d3c585a-30ec-40dc-991a-1affe63034fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832000347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.832000347
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4040297989
Short name T679
Test name
Test status
Simulation time 288886151 ps
CPU time 3.44 seconds
Started Jun 04 12:51:32 PM PDT 24
Finished Jun 04 12:51:38 PM PDT 24
Peak memory 199220 kb
Host smart-264950b6-fd56-4664-8e23-3694b88dc1c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040297989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.4040297989
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3575927569
Short name T90
Test name
Test status
Simulation time 9810487271 ps
CPU time 16.55 seconds
Started Jun 04 12:51:33 PM PDT 24
Finished Jun 04 12:51:52 PM PDT 24
Peak memory 198864 kb
Host smart-95588f38-6259-47ad-9831-bbfde352c5a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575927569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3575927569
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2600682383
Short name T96
Test name
Test status
Simulation time 69288205 ps
CPU time 1.04 seconds
Started Jun 04 12:51:33 PM PDT 24
Finished Jun 04 12:51:37 PM PDT 24
Peak memory 199092 kb
Host smart-757be81d-bb92-4db6-b9ae-15f1a649ac2f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600682383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2600682383
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1359683147
Short name T55
Test name
Test status
Simulation time 141973892 ps
CPU time 1.72 seconds
Started Jun 04 12:51:33 PM PDT 24
Finished Jun 04 12:51:37 PM PDT 24
Peak memory 199384 kb
Host smart-76b71c07-be8b-48c7-aaad-c827c29fc991
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359683147 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1359683147
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1093787658
Short name T678
Test name
Test status
Simulation time 23173042 ps
CPU time 0.8 seconds
Started Jun 04 12:51:29 PM PDT 24
Finished Jun 04 12:51:31 PM PDT 24
Peak memory 198664 kb
Host smart-507aeeac-d080-4061-b0f6-0b54e876f968
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093787658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1093787658
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.4281956923
Short name T599
Test name
Test status
Simulation time 98580376 ps
CPU time 0.61 seconds
Started Jun 04 12:51:33 PM PDT 24
Finished Jun 04 12:51:35 PM PDT 24
Peak memory 194092 kb
Host smart-63465fd0-3adc-4909-9e66-05112a4cc4cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281956923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.4281956923
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2738113981
Short name T655
Test name
Test status
Simulation time 36061803 ps
CPU time 1.57 seconds
Started Jun 04 12:51:32 PM PDT 24
Finished Jun 04 12:51:36 PM PDT 24
Peak memory 199256 kb
Host smart-a47f709a-8477-45ba-bc59-b98d0cf12d0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738113981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.2738113981
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2934626165
Short name T623
Test name
Test status
Simulation time 121997219 ps
CPU time 2.34 seconds
Started Jun 04 12:51:34 PM PDT 24
Finished Jun 04 12:51:38 PM PDT 24
Peak memory 199348 kb
Host smart-306a9ef5-8400-4169-bcc7-b205104b17b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934626165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2934626165
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1199987955
Short name T692
Test name
Test status
Simulation time 42609745 ps
CPU time 0.6 seconds
Started Jun 04 12:51:48 PM PDT 24
Finished Jun 04 12:51:50 PM PDT 24
Peak memory 194192 kb
Host smart-629022b4-a568-4466-b9ed-ec6f11f52ff9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199987955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1199987955
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.4089800031
Short name T701
Test name
Test status
Simulation time 12289336 ps
CPU time 0.61 seconds
Started Jun 04 12:51:47 PM PDT 24
Finished Jun 04 12:51:49 PM PDT 24
Peak memory 194192 kb
Host smart-9c3c4384-0ab8-4970-a23c-20f7c92c4455
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089800031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.4089800031
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.68610511
Short name T644
Test name
Test status
Simulation time 12849758 ps
CPU time 0.58 seconds
Started Jun 04 12:51:40 PM PDT 24
Finished Jun 04 12:51:42 PM PDT 24
Peak memory 194064 kb
Host smart-ef9a372b-c319-4c38-8857-dacd3b3a1e10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68610511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.68610511
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3085656311
Short name T636
Test name
Test status
Simulation time 18319473 ps
CPU time 0.65 seconds
Started Jun 04 12:51:45 PM PDT 24
Finished Jun 04 12:51:46 PM PDT 24
Peak memory 194124 kb
Host smart-f22181ec-a962-4327-b0fb-e4d92760a509
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085656311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3085656311
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.4288957094
Short name T673
Test name
Test status
Simulation time 11746427 ps
CPU time 0.58 seconds
Started Jun 04 12:51:58 PM PDT 24
Finished Jun 04 12:52:00 PM PDT 24
Peak memory 193960 kb
Host smart-b7514a87-3095-4992-b9b5-c3f633258bff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288957094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.4288957094
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1238554969
Short name T659
Test name
Test status
Simulation time 12100444 ps
CPU time 0.56 seconds
Started Jun 04 12:51:45 PM PDT 24
Finished Jun 04 12:51:47 PM PDT 24
Peak memory 194144 kb
Host smart-7e038ea7-99f1-4601-bf1d-aac5ba0191d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238554969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1238554969
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2057463907
Short name T604
Test name
Test status
Simulation time 11110916 ps
CPU time 0.61 seconds
Started Jun 04 12:51:48 PM PDT 24
Finished Jun 04 12:51:50 PM PDT 24
Peak memory 194112 kb
Host smart-ccf72a65-6f8b-4168-a37b-e53a3d35ff01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057463907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2057463907
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1729954724
Short name T598
Test name
Test status
Simulation time 14718611 ps
CPU time 0.59 seconds
Started Jun 04 12:51:50 PM PDT 24
Finished Jun 04 12:51:52 PM PDT 24
Peak memory 194136 kb
Host smart-03179a71-557b-40aa-a680-58788ba22d8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729954724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1729954724
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2325887358
Short name T646
Test name
Test status
Simulation time 12962894 ps
CPU time 0.59 seconds
Started Jun 04 12:51:50 PM PDT 24
Finished Jun 04 12:51:52 PM PDT 24
Peak memory 194220 kb
Host smart-7aa36240-9146-401d-9843-aeb260f2c44e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325887358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2325887358
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1662330663
Short name T721
Test name
Test status
Simulation time 43664551 ps
CPU time 0.55 seconds
Started Jun 04 12:51:47 PM PDT 24
Finished Jun 04 12:51:50 PM PDT 24
Peak memory 194040 kb
Host smart-be92dbb8-6651-4155-a704-f0443c745cf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662330663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1662330663
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1415483027
Short name T57
Test name
Test status
Simulation time 456644781 ps
CPU time 8.99 seconds
Started Jun 04 12:51:33 PM PDT 24
Finished Jun 04 12:51:44 PM PDT 24
Peak memory 198868 kb
Host smart-88e558a3-aa2f-4faf-889a-36a8d08bca85
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415483027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1415483027
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.4217141510
Short name T670
Test name
Test status
Simulation time 230640762 ps
CPU time 5.3 seconds
Started Jun 04 12:51:37 PM PDT 24
Finished Jun 04 12:51:44 PM PDT 24
Peak memory 199192 kb
Host smart-ea00c48b-462c-416d-aa27-e39ef8ac60cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217141510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.4217141510
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.361492210
Short name T697
Test name
Test status
Simulation time 31343118 ps
CPU time 0.93 seconds
Started Jun 04 12:51:31 PM PDT 24
Finished Jun 04 12:51:33 PM PDT 24
Peak memory 198420 kb
Host smart-6101151b-5ed5-4759-88d7-0165440127f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361492210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.361492210
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.223760030
Short name T635
Test name
Test status
Simulation time 245425805 ps
CPU time 1.78 seconds
Started Jun 04 12:51:33 PM PDT 24
Finished Jun 04 12:51:37 PM PDT 24
Peak memory 199376 kb
Host smart-ad897075-d74b-4fba-9ae7-fdb495c0770a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223760030 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.223760030
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1597426887
Short name T93
Test name
Test status
Simulation time 15607889 ps
CPU time 0.7 seconds
Started Jun 04 12:51:32 PM PDT 24
Finished Jun 04 12:51:35 PM PDT 24
Peak memory 197116 kb
Host smart-365ccaf4-0ad2-4a8b-93a3-ac29d2d8c200
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597426887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1597426887
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2949723989
Short name T79
Test name
Test status
Simulation time 56499416 ps
CPU time 0.63 seconds
Started Jun 04 12:51:43 PM PDT 24
Finished Jun 04 12:51:45 PM PDT 24
Peak memory 194184 kb
Host smart-bdc26b63-5448-4fa7-a685-fc07dbfececb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949723989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2949723989
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1525965304
Short name T656
Test name
Test status
Simulation time 25276535 ps
CPU time 1.15 seconds
Started Jun 04 12:51:32 PM PDT 24
Finished Jun 04 12:51:35 PM PDT 24
Peak memory 199124 kb
Host smart-85be987f-8347-419b-a81e-4799241cfb26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525965304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1525965304
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1753239007
Short name T694
Test name
Test status
Simulation time 50941156 ps
CPU time 2.01 seconds
Started Jun 04 12:51:32 PM PDT 24
Finished Jun 04 12:51:36 PM PDT 24
Peak memory 199464 kb
Host smart-96553560-8f1e-4b83-804f-4f4293134bee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753239007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1753239007
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3892964930
Short name T117
Test name
Test status
Simulation time 50900463 ps
CPU time 1.78 seconds
Started Jun 04 12:51:32 PM PDT 24
Finished Jun 04 12:51:36 PM PDT 24
Peak memory 199380 kb
Host smart-60336ce7-5e74-414a-a188-a61b672a2a8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892964930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3892964930
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.3367926413
Short name T639
Test name
Test status
Simulation time 16225541 ps
CPU time 0.63 seconds
Started Jun 04 12:51:44 PM PDT 24
Finished Jun 04 12:51:46 PM PDT 24
Peak memory 194416 kb
Host smart-6da12a7b-89db-4e02-b31f-d38ea1e9525c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367926413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3367926413
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1134489211
Short name T684
Test name
Test status
Simulation time 42713227 ps
CPU time 0.57 seconds
Started Jun 04 12:51:46 PM PDT 24
Finished Jun 04 12:51:48 PM PDT 24
Peak memory 194144 kb
Host smart-423e2759-41f0-4f0c-81d1-45f62165a7b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134489211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1134489211
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2329196207
Short name T618
Test name
Test status
Simulation time 15801159 ps
CPU time 0.6 seconds
Started Jun 04 12:51:53 PM PDT 24
Finished Jun 04 12:51:55 PM PDT 24
Peak memory 194100 kb
Host smart-d37d8b37-bab7-480f-9c75-420a74ebedc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329196207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2329196207
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.11868179
Short name T612
Test name
Test status
Simulation time 28923883 ps
CPU time 0.63 seconds
Started Jun 04 12:51:50 PM PDT 24
Finished Jun 04 12:51:52 PM PDT 24
Peak memory 194112 kb
Host smart-d71fe6ec-4096-4098-aee7-f2e77171bfcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11868179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.11868179
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3580925871
Short name T597
Test name
Test status
Simulation time 25874209 ps
CPU time 0.58 seconds
Started Jun 04 12:51:46 PM PDT 24
Finished Jun 04 12:51:48 PM PDT 24
Peak memory 194116 kb
Host smart-9eba8cbd-e796-4928-b5f0-f93cf2a1a783
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580925871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3580925871
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.353821473
Short name T610
Test name
Test status
Simulation time 22132976 ps
CPU time 0.57 seconds
Started Jun 04 12:51:46 PM PDT 24
Finished Jun 04 12:51:48 PM PDT 24
Peak memory 194000 kb
Host smart-3822e3cc-c000-499b-9214-0456e56c7b19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353821473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.353821473
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.455241609
Short name T617
Test name
Test status
Simulation time 45372089 ps
CPU time 0.61 seconds
Started Jun 04 12:51:46 PM PDT 24
Finished Jun 04 12:51:48 PM PDT 24
Peak memory 194116 kb
Host smart-90668573-7a68-4ee4-82a9-0b91e32be6f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455241609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.455241609
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.196963701
Short name T667
Test name
Test status
Simulation time 141846768 ps
CPU time 0.6 seconds
Started Jun 04 12:51:44 PM PDT 24
Finished Jun 04 12:51:46 PM PDT 24
Peak memory 194188 kb
Host smart-b2e04b7d-1f03-4cfe-9e4c-fdb3aba91eb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196963701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.196963701
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2170583474
Short name T633
Test name
Test status
Simulation time 20672403 ps
CPU time 0.59 seconds
Started Jun 04 12:51:46 PM PDT 24
Finished Jun 04 12:51:48 PM PDT 24
Peak memory 194144 kb
Host smart-356e6b20-ec05-4d1f-8844-60c12095929a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170583474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2170583474
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2241470985
Short name T664
Test name
Test status
Simulation time 21554503 ps
CPU time 0.59 seconds
Started Jun 04 12:51:46 PM PDT 24
Finished Jun 04 12:51:48 PM PDT 24
Peak memory 194136 kb
Host smart-d9bbc673-244a-49b6-92b5-2654622a751a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241470985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2241470985
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2619536741
Short name T687
Test name
Test status
Simulation time 248414092 ps
CPU time 2.39 seconds
Started Jun 04 12:51:31 PM PDT 24
Finished Jun 04 12:51:35 PM PDT 24
Peak memory 207512 kb
Host smart-38a32d65-c960-48d6-a99d-565c0cb89988
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619536741 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2619536741
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.888551725
Short name T689
Test name
Test status
Simulation time 56394361 ps
CPU time 0.95 seconds
Started Jun 04 12:51:36 PM PDT 24
Finished Jun 04 12:51:38 PM PDT 24
Peak memory 198636 kb
Host smart-b9a2c0d8-b6ba-4feb-b9e9-53d2cc6a27cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888551725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.888551725
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2953753659
Short name T674
Test name
Test status
Simulation time 18118183 ps
CPU time 0.61 seconds
Started Jun 04 12:51:36 PM PDT 24
Finished Jun 04 12:51:39 PM PDT 24
Peak memory 194008 kb
Host smart-d21ca9b6-d5fe-4cd3-82ad-56af7b180ed5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953753659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2953753659
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1607278769
Short name T700
Test name
Test status
Simulation time 210969890 ps
CPU time 2.13 seconds
Started Jun 04 12:51:33 PM PDT 24
Finished Jun 04 12:51:37 PM PDT 24
Peak memory 199364 kb
Host smart-906854ec-c084-475d-9638-7af99c9f50c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607278769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1607278769
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3929845368
Short name T631
Test name
Test status
Simulation time 183489983 ps
CPU time 2.16 seconds
Started Jun 04 12:51:39 PM PDT 24
Finished Jun 04 12:51:42 PM PDT 24
Peak memory 199376 kb
Host smart-27276486-dc11-4050-8943-9b4b91f642c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929845368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3929845368
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.171529512
Short name T116
Test name
Test status
Simulation time 130341099 ps
CPU time 3.91 seconds
Started Jun 04 12:51:33 PM PDT 24
Finished Jun 04 12:51:39 PM PDT 24
Peak memory 199300 kb
Host smart-3050be99-2808-4f69-9605-8a2c0b9cb0b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171529512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.171529512
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1077797269
Short name T61
Test name
Test status
Simulation time 56381287 ps
CPU time 1.04 seconds
Started Jun 04 12:51:35 PM PDT 24
Finished Jun 04 12:51:38 PM PDT 24
Peak memory 199228 kb
Host smart-3571a378-cabd-430a-a09a-fb054d9ec813
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077797269 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1077797269
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2230301061
Short name T596
Test name
Test status
Simulation time 110074710 ps
CPU time 0.84 seconds
Started Jun 04 12:51:37 PM PDT 24
Finished Jun 04 12:51:39 PM PDT 24
Peak memory 199112 kb
Host smart-6f06b2c1-ac58-4a9a-b2bd-2510080fff5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230301061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2230301061
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.303967770
Short name T632
Test name
Test status
Simulation time 13056147 ps
CPU time 0.6 seconds
Started Jun 04 12:51:33 PM PDT 24
Finished Jun 04 12:51:36 PM PDT 24
Peak memory 194156 kb
Host smart-26877edc-dde5-4ef0-bb2d-2d77a715abdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303967770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.303967770
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.4270940196
Short name T704
Test name
Test status
Simulation time 133029807 ps
CPU time 1.67 seconds
Started Jun 04 12:51:36 PM PDT 24
Finished Jun 04 12:51:39 PM PDT 24
Peak memory 199228 kb
Host smart-cfb7505e-4d67-41ab-a8b9-253bff1cff22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270940196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.4270940196
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3257541479
Short name T60
Test name
Test status
Simulation time 43030746 ps
CPU time 2.24 seconds
Started Jun 04 12:51:32 PM PDT 24
Finished Jun 04 12:51:36 PM PDT 24
Peak memory 199260 kb
Host smart-c855ef5f-5b09-47f5-8937-1705e6a79a49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257541479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3257541479
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3804434518
Short name T698
Test name
Test status
Simulation time 307377214 ps
CPU time 1.72 seconds
Started Jun 04 12:51:33 PM PDT 24
Finished Jun 04 12:51:37 PM PDT 24
Peak memory 199372 kb
Host smart-ec92e0a4-7ff2-4b61-80ac-558d1cb243fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804434518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3804434518
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3176734917
Short name T614
Test name
Test status
Simulation time 235026937 ps
CPU time 1.83 seconds
Started Jun 04 12:51:36 PM PDT 24
Finished Jun 04 12:51:39 PM PDT 24
Peak memory 199384 kb
Host smart-e01fe89d-bce3-4024-8872-45363f98bdce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176734917 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.3176734917
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3722300618
Short name T641
Test name
Test status
Simulation time 74356574 ps
CPU time 0.82 seconds
Started Jun 04 12:51:36 PM PDT 24
Finished Jun 04 12:51:38 PM PDT 24
Peak memory 198368 kb
Host smart-42cdba84-4e62-4278-85c2-4c573c15d90c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722300618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3722300618
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.3471274259
Short name T714
Test name
Test status
Simulation time 11277910 ps
CPU time 0.59 seconds
Started Jun 04 12:51:36 PM PDT 24
Finished Jun 04 12:51:39 PM PDT 24
Peak memory 193944 kb
Host smart-81c24bd3-cd9b-4ecc-8c73-ead772611316
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471274259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3471274259
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2722188983
Short name T723
Test name
Test status
Simulation time 86727756 ps
CPU time 1.96 seconds
Started Jun 04 12:51:37 PM PDT 24
Finished Jun 04 12:51:41 PM PDT 24
Peak memory 199392 kb
Host smart-6d50b639-2ac4-4474-b21c-f9b66fb9994d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722188983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2722188983
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.891399275
Short name T718
Test name
Test status
Simulation time 33908642 ps
CPU time 1.74 seconds
Started Jun 04 12:51:34 PM PDT 24
Finished Jun 04 12:51:38 PM PDT 24
Peak memory 199432 kb
Host smart-50b2f271-b575-41f3-ae8d-89354ab3f403
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891399275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.891399275
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1094446693
Short name T120
Test name
Test status
Simulation time 1106570995 ps
CPU time 4.92 seconds
Started Jun 04 12:51:33 PM PDT 24
Finished Jun 04 12:51:41 PM PDT 24
Peak memory 199372 kb
Host smart-4a475947-f09c-46fc-aef3-cb98ea22cdf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094446693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1094446693
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.517960592
Short name T607
Test name
Test status
Simulation time 328353073 ps
CPU time 2.07 seconds
Started Jun 04 12:51:37 PM PDT 24
Finished Jun 04 12:51:40 PM PDT 24
Peak memory 199244 kb
Host smart-cb1a9278-4f3a-4707-ab7d-64d58b0da854
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517960592 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.517960592
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2365537732
Short name T653
Test name
Test status
Simulation time 155330789 ps
CPU time 0.71 seconds
Started Jun 04 12:51:33 PM PDT 24
Finished Jun 04 12:51:36 PM PDT 24
Peak memory 196732 kb
Host smart-8dc1fdaf-72a1-4040-bb92-decd9375e050
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365537732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2365537732
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.4277062451
Short name T708
Test name
Test status
Simulation time 18174451 ps
CPU time 0.64 seconds
Started Jun 04 12:51:36 PM PDT 24
Finished Jun 04 12:51:39 PM PDT 24
Peak memory 194104 kb
Host smart-303a609e-b5d3-4f97-94dd-e7f174556033
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277062451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.4277062451
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1724031130
Short name T629
Test name
Test status
Simulation time 365534372 ps
CPU time 1.47 seconds
Started Jun 04 12:51:33 PM PDT 24
Finished Jun 04 12:51:37 PM PDT 24
Peak memory 198544 kb
Host smart-986b7179-0057-48ce-8f85-8ac13d923dfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724031130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1724031130
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.4099126950
Short name T650
Test name
Test status
Simulation time 79494415 ps
CPU time 4.06 seconds
Started Jun 04 12:51:35 PM PDT 24
Finished Jun 04 12:51:41 PM PDT 24
Peak memory 199380 kb
Host smart-06869973-309a-4c64-9116-314f10f6133d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099126950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.4099126950
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2339237055
Short name T121
Test name
Test status
Simulation time 581364632 ps
CPU time 1.98 seconds
Started Jun 04 12:51:33 PM PDT 24
Finished Jun 04 12:51:37 PM PDT 24
Peak memory 199364 kb
Host smart-e6a69d5b-6646-4e95-a3d0-18141f428bda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339237055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.2339237055
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3128447398
Short name T699
Test name
Test status
Simulation time 103720436311 ps
CPU time 420.87 seconds
Started Jun 04 12:51:46 PM PDT 24
Finished Jun 04 12:58:48 PM PDT 24
Peak memory 214856 kb
Host smart-5e86f96b-2abf-44aa-8c56-6914b4dd258c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128447398 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3128447398
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.981466124
Short name T88
Test name
Test status
Simulation time 154637775 ps
CPU time 0.8 seconds
Started Jun 04 12:51:41 PM PDT 24
Finished Jun 04 12:51:43 PM PDT 24
Peak memory 198288 kb
Host smart-902f3042-c94e-42fc-987a-ba3430871153
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981466124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.981466124
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.3543088502
Short name T609
Test name
Test status
Simulation time 52286537 ps
CPU time 0.6 seconds
Started Jun 04 12:51:39 PM PDT 24
Finished Jun 04 12:51:41 PM PDT 24
Peak memory 194096 kb
Host smart-207657d3-06f1-4edd-a618-6cbbbaac6af8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543088502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3543088502
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.486257525
Short name T645
Test name
Test status
Simulation time 352105004 ps
CPU time 1.2 seconds
Started Jun 04 12:51:39 PM PDT 24
Finished Jun 04 12:51:41 PM PDT 24
Peak memory 198852 kb
Host smart-481840da-f90d-475f-8e37-036a8de2a713
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486257525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.486257525
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.179692149
Short name T605
Test name
Test status
Simulation time 35742122 ps
CPU time 1.87 seconds
Started Jun 04 12:51:46 PM PDT 24
Finished Jun 04 12:51:49 PM PDT 24
Peak memory 199340 kb
Host smart-8725d358-1f47-464a-af58-88aabf7459d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179692149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.179692149
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2714730630
Short name T677
Test name
Test status
Simulation time 206441236 ps
CPU time 1.85 seconds
Started Jun 04 12:51:40 PM PDT 24
Finished Jun 04 12:51:43 PM PDT 24
Peak memory 199416 kb
Host smart-69b02e58-bc47-4f22-bba5-ed4f0436e0a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714730630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2714730630
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1595168537
Short name T332
Test name
Test status
Simulation time 12968888 ps
CPU time 0.57 seconds
Started Jun 04 12:27:16 PM PDT 24
Finished Jun 04 12:27:18 PM PDT 24
Peak memory 194788 kb
Host smart-b5b499b1-0bb1-4fe1-bdb2-2342313756a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595168537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1595168537
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.521794630
Short name T487
Test name
Test status
Simulation time 3429779613 ps
CPU time 40.79 seconds
Started Jun 04 12:27:10 PM PDT 24
Finished Jun 04 12:27:53 PM PDT 24
Peak memory 224472 kb
Host smart-3efad1ce-f0ae-42ed-bac2-817c0fbd515c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=521794630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.521794630
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.1113950484
Short name T184
Test name
Test status
Simulation time 277454575 ps
CPU time 5.47 seconds
Started Jun 04 12:27:06 PM PDT 24
Finished Jun 04 12:27:13 PM PDT 24
Peak memory 199896 kb
Host smart-d20a8bd0-2f9c-4fdb-a994-ba0fa6022cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113950484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1113950484
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1370674093
Short name T500
Test name
Test status
Simulation time 7471980234 ps
CPU time 258.78 seconds
Started Jun 04 12:27:10 PM PDT 24
Finished Jun 04 12:31:30 PM PDT 24
Peak memory 466836 kb
Host smart-a7abb7fc-1f6d-4063-9d06-c4345b35f9bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1370674093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1370674093
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2027216400
Short name T31
Test name
Test status
Simulation time 13416268306 ps
CPU time 162.44 seconds
Started Jun 04 12:27:28 PM PDT 24
Finished Jun 04 12:30:12 PM PDT 24
Peak memory 199904 kb
Host smart-6ddf5d21-a962-4025-a43f-20f57db5758c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027216400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2027216400
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.775724298
Short name T492
Test name
Test status
Simulation time 7020489894 ps
CPU time 99.95 seconds
Started Jun 04 12:27:03 PM PDT 24
Finished Jun 04 12:28:44 PM PDT 24
Peak memory 199992 kb
Host smart-9b8dabba-5df8-4347-86ef-746ccca25d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775724298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.775724298
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.3395413913
Short name T317
Test name
Test status
Simulation time 194941192 ps
CPU time 5.94 seconds
Started Jun 04 12:27:07 PM PDT 24
Finished Jun 04 12:27:14 PM PDT 24
Peak memory 199836 kb
Host smart-67b8b5b7-b366-44ff-91f2-85e6895de949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395413913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3395413913
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.1816847908
Short name T143
Test name
Test status
Simulation time 32986498 ps
CPU time 1.26 seconds
Started Jun 04 12:27:27 PM PDT 24
Finished Jun 04 12:27:31 PM PDT 24
Peak memory 199760 kb
Host smart-72131e5e-1d90-4bb1-b5af-3549f193556d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816847908 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.1816847908
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.3200374250
Short name T413
Test name
Test status
Simulation time 24191041301 ps
CPU time 369.87 seconds
Started Jun 04 12:27:28 PM PDT 24
Finished Jun 04 12:33:40 PM PDT 24
Peak memory 199912 kb
Host smart-f5abe11c-3235-4a6b-b38a-7a624602df28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200374250 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.3200374250
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.2735646736
Short name T523
Test name
Test status
Simulation time 29660028692 ps
CPU time 69.82 seconds
Started Jun 04 12:27:14 PM PDT 24
Finished Jun 04 12:28:25 PM PDT 24
Peak memory 199920 kb
Host smart-83cecda4-32d8-4e7d-acf0-f5e5e4da5179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735646736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.2735646736
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.769780321
Short name T469
Test name
Test status
Simulation time 11124833 ps
CPU time 0.57 seconds
Started Jun 04 12:27:17 PM PDT 24
Finished Jun 04 12:27:19 PM PDT 24
Peak memory 195504 kb
Host smart-a971ee61-1f17-4c42-967a-36f0fade40e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769780321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.769780321
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3527466200
Short name T286
Test name
Test status
Simulation time 324265612 ps
CPU time 18.55 seconds
Started Jun 04 12:27:16 PM PDT 24
Finished Jun 04 12:27:37 PM PDT 24
Peak memory 232636 kb
Host smart-b914e6f1-66b1-4512-a824-43fd4957d038
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3527466200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3527466200
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.414483030
Short name T268
Test name
Test status
Simulation time 8036662991 ps
CPU time 61.12 seconds
Started Jun 04 12:27:16 PM PDT 24
Finished Jun 04 12:28:19 PM PDT 24
Peak memory 199976 kb
Host smart-896653ea-f05a-4859-bf7d-96ffc3a15386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414483030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.414483030
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2543210883
Short name T49
Test name
Test status
Simulation time 8354400232 ps
CPU time 490.21 seconds
Started Jun 04 12:27:14 PM PDT 24
Finished Jun 04 12:35:26 PM PDT 24
Peak memory 629872 kb
Host smart-78708b8b-80b7-44bb-b351-9f3f840d4e8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2543210883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2543210883
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.86690754
Short name T593
Test name
Test status
Simulation time 17446162916 ps
CPU time 119.12 seconds
Started Jun 04 12:27:19 PM PDT 24
Finished Jun 04 12:29:19 PM PDT 24
Peak memory 199972 kb
Host smart-bf3338fb-5325-4528-b656-b4ea313ebc87
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86690754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.86690754
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2825407555
Short name T517
Test name
Test status
Simulation time 40123029686 ps
CPU time 88.58 seconds
Started Jun 04 12:27:14 PM PDT 24
Finished Jun 04 12:28:44 PM PDT 24
Peak memory 199908 kb
Host smart-0fe46df6-6ae0-48df-827f-bd20d3c7851a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825407555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2825407555
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3405339582
Short name T24
Test name
Test status
Simulation time 82138133 ps
CPU time 1 seconds
Started Jun 04 12:27:17 PM PDT 24
Finished Jun 04 12:27:19 PM PDT 24
Peak memory 219428 kb
Host smart-b3287c9c-8360-480a-909c-942b416e51c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405339582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3405339582
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3777300920
Short name T359
Test name
Test status
Simulation time 935051926 ps
CPU time 5.96 seconds
Started Jun 04 12:27:18 PM PDT 24
Finished Jun 04 12:27:25 PM PDT 24
Peak memory 200016 kb
Host smart-a01c41ec-7d94-427c-bcdf-ca07bd7c0be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777300920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3777300920
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1619375766
Short name T501
Test name
Test status
Simulation time 627047878 ps
CPU time 30.83 seconds
Started Jun 04 12:27:16 PM PDT 24
Finished Jun 04 12:27:49 PM PDT 24
Peak memory 199912 kb
Host smart-57f00ffc-020e-4c75-924c-d6b6141cd69f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619375766 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1619375766
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.1047385869
Short name T361
Test name
Test status
Simulation time 66972308 ps
CPU time 1.37 seconds
Started Jun 04 12:27:19 PM PDT 24
Finished Jun 04 12:27:21 PM PDT 24
Peak memory 200032 kb
Host smart-7bc891f6-d9ae-4ff6-9fe4-8502cd1652c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047385869 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.1047385869
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.491736784
Short name T586
Test name
Test status
Simulation time 169445941305 ps
CPU time 464.24 seconds
Started Jun 04 12:27:15 PM PDT 24
Finished Jun 04 12:35:01 PM PDT 24
Peak memory 199900 kb
Host smart-81d015dd-a838-4245-be14-1122e98603c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491736784 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.491736784
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1963710962
Short name T235
Test name
Test status
Simulation time 2664342792 ps
CPU time 46.22 seconds
Started Jun 04 12:27:14 PM PDT 24
Finished Jun 04 12:28:02 PM PDT 24
Peak memory 200008 kb
Host smart-87f7e00a-670b-4a2c-b66d-757da950758f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963710962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1963710962
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.746378484
Short name T280
Test name
Test status
Simulation time 38579851 ps
CPU time 0.56 seconds
Started Jun 04 12:27:42 PM PDT 24
Finished Jun 04 12:27:44 PM PDT 24
Peak memory 194780 kb
Host smart-a67010a0-8d5c-4c1d-b96b-e84bc2ae82a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746378484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.746378484
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1961554197
Short name T15
Test name
Test status
Simulation time 731147835 ps
CPU time 33.21 seconds
Started Jun 04 12:27:38 PM PDT 24
Finished Jun 04 12:28:12 PM PDT 24
Peak memory 208052 kb
Host smart-0870e268-a561-413f-845c-83c6a86649a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1961554197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1961554197
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.18697332
Short name T502
Test name
Test status
Simulation time 12204700777 ps
CPU time 267.94 seconds
Started Jun 04 12:27:38 PM PDT 24
Finished Jun 04 12:32:07 PM PDT 24
Peak memory 651632 kb
Host smart-35a0255f-9dca-43f2-9747-f3cbca13a90b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=18697332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.18697332
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.1888126779
Short name T490
Test name
Test status
Simulation time 2640593639 ps
CPU time 131.4 seconds
Started Jun 04 12:27:33 PM PDT 24
Finished Jun 04 12:29:46 PM PDT 24
Peak memory 199904 kb
Host smart-502d3f42-a1c2-4098-b59e-058a416924c1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888126779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1888126779
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.1080567619
Short name T22
Test name
Test status
Simulation time 13005603266 ps
CPU time 61.8 seconds
Started Jun 04 12:27:36 PM PDT 24
Finished Jun 04 12:28:39 PM PDT 24
Peak memory 200036 kb
Host smart-51b8bdbf-b05b-434a-9c59-f966041830cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080567619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1080567619
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.2709699989
Short name T176
Test name
Test status
Simulation time 28979243 ps
CPU time 1.24 seconds
Started Jun 04 12:27:34 PM PDT 24
Finished Jun 04 12:27:36 PM PDT 24
Peak memory 199776 kb
Host smart-dce1a2a4-bc81-4178-a25a-95061e943805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709699989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.2709699989
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3272905475
Short name T326
Test name
Test status
Simulation time 4680702813 ps
CPU time 241.89 seconds
Started Jun 04 12:27:38 PM PDT 24
Finished Jun 04 12:31:41 PM PDT 24
Peak memory 216416 kb
Host smart-46bf6913-a10c-4f11-847b-33613a6f68ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272905475 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3272905475
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.3379076741
Short name T380
Test name
Test status
Simulation time 101655451 ps
CPU time 1.18 seconds
Started Jun 04 12:27:33 PM PDT 24
Finished Jun 04 12:27:35 PM PDT 24
Peak memory 199888 kb
Host smart-c0276fa4-d880-468d-a0a4-f44e29f06f0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379076741 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.3379076741
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.4159445411
Short name T335
Test name
Test status
Simulation time 343255352116 ps
CPU time 492.66 seconds
Started Jun 04 12:27:36 PM PDT 24
Finished Jun 04 12:35:50 PM PDT 24
Peak memory 199848 kb
Host smart-3a47250f-27fb-4b3c-bc3d-65dca62e9954
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159445411 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.4159445411
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2643737432
Short name T401
Test name
Test status
Simulation time 10543750065 ps
CPU time 13.57 seconds
Started Jun 04 12:27:41 PM PDT 24
Finished Jun 04 12:27:56 PM PDT 24
Peak memory 200012 kb
Host smart-beba0824-399d-40e2-a7b3-0bded0fe9214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643737432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2643737432
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.723124225
Short name T133
Test name
Test status
Simulation time 12642570 ps
CPU time 0.58 seconds
Started Jun 04 12:27:34 PM PDT 24
Finished Jun 04 12:27:36 PM PDT 24
Peak memory 195860 kb
Host smart-1432d985-5653-41fa-bcdd-6c0dcdf7f485
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723124225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.723124225
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.3837657515
Short name T462
Test name
Test status
Simulation time 482269404 ps
CPU time 12.56 seconds
Started Jun 04 12:27:38 PM PDT 24
Finished Jun 04 12:27:52 PM PDT 24
Peak memory 199948 kb
Host smart-c7880802-383c-49a4-b8fb-b9bb98d83620
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3837657515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3837657515
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.236035353
Short name T325
Test name
Test status
Simulation time 1389324629 ps
CPU time 20.96 seconds
Started Jun 04 12:27:36 PM PDT 24
Finished Jun 04 12:27:58 PM PDT 24
Peak memory 199960 kb
Host smart-65fc2e50-0dfe-4898-be5d-b0507b0890e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236035353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.236035353
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.2552867884
Short name T216
Test name
Test status
Simulation time 635012091 ps
CPU time 109.75 seconds
Started Jun 04 12:27:41 PM PDT 24
Finished Jun 04 12:29:32 PM PDT 24
Peak memory 420272 kb
Host smart-8a7ae088-fcbd-4e97-8236-acc5acaef9ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2552867884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2552867884
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2046933296
Short name T250
Test name
Test status
Simulation time 18856375288 ps
CPU time 43.07 seconds
Started Jun 04 12:27:34 PM PDT 24
Finished Jun 04 12:28:18 PM PDT 24
Peak memory 200004 kb
Host smart-444fdad2-44ba-4dfe-ae2a-100ac55b165e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046933296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2046933296
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_smoke.819649525
Short name T314
Test name
Test status
Simulation time 584933231 ps
CPU time 6.52 seconds
Started Jun 04 12:27:33 PM PDT 24
Finished Jun 04 12:27:41 PM PDT 24
Peak memory 199856 kb
Host smart-cb448ea2-e3ec-403e-9da0-6d43d1c08e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819649525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.819649525
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.1381398555
Short name T12
Test name
Test status
Simulation time 63364433382 ps
CPU time 3731.51 seconds
Started Jun 04 12:27:38 PM PDT 24
Finished Jun 04 01:29:51 PM PDT 24
Peak memory 815700 kb
Host smart-eae2fe2b-7b8f-4632-87fc-dde6f7e256c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381398555 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1381398555
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.4255433897
Short name T179
Test name
Test status
Simulation time 118006145 ps
CPU time 1.23 seconds
Started Jun 04 12:27:41 PM PDT 24
Finished Jun 04 12:27:44 PM PDT 24
Peak memory 199944 kb
Host smart-39d3ab5d-54a6-4977-992d-6343b2f729b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255433897 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.4255433897
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.3340095895
Short name T166
Test name
Test status
Simulation time 160898255110 ps
CPU time 512.14 seconds
Started Jun 04 12:27:32 PM PDT 24
Finished Jun 04 12:36:05 PM PDT 24
Peak memory 199968 kb
Host smart-d7e7f216-1762-475f-8e83-2e4852da4cf5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340095895 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.3340095895
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.3747064529
Short name T223
Test name
Test status
Simulation time 336871443 ps
CPU time 20.53 seconds
Started Jun 04 12:27:39 PM PDT 24
Finished Jun 04 12:28:00 PM PDT 24
Peak memory 199928 kb
Host smart-946088b7-c73e-4f74-9a58-ca571f04214e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747064529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3747064529
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.4035643531
Short name T130
Test name
Test status
Simulation time 15463067 ps
CPU time 0.61 seconds
Started Jun 04 12:27:48 PM PDT 24
Finished Jun 04 12:27:50 PM PDT 24
Peak memory 196504 kb
Host smart-601445d3-799d-40af-af85-35710deb2790
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035643531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.4035643531
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.110122084
Short name T218
Test name
Test status
Simulation time 278388477 ps
CPU time 3.08 seconds
Started Jun 04 12:27:37 PM PDT 24
Finished Jun 04 12:27:41 PM PDT 24
Peak memory 199892 kb
Host smart-4398d9f7-6213-4767-85c2-b384cd12dee0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=110122084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.110122084
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.3216857089
Short name T155
Test name
Test status
Simulation time 353188862 ps
CPU time 2.04 seconds
Started Jun 04 12:27:37 PM PDT 24
Finished Jun 04 12:27:40 PM PDT 24
Peak memory 199900 kb
Host smart-63d520f1-4821-4a1d-82c8-a3fe780367a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216857089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.3216857089
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.469242763
Short name T135
Test name
Test status
Simulation time 5352583215 ps
CPU time 229.24 seconds
Started Jun 04 12:27:33 PM PDT 24
Finished Jun 04 12:31:23 PM PDT 24
Peak memory 644860 kb
Host smart-f3a430de-ec62-4e6f-b93b-c8e71a0f0781
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=469242763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.469242763
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1337624945
Short name T131
Test name
Test status
Simulation time 34092053899 ps
CPU time 151.72 seconds
Started Jun 04 12:27:35 PM PDT 24
Finished Jun 04 12:30:08 PM PDT 24
Peak memory 199848 kb
Host smart-957f3191-22d5-45a3-8d07-01f5ff845437
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337624945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1337624945
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.851094012
Short name T484
Test name
Test status
Simulation time 2203149448 ps
CPU time 42.45 seconds
Started Jun 04 12:27:38 PM PDT 24
Finished Jun 04 12:28:22 PM PDT 24
Peak memory 200084 kb
Host smart-d775c9cd-92cc-4b06-96f2-d579244e295f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851094012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.851094012
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.2271962015
Short name T129
Test name
Test status
Simulation time 43562168 ps
CPU time 1.49 seconds
Started Jun 04 12:27:36 PM PDT 24
Finished Jun 04 12:27:39 PM PDT 24
Peak memory 199908 kb
Host smart-c22d503f-8b47-4264-ba8f-66dd59b3d83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271962015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2271962015
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.4015432734
Short name T33
Test name
Test status
Simulation time 20554915 ps
CPU time 0.61 seconds
Started Jun 04 12:27:50 PM PDT 24
Finished Jun 04 12:27:52 PM PDT 24
Peak memory 195520 kb
Host smart-fe9c8e71-d7d8-463c-afa8-1618d643368f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015432734 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.4015432734
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.146208840
Short name T70
Test name
Test status
Simulation time 29592918 ps
CPU time 0.99 seconds
Started Jun 04 12:27:35 PM PDT 24
Finished Jun 04 12:27:37 PM PDT 24
Peak memory 199460 kb
Host smart-29b0ff02-e1e2-43fd-a3e2-9d19ea8ec027
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146208840 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_hmac_vectors.146208840
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.4060462632
Short name T566
Test name
Test status
Simulation time 100006542102 ps
CPU time 455.72 seconds
Started Jun 04 12:27:33 PM PDT 24
Finished Jun 04 12:35:10 PM PDT 24
Peak memory 199856 kb
Host smart-321702b2-d33b-4894-b30b-5cbecbe93e3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060462632 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.4060462632
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3613916392
Short name T257
Test name
Test status
Simulation time 6704648149 ps
CPU time 91.98 seconds
Started Jun 04 12:27:36 PM PDT 24
Finished Jun 04 12:29:09 PM PDT 24
Peak memory 199956 kb
Host smart-ef60040f-fd61-4529-a7f7-070d052aa1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613916392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3613916392
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3826407521
Short name T169
Test name
Test status
Simulation time 425930409 ps
CPU time 5.31 seconds
Started Jun 04 12:27:43 PM PDT 24
Finished Jun 04 12:27:49 PM PDT 24
Peak memory 199852 kb
Host smart-b550cbde-5544-4a3b-8edd-d28d9b3ff653
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3826407521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3826407521
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2989233625
Short name T98
Test name
Test status
Simulation time 4352443934 ps
CPU time 52.61 seconds
Started Jun 04 12:27:44 PM PDT 24
Finished Jun 04 12:28:38 PM PDT 24
Peak memory 199916 kb
Host smart-7c854ba9-70df-4442-b780-0c3bdcf28969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989233625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2989233625
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.4085138567
Short name T146
Test name
Test status
Simulation time 698874276 ps
CPU time 52.67 seconds
Started Jun 04 12:27:47 PM PDT 24
Finished Jun 04 12:28:41 PM PDT 24
Peak memory 316004 kb
Host smart-720fe8d0-d4b6-473c-8514-e4ef2d7d3088
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4085138567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.4085138567
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2732725544
Short name T417
Test name
Test status
Simulation time 532889897 ps
CPU time 7.6 seconds
Started Jun 04 12:27:47 PM PDT 24
Finished Jun 04 12:27:56 PM PDT 24
Peak memory 199788 kb
Host smart-5157b3e8-7e3d-44f1-bb3b-8cab11fc6d48
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732725544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2732725544
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.477123958
Short name T298
Test name
Test status
Simulation time 3952020053 ps
CPU time 28.83 seconds
Started Jun 04 12:27:44 PM PDT 24
Finished Jun 04 12:28:15 PM PDT 24
Peak memory 200092 kb
Host smart-c2d01ce8-da4f-4f84-83f5-925f8ce59422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477123958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.477123958
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.4194752406
Short name T495
Test name
Test status
Simulation time 790565598 ps
CPU time 7.62 seconds
Started Jun 04 12:27:45 PM PDT 24
Finished Jun 04 12:27:55 PM PDT 24
Peak memory 199984 kb
Host smart-f0744fa4-e773-49dd-a14a-73dcb3e093f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194752406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.4194752406
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2288879353
Short name T441
Test name
Test status
Simulation time 63798447445 ps
CPU time 267.99 seconds
Started Jun 04 12:27:44 PM PDT 24
Finished Jun 04 12:32:14 PM PDT 24
Peak memory 224620 kb
Host smart-56dc14a2-788e-4683-a0a8-a85cd50d9920
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288879353 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2288879353
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.1285578842
Short name T346
Test name
Test status
Simulation time 59632323 ps
CPU time 1.34 seconds
Started Jun 04 12:27:45 PM PDT 24
Finished Jun 04 12:27:49 PM PDT 24
Peak memory 198916 kb
Host smart-e1658dd6-9450-4638-bec9-ac977bd51d6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285578842 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.1285578842
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.3550659711
Short name T338
Test name
Test status
Simulation time 294745109421 ps
CPU time 487.4 seconds
Started Jun 04 12:27:46 PM PDT 24
Finished Jun 04 12:35:55 PM PDT 24
Peak memory 199892 kb
Host smart-c273dac9-0089-4255-8f07-f85a5cb1362f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550659711 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.3550659711
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.4042403710
Short name T360
Test name
Test status
Simulation time 3283580449 ps
CPU time 62.86 seconds
Started Jun 04 12:27:44 PM PDT 24
Finished Jun 04 12:28:49 PM PDT 24
Peak memory 199912 kb
Host smart-df2583cc-a230-4717-b8a9-8cdbe4f1158b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042403710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.4042403710
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2941328647
Short name T17
Test name
Test status
Simulation time 38508951 ps
CPU time 0.63 seconds
Started Jun 04 12:27:43 PM PDT 24
Finished Jun 04 12:27:45 PM PDT 24
Peak memory 195392 kb
Host smart-65409e98-cc1c-4031-99b6-5869c35a95f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941328647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2941328647
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.256198271
Short name T206
Test name
Test status
Simulation time 576263291 ps
CPU time 27.26 seconds
Started Jun 04 12:27:45 PM PDT 24
Finished Jun 04 12:28:14 PM PDT 24
Peak memory 223020 kb
Host smart-f150008f-0261-4c3e-8ae2-f5040757d92d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=256198271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.256198271
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3886584182
Short name T496
Test name
Test status
Simulation time 2986430694 ps
CPU time 55.59 seconds
Started Jun 04 12:27:45 PM PDT 24
Finished Jun 04 12:28:43 PM PDT 24
Peak memory 200016 kb
Host smart-955b4c3d-511f-4158-ac0c-eedd624ffdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886584182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3886584182
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.2558617006
Short name T248
Test name
Test status
Simulation time 6963937773 ps
CPU time 430.23 seconds
Started Jun 04 12:27:44 PM PDT 24
Finished Jun 04 12:34:56 PM PDT 24
Peak memory 676876 kb
Host smart-022d0b8d-ffc5-4712-816c-b62ed2e89aef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2558617006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2558617006
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.147681981
Short name T407
Test name
Test status
Simulation time 18573724102 ps
CPU time 193.43 seconds
Started Jun 04 12:27:44 PM PDT 24
Finished Jun 04 12:30:59 PM PDT 24
Peak memory 199956 kb
Host smart-762c3005-055b-4c82-a348-87602fd049ba
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147681981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.147681981
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.775821373
Short name T545
Test name
Test status
Simulation time 7805676317 ps
CPU time 117.61 seconds
Started Jun 04 12:27:48 PM PDT 24
Finished Jun 04 12:29:47 PM PDT 24
Peak memory 200036 kb
Host smart-87195c39-d5d1-49b2-8bc1-3ba87149e3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775821373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.775821373
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.4239278641
Short name T368
Test name
Test status
Simulation time 93324062 ps
CPU time 3.3 seconds
Started Jun 04 12:27:44 PM PDT 24
Finished Jun 04 12:27:49 PM PDT 24
Peak memory 199876 kb
Host smart-faca6f75-fb6b-471b-ba18-3f7d3028753c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239278641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.4239278641
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2999442636
Short name T220
Test name
Test status
Simulation time 51216381350 ps
CPU time 1242.02 seconds
Started Jun 04 12:27:54 PM PDT 24
Finished Jun 04 12:48:38 PM PDT 24
Peak memory 761744 kb
Host smart-672587a1-1dc5-4749-87a3-4c50ce153f2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999442636 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2999442636
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.2518017137
Short name T372
Test name
Test status
Simulation time 179017290 ps
CPU time 1.06 seconds
Started Jun 04 12:27:44 PM PDT 24
Finished Jun 04 12:27:47 PM PDT 24
Peak memory 199612 kb
Host smart-8830d2a6-a27d-4fd8-b3de-ff0946e569f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518017137 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.2518017137
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.1144517452
Short name T48
Test name
Test status
Simulation time 39792611247 ps
CPU time 488.38 seconds
Started Jun 04 12:27:44 PM PDT 24
Finished Jun 04 12:35:54 PM PDT 24
Peak memory 200100 kb
Host smart-3e90b768-fb52-4ab9-b05f-b9d2ba0ebefb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144517452 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.1144517452
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.927063738
Short name T399
Test name
Test status
Simulation time 2446629054 ps
CPU time 88.77 seconds
Started Jun 04 12:27:44 PM PDT 24
Finished Jun 04 12:29:15 PM PDT 24
Peak memory 199956 kb
Host smart-15b85fd2-bca5-4e80-88e4-8ccc8ff68fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927063738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.927063738
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.2144632869
Short name T299
Test name
Test status
Simulation time 11550087 ps
CPU time 0.58 seconds
Started Jun 04 12:27:44 PM PDT 24
Finished Jun 04 12:27:47 PM PDT 24
Peak memory 196496 kb
Host smart-114e00a5-e7ab-4924-bf9c-639aac711c36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144632869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2144632869
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.2752270121
Short name T219
Test name
Test status
Simulation time 7186660054 ps
CPU time 28.89 seconds
Started Jun 04 12:27:44 PM PDT 24
Finished Jun 04 12:28:15 PM PDT 24
Peak memory 227512 kb
Host smart-44613f58-3a62-4212-8b00-72e29bb46b5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2752270121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2752270121
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3816074987
Short name T454
Test name
Test status
Simulation time 2691693643 ps
CPU time 38.45 seconds
Started Jun 04 12:27:46 PM PDT 24
Finished Jun 04 12:28:26 PM PDT 24
Peak memory 200048 kb
Host smart-8240cadd-3146-4a61-aa9f-f595a3e51846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816074987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3816074987
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.379890213
Short name T451
Test name
Test status
Simulation time 2527122555 ps
CPU time 591.68 seconds
Started Jun 04 12:27:49 PM PDT 24
Finished Jun 04 12:37:42 PM PDT 24
Peak memory 717832 kb
Host smart-8218f399-5dba-4031-a9a0-59e539a43aec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=379890213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.379890213
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.4118387023
Short name T161
Test name
Test status
Simulation time 13183597895 ps
CPU time 166.78 seconds
Started Jun 04 12:27:51 PM PDT 24
Finished Jun 04 12:30:39 PM PDT 24
Peak memory 199984 kb
Host smart-2e0c5da6-ff7f-46ea-bfbc-24f942f58e0f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118387023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.4118387023
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1133619399
Short name T284
Test name
Test status
Simulation time 136244560 ps
CPU time 4.23 seconds
Started Jun 04 12:27:50 PM PDT 24
Finished Jun 04 12:27:55 PM PDT 24
Peak memory 199944 kb
Host smart-ae4a70ff-6946-4586-9c22-38234dcf4a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133619399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1133619399
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.29542188
Short name T382
Test name
Test status
Simulation time 331861618 ps
CPU time 4.81 seconds
Started Jun 04 12:27:48 PM PDT 24
Finished Jun 04 12:27:54 PM PDT 24
Peak memory 199972 kb
Host smart-2e53fdbc-071b-46ca-aed7-58cf0c8304fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29542188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.29542188
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.185060334
Short name T177
Test name
Test status
Simulation time 54763300973 ps
CPU time 1485.31 seconds
Started Jun 04 12:27:43 PM PDT 24
Finished Jun 04 12:52:30 PM PDT 24
Peak memory 816396 kb
Host smart-314dfe69-e44d-4af1-b342-51a07dd0234f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185060334 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.185060334
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.3710586509
Short name T403
Test name
Test status
Simulation time 251843886 ps
CPU time 1.21 seconds
Started Jun 04 12:27:50 PM PDT 24
Finished Jun 04 12:27:52 PM PDT 24
Peak memory 199964 kb
Host smart-14dcb2a9-5079-47a1-924f-3a60f11ddd87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710586509 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.3710586509
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.2335595048
Short name T511
Test name
Test status
Simulation time 121139551298 ps
CPU time 538.31 seconds
Started Jun 04 12:27:47 PM PDT 24
Finished Jun 04 12:36:47 PM PDT 24
Peak memory 199852 kb
Host smart-92ab8a1f-31a9-4a7e-9a71-e05ad6db2e8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335595048 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.2335595048
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.524130594
Short name T244
Test name
Test status
Simulation time 19353022011 ps
CPU time 89.82 seconds
Started Jun 04 12:27:46 PM PDT 24
Finished Jun 04 12:29:18 PM PDT 24
Peak memory 200072 kb
Host smart-4b89c69d-562d-4c2e-bbdd-ee2d426ec2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524130594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.524130594
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.996229058
Short name T504
Test name
Test status
Simulation time 11562375 ps
CPU time 0.58 seconds
Started Jun 04 12:27:44 PM PDT 24
Finished Jun 04 12:27:46 PM PDT 24
Peak memory 195860 kb
Host smart-aed41587-52b4-489a-a95b-eef443111555
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996229058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.996229058
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.661170754
Short name T313
Test name
Test status
Simulation time 2079798365 ps
CPU time 24.33 seconds
Started Jun 04 12:27:43 PM PDT 24
Finished Jun 04 12:28:09 PM PDT 24
Peak memory 199836 kb
Host smart-ce5e44e0-0f12-4b3c-8cab-37650b497b82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=661170754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.661170754
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.4160234279
Short name T350
Test name
Test status
Simulation time 1018334946 ps
CPU time 26.66 seconds
Started Jun 04 12:27:46 PM PDT 24
Finished Jun 04 12:28:14 PM PDT 24
Peak memory 199892 kb
Host smart-057f27d6-f4bc-406b-80be-f9f6233be8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160234279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.4160234279
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2188519912
Short name T318
Test name
Test status
Simulation time 11464157003 ps
CPU time 680.99 seconds
Started Jun 04 12:27:45 PM PDT 24
Finished Jun 04 12:39:08 PM PDT 24
Peak memory 679080 kb
Host smart-e1779af1-586b-4433-be59-14d6b9faad3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2188519912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2188519912
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.2142981801
Short name T203
Test name
Test status
Simulation time 2208573324 ps
CPU time 6.75 seconds
Started Jun 04 12:27:43 PM PDT 24
Finished Jun 04 12:27:51 PM PDT 24
Peak memory 199832 kb
Host smart-c271b38b-082f-4f40-bba4-0e05dfff0a95
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142981801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2142981801
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1750188075
Short name T188
Test name
Test status
Simulation time 15294862922 ps
CPU time 63.78 seconds
Started Jun 04 12:27:44 PM PDT 24
Finished Jun 04 12:28:49 PM PDT 24
Peak memory 199980 kb
Host smart-1f559990-3de8-4521-bb52-5953aa7d0943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750188075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1750188075
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.14808710
Short name T172
Test name
Test status
Simulation time 226120567 ps
CPU time 1.25 seconds
Started Jun 04 12:27:44 PM PDT 24
Finished Jun 04 12:27:47 PM PDT 24
Peak memory 199728 kb
Host smart-c2fb94b6-09d8-47a2-bf92-6cc465704d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14808710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.14808710
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3583217933
Short name T63
Test name
Test status
Simulation time 41264989753 ps
CPU time 2359.09 seconds
Started Jun 04 12:27:45 PM PDT 24
Finished Jun 04 01:07:06 PM PDT 24
Peak memory 823136 kb
Host smart-7b5ec762-2c72-4fb1-a426-548e541dd79e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583217933 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3583217933
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.607293818
Short name T552
Test name
Test status
Simulation time 33753107 ps
CPU time 1.28 seconds
Started Jun 04 12:27:47 PM PDT 24
Finished Jun 04 12:27:50 PM PDT 24
Peak memory 199904 kb
Host smart-4a6b961b-dd2d-44c4-aa42-39e7f23ed553
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607293818 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.hmac_test_hmac_vectors.607293818
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.416414576
Short name T227
Test name
Test status
Simulation time 332428792725 ps
CPU time 490.48 seconds
Started Jun 04 12:27:48 PM PDT 24
Finished Jun 04 12:36:00 PM PDT 24
Peak memory 199876 kb
Host smart-5d804f95-bd30-4034-ab74-065b8e1add86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416414576 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.416414576
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2365133468
Short name T453
Test name
Test status
Simulation time 4109079773 ps
CPU time 76.39 seconds
Started Jun 04 12:27:51 PM PDT 24
Finished Jun 04 12:29:08 PM PDT 24
Peak memory 199988 kb
Host smart-830c36e9-8202-4970-8863-b08b975adc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365133468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2365133468
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3134483375
Short name T193
Test name
Test status
Simulation time 13553021 ps
CPU time 0.56 seconds
Started Jun 04 12:28:00 PM PDT 24
Finished Jun 04 12:28:03 PM PDT 24
Peak memory 195384 kb
Host smart-00ec94be-2da9-4780-ad55-a5e4204a1188
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134483375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3134483375
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.98618429
Short name T265
Test name
Test status
Simulation time 195469149 ps
CPU time 10.45 seconds
Started Jun 04 12:27:54 PM PDT 24
Finished Jun 04 12:28:05 PM PDT 24
Peak memory 209164 kb
Host smart-517264ab-61ee-4e14-bcbf-e5bd9b7cfd0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=98618429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.98618429
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3677357655
Short name T363
Test name
Test status
Simulation time 3929768433 ps
CPU time 39.38 seconds
Started Jun 04 12:27:54 PM PDT 24
Finished Jun 04 12:28:34 PM PDT 24
Peak memory 199980 kb
Host smart-ea4efde3-3926-4314-b1d1-beb7a3a157cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677357655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3677357655
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.223081229
Short name T486
Test name
Test status
Simulation time 1387839611 ps
CPU time 49.82 seconds
Started Jun 04 12:27:54 PM PDT 24
Finished Jun 04 12:28:45 PM PDT 24
Peak memory 328952 kb
Host smart-08e26d46-e875-46d8-b9c5-5ad358bfff8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=223081229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.223081229
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.12560198
Short name T397
Test name
Test status
Simulation time 17385045211 ps
CPU time 212.57 seconds
Started Jun 04 12:27:54 PM PDT 24
Finished Jun 04 12:31:28 PM PDT 24
Peak memory 200004 kb
Host smart-736ab32d-67dc-44e9-855a-083f45116921
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12560198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.12560198
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.1111905461
Short name T210
Test name
Test status
Simulation time 6642541300 ps
CPU time 131.5 seconds
Started Jun 04 12:27:46 PM PDT 24
Finished Jun 04 12:29:59 PM PDT 24
Peak memory 199916 kb
Host smart-7d6bcdf5-9443-4900-9d09-efbb9baea54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111905461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1111905461
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3190963282
Short name T509
Test name
Test status
Simulation time 253661737 ps
CPU time 3.3 seconds
Started Jun 04 12:27:50 PM PDT 24
Finished Jun 04 12:27:55 PM PDT 24
Peak memory 199932 kb
Host smart-48fcbc46-3b2d-462c-b51d-200dbf51545f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190963282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3190963282
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.611856450
Short name T108
Test name
Test status
Simulation time 85568016474 ps
CPU time 3067.36 seconds
Started Jun 04 12:27:54 PM PDT 24
Finished Jun 04 01:19:03 PM PDT 24
Peak memory 809396 kb
Host smart-67759186-ee82-4ce6-b863-6006387b2ea7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611856450 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.611856450
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.2145816796
Short name T569
Test name
Test status
Simulation time 69092342 ps
CPU time 1.03 seconds
Started Jun 04 12:27:49 PM PDT 24
Finished Jun 04 12:27:51 PM PDT 24
Peak memory 199676 kb
Host smart-c8d39452-9e92-49eb-bde8-e2feb94d8f82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145816796 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.2145816796
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.286085229
Short name T449
Test name
Test status
Simulation time 54190722533 ps
CPU time 485.57 seconds
Started Jun 04 12:27:44 PM PDT 24
Finished Jun 04 12:35:51 PM PDT 24
Peak memory 199884 kb
Host smart-e0413f7a-02f5-4538-9007-fd3971ec5193
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286085229 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.286085229
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.323791974
Short name T302
Test name
Test status
Simulation time 571817763 ps
CPU time 24.23 seconds
Started Jun 04 12:27:46 PM PDT 24
Finished Jun 04 12:28:12 PM PDT 24
Peak memory 199928 kb
Host smart-2fc9e03d-d10f-478b-959e-c7f5c8ff7f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323791974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.323791974
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/172.hmac_stress_all_with_rand_reset.1287063135
Short name T59
Test name
Test status
Simulation time 81143171660 ps
CPU time 2051.48 seconds
Started Jun 04 12:30:21 PM PDT 24
Finished Jun 04 01:04:34 PM PDT 24
Peak memory 790356 kb
Host smart-0cd57618-8c21-4f69-9919-6a31f56a93bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1287063135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.hmac_stress_all_with_rand_reset.1287063135
Directory /workspace/172.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/174.hmac_stress_all_with_rand_reset.2538814306
Short name T5
Test name
Test status
Simulation time 101461105181 ps
CPU time 4257.08 seconds
Started Jun 04 12:30:21 PM PDT 24
Finished Jun 04 01:41:19 PM PDT 24
Peak memory 249260 kb
Host smart-16e786e4-0e56-4ca5-96e7-ef23b5078463
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2538814306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.hmac_stress_all_with_rand_reset.2538814306
Directory /workspace/174.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1062583419
Short name T163
Test name
Test status
Simulation time 12796935 ps
CPU time 0.59 seconds
Started Jun 04 12:27:57 PM PDT 24
Finished Jun 04 12:27:59 PM PDT 24
Peak memory 195820 kb
Host smart-2bc6b253-c930-406d-8d2d-a103df102580
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062583419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1062583419
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2977252244
Short name T575
Test name
Test status
Simulation time 304083262 ps
CPU time 4.94 seconds
Started Jun 04 12:27:59 PM PDT 24
Finished Jun 04 12:28:06 PM PDT 24
Peak memory 208056 kb
Host smart-e897f046-7426-4165-9b1e-0bc78876fa9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2977252244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2977252244
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3183219360
Short name T170
Test name
Test status
Simulation time 3859622255 ps
CPU time 53.81 seconds
Started Jun 04 12:27:58 PM PDT 24
Finished Jun 04 12:28:55 PM PDT 24
Peak memory 200016 kb
Host smart-a8a3e76d-dff1-4166-ba53-8745386b9885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183219360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3183219360
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.572087112
Short name T162
Test name
Test status
Simulation time 9552720711 ps
CPU time 549.15 seconds
Started Jun 04 12:28:00 PM PDT 24
Finished Jun 04 12:37:12 PM PDT 24
Peak memory 702460 kb
Host smart-dd39efd9-7022-45e7-b544-eefabe6cbefe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=572087112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.572087112
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.2067823661
Short name T9
Test name
Test status
Simulation time 13178698883 ps
CPU time 43.12 seconds
Started Jun 04 12:28:03 PM PDT 24
Finished Jun 04 12:28:48 PM PDT 24
Peak memory 200008 kb
Host smart-0177608a-72b5-4413-a7b3-e5bf8d15f9c5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067823661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2067823661
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.270275003
Short name T546
Test name
Test status
Simulation time 422095102 ps
CPU time 23.13 seconds
Started Jun 04 12:28:04 PM PDT 24
Finished Jun 04 12:28:30 PM PDT 24
Peak memory 199908 kb
Host smart-a4c83796-f93a-4b7f-ba3b-2db4c7f4a008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270275003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.270275003
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3140544091
Short name T128
Test name
Test status
Simulation time 604575147 ps
CPU time 8.04 seconds
Started Jun 04 12:28:02 PM PDT 24
Finished Jun 04 12:28:12 PM PDT 24
Peak memory 199832 kb
Host smart-6f447d0d-5279-47bc-9ab8-ba4fddbb60ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140544091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3140544091
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3673555406
Short name T556
Test name
Test status
Simulation time 38789816735 ps
CPU time 2147.3 seconds
Started Jun 04 12:27:57 PM PDT 24
Finished Jun 04 01:03:46 PM PDT 24
Peak memory 231300 kb
Host smart-4baad595-2273-4546-82df-7577f57d1cf1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673555406 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3673555406
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.932431029
Short name T493
Test name
Test status
Simulation time 28415317 ps
CPU time 1.1 seconds
Started Jun 04 12:27:58 PM PDT 24
Finished Jun 04 12:28:02 PM PDT 24
Peak memory 199648 kb
Host smart-ad0714dd-fd74-4926-b72e-db7872664055
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932431029 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_hmac_vectors.932431029
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.433482146
Short name T384
Test name
Test status
Simulation time 8982602205 ps
CPU time 485.91 seconds
Started Jun 04 12:28:00 PM PDT 24
Finished Jun 04 12:36:08 PM PDT 24
Peak memory 199876 kb
Host smart-a311801b-23a7-45ba-a2be-cc9396ef12a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433482146 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.433482146
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.3915452627
Short name T442
Test name
Test status
Simulation time 14054190014 ps
CPU time 31.17 seconds
Started Jun 04 12:28:03 PM PDT 24
Finished Jun 04 12:28:36 PM PDT 24
Peak memory 200008 kb
Host smart-ce19e1ba-c645-4b53-94eb-e23696517da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915452627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3915452627
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.4193187619
Short name T498
Test name
Test status
Simulation time 17594022 ps
CPU time 0.57 seconds
Started Jun 04 12:27:59 PM PDT 24
Finished Jun 04 12:28:02 PM PDT 24
Peak memory 196544 kb
Host smart-4d576732-05d8-4231-9ce0-3ce97eecc2bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193187619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.4193187619
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3809471896
Short name T344
Test name
Test status
Simulation time 203332422 ps
CPU time 8.68 seconds
Started Jun 04 12:28:00 PM PDT 24
Finished Jun 04 12:28:12 PM PDT 24
Peak memory 216280 kb
Host smart-bc00709f-f25b-4146-b2d5-c7debc560358
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3809471896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3809471896
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1538647843
Short name T226
Test name
Test status
Simulation time 1436149109 ps
CPU time 69.36 seconds
Started Jun 04 12:27:58 PM PDT 24
Finished Jun 04 12:29:10 PM PDT 24
Peak memory 199884 kb
Host smart-1a579967-5ef8-460e-a51d-d6891202c997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538647843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1538647843
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2373954751
Short name T104
Test name
Test status
Simulation time 14887486415 ps
CPU time 633.43 seconds
Started Jun 04 12:28:18 PM PDT 24
Finished Jun 04 12:38:52 PM PDT 24
Peak memory 683020 kb
Host smart-ddb30a72-7289-416b-a3e2-94a322a8acab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2373954751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2373954751
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.1517561618
Short name T553
Test name
Test status
Simulation time 4635738638 ps
CPU time 80.94 seconds
Started Jun 04 12:27:57 PM PDT 24
Finished Jun 04 12:29:19 PM PDT 24
Peak memory 199844 kb
Host smart-057ae630-580a-4717-9340-5caa550f7dce
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517561618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.1517561618
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.2730198837
Short name T455
Test name
Test status
Simulation time 12626863962 ps
CPU time 68.34 seconds
Started Jun 04 12:28:00 PM PDT 24
Finished Jun 04 12:29:11 PM PDT 24
Peak memory 200052 kb
Host smart-a1754b2c-dc8b-4f6d-b2e0-5a03c0d5fff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730198837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2730198837
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.2434232456
Short name T294
Test name
Test status
Simulation time 44317529 ps
CPU time 0.96 seconds
Started Jun 04 12:28:03 PM PDT 24
Finished Jun 04 12:28:06 PM PDT 24
Peak memory 198772 kb
Host smart-9829922a-5723-4981-97ab-e08e69f662e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434232456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2434232456
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.881093745
Short name T72
Test name
Test status
Simulation time 174213970232 ps
CPU time 3187.6 seconds
Started Jun 04 12:27:58 PM PDT 24
Finished Jun 04 01:21:09 PM PDT 24
Peak memory 766140 kb
Host smart-edcc918c-3f53-4b81-b252-00da0c73c9b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881093745 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.881093745
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_stress_all_with_rand_reset.1931371137
Short name T40
Test name
Test status
Simulation time 134819639785 ps
CPU time 1795.49 seconds
Started Jun 04 12:28:00 PM PDT 24
Finished Jun 04 12:57:58 PM PDT 24
Peak memory 411712 kb
Host smart-96a80ca6-1fb0-44fd-a57b-87d3a9180fc1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1931371137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all_with_rand_reset.1931371137
Directory /workspace/19.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.70975385
Short name T447
Test name
Test status
Simulation time 108954206 ps
CPU time 1.07 seconds
Started Jun 04 12:28:03 PM PDT 24
Finished Jun 04 12:28:06 PM PDT 24
Peak memory 199908 kb
Host smart-ed5a9120-2214-430d-bb5d-82404a523d98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70975385 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.hmac_test_hmac_vectors.70975385
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.2490647561
Short name T69
Test name
Test status
Simulation time 152404134115 ps
CPU time 466.11 seconds
Started Jun 04 12:27:58 PM PDT 24
Finished Jun 04 12:35:47 PM PDT 24
Peak memory 199908 kb
Host smart-7b2c0e9a-9b73-4f46-9a5a-72503fc7e66d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490647561 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.2490647561
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.4228272827
Short name T513
Test name
Test status
Simulation time 335961278 ps
CPU time 13.42 seconds
Started Jun 04 12:27:58 PM PDT 24
Finished Jun 04 12:28:14 PM PDT 24
Peak memory 199888 kb
Host smart-d0fe9893-dee2-4b63-bf9d-6ba4051b2f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228272827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.4228272827
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.839305043
Short name T393
Test name
Test status
Simulation time 77173693 ps
CPU time 0.54 seconds
Started Jun 04 12:27:16 PM PDT 24
Finished Jun 04 12:27:18 PM PDT 24
Peak memory 194772 kb
Host smart-a39535a7-c265-4bee-b2d5-6e95df84c918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839305043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.839305043
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1659051287
Short name T288
Test name
Test status
Simulation time 780217335 ps
CPU time 11.19 seconds
Started Jun 04 12:27:16 PM PDT 24
Finished Jun 04 12:27:29 PM PDT 24
Peak memory 222432 kb
Host smart-3e296a63-53c9-4b59-a4fd-c9e378a37746
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1659051287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1659051287
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3657678256
Short name T331
Test name
Test status
Simulation time 8061739533 ps
CPU time 45.12 seconds
Started Jun 04 12:27:27 PM PDT 24
Finished Jun 04 12:28:15 PM PDT 24
Peak memory 199900 kb
Host smart-bfbd8dff-0183-4b2b-90c1-e1aabea258f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657678256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3657678256
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3206172427
Short name T2
Test name
Test status
Simulation time 1711213831 ps
CPU time 355.32 seconds
Started Jun 04 12:27:17 PM PDT 24
Finished Jun 04 12:33:14 PM PDT 24
Peak memory 673180 kb
Host smart-12846f2e-2eb8-4766-839e-ee3cae1d8221
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3206172427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3206172427
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.866311973
Short name T549
Test name
Test status
Simulation time 11627403838 ps
CPU time 98.25 seconds
Started Jun 04 12:27:15 PM PDT 24
Finished Jun 04 12:28:55 PM PDT 24
Peak memory 199952 kb
Host smart-13d19565-5a0f-45e9-9c03-c009a532eff8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866311973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.866311973
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.263884178
Short name T83
Test name
Test status
Simulation time 2465711034 ps
CPU time 33.6 seconds
Started Jun 04 12:27:15 PM PDT 24
Finished Jun 04 12:27:51 PM PDT 24
Peak memory 199984 kb
Host smart-a59833a9-7cad-4874-9253-06399bec7507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263884178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.263884178
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.1880014355
Short name T25
Test name
Test status
Simulation time 132697834 ps
CPU time 0.96 seconds
Started Jun 04 12:27:20 PM PDT 24
Finished Jun 04 12:27:22 PM PDT 24
Peak memory 218388 kb
Host smart-eb47a4e0-f39d-4e9b-9225-3603b083c551
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880014355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1880014355
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.3588057564
Short name T420
Test name
Test status
Simulation time 1447413298 ps
CPU time 8.19 seconds
Started Jun 04 12:27:14 PM PDT 24
Finished Jun 04 12:27:23 PM PDT 24
Peak memory 199856 kb
Host smart-2d1cf129-03f3-4ccb-a3ed-c66c5221df0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588057564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3588057564
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.242573568
Short name T77
Test name
Test status
Simulation time 331853759880 ps
CPU time 1206.88 seconds
Started Jun 04 12:27:15 PM PDT 24
Finished Jun 04 12:47:23 PM PDT 24
Peak memory 240552 kb
Host smart-cac9aa46-291e-4f85-b929-41dc4f2cb6a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242573568 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.242573568
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.1922690748
Short name T464
Test name
Test status
Simulation time 59813213 ps
CPU time 1.33 seconds
Started Jun 04 12:27:16 PM PDT 24
Finished Jun 04 12:27:18 PM PDT 24
Peak memory 199952 kb
Host smart-e0b81bf9-5a86-4718-bee1-6d06122f031a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922690748 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.1922690748
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.1763083614
Short name T357
Test name
Test status
Simulation time 39809802187 ps
CPU time 493.64 seconds
Started Jun 04 12:27:17 PM PDT 24
Finished Jun 04 12:35:32 PM PDT 24
Peak memory 199892 kb
Host smart-c85b9f0c-4f1c-4c2d-9543-440e3f493ba1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763083614 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.1763083614
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.4140007097
Short name T191
Test name
Test status
Simulation time 1250719795 ps
CPU time 60.31 seconds
Started Jun 04 12:27:15 PM PDT 24
Finished Jun 04 12:28:17 PM PDT 24
Peak memory 199912 kb
Host smart-7f8d9566-671b-4773-9a6d-934158415773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140007097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.4140007097
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.3916829784
Short name T328
Test name
Test status
Simulation time 40086192 ps
CPU time 0.62 seconds
Started Jun 04 12:27:59 PM PDT 24
Finished Jun 04 12:28:02 PM PDT 24
Peak memory 195776 kb
Host smart-e3d728c2-ffa1-4dfd-9814-ebbfd31d596b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916829784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.3916829784
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.3523886695
Short name T465
Test name
Test status
Simulation time 2258241652 ps
CPU time 25.05 seconds
Started Jun 04 12:28:00 PM PDT 24
Finished Jun 04 12:28:28 PM PDT 24
Peak memory 200064 kb
Host smart-40fff881-ec2b-4ba7-91fb-481514cbea5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3523886695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.3523886695
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3638081067
Short name T594
Test name
Test status
Simulation time 78356626 ps
CPU time 3.75 seconds
Started Jun 04 12:28:01 PM PDT 24
Finished Jun 04 12:28:07 PM PDT 24
Peak memory 199944 kb
Host smart-6cb15b58-9fa2-47a8-8527-210d33b9c481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638081067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3638081067
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3830180710
Short name T364
Test name
Test status
Simulation time 87005088 ps
CPU time 0.9 seconds
Started Jun 04 12:28:01 PM PDT 24
Finished Jun 04 12:28:04 PM PDT 24
Peak memory 198316 kb
Host smart-45374049-8bf7-408d-90a1-40cecf413ae7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3830180710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3830180710
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1377404836
Short name T207
Test name
Test status
Simulation time 34882464131 ps
CPU time 227.37 seconds
Started Jun 04 12:28:03 PM PDT 24
Finished Jun 04 12:31:52 PM PDT 24
Peak memory 200028 kb
Host smart-6fe5388c-8f06-4dfe-b810-5ad52dfa5789
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377404836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1377404836
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2482398639
Short name T521
Test name
Test status
Simulation time 2100650614 ps
CPU time 8.93 seconds
Started Jun 04 12:28:00 PM PDT 24
Finished Jun 04 12:28:11 PM PDT 24
Peak memory 200032 kb
Host smart-cb79c958-d49c-4b2a-b00b-ddee6ddc2b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482398639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2482398639
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.857500653
Short name T560
Test name
Test status
Simulation time 191086482 ps
CPU time 6.19 seconds
Started Jun 04 12:27:59 PM PDT 24
Finished Jun 04 12:28:07 PM PDT 24
Peak memory 199844 kb
Host smart-909c3cbc-1bfb-49e0-84f6-df5c276afac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857500653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.857500653
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.792004836
Short name T99
Test name
Test status
Simulation time 319872448 ps
CPU time 12.64 seconds
Started Jun 04 12:28:03 PM PDT 24
Finished Jun 04 12:28:18 PM PDT 24
Peak memory 199952 kb
Host smart-9525e988-484f-408d-9b15-fd453572fb11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792004836 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.792004836
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.2581576688
Short name T543
Test name
Test status
Simulation time 82727753 ps
CPU time 1.4 seconds
Started Jun 04 12:27:59 PM PDT 24
Finished Jun 04 12:28:03 PM PDT 24
Peak memory 199832 kb
Host smart-dc2fc24f-ffd2-481d-ad52-5c0d010d10f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581576688 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.2581576688
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.1984960585
Short name T532
Test name
Test status
Simulation time 100437893486 ps
CPU time 417.19 seconds
Started Jun 04 12:28:04 PM PDT 24
Finished Jun 04 12:35:03 PM PDT 24
Peak memory 199860 kb
Host smart-0078907c-8415-4f04-af6f-d6c12570911b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984960585 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.1984960585
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3334024584
Short name T147
Test name
Test status
Simulation time 1976823426 ps
CPU time 27.22 seconds
Started Jun 04 12:27:56 PM PDT 24
Finished Jun 04 12:28:24 PM PDT 24
Peak memory 199908 kb
Host smart-74721681-7e76-42a5-bfe3-d35769834533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334024584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3334024584
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2126749041
Short name T489
Test name
Test status
Simulation time 19295735 ps
CPU time 0.58 seconds
Started Jun 04 12:28:02 PM PDT 24
Finished Jun 04 12:28:05 PM PDT 24
Peak memory 195808 kb
Host smart-93f8249d-c042-4107-8921-a98412ed442c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126749041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2126749041
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3912812996
Short name T68
Test name
Test status
Simulation time 839959456 ps
CPU time 25.65 seconds
Started Jun 04 12:27:59 PM PDT 24
Finished Jun 04 12:28:28 PM PDT 24
Peak memory 228828 kb
Host smart-ec0a3c33-698e-4fb2-8fcf-9b9cfc40d791
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3912812996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3912812996
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3578667805
Short name T67
Test name
Test status
Simulation time 13744741671 ps
CPU time 67.1 seconds
Started Jun 04 12:28:02 PM PDT 24
Finished Jun 04 12:29:11 PM PDT 24
Peak memory 200016 kb
Host smart-93fb109b-f93b-4c87-977e-727417393d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578667805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3578667805
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1335287618
Short name T100
Test name
Test status
Simulation time 4632245459 ps
CPU time 586.68 seconds
Started Jun 04 12:27:58 PM PDT 24
Finished Jun 04 12:37:48 PM PDT 24
Peak memory 655656 kb
Host smart-ef38a208-4dfc-44ea-a5a9-545159ed4166
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1335287618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1335287618
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.904948464
Short name T582
Test name
Test status
Simulation time 2504856777 ps
CPU time 133.46 seconds
Started Jun 04 12:27:58 PM PDT 24
Finished Jun 04 12:30:13 PM PDT 24
Peak memory 200008 kb
Host smart-49a0131b-c6ee-46df-a65c-2ebd6511f02b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904948464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.904948464
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2828289159
Short name T134
Test name
Test status
Simulation time 6196077859 ps
CPU time 85.54 seconds
Started Jun 04 12:27:57 PM PDT 24
Finished Jun 04 12:29:24 PM PDT 24
Peak memory 199976 kb
Host smart-e4ad52fb-f5f4-49ce-aac4-f69e23770127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828289159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2828289159
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3603828307
Short name T237
Test name
Test status
Simulation time 641987372 ps
CPU time 8.68 seconds
Started Jun 04 12:28:03 PM PDT 24
Finished Jun 04 12:28:14 PM PDT 24
Peak memory 199932 kb
Host smart-0d777d71-1c9e-4bd0-bff0-81830ebe4464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603828307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3603828307
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.658764104
Short name T416
Test name
Test status
Simulation time 47875647393 ps
CPU time 1814.69 seconds
Started Jun 04 12:28:14 PM PDT 24
Finished Jun 04 12:58:30 PM PDT 24
Peak memory 656476 kb
Host smart-c6ab3a92-9909-4fb1-a8d7-43de2bb4a58a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658764104 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.658764104
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.4239627179
Short name T544
Test name
Test status
Simulation time 265866043 ps
CPU time 1.37 seconds
Started Jun 04 12:28:01 PM PDT 24
Finished Jun 04 12:28:05 PM PDT 24
Peak memory 199736 kb
Host smart-6fc785f0-5338-4bb7-aa32-422fd2ad72f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239627179 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.4239627179
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.1049645943
Short name T410
Test name
Test status
Simulation time 69119889019 ps
CPU time 461.22 seconds
Started Jun 04 12:28:00 PM PDT 24
Finished Jun 04 12:35:44 PM PDT 24
Peak memory 200080 kb
Host smart-ec708a8f-b974-4904-a8ae-64937151c415
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049645943 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.1049645943
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2710024076
Short name T271
Test name
Test status
Simulation time 10442728545 ps
CPU time 43.6 seconds
Started Jun 04 12:28:01 PM PDT 24
Finished Jun 04 12:28:47 PM PDT 24
Peak memory 199948 kb
Host smart-ad0edf33-fc9a-4688-9bc0-e19424d45cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710024076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2710024076
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1211756282
Short name T319
Test name
Test status
Simulation time 42809188 ps
CPU time 0.58 seconds
Started Jun 04 12:28:07 PM PDT 24
Finished Jun 04 12:28:09 PM PDT 24
Peak memory 195768 kb
Host smart-19724443-4865-46fb-a535-fe6d69f6a738
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211756282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1211756282
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2452258282
Short name T175
Test name
Test status
Simulation time 889092240 ps
CPU time 47.72 seconds
Started Jun 04 12:28:04 PM PDT 24
Finished Jun 04 12:28:55 PM PDT 24
Peak memory 232640 kb
Host smart-c212997e-b87e-4c15-9176-343b849c1936
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2452258282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2452258282
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.184010073
Short name T113
Test name
Test status
Simulation time 6022137860 ps
CPU time 15.22 seconds
Started Jun 04 12:28:11 PM PDT 24
Finished Jun 04 12:28:28 PM PDT 24
Peak memory 200016 kb
Host smart-9c2da4ab-b176-4623-b99c-e02d4569cca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184010073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.184010073
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.799385961
Short name T479
Test name
Test status
Simulation time 1533899533 ps
CPU time 147.76 seconds
Started Jun 04 12:27:57 PM PDT 24
Finished Jun 04 12:30:27 PM PDT 24
Peak memory 461476 kb
Host smart-92914296-7b03-47c3-8df0-54882a84257c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=799385961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.799385961
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.3111869151
Short name T283
Test name
Test status
Simulation time 3552427152 ps
CPU time 63.47 seconds
Started Jun 04 12:28:12 PM PDT 24
Finished Jun 04 12:29:17 PM PDT 24
Peak memory 199884 kb
Host smart-e055e36e-5a96-4c4a-8b68-69aea81ec73e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111869151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3111869151
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.785319152
Short name T269
Test name
Test status
Simulation time 10652045913 ps
CPU time 37.46 seconds
Started Jun 04 12:28:00 PM PDT 24
Finished Jun 04 12:28:40 PM PDT 24
Peak memory 200044 kb
Host smart-4f34c3d5-881d-43a1-8f11-887bc0d625d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785319152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.785319152
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.3837552156
Short name T196
Test name
Test status
Simulation time 1859640056 ps
CPU time 10.11 seconds
Started Jun 04 12:27:58 PM PDT 24
Finished Jun 04 12:28:11 PM PDT 24
Peak memory 200036 kb
Host smart-620637ad-f7f1-4101-b7db-995235679f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837552156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3837552156
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.1069865971
Short name T562
Test name
Test status
Simulation time 119944378 ps
CPU time 1.28 seconds
Started Jun 04 12:28:09 PM PDT 24
Finished Jun 04 12:28:12 PM PDT 24
Peak memory 199976 kb
Host smart-21945e17-fac8-4187-801a-38379b7af834
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069865971 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.1069865971
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.1862770804
Short name T132
Test name
Test status
Simulation time 14998416758 ps
CPU time 451.33 seconds
Started Jun 04 12:28:11 PM PDT 24
Finished Jun 04 12:35:44 PM PDT 24
Peak memory 199932 kb
Host smart-8dc064c7-ffab-406b-8158-ed9d6a90e87b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862770804 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.1862770804
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2425700325
Short name T321
Test name
Test status
Simulation time 4023277243 ps
CPU time 38.1 seconds
Started Jun 04 12:28:08 PM PDT 24
Finished Jun 04 12:28:48 PM PDT 24
Peak memory 199948 kb
Host smart-19994490-90ce-4196-8ab7-9e483a0068b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425700325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2425700325
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.1532077611
Short name T278
Test name
Test status
Simulation time 37169510 ps
CPU time 0.55 seconds
Started Jun 04 12:28:13 PM PDT 24
Finished Jun 04 12:28:15 PM PDT 24
Peak memory 195428 kb
Host smart-20d76230-84e8-48ff-b781-ce05c469ab64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532077611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1532077611
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1201427787
Short name T476
Test name
Test status
Simulation time 800529958 ps
CPU time 36.01 seconds
Started Jun 04 12:28:09 PM PDT 24
Finished Jun 04 12:28:46 PM PDT 24
Peak memory 240860 kb
Host smart-c6ab5bde-e476-421e-b58c-3fd24bab89f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1201427787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1201427787
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.4045005296
Short name T587
Test name
Test status
Simulation time 6055274731 ps
CPU time 29.75 seconds
Started Jun 04 12:28:06 PM PDT 24
Finished Jun 04 12:28:38 PM PDT 24
Peak memory 199916 kb
Host smart-993ca85c-4450-4e63-b308-7203e2f3a165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045005296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.4045005296
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.8535765
Short name T536
Test name
Test status
Simulation time 11897496671 ps
CPU time 153.9 seconds
Started Jun 04 12:28:09 PM PDT 24
Finished Jun 04 12:30:44 PM PDT 24
Peak memory 446448 kb
Host smart-4e445e02-a112-4aeb-85b6-04e44c967aa8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=8535765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.8535765
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3310586325
Short name T422
Test name
Test status
Simulation time 11514507085 ps
CPU time 141.73 seconds
Started Jun 04 12:28:06 PM PDT 24
Finished Jun 04 12:30:30 PM PDT 24
Peak memory 200068 kb
Host smart-da9273ae-ccff-40bc-8ebe-3017444f2c5c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310586325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3310586325
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.4129650219
Short name T292
Test name
Test status
Simulation time 3931834732 ps
CPU time 41.21 seconds
Started Jun 04 12:28:11 PM PDT 24
Finished Jun 04 12:28:54 PM PDT 24
Peak memory 200020 kb
Host smart-9f1e828e-4f3f-418c-83a5-2adea2a0e3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129650219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.4129650219
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.3516654804
Short name T388
Test name
Test status
Simulation time 61075898 ps
CPU time 1.46 seconds
Started Jun 04 12:28:14 PM PDT 24
Finished Jun 04 12:28:17 PM PDT 24
Peak memory 199876 kb
Host smart-a62d6631-a00a-47a1-9b7c-527eb24f1158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516654804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3516654804
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.1146289339
Short name T109
Test name
Test status
Simulation time 96983830492 ps
CPU time 2136.14 seconds
Started Jun 04 12:28:06 PM PDT 24
Finished Jun 04 01:03:45 PM PDT 24
Peak memory 735664 kb
Host smart-10ac4299-d673-45a9-9651-e9f8c4d85567
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146289339 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1146289339
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.747022818
Short name T315
Test name
Test status
Simulation time 59525314 ps
CPU time 1.31 seconds
Started Jun 04 12:28:09 PM PDT 24
Finished Jun 04 12:28:12 PM PDT 24
Peak memory 199888 kb
Host smart-5a84af16-98a8-4e82-8019-815f61c5bf6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747022818 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_hmac_vectors.747022818
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.115205694
Short name T156
Test name
Test status
Simulation time 65886810198 ps
CPU time 449.07 seconds
Started Jun 04 12:28:11 PM PDT 24
Finished Jun 04 12:35:42 PM PDT 24
Peak memory 199924 kb
Host smart-2d8d10be-692a-4410-882a-d461a3028660
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115205694 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.115205694
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1403816478
Short name T253
Test name
Test status
Simulation time 1499292020 ps
CPU time 23.16 seconds
Started Jun 04 12:28:10 PM PDT 24
Finished Jun 04 12:28:34 PM PDT 24
Peak memory 199932 kb
Host smart-3c5f91af-e9da-47cc-a41d-2a59c997c40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403816478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1403816478
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3395503607
Short name T71
Test name
Test status
Simulation time 14536205 ps
CPU time 0.57 seconds
Started Jun 04 12:28:08 PM PDT 24
Finished Jun 04 12:28:10 PM PDT 24
Peak memory 194728 kb
Host smart-fd17ae72-6a0c-45b6-8848-81002ed90125
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395503607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3395503607
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.695150484
Short name T337
Test name
Test status
Simulation time 54330500 ps
CPU time 2.67 seconds
Started Jun 04 12:28:13 PM PDT 24
Finished Jun 04 12:28:17 PM PDT 24
Peak memory 199816 kb
Host smart-535c2b04-ea9d-4a03-a272-e0f5b768a5a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=695150484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.695150484
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2970294450
Short name T291
Test name
Test status
Simulation time 1497774760 ps
CPU time 28.27 seconds
Started Jun 04 12:28:12 PM PDT 24
Finished Jun 04 12:28:42 PM PDT 24
Peak memory 199824 kb
Host smart-8e848d70-38c3-447e-857d-8d9c708b5b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970294450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2970294450
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.2688107791
Short name T503
Test name
Test status
Simulation time 6106867066 ps
CPU time 940.46 seconds
Started Jun 04 12:28:05 PM PDT 24
Finished Jun 04 12:43:48 PM PDT 24
Peak memory 776844 kb
Host smart-1f1773ca-18c2-453b-a749-43f87cc819fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2688107791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.2688107791
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2438584263
Short name T168
Test name
Test status
Simulation time 14828876698 ps
CPU time 184.9 seconds
Started Jun 04 12:28:08 PM PDT 24
Finished Jun 04 12:31:14 PM PDT 24
Peak memory 200060 kb
Host smart-4ae6fd4e-397c-47e6-85bb-1edbe3e20819
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438584263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2438584263
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.263165473
Short name T358
Test name
Test status
Simulation time 4036899340 ps
CPU time 75.89 seconds
Started Jun 04 12:28:10 PM PDT 24
Finished Jun 04 12:29:28 PM PDT 24
Peak memory 199944 kb
Host smart-54ad5788-ed4a-4a2f-8ffd-36ce922fce25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263165473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.263165473
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2113961919
Short name T426
Test name
Test status
Simulation time 2535746968 ps
CPU time 8.64 seconds
Started Jun 04 12:28:14 PM PDT 24
Finished Jun 04 12:28:24 PM PDT 24
Peak memory 199960 kb
Host smart-d25e7ff0-afaa-4e1b-baf4-010a8a88a905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113961919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2113961919
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.1186045766
Short name T387
Test name
Test status
Simulation time 173445412 ps
CPU time 1.12 seconds
Started Jun 04 12:28:11 PM PDT 24
Finished Jun 04 12:28:14 PM PDT 24
Peak memory 199920 kb
Host smart-1a859930-f81f-4286-99eb-435262953aac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186045766 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.1186045766
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.3293380619
Short name T425
Test name
Test status
Simulation time 8504392024 ps
CPU time 466.44 seconds
Started Jun 04 12:28:08 PM PDT 24
Finished Jun 04 12:35:56 PM PDT 24
Peak memory 199928 kb
Host smart-9a7d05e1-a3e3-4928-af61-f00a7ea03b51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293380619 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.3293380619
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2291294948
Short name T494
Test name
Test status
Simulation time 2422108207 ps
CPU time 57.7 seconds
Started Jun 04 12:28:11 PM PDT 24
Finished Jun 04 12:29:11 PM PDT 24
Peak memory 199988 kb
Host smart-b61493d4-0224-4d42-b2e8-b3dc6e7ab0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291294948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2291294948
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.1965052790
Short name T411
Test name
Test status
Simulation time 86206670 ps
CPU time 0.58 seconds
Started Jun 04 12:28:15 PM PDT 24
Finished Jun 04 12:28:16 PM PDT 24
Peak memory 195760 kb
Host smart-8cee14b1-7357-401a-bdfa-be793365fde5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965052790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1965052790
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.309667035
Short name T564
Test name
Test status
Simulation time 101703865 ps
CPU time 2.76 seconds
Started Jun 04 12:28:15 PM PDT 24
Finished Jun 04 12:28:19 PM PDT 24
Peak memory 208048 kb
Host smart-79a7d1c6-6809-44c4-8bb0-fc6dadb74833
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=309667035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.309667035
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.728563715
Short name T374
Test name
Test status
Simulation time 5792889225 ps
CPU time 28.43 seconds
Started Jun 04 12:28:06 PM PDT 24
Finished Jun 04 12:28:37 PM PDT 24
Peak memory 199988 kb
Host smart-6c767372-3010-436a-a5f7-208513172012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728563715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.728563715
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.3153230681
Short name T64
Test name
Test status
Simulation time 2799206974 ps
CPU time 707.81 seconds
Started Jun 04 12:28:09 PM PDT 24
Finished Jun 04 12:39:58 PM PDT 24
Peak memory 723676 kb
Host smart-52791d66-bb46-48c1-814d-529da112a03d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3153230681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3153230681
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.566145140
Short name T320
Test name
Test status
Simulation time 101423849976 ps
CPU time 157.62 seconds
Started Jun 04 12:28:16 PM PDT 24
Finished Jun 04 12:30:55 PM PDT 24
Peak memory 199856 kb
Host smart-d40c9489-cf98-4081-90a9-10bfe4a31917
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566145140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.566145140
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.884852174
Short name T540
Test name
Test status
Simulation time 13095856058 ps
CPU time 69.01 seconds
Started Jun 04 12:28:11 PM PDT 24
Finished Jun 04 12:29:22 PM PDT 24
Peak memory 200012 kb
Host smart-123e22f5-3f4f-48f0-b99b-7fb7b224cec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884852174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.884852174
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.52476108
Short name T37
Test name
Test status
Simulation time 443257336 ps
CPU time 3.8 seconds
Started Jun 04 12:28:08 PM PDT 24
Finished Jun 04 12:28:13 PM PDT 24
Peak memory 199980 kb
Host smart-c591b72d-1392-40f0-9956-79badeed0a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52476108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.52476108
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.31170217
Short name T535
Test name
Test status
Simulation time 385754224 ps
CPU time 17.27 seconds
Started Jun 04 12:28:16 PM PDT 24
Finished Jun 04 12:28:34 PM PDT 24
Peak memory 199840 kb
Host smart-2ef8796a-90f5-481e-ae64-576a8bedde85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31170217 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.31170217
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.3548015414
Short name T514
Test name
Test status
Simulation time 59328225 ps
CPU time 1.32 seconds
Started Jun 04 12:28:10 PM PDT 24
Finished Jun 04 12:28:13 PM PDT 24
Peak memory 199892 kb
Host smart-948afab4-c9ec-47c9-b6eb-290884cf7439
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548015414 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.3548015414
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.1880377116
Short name T370
Test name
Test status
Simulation time 13757710761 ps
CPU time 410.24 seconds
Started Jun 04 12:28:14 PM PDT 24
Finished Jun 04 12:35:06 PM PDT 24
Peak memory 199880 kb
Host smart-2081ff4f-ce22-4e3d-9f79-4bbb22aeb918
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880377116 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.1880377116
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.301822744
Short name T38
Test name
Test status
Simulation time 4591206426 ps
CPU time 51.74 seconds
Started Jun 04 12:28:10 PM PDT 24
Finished Jun 04 12:29:04 PM PDT 24
Peak memory 200040 kb
Host smart-c11dbda5-d557-446e-b6d5-244474522088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301822744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.301822744
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.206759528
Short name T164
Test name
Test status
Simulation time 13605609 ps
CPU time 0.58 seconds
Started Jun 04 12:28:22 PM PDT 24
Finished Jun 04 12:28:24 PM PDT 24
Peak memory 195860 kb
Host smart-71712abb-1cff-4a16-92b5-dee78a5c8a2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206759528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.206759528
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.1883024269
Short name T538
Test name
Test status
Simulation time 6716119451 ps
CPU time 20.64 seconds
Started Jun 04 12:28:17 PM PDT 24
Finished Jun 04 12:28:39 PM PDT 24
Peak memory 208160 kb
Host smart-94a6c8ca-548f-4fea-ab5d-8abc634dbfbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1883024269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1883024269
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.593211440
Short name T236
Test name
Test status
Simulation time 447976983 ps
CPU time 24.7 seconds
Started Jun 04 12:28:23 PM PDT 24
Finished Jun 04 12:28:48 PM PDT 24
Peak memory 199980 kb
Host smart-57c1c170-2c16-4c80-9f54-a6730c6ff82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593211440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.593211440
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3919823333
Short name T460
Test name
Test status
Simulation time 810496549 ps
CPU time 149.12 seconds
Started Jun 04 12:28:18 PM PDT 24
Finished Jun 04 12:30:48 PM PDT 24
Peak memory 430764 kb
Host smart-412e5144-4370-4571-997d-1f8f87cedb8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3919823333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3919823333
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.711754752
Short name T448
Test name
Test status
Simulation time 22518967927 ps
CPU time 78.39 seconds
Started Jun 04 12:28:21 PM PDT 24
Finished Jun 04 12:29:40 PM PDT 24
Peak memory 200056 kb
Host smart-c4241284-ca56-47eb-9bbc-09494f0933fa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711754752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.711754752
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1117990877
Short name T352
Test name
Test status
Simulation time 1476937106 ps
CPU time 81.68 seconds
Started Jun 04 12:28:21 PM PDT 24
Finished Jun 04 12:29:44 PM PDT 24
Peak memory 199952 kb
Host smart-05e48084-02f7-4575-aa61-719cfb7af179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117990877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1117990877
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.652452421
Short name T200
Test name
Test status
Simulation time 69604072 ps
CPU time 1.49 seconds
Started Jun 04 12:28:10 PM PDT 24
Finished Jun 04 12:28:13 PM PDT 24
Peak memory 200008 kb
Host smart-27fdca23-4c8c-4b9f-8ffc-4b331e36121f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652452421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.652452421
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.1308674423
Short name T463
Test name
Test status
Simulation time 94538393992 ps
CPU time 1353.67 seconds
Started Jun 04 12:28:18 PM PDT 24
Finished Jun 04 12:50:53 PM PDT 24
Peak memory 215912 kb
Host smart-739e87c3-3430-46cf-93c0-9d450e9b6f7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308674423 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1308674423
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.2827736734
Short name T281
Test name
Test status
Simulation time 480202826 ps
CPU time 1.15 seconds
Started Jun 04 12:28:21 PM PDT 24
Finished Jun 04 12:28:23 PM PDT 24
Peak memory 200008 kb
Host smart-cdfecf43-abac-4466-b755-8fac547be900
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827736734 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.2827736734
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.3397539661
Short name T592
Test name
Test status
Simulation time 29264861440 ps
CPU time 498.49 seconds
Started Jun 04 12:28:17 PM PDT 24
Finished Jun 04 12:36:37 PM PDT 24
Peak memory 199984 kb
Host smart-ca5cca73-8f1c-4b32-b588-f79354d6c716
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397539661 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.3397539661
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3971345633
Short name T262
Test name
Test status
Simulation time 539411127 ps
CPU time 23.31 seconds
Started Jun 04 12:28:19 PM PDT 24
Finished Jun 04 12:28:43 PM PDT 24
Peak memory 199832 kb
Host smart-34c19659-ff99-4b86-b42d-94e58a1bed80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971345633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3971345633
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.3044072328
Short name T287
Test name
Test status
Simulation time 88495895 ps
CPU time 0.57 seconds
Started Jun 04 12:28:32 PM PDT 24
Finished Jun 04 12:28:33 PM PDT 24
Peak memory 196492 kb
Host smart-1b6e01bd-68c9-40b1-a97d-bd073dea0e28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044072328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3044072328
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3301853662
Short name T107
Test name
Test status
Simulation time 1570354564 ps
CPU time 36.51 seconds
Started Jun 04 12:28:20 PM PDT 24
Finished Jun 04 12:28:57 PM PDT 24
Peak memory 216208 kb
Host smart-05a6bd30-9945-4372-a93a-547a119f143c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3301853662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3301853662
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.485667505
Short name T266
Test name
Test status
Simulation time 9000687100 ps
CPU time 67.4 seconds
Started Jun 04 12:28:21 PM PDT 24
Finished Jun 04 12:29:29 PM PDT 24
Peak memory 200044 kb
Host smart-0b9c8fde-c484-4d21-b9c2-c56938cf5e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485667505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.485667505
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.4287300014
Short name T229
Test name
Test status
Simulation time 14874739514 ps
CPU time 850.9 seconds
Started Jun 04 12:28:33 PM PDT 24
Finished Jun 04 12:42:45 PM PDT 24
Peak memory 716104 kb
Host smart-28426cb5-8d9b-45c8-a720-dc08bb9776ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4287300014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.4287300014
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.1310087621
Short name T424
Test name
Test status
Simulation time 2984369612 ps
CPU time 9.81 seconds
Started Jun 04 12:28:28 PM PDT 24
Finished Jun 04 12:28:39 PM PDT 24
Peak memory 199872 kb
Host smart-3379b355-3010-4109-a4f8-dbf8f778920b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310087621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1310087621
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.945271491
Short name T204
Test name
Test status
Simulation time 979333737 ps
CPU time 54.06 seconds
Started Jun 04 12:28:33 PM PDT 24
Finished Jun 04 12:29:28 PM PDT 24
Peak memory 199900 kb
Host smart-e772c36c-06e7-4330-9cab-3d9e72c128f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945271491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.945271491
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2419729803
Short name T339
Test name
Test status
Simulation time 644562052 ps
CPU time 8.76 seconds
Started Jun 04 12:28:19 PM PDT 24
Finished Jun 04 12:28:29 PM PDT 24
Peak memory 199980 kb
Host smart-ff45267c-9bca-4414-a04f-09a3c279871a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419729803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2419729803
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.2672936965
Short name T251
Test name
Test status
Simulation time 148664693 ps
CPU time 1.21 seconds
Started Jun 04 12:28:20 PM PDT 24
Finished Jun 04 12:28:23 PM PDT 24
Peak memory 199968 kb
Host smart-f534ca6b-8bb1-4b2f-9a35-0d22182fd1f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672936965 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.2672936965
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.996552076
Short name T392
Test name
Test status
Simulation time 6923405985 ps
CPU time 398.82 seconds
Started Jun 04 12:28:17 PM PDT 24
Finished Jun 04 12:34:57 PM PDT 24
Peak memory 199908 kb
Host smart-6224a877-ac90-4728-ae94-b72e41d37652
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996552076 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.996552076
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.3249634364
Short name T213
Test name
Test status
Simulation time 4331603541 ps
CPU time 82.39 seconds
Started Jun 04 12:28:21 PM PDT 24
Finished Jun 04 12:29:44 PM PDT 24
Peak memory 199980 kb
Host smart-da99127a-920a-4aed-9c58-a7bb8841dd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249634364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3249634364
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2938939287
Short name T533
Test name
Test status
Simulation time 41277832 ps
CPU time 0.59 seconds
Started Jun 04 12:28:33 PM PDT 24
Finished Jun 04 12:28:35 PM PDT 24
Peak memory 195776 kb
Host smart-b06dcee6-8c5e-442c-a275-ed9ac2a9caf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938939287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2938939287
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.716440946
Short name T239
Test name
Test status
Simulation time 297085088 ps
CPU time 11.65 seconds
Started Jun 04 12:28:18 PM PDT 24
Finished Jun 04 12:28:30 PM PDT 24
Peak memory 215496 kb
Host smart-96b2ae1d-32cd-4a75-9ad2-759198dece2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=716440946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.716440946
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.2224204673
Short name T519
Test name
Test status
Simulation time 476142629 ps
CPU time 2.74 seconds
Started Jun 04 12:28:22 PM PDT 24
Finished Jun 04 12:28:26 PM PDT 24
Peak memory 199696 kb
Host smart-50422e5c-e998-4ecb-bf5c-673a6daebf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224204673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2224204673
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.1534583905
Short name T527
Test name
Test status
Simulation time 11216766277 ps
CPU time 491.07 seconds
Started Jun 04 12:28:32 PM PDT 24
Finished Jun 04 12:36:44 PM PDT 24
Peak memory 684824 kb
Host smart-358b17de-0e1a-4ae2-a6e3-c00a41f0c821
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1534583905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1534583905
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3693955241
Short name T365
Test name
Test status
Simulation time 294786020 ps
CPU time 4.05 seconds
Started Jun 04 12:28:34 PM PDT 24
Finished Jun 04 12:28:39 PM PDT 24
Peak memory 199788 kb
Host smart-522b42ae-9691-4b72-9f1c-f66d3c46b4f6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693955241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3693955241
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1574062192
Short name T551
Test name
Test status
Simulation time 4669990530 ps
CPU time 24.38 seconds
Started Jun 04 12:28:33 PM PDT 24
Finished Jun 04 12:28:58 PM PDT 24
Peak memory 199904 kb
Host smart-fe62f2bd-5071-48c3-a668-bad4bea1a0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574062192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1574062192
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3767488953
Short name T355
Test name
Test status
Simulation time 165828323 ps
CPU time 5.76 seconds
Started Jun 04 12:28:18 PM PDT 24
Finished Jun 04 12:28:25 PM PDT 24
Peak memory 199872 kb
Host smart-791c0612-37c4-481d-bb63-09a3aaff88f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767488953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3767488953
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.4282426938
Short name T404
Test name
Test status
Simulation time 8552498992 ps
CPU time 498.67 seconds
Started Jun 04 12:28:22 PM PDT 24
Finished Jun 04 12:36:42 PM PDT 24
Peak memory 673836 kb
Host smart-b2825b03-3b48-4fd7-9e46-b8385b00f2f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282426938 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.4282426938
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.3716592560
Short name T127
Test name
Test status
Simulation time 34669535 ps
CPU time 1.29 seconds
Started Jun 04 12:28:18 PM PDT 24
Finished Jun 04 12:28:20 PM PDT 24
Peak memory 199916 kb
Host smart-e69450c3-ddeb-4c9f-8fe3-1302cfadfcb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716592560 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.3716592560
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.3966963923
Short name T433
Test name
Test status
Simulation time 88804081556 ps
CPU time 404.78 seconds
Started Jun 04 12:28:22 PM PDT 24
Finished Jun 04 12:35:08 PM PDT 24
Peak memory 200028 kb
Host smart-96b90e08-339b-48e7-b100-cf2bb782711d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966963923 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.3966963923
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3352238569
Short name T112
Test name
Test status
Simulation time 24497872155 ps
CPU time 37.21 seconds
Started Jun 04 12:28:28 PM PDT 24
Finished Jun 04 12:29:07 PM PDT 24
Peak memory 199936 kb
Host smart-79c187a3-cc18-4fe5-abe9-2f3c0954df55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352238569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3352238569
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.2795119936
Short name T499
Test name
Test status
Simulation time 83387219 ps
CPU time 0.61 seconds
Started Jun 04 12:28:28 PM PDT 24
Finished Jun 04 12:28:30 PM PDT 24
Peak memory 196556 kb
Host smart-6510b1a4-0027-447f-98ce-75d49493bfbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795119936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2795119936
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2816900599
Short name T468
Test name
Test status
Simulation time 691662645 ps
CPU time 38.8 seconds
Started Jun 04 12:28:20 PM PDT 24
Finished Jun 04 12:28:59 PM PDT 24
Peak memory 232604 kb
Host smart-644a984c-8fa9-4873-b5f6-f9d3331c742f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2816900599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2816900599
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.132997596
Short name T32
Test name
Test status
Simulation time 3403887818 ps
CPU time 62.48 seconds
Started Jun 04 12:28:26 PM PDT 24
Finished Jun 04 12:29:29 PM PDT 24
Peak memory 199952 kb
Host smart-cd999c74-4ff6-45bc-ae83-c90791c5fec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132997596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.132997596
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.4121399653
Short name T306
Test name
Test status
Simulation time 5355104863 ps
CPU time 617.82 seconds
Started Jun 04 12:28:28 PM PDT 24
Finished Jun 04 12:38:47 PM PDT 24
Peak memory 729232 kb
Host smart-ecaf6ada-83ea-437e-afec-52546cac218c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4121399653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.4121399653
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.1703176885
Short name T260
Test name
Test status
Simulation time 6224524764 ps
CPU time 41.7 seconds
Started Jun 04 12:28:29 PM PDT 24
Finished Jun 04 12:29:12 PM PDT 24
Peak memory 199900 kb
Host smart-c00c8b17-2c2d-47b1-859b-8cab823073e0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703176885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1703176885
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.3716295976
Short name T180
Test name
Test status
Simulation time 6027614754 ps
CPU time 31.65 seconds
Started Jun 04 12:28:33 PM PDT 24
Finished Jun 04 12:29:05 PM PDT 24
Peak memory 199908 kb
Host smart-1d1e480f-e68f-4a70-836c-2bff9a7ab194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716295976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3716295976
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.870311437
Short name T297
Test name
Test status
Simulation time 242167684 ps
CPU time 2.28 seconds
Started Jun 04 12:28:32 PM PDT 24
Finished Jun 04 12:28:35 PM PDT 24
Peak memory 199840 kb
Host smart-29c82f2f-ba26-49f1-aacc-fc4a1ed731a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870311437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.870311437
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.3391811805
Short name T295
Test name
Test status
Simulation time 2721555598 ps
CPU time 139.87 seconds
Started Jun 04 12:28:29 PM PDT 24
Finished Jun 04 12:30:50 PM PDT 24
Peak memory 199928 kb
Host smart-a38561ed-5b73-450a-9f7b-46536fdce20e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391811805 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3391811805
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.1070250433
Short name T367
Test name
Test status
Simulation time 244108828 ps
CPU time 1.29 seconds
Started Jun 04 12:28:27 PM PDT 24
Finished Jun 04 12:28:29 PM PDT 24
Peak memory 199960 kb
Host smart-fe253868-c4c5-477e-8432-de64bf50c66f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070250433 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.1070250433
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.1182068507
Short name T351
Test name
Test status
Simulation time 14812812688 ps
CPU time 443.09 seconds
Started Jun 04 12:28:28 PM PDT 24
Finished Jun 04 12:35:52 PM PDT 24
Peak memory 199976 kb
Host smart-8c96088c-ddf4-4a2f-9e7f-585954a87a4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182068507 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.1182068507
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.3397039656
Short name T1
Test name
Test status
Simulation time 2846580877 ps
CPU time 57.13 seconds
Started Jun 04 12:28:29 PM PDT 24
Finished Jun 04 12:29:27 PM PDT 24
Peak memory 199872 kb
Host smart-be0ef278-f422-45dc-9935-9e23758b4ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397039656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3397039656
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.1089850553
Short name T255
Test name
Test status
Simulation time 37471673 ps
CPU time 0.58 seconds
Started Jun 04 12:27:15 PM PDT 24
Finished Jun 04 12:27:17 PM PDT 24
Peak memory 194720 kb
Host smart-d6f9db15-0c80-43fb-b38b-fb5ec8c97271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089850553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1089850553
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.1181144951
Short name T243
Test name
Test status
Simulation time 201391999 ps
CPU time 5.48 seconds
Started Jun 04 12:27:17 PM PDT 24
Finished Jun 04 12:27:24 PM PDT 24
Peak memory 199884 kb
Host smart-f126b1ad-eadd-4504-ac3a-5fcb1675a9de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1181144951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1181144951
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.602727995
Short name T341
Test name
Test status
Simulation time 4200783357 ps
CPU time 60.18 seconds
Started Jun 04 12:27:19 PM PDT 24
Finished Jun 04 12:28:21 PM PDT 24
Peak memory 200028 kb
Host smart-744e85dc-9596-4430-b6a6-538df7fd20af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602727995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.602727995
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3876025684
Short name T570
Test name
Test status
Simulation time 6336123434 ps
CPU time 480.44 seconds
Started Jun 04 12:27:16 PM PDT 24
Finished Jun 04 12:35:18 PM PDT 24
Peak memory 719560 kb
Host smart-940ec402-da9a-4aa3-909a-940b08c55996
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3876025684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3876025684
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2992535616
Short name T182
Test name
Test status
Simulation time 2830853097 ps
CPU time 35.9 seconds
Started Jun 04 12:27:16 PM PDT 24
Finished Jun 04 12:27:54 PM PDT 24
Peak memory 199916 kb
Host smart-1833a538-1e91-490f-95a9-ae74ef24eb49
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992535616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2992535616
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.1148617441
Short name T577
Test name
Test status
Simulation time 12735320660 ps
CPU time 61.55 seconds
Started Jun 04 12:27:15 PM PDT 24
Finished Jun 04 12:28:17 PM PDT 24
Peak memory 200060 kb
Host smart-2211fe85-1337-489a-914b-23d52277aa23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148617441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1148617441
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.4043738359
Short name T26
Test name
Test status
Simulation time 358299804 ps
CPU time 1.01 seconds
Started Jun 04 12:27:15 PM PDT 24
Finished Jun 04 12:27:17 PM PDT 24
Peak memory 219376 kb
Host smart-8a9dd470-14d1-4142-b3e8-b82ff28a82e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043738359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.4043738359
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3024852944
Short name T390
Test name
Test status
Simulation time 268490012 ps
CPU time 4.61 seconds
Started Jun 04 12:27:19 PM PDT 24
Finished Jun 04 12:27:25 PM PDT 24
Peak memory 199992 kb
Host smart-a4618282-81b6-4e7a-a681-a9f9413bed62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024852944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3024852944
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.3483886440
Short name T558
Test name
Test status
Simulation time 34437770 ps
CPU time 1.47 seconds
Started Jun 04 12:27:16 PM PDT 24
Finished Jun 04 12:27:20 PM PDT 24
Peak memory 199944 kb
Host smart-eadfd31d-1410-4118-b8c9-1f7cb206fdba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483886440 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.3483886440
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.1877335283
Short name T488
Test name
Test status
Simulation time 8027619258 ps
CPU time 435.68 seconds
Started Jun 04 12:27:16 PM PDT 24
Finished Jun 04 12:34:33 PM PDT 24
Peak memory 199876 kb
Host smart-12538e08-b707-4826-9b77-6691efbcfa0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877335283 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.1877335283
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1673893063
Short name T573
Test name
Test status
Simulation time 5560857632 ps
CPU time 50.7 seconds
Started Jun 04 12:27:18 PM PDT 24
Finished Jun 04 12:28:10 PM PDT 24
Peak memory 199944 kb
Host smart-796a9b2e-4161-46e7-b2d7-3bed07da35fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673893063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1673893063
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.2228512883
Short name T408
Test name
Test status
Simulation time 63200349 ps
CPU time 0.59 seconds
Started Jun 04 12:28:29 PM PDT 24
Finished Jun 04 12:28:31 PM PDT 24
Peak memory 195836 kb
Host smart-8ca023a0-8a9c-4432-b9a2-28e93e2b14e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228512883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2228512883
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1798594639
Short name T41
Test name
Test status
Simulation time 993646681 ps
CPU time 45.27 seconds
Started Jun 04 12:28:28 PM PDT 24
Finished Jun 04 12:29:15 PM PDT 24
Peak memory 220404 kb
Host smart-560ced9e-dcda-483e-9cf9-de0627b0ac02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1798594639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1798594639
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.659750360
Short name T418
Test name
Test status
Simulation time 2637232010 ps
CPU time 24.23 seconds
Started Jun 04 12:28:29 PM PDT 24
Finished Jun 04 12:28:54 PM PDT 24
Peak memory 199980 kb
Host smart-c9907186-0f7f-4ed4-8de6-9b361f7ca3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659750360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.659750360
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.1760559757
Short name T516
Test name
Test status
Simulation time 10215792550 ps
CPU time 594.14 seconds
Started Jun 04 12:28:29 PM PDT 24
Finished Jun 04 12:38:25 PM PDT 24
Peak memory 631660 kb
Host smart-07a18b1b-057f-49b7-8e15-c72f09c947ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1760559757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1760559757
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.2663343593
Short name T233
Test name
Test status
Simulation time 1335252625 ps
CPU time 35.6 seconds
Started Jun 04 12:28:34 PM PDT 24
Finished Jun 04 12:29:11 PM PDT 24
Peak memory 199936 kb
Host smart-8b286c55-2bbd-406f-bb26-074dfc9d4d47
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663343593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2663343593
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1513037296
Short name T272
Test name
Test status
Simulation time 3042279186 ps
CPU time 46.41 seconds
Started Jun 04 12:28:27 PM PDT 24
Finished Jun 04 12:29:15 PM PDT 24
Peak memory 199872 kb
Host smart-57f58e5f-b846-4e6e-86f2-fa327f2f6a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513037296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1513037296
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3764332028
Short name T334
Test name
Test status
Simulation time 264260721 ps
CPU time 5.01 seconds
Started Jun 04 12:28:29 PM PDT 24
Finished Jun 04 12:28:36 PM PDT 24
Peak memory 199952 kb
Host smart-12c21d93-35e4-436b-86ef-138f80244f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764332028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3764332028
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1096255102
Short name T78
Test name
Test status
Simulation time 405752230878 ps
CPU time 1672.12 seconds
Started Jun 04 12:28:34 PM PDT 24
Finished Jun 04 12:56:28 PM PDT 24
Peak memory 608048 kb
Host smart-60cfc7fe-e40f-448f-8745-50714f489720
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096255102 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1096255102
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.3450269638
Short name T80
Test name
Test status
Simulation time 245682395 ps
CPU time 1.37 seconds
Started Jun 04 12:28:28 PM PDT 24
Finished Jun 04 12:28:31 PM PDT 24
Peak memory 199960 kb
Host smart-a0159486-cea5-48d4-ad1c-8f4a85149eea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450269638 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.3450269638
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.1154329408
Short name T428
Test name
Test status
Simulation time 7433027810 ps
CPU time 398.57 seconds
Started Jun 04 12:28:34 PM PDT 24
Finished Jun 04 12:35:14 PM PDT 24
Peak memory 199948 kb
Host smart-cce7c00d-dba4-4979-be2b-58ea3168deb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154329408 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.1154329408
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3981027422
Short name T369
Test name
Test status
Simulation time 1710364726 ps
CPU time 4.7 seconds
Started Jun 04 12:28:29 PM PDT 24
Finished Jun 04 12:28:35 PM PDT 24
Peak memory 200008 kb
Host smart-cad28f3b-0fdf-457c-8852-bbb33ebb55ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981027422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3981027422
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3273666578
Short name T139
Test name
Test status
Simulation time 12659848 ps
CPU time 0.56 seconds
Started Jun 04 12:28:39 PM PDT 24
Finished Jun 04 12:28:41 PM PDT 24
Peak memory 194804 kb
Host smart-ff33dedb-54d1-4541-b823-1a7b3d443318
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273666578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3273666578
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2998405280
Short name T45
Test name
Test status
Simulation time 628634492 ps
CPU time 25.18 seconds
Started Jun 04 12:28:28 PM PDT 24
Finished Jun 04 12:28:55 PM PDT 24
Peak memory 211116 kb
Host smart-ce30809e-68e9-48cc-b7a5-0319da5494a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2998405280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2998405280
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3590887977
Short name T171
Test name
Test status
Simulation time 4103322352 ps
CPU time 27.51 seconds
Started Jun 04 12:28:39 PM PDT 24
Finished Jun 04 12:29:08 PM PDT 24
Peak memory 200020 kb
Host smart-58220d7f-e3af-43aa-9517-8fa5c0ba8311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590887977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3590887977
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2851626162
Short name T394
Test name
Test status
Simulation time 13773276270 ps
CPU time 958.86 seconds
Started Jun 04 12:28:39 PM PDT 24
Finished Jun 04 12:44:39 PM PDT 24
Peak memory 757796 kb
Host smart-d8e5a475-2b94-49db-81d8-ab263f62e9cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2851626162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2851626162
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.1609072037
Short name T324
Test name
Test status
Simulation time 896926272 ps
CPU time 47.33 seconds
Started Jun 04 12:28:40 PM PDT 24
Finished Jun 04 12:29:28 PM PDT 24
Peak memory 199840 kb
Host smart-3ddc04d6-0b92-4506-9389-bab697a4108c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609072037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1609072037
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3537815299
Short name T246
Test name
Test status
Simulation time 1665717317 ps
CPU time 13.62 seconds
Started Jun 04 12:28:30 PM PDT 24
Finished Jun 04 12:28:44 PM PDT 24
Peak memory 199960 kb
Host smart-51d63997-955d-4a62-9f94-9af9a4a6543b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537815299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3537815299
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1126566096
Short name T452
Test name
Test status
Simulation time 103580244 ps
CPU time 3.11 seconds
Started Jun 04 12:28:29 PM PDT 24
Finished Jun 04 12:28:34 PM PDT 24
Peak memory 199920 kb
Host smart-a005cbe4-2996-4818-8177-4563ae5fa4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126566096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1126566096
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2106818158
Short name T446
Test name
Test status
Simulation time 70485822057 ps
CPU time 1553.27 seconds
Started Jun 04 12:28:39 PM PDT 24
Finished Jun 04 12:54:34 PM PDT 24
Peak memory 794412 kb
Host smart-949b7954-87d1-4ab3-80f0-e62f9d45fbcf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106818158 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2106818158
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.3197788149
Short name T429
Test name
Test status
Simulation time 50150361 ps
CPU time 1.13 seconds
Started Jun 04 12:28:39 PM PDT 24
Finished Jun 04 12:28:41 PM PDT 24
Peak memory 199936 kb
Host smart-8c63642f-6eb0-4a36-bfe4-d675adbb2954
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197788149 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.3197788149
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.4125774471
Short name T199
Test name
Test status
Simulation time 15797898230 ps
CPU time 434.53 seconds
Started Jun 04 12:28:41 PM PDT 24
Finished Jun 04 12:35:56 PM PDT 24
Peak memory 199972 kb
Host smart-3652470c-5a10-45c0-83da-cc1e893059b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125774471 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.4125774471
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.368982162
Short name T301
Test name
Test status
Simulation time 401799993 ps
CPU time 2.17 seconds
Started Jun 04 12:28:37 PM PDT 24
Finished Jun 04 12:28:41 PM PDT 24
Peak memory 199908 kb
Host smart-939d7bdf-8ca9-4318-931c-92ca908ee645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368982162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.368982162
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2452048061
Short name T443
Test name
Test status
Simulation time 23055039 ps
CPU time 0.56 seconds
Started Jun 04 12:28:39 PM PDT 24
Finished Jun 04 12:28:41 PM PDT 24
Peak memory 194728 kb
Host smart-69b1d943-5e69-4cef-b1d3-b2e2e116a3c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452048061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2452048061
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2585335246
Short name T391
Test name
Test status
Simulation time 1015681576 ps
CPU time 45.6 seconds
Started Jun 04 12:28:37 PM PDT 24
Finished Jun 04 12:29:23 PM PDT 24
Peak memory 224492 kb
Host smart-aa572024-f826-42e8-85d0-153cbd4b0672
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2585335246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2585335246
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1748091008
Short name T256
Test name
Test status
Simulation time 5204255287 ps
CPU time 19.46 seconds
Started Jun 04 12:28:39 PM PDT 24
Finished Jun 04 12:29:00 PM PDT 24
Peak memory 199908 kb
Host smart-39f75957-0ce0-4a50-915e-ce3c749a267a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748091008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1748091008
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.4185293034
Short name T483
Test name
Test status
Simulation time 6725628205 ps
CPU time 593.59 seconds
Started Jun 04 12:28:38 PM PDT 24
Finished Jun 04 12:38:33 PM PDT 24
Peak memory 690328 kb
Host smart-0835bff9-1dab-4cd3-a4a9-5f755eb3a3be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4185293034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.4185293034
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.163070136
Short name T534
Test name
Test status
Simulation time 4854097065 ps
CPU time 61.25 seconds
Started Jun 04 12:28:38 PM PDT 24
Finished Jun 04 12:29:41 PM PDT 24
Peak memory 200016 kb
Host smart-ac423a0b-3021-4386-bdd8-11e3e05bb2b3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163070136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.163070136
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.1655770092
Short name T50
Test name
Test status
Simulation time 557123346 ps
CPU time 30.69 seconds
Started Jun 04 12:28:38 PM PDT 24
Finished Jun 04 12:29:11 PM PDT 24
Peak memory 199924 kb
Host smart-1bec5278-7d28-4dce-baa1-7a899f2c670e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655770092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1655770092
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2717183566
Short name T316
Test name
Test status
Simulation time 567612669 ps
CPU time 6.86 seconds
Started Jun 04 12:28:38 PM PDT 24
Finished Jun 04 12:28:46 PM PDT 24
Peak memory 199896 kb
Host smart-0d966622-e13d-400a-aafa-282e977ef08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717183566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2717183566
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1472936053
Short name T76
Test name
Test status
Simulation time 21319477014 ps
CPU time 277.7 seconds
Started Jun 04 12:28:39 PM PDT 24
Finished Jun 04 12:33:18 PM PDT 24
Peak memory 199940 kb
Host smart-e00455fa-48ff-45dd-9f4d-5827f5ac8da9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472936053 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1472936053
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.625284218
Short name T531
Test name
Test status
Simulation time 505955478 ps
CPU time 1.41 seconds
Started Jun 04 12:28:41 PM PDT 24
Finished Jun 04 12:28:43 PM PDT 24
Peak memory 199892 kb
Host smart-323134af-1684-46f1-b345-25f41b62ab47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625284218 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_hmac_vectors.625284218
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.2932929179
Short name T436
Test name
Test status
Simulation time 6564532225 ps
CPU time 375.14 seconds
Started Jun 04 12:28:42 PM PDT 24
Finished Jun 04 12:34:58 PM PDT 24
Peak memory 199880 kb
Host smart-277ce805-4e44-40f8-83ac-7ffdaa913a7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932929179 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.2932929179
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.868145451
Short name T183
Test name
Test status
Simulation time 689330777 ps
CPU time 12.47 seconds
Started Jun 04 12:28:41 PM PDT 24
Finished Jun 04 12:28:54 PM PDT 24
Peak memory 199952 kb
Host smart-145b5a5f-b910-4175-bc78-d63144934b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868145451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.868145451
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2456440229
Short name T497
Test name
Test status
Simulation time 154560887 ps
CPU time 0.57 seconds
Started Jun 04 12:28:37 PM PDT 24
Finished Jun 04 12:28:39 PM PDT 24
Peak memory 195792 kb
Host smart-42728fb8-f4ea-42c7-8371-56015c1b4704
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456440229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2456440229
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.2367440695
Short name T340
Test name
Test status
Simulation time 876009649 ps
CPU time 35.67 seconds
Started Jun 04 12:28:38 PM PDT 24
Finished Jun 04 12:29:14 PM PDT 24
Peak memory 216344 kb
Host smart-fd45da99-f4ea-4c73-a49f-f5323dcd2b12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2367440695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2367440695
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1743143240
Short name T398
Test name
Test status
Simulation time 2538518059 ps
CPU time 328.16 seconds
Started Jun 04 12:28:42 PM PDT 24
Finished Jun 04 12:34:11 PM PDT 24
Peak memory 664160 kb
Host smart-ce2708ac-cf13-477d-89bd-b6c2715647a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1743143240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1743143240
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.3410858978
Short name T435
Test name
Test status
Simulation time 209155352 ps
CPU time 6.26 seconds
Started Jun 04 12:28:42 PM PDT 24
Finished Jun 04 12:28:49 PM PDT 24
Peak memory 199840 kb
Host smart-1a7caf8b-ba67-4da1-9425-cc377e7cc2bc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410858978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.3410858978
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.1349922418
Short name T526
Test name
Test status
Simulation time 2322895736 ps
CPU time 31.78 seconds
Started Jun 04 12:28:38 PM PDT 24
Finished Jun 04 12:29:11 PM PDT 24
Peak memory 199988 kb
Host smart-1d69a29d-7376-440f-968f-c5dfb1487d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349922418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1349922418
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1273440751
Short name T459
Test name
Test status
Simulation time 739453293 ps
CPU time 6.7 seconds
Started Jun 04 12:28:39 PM PDT 24
Finished Jun 04 12:28:47 PM PDT 24
Peak memory 199796 kb
Host smart-404f612c-6d91-4f80-a424-44d9c4ee29ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273440751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1273440751
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3037940164
Short name T378
Test name
Test status
Simulation time 10409131972 ps
CPU time 131.63 seconds
Started Jun 04 12:28:44 PM PDT 24
Finished Jun 04 12:30:57 PM PDT 24
Peak memory 224480 kb
Host smart-40005026-db48-4c55-b189-1674976a51c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037940164 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3037940164
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.2803358733
Short name T427
Test name
Test status
Simulation time 69192485 ps
CPU time 1.04 seconds
Started Jun 04 12:28:39 PM PDT 24
Finished Jun 04 12:28:42 PM PDT 24
Peak memory 199532 kb
Host smart-8f0bc001-ba2e-4045-9855-38232fba05c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803358733 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.2803358733
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.681688160
Short name T595
Test name
Test status
Simulation time 125447745610 ps
CPU time 512.01 seconds
Started Jun 04 12:28:42 PM PDT 24
Finished Jun 04 12:37:15 PM PDT 24
Peak memory 200000 kb
Host smart-7428f43d-6c0b-4e7a-bc60-d97ed120392c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681688160 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.681688160
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.1313990286
Short name T310
Test name
Test status
Simulation time 1462118766 ps
CPU time 56.13 seconds
Started Jun 04 12:28:41 PM PDT 24
Finished Jun 04 12:29:38 PM PDT 24
Peak memory 199904 kb
Host smart-30d8622c-56ea-4b7f-aa7a-439943eca01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313990286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1313990286
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2783251663
Short name T510
Test name
Test status
Simulation time 13949474 ps
CPU time 0.6 seconds
Started Jun 04 12:28:49 PM PDT 24
Finished Jun 04 12:28:50 PM PDT 24
Peak memory 195804 kb
Host smart-9d8d7010-bcb2-4e61-9a97-30c1c9df4956
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783251663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2783251663
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.732682347
Short name T66
Test name
Test status
Simulation time 625730792 ps
CPU time 8.83 seconds
Started Jun 04 12:28:39 PM PDT 24
Finished Jun 04 12:28:49 PM PDT 24
Peak memory 208120 kb
Host smart-f56e0514-8a0b-47b2-b27d-9500381087fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=732682347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.732682347
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1188871237
Short name T456
Test name
Test status
Simulation time 11292021082 ps
CPU time 53.22 seconds
Started Jun 04 12:28:50 PM PDT 24
Finished Jun 04 12:29:45 PM PDT 24
Peak memory 199920 kb
Host smart-3a22e6ba-3ad3-4e5e-82da-e7a3c3bca698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188871237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1188871237
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.2851505440
Short name T529
Test name
Test status
Simulation time 6619956761 ps
CPU time 841.71 seconds
Started Jun 04 12:28:50 PM PDT 24
Finished Jun 04 12:42:54 PM PDT 24
Peak memory 741920 kb
Host smart-b647d80f-bea4-4081-827c-224c2c1cf329
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2851505440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2851505440
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.2422738824
Short name T186
Test name
Test status
Simulation time 378344516 ps
CPU time 5.24 seconds
Started Jun 04 12:28:36 PM PDT 24
Finished Jun 04 12:28:42 PM PDT 24
Peak memory 199964 kb
Host smart-a64cea90-d196-4390-a2e7-2ac24d49ff2f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422738824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2422738824
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.4120956347
Short name T240
Test name
Test status
Simulation time 4336324220 ps
CPU time 62.17 seconds
Started Jun 04 12:28:51 PM PDT 24
Finished Jun 04 12:29:54 PM PDT 24
Peak memory 199936 kb
Host smart-5520cb23-afe0-4f4c-9c51-75ab2e5ea5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120956347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.4120956347
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1896320596
Short name T377
Test name
Test status
Simulation time 2270932289 ps
CPU time 12.81 seconds
Started Jun 04 12:28:44 PM PDT 24
Finished Jun 04 12:28:58 PM PDT 24
Peak memory 199920 kb
Host smart-7fef5376-1335-47ad-9468-87ec2d989a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896320596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1896320596
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.226606480
Short name T383
Test name
Test status
Simulation time 118225043 ps
CPU time 1.06 seconds
Started Jun 04 12:28:50 PM PDT 24
Finished Jun 04 12:28:53 PM PDT 24
Peak memory 199700 kb
Host smart-d0e021a4-4c89-4d3a-9749-d2901df4edd6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226606480 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.hmac_test_hmac_vectors.226606480
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.2084300931
Short name T524
Test name
Test status
Simulation time 31999779397 ps
CPU time 430.18 seconds
Started Jun 04 12:28:50 PM PDT 24
Finished Jun 04 12:36:02 PM PDT 24
Peak memory 199948 kb
Host smart-5a02e1a1-d084-49b5-9d9b-d93ae52076d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084300931 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.2084300931
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2899028973
Short name T249
Test name
Test status
Simulation time 682747973 ps
CPU time 35.28 seconds
Started Jun 04 12:28:40 PM PDT 24
Finished Jun 04 12:29:16 PM PDT 24
Peak memory 199952 kb
Host smart-82596c93-c2ce-4b18-9aa7-abac83b364a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899028973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2899028973
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.978105401
Short name T567
Test name
Test status
Simulation time 32950962 ps
CPU time 0.58 seconds
Started Jun 04 12:28:50 PM PDT 24
Finished Jun 04 12:28:53 PM PDT 24
Peak memory 195804 kb
Host smart-48d0832b-dbab-4df6-9ad8-fb40d2932404
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978105401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.978105401
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.3609906673
Short name T259
Test name
Test status
Simulation time 238805814 ps
CPU time 10.93 seconds
Started Jun 04 12:28:49 PM PDT 24
Finished Jun 04 12:29:01 PM PDT 24
Peak memory 199920 kb
Host smart-bc1fb30c-6020-44ff-83a7-f010c9bb670d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3609906673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3609906673
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3004576852
Short name T159
Test name
Test status
Simulation time 171962659 ps
CPU time 2.96 seconds
Started Jun 04 12:28:49 PM PDT 24
Finished Jun 04 12:28:53 PM PDT 24
Peak memory 199752 kb
Host smart-834339b6-7eaa-4399-a821-c19d2d5af9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004576852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3004576852
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3103501709
Short name T348
Test name
Test status
Simulation time 1795483156 ps
CPU time 368.2 seconds
Started Jun 04 12:28:47 PM PDT 24
Finished Jun 04 12:34:56 PM PDT 24
Peak memory 666756 kb
Host smart-2f7305a4-fe79-4f44-89df-b5a07ac3af3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3103501709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3103501709
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.4036307999
Short name T472
Test name
Test status
Simulation time 5002213549 ps
CPU time 90.26 seconds
Started Jun 04 12:28:48 PM PDT 24
Finished Jun 04 12:30:19 PM PDT 24
Peak memory 199956 kb
Host smart-5680a39d-18ad-4f47-9121-a21407c5469f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036307999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.4036307999
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3843983572
Short name T412
Test name
Test status
Simulation time 4878000197 ps
CPU time 68.38 seconds
Started Jun 04 12:28:49 PM PDT 24
Finished Jun 04 12:29:58 PM PDT 24
Peak memory 199924 kb
Host smart-5c35fd55-1cb8-4c6c-ae2f-417a8f4806b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843983572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3843983572
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.3199343112
Short name T478
Test name
Test status
Simulation time 31332914 ps
CPU time 1.19 seconds
Started Jun 04 12:28:45 PM PDT 24
Finished Jun 04 12:28:47 PM PDT 24
Peak memory 199860 kb
Host smart-8bda179b-1afd-421a-84d7-1721cd28bb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199343112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3199343112
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.705024633
Short name T571
Test name
Test status
Simulation time 67772862963 ps
CPU time 604.04 seconds
Started Jun 04 12:28:46 PM PDT 24
Finished Jun 04 12:38:51 PM PDT 24
Peak memory 248428 kb
Host smart-6530c9d4-6fc4-4f4b-a79d-2832ba1f1507
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705024633 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.705024633
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.3591719293
Short name T405
Test name
Test status
Simulation time 34569956 ps
CPU time 1.26 seconds
Started Jun 04 12:28:47 PM PDT 24
Finished Jun 04 12:28:50 PM PDT 24
Peak memory 199944 kb
Host smart-3aff0fb5-4735-42b7-b430-115061966427
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591719293 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.3591719293
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.3915956980
Short name T414
Test name
Test status
Simulation time 27798744633 ps
CPU time 496.79 seconds
Started Jun 04 12:28:50 PM PDT 24
Finished Jun 04 12:37:09 PM PDT 24
Peak memory 200036 kb
Host smart-196ddf00-8b41-4c4b-a9bd-f4ca80f1f50a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915956980 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.3915956980
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.1809804637
Short name T208
Test name
Test status
Simulation time 3548614135 ps
CPU time 76.56 seconds
Started Jun 04 12:28:48 PM PDT 24
Finished Jun 04 12:30:06 PM PDT 24
Peak memory 200016 kb
Host smart-1d16ebfd-209b-4ac0-b276-19d631c1800e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809804637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.1809804637
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1512524974
Short name T19
Test name
Test status
Simulation time 132783566 ps
CPU time 0.53 seconds
Started Jun 04 12:28:49 PM PDT 24
Finished Jun 04 12:28:51 PM PDT 24
Peak memory 194740 kb
Host smart-b0ced459-a859-4739-b11d-7d6f16dd2cb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512524974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1512524974
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.2530327821
Short name T47
Test name
Test status
Simulation time 810618653 ps
CPU time 9.42 seconds
Started Jun 04 12:28:49 PM PDT 24
Finished Jun 04 12:29:00 PM PDT 24
Peak memory 199928 kb
Host smart-d33ebb5f-8c92-468d-aacc-07843005d426
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2530327821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2530327821
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.164356535
Short name T482
Test name
Test status
Simulation time 1139739168 ps
CPU time 64.26 seconds
Started Jun 04 12:28:48 PM PDT 24
Finished Jun 04 12:29:54 PM PDT 24
Peak memory 199852 kb
Host smart-8b6d4e26-797e-4b46-8653-ebe098884fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164356535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.164356535
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.4086780730
Short name T303
Test name
Test status
Simulation time 2250110183 ps
CPU time 506.52 seconds
Started Jun 04 12:28:48 PM PDT 24
Finished Jun 04 12:37:16 PM PDT 24
Peak memory 624980 kb
Host smart-c1451867-9fd1-4dff-a7cf-b0ea694f5d87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4086780730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.4086780730
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.196225846
Short name T366
Test name
Test status
Simulation time 7812798530 ps
CPU time 102.18 seconds
Started Jun 04 12:28:50 PM PDT 24
Finished Jun 04 12:30:34 PM PDT 24
Peak memory 200000 kb
Host smart-798daa4e-40c9-4dcc-be68-90fe7edb1ea8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196225846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.196225846
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_smoke.4235139915
Short name T151
Test name
Test status
Simulation time 5116837370 ps
CPU time 14.73 seconds
Started Jun 04 12:28:48 PM PDT 24
Finished Jun 04 12:29:04 PM PDT 24
Peak memory 199996 kb
Host smart-08cf9e68-81ec-44fc-b690-ba35467be4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235139915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.4235139915
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.3754643621
Short name T289
Test name
Test status
Simulation time 68555680037 ps
CPU time 834.22 seconds
Started Jun 04 12:28:50 PM PDT 24
Finished Jun 04 12:42:46 PM PDT 24
Peak memory 240468 kb
Host smart-94b31de1-1262-4666-b607-577768d01d8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754643621 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.3754643621
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.457996696
Short name T415
Test name
Test status
Simulation time 69126471 ps
CPU time 1.37 seconds
Started Jun 04 12:28:50 PM PDT 24
Finished Jun 04 12:28:54 PM PDT 24
Peak memory 199844 kb
Host smart-997a708f-2f0f-4020-908a-da6866c46355
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457996696 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.hmac_test_hmac_vectors.457996696
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.1586011466
Short name T267
Test name
Test status
Simulation time 88922467879 ps
CPU time 548.86 seconds
Started Jun 04 12:28:48 PM PDT 24
Finished Jun 04 12:37:58 PM PDT 24
Peak memory 199920 kb
Host smart-ef90c2a0-3cfb-4505-8347-1bd28da8ef91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586011466 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.1586011466
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.848314039
Short name T430
Test name
Test status
Simulation time 7252108130 ps
CPU time 62.78 seconds
Started Jun 04 12:28:50 PM PDT 24
Finished Jun 04 12:29:54 PM PDT 24
Peak memory 199904 kb
Host smart-97aa121a-a6eb-4fe3-834a-8b6ada87a5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848314039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.848314039
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.1815805154
Short name T141
Test name
Test status
Simulation time 42865730 ps
CPU time 0.64 seconds
Started Jun 04 12:29:02 PM PDT 24
Finished Jun 04 12:29:04 PM PDT 24
Peak memory 194780 kb
Host smart-99e68a19-e649-4e85-bd11-07d015b491b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815805154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.1815805154
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.3015895855
Short name T106
Test name
Test status
Simulation time 449274084 ps
CPU time 10.18 seconds
Started Jun 04 12:28:57 PM PDT 24
Finished Jun 04 12:29:08 PM PDT 24
Peak memory 208188 kb
Host smart-bd2ffd51-a75a-45cb-adb6-556c3a150182
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3015895855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3015895855
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3358205962
Short name T386
Test name
Test status
Simulation time 6633241727 ps
CPU time 44.12 seconds
Started Jun 04 12:29:01 PM PDT 24
Finished Jun 04 12:29:47 PM PDT 24
Peak memory 199964 kb
Host smart-5d5e10b2-2ee4-4206-a69c-cbaa8328268f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358205962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3358205962
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2023315562
Short name T515
Test name
Test status
Simulation time 2811607993 ps
CPU time 645.94 seconds
Started Jun 04 12:29:04 PM PDT 24
Finished Jun 04 12:39:51 PM PDT 24
Peak memory 728992 kb
Host smart-370b44fe-7aca-4255-8fe2-252ce15c92e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2023315562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2023315562
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3050120068
Short name T329
Test name
Test status
Simulation time 21506729086 ps
CPU time 50.83 seconds
Started Jun 04 12:28:58 PM PDT 24
Finished Jun 04 12:29:50 PM PDT 24
Peak memory 199944 kb
Host smart-9983f9ff-893d-41d9-b08a-680eeb11e24b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050120068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3050120068
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3707590880
Short name T189
Test name
Test status
Simulation time 4976272197 ps
CPU time 95.05 seconds
Started Jun 04 12:28:47 PM PDT 24
Finished Jun 04 12:30:23 PM PDT 24
Peak memory 199892 kb
Host smart-97d3b8b6-b475-44db-b0e2-a14c56bae68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707590880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3707590880
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2238256576
Short name T547
Test name
Test status
Simulation time 160852681 ps
CPU time 1.99 seconds
Started Jun 04 12:28:49 PM PDT 24
Finished Jun 04 12:28:53 PM PDT 24
Peak memory 199928 kb
Host smart-41497f74-1c7a-44bb-8706-82ce976b0c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238256576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2238256576
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.3707713086
Short name T375
Test name
Test status
Simulation time 23510252148 ps
CPU time 311.13 seconds
Started Jun 04 12:29:01 PM PDT 24
Finished Jun 04 12:34:15 PM PDT 24
Peak memory 199980 kb
Host smart-2dddeaf7-c1ee-4d9c-9c87-5804379e318e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707713086 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3707713086
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.2764633853
Short name T160
Test name
Test status
Simulation time 74852052 ps
CPU time 1.32 seconds
Started Jun 04 12:28:57 PM PDT 24
Finished Jun 04 12:29:00 PM PDT 24
Peak memory 199888 kb
Host smart-23946bff-1450-4e13-8e65-165189d9b19d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764633853 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.2764633853
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.516635150
Short name T342
Test name
Test status
Simulation time 35263801985 ps
CPU time 353.23 seconds
Started Jun 04 12:28:59 PM PDT 24
Finished Jun 04 12:34:54 PM PDT 24
Peak memory 199848 kb
Host smart-c501c99d-89d2-4118-8029-8cad3903dd5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516635150 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.516635150
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1841412425
Short name T539
Test name
Test status
Simulation time 4036822239 ps
CPU time 73.04 seconds
Started Jun 04 12:29:02 PM PDT 24
Finished Jun 04 12:30:17 PM PDT 24
Peak memory 199912 kb
Host smart-c029b3b6-ce06-45c0-b41f-a50e018c9c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841412425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1841412425
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.1141179910
Short name T152
Test name
Test status
Simulation time 52678541 ps
CPU time 0.56 seconds
Started Jun 04 12:29:00 PM PDT 24
Finished Jun 04 12:29:03 PM PDT 24
Peak memory 194844 kb
Host smart-a12d2d03-2554-4c00-b955-1592da8d3dcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141179910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1141179910
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.462574262
Short name T14
Test name
Test status
Simulation time 847084273 ps
CPU time 39.57 seconds
Started Jun 04 12:28:57 PM PDT 24
Finished Jun 04 12:29:38 PM PDT 24
Peak memory 216328 kb
Host smart-370194f2-bccc-42c1-aba7-44b17925f62e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=462574262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.462574262
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3095628220
Short name T198
Test name
Test status
Simulation time 2693261298 ps
CPU time 54.35 seconds
Started Jun 04 12:29:02 PM PDT 24
Finished Jun 04 12:29:58 PM PDT 24
Peak memory 199960 kb
Host smart-e6b542ed-1e8d-4081-b68f-d3d6b1d181e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095628220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3095628220
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.1964443802
Short name T145
Test name
Test status
Simulation time 2529004441 ps
CPU time 625.06 seconds
Started Jun 04 12:29:00 PM PDT 24
Finished Jun 04 12:39:27 PM PDT 24
Peak memory 715908 kb
Host smart-aad4d2e1-2053-4397-9ada-152ffdac1441
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1964443802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.1964443802
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2758489214
Short name T473
Test name
Test status
Simulation time 49343882201 ps
CPU time 200.98 seconds
Started Jun 04 12:28:59 PM PDT 24
Finished Jun 04 12:32:22 PM PDT 24
Peak memory 199976 kb
Host smart-6126d777-376f-49e7-bb56-c0651b75d865
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758489214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2758489214
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.2120034277
Short name T23
Test name
Test status
Simulation time 6987783841 ps
CPU time 101.38 seconds
Started Jun 04 12:28:59 PM PDT 24
Finished Jun 04 12:30:43 PM PDT 24
Peak memory 199972 kb
Host smart-f794ba11-36a1-4a6b-b607-f2ffb94db56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120034277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2120034277
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2242513176
Short name T307
Test name
Test status
Simulation time 1071199477 ps
CPU time 9.65 seconds
Started Jun 04 12:28:57 PM PDT 24
Finished Jun 04 12:29:07 PM PDT 24
Peak memory 199924 kb
Host smart-9e1b50c1-e564-4b7b-a5b6-93bdcff55167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242513176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2242513176
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.307167997
Short name T20
Test name
Test status
Simulation time 27070039204 ps
CPU time 178.59 seconds
Started Jun 04 12:29:00 PM PDT 24
Finished Jun 04 12:32:01 PM PDT 24
Peak memory 249080 kb
Host smart-cb4065b7-113c-4ba8-9955-f97e33dc3c96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307167997 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.307167997
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.1561839661
Short name T275
Test name
Test status
Simulation time 218352965 ps
CPU time 1.15 seconds
Started Jun 04 12:28:59 PM PDT 24
Finished Jun 04 12:29:02 PM PDT 24
Peak memory 199812 kb
Host smart-86600c73-6b9f-4b1d-aea6-3c6e0abba034
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561839661 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.1561839661
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.1943662402
Short name T202
Test name
Test status
Simulation time 244642423821 ps
CPU time 437.99 seconds
Started Jun 04 12:28:59 PM PDT 24
Finished Jun 04 12:36:19 PM PDT 24
Peak memory 199864 kb
Host smart-8face35b-c897-4138-921a-1142d46ca4fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943662402 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.1943662402
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.258652233
Short name T528
Test name
Test status
Simulation time 2732110860 ps
CPU time 50.78 seconds
Started Jun 04 12:28:58 PM PDT 24
Finished Jun 04 12:29:51 PM PDT 24
Peak memory 199996 kb
Host smart-2b27873c-c172-4a4e-a817-d91e45120b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258652233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.258652233
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.942736582
Short name T589
Test name
Test status
Simulation time 14535053 ps
CPU time 0.57 seconds
Started Jun 04 12:28:56 PM PDT 24
Finished Jun 04 12:28:58 PM PDT 24
Peak memory 194748 kb
Host smart-86c0af35-20dd-46f6-a758-6b255ef89d38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942736582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.942736582
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3001327932
Short name T309
Test name
Test status
Simulation time 510971138 ps
CPU time 5.8 seconds
Started Jun 04 12:29:00 PM PDT 24
Finished Jun 04 12:29:08 PM PDT 24
Peak memory 208056 kb
Host smart-7598ce3c-fbe4-49e6-ba53-c03d737169c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3001327932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3001327932
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1400064514
Short name T471
Test name
Test status
Simulation time 51196473 ps
CPU time 1.23 seconds
Started Jun 04 12:29:02 PM PDT 24
Finished Jun 04 12:29:05 PM PDT 24
Peak memory 199632 kb
Host smart-0c948929-12b4-40da-9f0c-ae301f9ac524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400064514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1400064514
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3105279524
Short name T576
Test name
Test status
Simulation time 43344156575 ps
CPU time 739.38 seconds
Started Jun 04 12:28:58 PM PDT 24
Finished Jun 04 12:41:19 PM PDT 24
Peak memory 717336 kb
Host smart-5ffad8db-2c81-4de2-a25a-96ffb80f5144
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3105279524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3105279524
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.700370322
Short name T336
Test name
Test status
Simulation time 951054539 ps
CPU time 53.81 seconds
Started Jun 04 12:28:59 PM PDT 24
Finished Jun 04 12:29:54 PM PDT 24
Peak memory 199992 kb
Host smart-3fd8a694-e63f-4a5e-bbc4-689e2d6d9ad8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700370322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.700370322
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.2718895448
Short name T437
Test name
Test status
Simulation time 2462159868 ps
CPU time 71.77 seconds
Started Jun 04 12:29:00 PM PDT 24
Finished Jun 04 12:30:14 PM PDT 24
Peak memory 199964 kb
Host smart-5d812ce6-9e1f-46f7-a033-838f51d16887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718895448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.2718895448
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2980747162
Short name T174
Test name
Test status
Simulation time 38469374 ps
CPU time 0.96 seconds
Started Jun 04 12:29:00 PM PDT 24
Finished Jun 04 12:29:03 PM PDT 24
Peak memory 198868 kb
Host smart-c204ce1f-df02-40ac-8acf-ce5394cd9812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980747162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2980747162
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3811967631
Short name T35
Test name
Test status
Simulation time 28462121 ps
CPU time 0.75 seconds
Started Jun 04 12:29:02 PM PDT 24
Finished Jun 04 12:29:04 PM PDT 24
Peak memory 195476 kb
Host smart-24628e3b-bc16-4d49-8c50-f221b774a0a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811967631 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3811967631
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.2533893117
Short name T439
Test name
Test status
Simulation time 61558102 ps
CPU time 1.3 seconds
Started Jun 04 12:29:01 PM PDT 24
Finished Jun 04 12:29:04 PM PDT 24
Peak memory 199828 kb
Host smart-a59705bd-db91-454a-a208-073c8e3c7234
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533893117 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.2533893117
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.1821943870
Short name T327
Test name
Test status
Simulation time 54451769514 ps
CPU time 535.31 seconds
Started Jun 04 12:28:59 PM PDT 24
Finished Jun 04 12:37:56 PM PDT 24
Peak memory 199980 kb
Host smart-413180d5-db60-4ce2-aa0f-90170dcb0c9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821943870 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.1821943870
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.4259790919
Short name T505
Test name
Test status
Simulation time 511525686 ps
CPU time 23.04 seconds
Started Jun 04 12:28:57 PM PDT 24
Finished Jun 04 12:29:22 PM PDT 24
Peak memory 199904 kb
Host smart-b9d12e8b-c812-4688-a460-01bbd5371527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259790919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.4259790919
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.59558868
Short name T568
Test name
Test status
Simulation time 25915202 ps
CPU time 0.58 seconds
Started Jun 04 12:27:26 PM PDT 24
Finished Jun 04 12:27:28 PM PDT 24
Peak memory 195864 kb
Host smart-d01654b4-5be3-4dd3-b740-62d5ee594c6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59558868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.59558868
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3874696477
Short name T44
Test name
Test status
Simulation time 156641669 ps
CPU time 2.54 seconds
Started Jun 04 12:27:28 PM PDT 24
Finished Jun 04 12:27:32 PM PDT 24
Peak memory 207904 kb
Host smart-081cd218-7f00-4fe1-b7e7-f63bf7499d54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3874696477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3874696477
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.1351369532
Short name T395
Test name
Test status
Simulation time 497936614 ps
CPU time 5.09 seconds
Started Jun 04 12:27:24 PM PDT 24
Finished Jun 04 12:27:30 PM PDT 24
Peak memory 199864 kb
Host smart-f97a2989-309f-4209-82c7-7af6684f018f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351369532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.1351369532
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.3298083689
Short name T311
Test name
Test status
Simulation time 790189152 ps
CPU time 227.13 seconds
Started Jun 04 12:27:18 PM PDT 24
Finished Jun 04 12:31:06 PM PDT 24
Peak memory 672972 kb
Host smart-fa82ac8a-e88f-451f-94eb-5a4c070605b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3298083689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.3298083689
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.883842647
Short name T491
Test name
Test status
Simulation time 1914785995 ps
CPU time 107.97 seconds
Started Jun 04 12:27:23 PM PDT 24
Finished Jun 04 12:29:12 PM PDT 24
Peak memory 200092 kb
Host smart-580bbfd6-ff02-4526-8c99-9f618cbb0b07
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883842647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.883842647
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.411695234
Short name T434
Test name
Test status
Simulation time 3542293843 ps
CPU time 68.79 seconds
Started Jun 04 12:27:17 PM PDT 24
Finished Jun 04 12:28:27 PM PDT 24
Peak memory 199956 kb
Host smart-e347294a-c65c-455e-9e54-93b475e3580f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411695234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.411695234
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1957079876
Short name T27
Test name
Test status
Simulation time 37280288 ps
CPU time 0.78 seconds
Started Jun 04 12:27:26 PM PDT 24
Finished Jun 04 12:27:29 PM PDT 24
Peak memory 218296 kb
Host smart-fadab1cd-3550-4349-a919-d309c228ddf5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957079876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1957079876
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.2473374052
Short name T153
Test name
Test status
Simulation time 463429368 ps
CPU time 4.22 seconds
Started Jun 04 12:27:28 PM PDT 24
Finished Jun 04 12:27:34 PM PDT 24
Peak memory 199836 kb
Host smart-102167e0-711f-4491-9201-2fe68c7c57a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473374052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2473374052
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2408645238
Short name T354
Test name
Test status
Simulation time 23489452318 ps
CPU time 455.46 seconds
Started Jun 04 12:27:28 PM PDT 24
Finished Jun 04 12:35:06 PM PDT 24
Peak memory 656964 kb
Host smart-5556a68e-69fd-45a4-9cf9-ff0e67d82adb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408645238 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2408645238
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.4196524415
Short name T211
Test name
Test status
Simulation time 269276314 ps
CPU time 1.09 seconds
Started Jun 04 12:27:23 PM PDT 24
Finished Jun 04 12:27:25 PM PDT 24
Peak memory 199936 kb
Host smart-37a0b2cb-a085-4d4f-a957-623406d1e35f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196524415 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.4196524415
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.2044469199
Short name T215
Test name
Test status
Simulation time 14410228898 ps
CPU time 395.07 seconds
Started Jun 04 12:27:25 PM PDT 24
Finished Jun 04 12:34:02 PM PDT 24
Peak memory 199892 kb
Host smart-378d7d53-908c-4397-b641-85c3d22dc097
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044469199 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.2044469199
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.3778935439
Short name T158
Test name
Test status
Simulation time 558732352 ps
CPU time 12.97 seconds
Started Jun 04 12:27:28 PM PDT 24
Finished Jun 04 12:27:43 PM PDT 24
Peak memory 199900 kb
Host smart-078673d4-5b14-45ff-bbb4-4a7c47004cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778935439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3778935439
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3606827027
Short name T264
Test name
Test status
Simulation time 39095396 ps
CPU time 0.57 seconds
Started Jun 04 12:29:01 PM PDT 24
Finished Jun 04 12:29:03 PM PDT 24
Peak memory 195716 kb
Host smart-f5690fc7-a3a0-42d6-aead-0839b8206889
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606827027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3606827027
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.2866681579
Short name T541
Test name
Test status
Simulation time 309832027 ps
CPU time 21.07 seconds
Started Jun 04 12:29:01 PM PDT 24
Finished Jun 04 12:29:24 PM PDT 24
Peak memory 232344 kb
Host smart-c152a4bc-a577-40fa-a198-13f98215c1c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2866681579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2866681579
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3537091250
Short name T480
Test name
Test status
Simulation time 1662264400 ps
CPU time 12.96 seconds
Started Jun 04 12:28:58 PM PDT 24
Finished Jun 04 12:29:13 PM PDT 24
Peak memory 200076 kb
Host smart-98485e74-baa0-4b17-8d58-70f98aa7a46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537091250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3537091250
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1258488887
Short name T165
Test name
Test status
Simulation time 7162104769 ps
CPU time 321.46 seconds
Started Jun 04 12:28:59 PM PDT 24
Finished Jun 04 12:34:22 PM PDT 24
Peak memory 450092 kb
Host smart-9e02eddb-6e96-4de5-9df0-b2f396e1da11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1258488887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1258488887
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2091994051
Short name T590
Test name
Test status
Simulation time 51771887729 ps
CPU time 220.15 seconds
Started Jun 04 12:28:59 PM PDT 24
Finished Jun 04 12:32:41 PM PDT 24
Peak memory 199944 kb
Host smart-28da47ea-cf07-4e7b-a1f4-e719493190aa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091994051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2091994051
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.40034082
Short name T470
Test name
Test status
Simulation time 8610343628 ps
CPU time 58.31 seconds
Started Jun 04 12:28:58 PM PDT 24
Finished Jun 04 12:29:58 PM PDT 24
Peak memory 200000 kb
Host smart-63f50d4f-befc-480b-899d-6b6f01c49d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40034082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.40034082
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2952754832
Short name T261
Test name
Test status
Simulation time 1083467661 ps
CPU time 6.36 seconds
Started Jun 04 12:28:58 PM PDT 24
Finished Jun 04 12:29:06 PM PDT 24
Peak memory 199816 kb
Host smart-3ba0eaa5-5d32-4ad0-83b8-da5fc068fa7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952754832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2952754832
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2548960694
Short name T201
Test name
Test status
Simulation time 73367696506 ps
CPU time 535.44 seconds
Started Jun 04 12:28:58 PM PDT 24
Finished Jun 04 12:37:55 PM PDT 24
Peak memory 218336 kb
Host smart-3985b106-c184-4840-9ff1-050cd5c147f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548960694 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2548960694
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.3061299337
Short name T148
Test name
Test status
Simulation time 301657489 ps
CPU time 1.39 seconds
Started Jun 04 12:28:59 PM PDT 24
Finished Jun 04 12:29:02 PM PDT 24
Peak memory 200044 kb
Host smart-f835e714-8771-48c1-8ddc-455a3c4e5cff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061299337 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.3061299337
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.1311738091
Short name T506
Test name
Test status
Simulation time 35496384148 ps
CPU time 432.29 seconds
Started Jun 04 12:29:00 PM PDT 24
Finished Jun 04 12:36:14 PM PDT 24
Peak memory 199988 kb
Host smart-c3881ef4-1653-41fe-8554-685118aeab24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311738091 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.1311738091
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.1658563075
Short name T353
Test name
Test status
Simulation time 4650279315 ps
CPU time 16.86 seconds
Started Jun 04 12:29:00 PM PDT 24
Finished Jun 04 12:29:19 PM PDT 24
Peak memory 199932 kb
Host smart-e9cb3f9f-8cc1-448f-bbff-da884e1e2234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658563075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1658563075
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1255470281
Short name T520
Test name
Test status
Simulation time 283930548 ps
CPU time 0.59 seconds
Started Jun 04 12:29:12 PM PDT 24
Finished Jun 04 12:29:14 PM PDT 24
Peak memory 195556 kb
Host smart-34c8f28a-a422-43a4-9864-335c0e25b530
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255470281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1255470281
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.4031636886
Short name T379
Test name
Test status
Simulation time 701907537 ps
CPU time 29.67 seconds
Started Jun 04 12:29:10 PM PDT 24
Finished Jun 04 12:29:40 PM PDT 24
Peak memory 211992 kb
Host smart-0c0ab483-f611-454e-a654-149b4f543627
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4031636886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.4031636886
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1821711169
Short name T125
Test name
Test status
Simulation time 164014733 ps
CPU time 7.65 seconds
Started Jun 04 12:29:11 PM PDT 24
Finished Jun 04 12:29:20 PM PDT 24
Peak memory 199936 kb
Host smart-ef780889-e46d-4e28-bbf3-c3bfcd997c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821711169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1821711169
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.446690913
Short name T322
Test name
Test status
Simulation time 2346646263 ps
CPU time 698.75 seconds
Started Jun 04 12:29:12 PM PDT 24
Finished Jun 04 12:40:52 PM PDT 24
Peak memory 730676 kb
Host smart-20eca053-473e-4cd0-82ff-e245e9f45222
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=446690913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.446690913
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2144945935
Short name T238
Test name
Test status
Simulation time 4129432644 ps
CPU time 19.92 seconds
Started Jun 04 12:29:10 PM PDT 24
Finished Jun 04 12:29:31 PM PDT 24
Peak memory 199976 kb
Host smart-326d91a5-91c2-4d49-bf81-311f8355de8f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144945935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2144945935
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.351158185
Short name T36
Test name
Test status
Simulation time 9567171532 ps
CPU time 50.87 seconds
Started Jun 04 12:29:11 PM PDT 24
Finished Jun 04 12:30:03 PM PDT 24
Peak memory 200020 kb
Host smart-06ccb563-3112-48d3-b3f3-0a2c68e1e1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351158185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.351158185
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.4075721924
Short name T138
Test name
Test status
Simulation time 1189514029 ps
CPU time 9.18 seconds
Started Jun 04 12:29:11 PM PDT 24
Finished Jun 04 12:29:21 PM PDT 24
Peak memory 199868 kb
Host smart-c08f10d9-1414-4242-976b-0a886f25e69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075721924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.4075721924
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1939319715
Short name T82
Test name
Test status
Simulation time 63318493146 ps
CPU time 2081.35 seconds
Started Jun 04 12:29:10 PM PDT 24
Finished Jun 04 01:03:53 PM PDT 24
Peak memory 741744 kb
Host smart-089bed65-9f6c-4140-becf-7e9cdf51302e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939319715 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1939319715
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.3815965349
Short name T431
Test name
Test status
Simulation time 193915008 ps
CPU time 1.12 seconds
Started Jun 04 12:29:08 PM PDT 24
Finished Jun 04 12:29:10 PM PDT 24
Peak memory 200008 kb
Host smart-21650818-c082-4a3b-8263-618e77de795f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815965349 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.3815965349
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.2066960587
Short name T450
Test name
Test status
Simulation time 208666633871 ps
CPU time 481.37 seconds
Started Jun 04 12:29:09 PM PDT 24
Finished Jun 04 12:37:11 PM PDT 24
Peak memory 199988 kb
Host smart-ceb670ad-887c-4632-b3af-4a05b5355524
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066960587 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.2066960587
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3908385726
Short name T396
Test name
Test status
Simulation time 36649559 ps
CPU time 2 seconds
Started Jun 04 12:29:08 PM PDT 24
Finished Jun 04 12:29:11 PM PDT 24
Peak memory 199820 kb
Host smart-fc2d9294-0dd7-4df6-a794-2dadc8fe9c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908385726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3908385726
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.79177004
Short name T557
Test name
Test status
Simulation time 16537264 ps
CPU time 0.64 seconds
Started Jun 04 12:29:13 PM PDT 24
Finished Jun 04 12:29:14 PM PDT 24
Peak memory 195772 kb
Host smart-fc628375-45f4-48de-9c8c-c3fe0cf32db1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79177004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.79177004
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1909527498
Short name T522
Test name
Test status
Simulation time 9954803715 ps
CPU time 38.87 seconds
Started Jun 04 12:29:09 PM PDT 24
Finished Jun 04 12:29:49 PM PDT 24
Peak memory 224664 kb
Host smart-64c065fc-16d8-4a4d-aa40-624b4b1d6ee1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1909527498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1909527498
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1865417333
Short name T467
Test name
Test status
Simulation time 4490511863 ps
CPU time 62.48 seconds
Started Jun 04 12:29:11 PM PDT 24
Finished Jun 04 12:30:15 PM PDT 24
Peak memory 199972 kb
Host smart-7ccc4607-ce83-4e17-a776-6854ead94344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865417333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1865417333
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1811958194
Short name T585
Test name
Test status
Simulation time 727021118 ps
CPU time 148.27 seconds
Started Jun 04 12:29:11 PM PDT 24
Finished Jun 04 12:31:40 PM PDT 24
Peak memory 433028 kb
Host smart-1b8773b2-fb80-4c32-9330-c8dbf54544b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1811958194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1811958194
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2916572853
Short name T554
Test name
Test status
Simulation time 3509961872 ps
CPU time 43.42 seconds
Started Jun 04 12:29:09 PM PDT 24
Finished Jun 04 12:29:53 PM PDT 24
Peak memory 199764 kb
Host smart-b8bec6f9-abb2-43db-8024-8747a309ed01
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916572853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2916572853
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.4036433274
Short name T194
Test name
Test status
Simulation time 5397920051 ps
CPU time 39.19 seconds
Started Jun 04 12:29:09 PM PDT 24
Finished Jun 04 12:29:49 PM PDT 24
Peak memory 199964 kb
Host smart-8fbc9117-5e00-4535-970c-88adc60f9293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036433274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.4036433274
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1078124927
Short name T30
Test name
Test status
Simulation time 68038359 ps
CPU time 1.88 seconds
Started Jun 04 12:29:14 PM PDT 24
Finished Jun 04 12:29:17 PM PDT 24
Peak memory 199904 kb
Host smart-bf40fbd1-0731-41ed-9b7e-88338aac474e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078124927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1078124927
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.1272562486
Short name T542
Test name
Test status
Simulation time 114132243068 ps
CPU time 2937.66 seconds
Started Jun 04 12:29:11 PM PDT 24
Finished Jun 04 01:18:10 PM PDT 24
Peak memory 827780 kb
Host smart-a38e8823-91e8-4e43-a3dd-3c0445a7cf66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272562486 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1272562486
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.3425443837
Short name T270
Test name
Test status
Simulation time 573888984 ps
CPU time 1.44 seconds
Started Jun 04 12:29:11 PM PDT 24
Finished Jun 04 12:29:14 PM PDT 24
Peak memory 199932 kb
Host smart-e64765b4-fb25-44e7-a500-89ec0585b46f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425443837 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.3425443837
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.483879755
Short name T409
Test name
Test status
Simulation time 16520023588 ps
CPU time 461.04 seconds
Started Jun 04 12:29:11 PM PDT 24
Finished Jun 04 12:36:53 PM PDT 24
Peak memory 200000 kb
Host smart-68b4dc9a-0d5c-441f-b8b4-eb28a79ba818
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483879755 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.483879755
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.1196073713
Short name T583
Test name
Test status
Simulation time 120651450 ps
CPU time 3.75 seconds
Started Jun 04 12:29:12 PM PDT 24
Finished Jun 04 12:29:17 PM PDT 24
Peak memory 199920 kb
Host smart-1e9fa749-b534-4fbf-b4ad-4c99f48be59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196073713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1196073713
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3504099536
Short name T140
Test name
Test status
Simulation time 14111560 ps
CPU time 0.6 seconds
Started Jun 04 12:29:20 PM PDT 24
Finished Jun 04 12:29:21 PM PDT 24
Peak memory 194744 kb
Host smart-694a03ae-1523-4ffe-b7ba-4dd0d33adcbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504099536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3504099536
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.4048146753
Short name T578
Test name
Test status
Simulation time 421237256 ps
CPU time 14.18 seconds
Started Jun 04 12:29:10 PM PDT 24
Finished Jun 04 12:29:26 PM PDT 24
Peak memory 208112 kb
Host smart-c6075cca-e378-46c7-bcd1-9d14f4c41878
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4048146753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.4048146753
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2282775956
Short name T312
Test name
Test status
Simulation time 60608449809 ps
CPU time 69.9 seconds
Started Jun 04 12:29:11 PM PDT 24
Finished Jun 04 12:30:22 PM PDT 24
Peak memory 199964 kb
Host smart-36823067-d023-4de2-86b2-32f22e893699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282775956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2282775956
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2606924685
Short name T376
Test name
Test status
Simulation time 2091352709 ps
CPU time 458.52 seconds
Started Jun 04 12:29:10 PM PDT 24
Finished Jun 04 12:36:49 PM PDT 24
Peak memory 517184 kb
Host smart-c0cb8f72-ecee-4e2b-a356-14711a0f0fe0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2606924685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2606924685
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.770942447
Short name T518
Test name
Test status
Simulation time 1341583071 ps
CPU time 68.34 seconds
Started Jun 04 12:29:09 PM PDT 24
Finished Jun 04 12:30:18 PM PDT 24
Peak memory 199908 kb
Host smart-6c6a9fa3-9e21-430d-97f5-51cecfd0be03
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770942447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.770942447
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3909912576
Short name T4
Test name
Test status
Simulation time 6813869359 ps
CPU time 96.3 seconds
Started Jun 04 12:29:12 PM PDT 24
Finished Jun 04 12:30:49 PM PDT 24
Peak memory 200084 kb
Host smart-8c3b8a1a-56f6-4c72-bedc-966cedcb38e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909912576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3909912576
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.1603314227
Short name T343
Test name
Test status
Simulation time 1737000447 ps
CPU time 8.53 seconds
Started Jun 04 12:29:10 PM PDT 24
Finished Jun 04 12:29:20 PM PDT 24
Peak memory 199992 kb
Host smart-750f5ce0-21c5-4219-91e4-2b7622fd22bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603314227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1603314227
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.2256637030
Short name T181
Test name
Test status
Simulation time 39698923618 ps
CPU time 582.05 seconds
Started Jun 04 12:29:21 PM PDT 24
Finished Jun 04 12:39:04 PM PDT 24
Peak memory 208236 kb
Host smart-38dc55f6-db1e-469e-b7ea-ee8fd62f9af2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256637030 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2256637030
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.3462387309
Short name T81
Test name
Test status
Simulation time 267735088 ps
CPU time 1.12 seconds
Started Jun 04 12:29:19 PM PDT 24
Finished Jun 04 12:29:21 PM PDT 24
Peak memory 199864 kb
Host smart-b8efd7d0-341b-47c3-8cb9-bb4756cf3e81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462387309 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.3462387309
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.3754176958
Short name T258
Test name
Test status
Simulation time 37039715305 ps
CPU time 487.05 seconds
Started Jun 04 12:29:26 PM PDT 24
Finished Jun 04 12:37:35 PM PDT 24
Peak memory 199624 kb
Host smart-d657dab4-3cd7-40f5-b978-3f5c2d18c2f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754176958 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.3754176958
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.3844651909
Short name T559
Test name
Test status
Simulation time 1349167432 ps
CPU time 13.24 seconds
Started Jun 04 12:29:19 PM PDT 24
Finished Jun 04 12:29:33 PM PDT 24
Peak memory 199852 kb
Host smart-06cb3ac3-f0ca-4fee-80d9-b4e9b41c46fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844651909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3844651909
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3024115824
Short name T444
Test name
Test status
Simulation time 88496176 ps
CPU time 0.61 seconds
Started Jun 04 12:29:26 PM PDT 24
Finished Jun 04 12:29:29 PM PDT 24
Peak memory 196180 kb
Host smart-e572c89e-01d4-46d8-86c4-a04d5d4a4652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024115824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3024115824
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2559353843
Short name T42
Test name
Test status
Simulation time 251761054 ps
CPU time 16.62 seconds
Started Jun 04 12:29:22 PM PDT 24
Finished Jun 04 12:29:40 PM PDT 24
Peak memory 225100 kb
Host smart-234b91d2-6897-4892-8aa6-47f965eff179
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2559353843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2559353843
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.2308230645
Short name T402
Test name
Test status
Simulation time 1590930668 ps
CPU time 32.5 seconds
Started Jun 04 12:29:20 PM PDT 24
Finished Jun 04 12:29:53 PM PDT 24
Peak memory 199948 kb
Host smart-39c3f1a4-523d-49d8-8f30-1feaf98d4438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308230645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2308230645
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1541974019
Short name T209
Test name
Test status
Simulation time 4404811715 ps
CPU time 591.7 seconds
Started Jun 04 12:29:21 PM PDT 24
Finished Jun 04 12:39:14 PM PDT 24
Peak memory 727104 kb
Host smart-dd229eb8-2a67-4d0f-83ce-3549f295bec5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1541974019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1541974019
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3400488068
Short name T247
Test name
Test status
Simulation time 14810354734 ps
CPU time 132.11 seconds
Started Jun 04 12:29:21 PM PDT 24
Finished Jun 04 12:31:34 PM PDT 24
Peak memory 199928 kb
Host smart-dbaf6a2d-dc45-4426-8156-1efb890b24b5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400488068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3400488068
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.877908468
Short name T525
Test name
Test status
Simulation time 2920605313 ps
CPU time 51.85 seconds
Started Jun 04 12:29:27 PM PDT 24
Finished Jun 04 12:30:21 PM PDT 24
Peak memory 199948 kb
Host smart-49190900-5a80-4295-b294-75be93412fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877908468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.877908468
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.457838123
Short name T273
Test name
Test status
Simulation time 818927044 ps
CPU time 4.4 seconds
Started Jun 04 12:29:19 PM PDT 24
Finished Jun 04 12:29:24 PM PDT 24
Peak memory 199832 kb
Host smart-18d6506f-b0a2-46c4-8eac-713f6f54194d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457838123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.457838123
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2077291028
Short name T296
Test name
Test status
Simulation time 2348023967 ps
CPU time 361.72 seconds
Started Jun 04 12:29:31 PM PDT 24
Finished Jun 04 12:35:34 PM PDT 24
Peak memory 587408 kb
Host smart-244a2045-6660-403c-bbb4-f7b7afe4192f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077291028 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2077291028
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_stress_all_with_rand_reset.360728031
Short name T6
Test name
Test status
Simulation time 50508867336 ps
CPU time 2166.93 seconds
Started Jun 04 12:29:21 PM PDT 24
Finished Jun 04 01:05:29 PM PDT 24
Peak memory 816648 kb
Host smart-48a8faa8-e2d5-4c7b-8d9b-9257f8e51d9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=360728031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all_with_rand_reset.360728031
Directory /workspace/44.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.3156675390
Short name T477
Test name
Test status
Simulation time 87620586 ps
CPU time 1.39 seconds
Started Jun 04 12:29:26 PM PDT 24
Finished Jun 04 12:29:28 PM PDT 24
Peak memory 199836 kb
Host smart-bdb74f3d-9111-46b4-af36-b7e236555ee0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156675390 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.3156675390
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.332087874
Short name T285
Test name
Test status
Simulation time 33972415312 ps
CPU time 495.94 seconds
Started Jun 04 12:29:27 PM PDT 24
Finished Jun 04 12:37:46 PM PDT 24
Peak memory 200212 kb
Host smart-fdff663e-4e2b-4d7b-bbb7-c2aaff64b5f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332087874 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.332087874
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.3947708570
Short name T136
Test name
Test status
Simulation time 116324490 ps
CPU time 5.39 seconds
Started Jun 04 12:29:22 PM PDT 24
Finished Jun 04 12:29:28 PM PDT 24
Peak memory 199924 kb
Host smart-c9cd8bf1-8ad7-4eea-b480-a1eb3a4b7de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947708570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.3947708570
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.1524490184
Short name T214
Test name
Test status
Simulation time 24384989 ps
CPU time 0.59 seconds
Started Jun 04 12:29:19 PM PDT 24
Finished Jun 04 12:29:21 PM PDT 24
Peak memory 194760 kb
Host smart-7f762d98-8b16-4eb5-a9b2-849e21be27fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524490184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1524490184
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1951427341
Short name T481
Test name
Test status
Simulation time 3332936000 ps
CPU time 43.01 seconds
Started Jun 04 12:29:22 PM PDT 24
Finished Jun 04 12:30:06 PM PDT 24
Peak memory 226560 kb
Host smart-4ce0576c-83ca-4278-96ff-8c7a508648e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1951427341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1951427341
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.4235941562
Short name T362
Test name
Test status
Simulation time 69851236073 ps
CPU time 91.27 seconds
Started Jun 04 12:29:19 PM PDT 24
Finished Jun 04 12:30:51 PM PDT 24
Peak memory 199948 kb
Host smart-f1ba6961-fcd4-4709-8af4-d618f8e52723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235941562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.4235941562
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1960267970
Short name T588
Test name
Test status
Simulation time 3145929439 ps
CPU time 633.83 seconds
Started Jun 04 12:29:29 PM PDT 24
Finished Jun 04 12:40:05 PM PDT 24
Peak memory 660056 kb
Host smart-89a06652-a888-4672-8035-7c53387f4cac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1960267970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1960267970
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.4234909471
Short name T423
Test name
Test status
Simulation time 7319556932 ps
CPU time 100.8 seconds
Started Jun 04 12:29:18 PM PDT 24
Finished Jun 04 12:31:00 PM PDT 24
Peak memory 199932 kb
Host smart-139de45d-4439-495e-9423-f7160e230d26
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234909471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.4234909471
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1487181821
Short name T230
Test name
Test status
Simulation time 939056316 ps
CPU time 16.96 seconds
Started Jun 04 12:29:20 PM PDT 24
Finished Jun 04 12:29:38 PM PDT 24
Peak memory 199940 kb
Host smart-1531b5e5-fb42-450e-b355-859e2c112a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487181821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1487181821
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3605774874
Short name T167
Test name
Test status
Simulation time 500863906 ps
CPU time 4.17 seconds
Started Jun 04 12:29:18 PM PDT 24
Finished Jun 04 12:29:23 PM PDT 24
Peak memory 199932 kb
Host smart-f2b9c0e7-d3bc-4cdc-a32c-2e82f958804a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605774874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3605774874
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.3190953746
Short name T187
Test name
Test status
Simulation time 12243758052 ps
CPU time 672.4 seconds
Started Jun 04 12:29:20 PM PDT 24
Finished Jun 04 12:40:33 PM PDT 24
Peak memory 225520 kb
Host smart-05fe8abd-935b-46b5-af88-105f81e0cf1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190953746 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.3190953746
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.576304150
Short name T421
Test name
Test status
Simulation time 91823299 ps
CPU time 1.07 seconds
Started Jun 04 12:29:26 PM PDT 24
Finished Jun 04 12:29:28 PM PDT 24
Peak memory 199832 kb
Host smart-80b6afd0-8276-4228-9c60-0db14271e07e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576304150 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_hmac_vectors.576304150
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.1855752191
Short name T333
Test name
Test status
Simulation time 15584530360 ps
CPU time 423.41 seconds
Started Jun 04 12:29:20 PM PDT 24
Finished Jun 04 12:36:25 PM PDT 24
Peak memory 199916 kb
Host smart-9c8246b1-f84d-42d1-9b0d-fe5db4b8f253
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855752191 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.1855752191
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3428852741
Short name T432
Test name
Test status
Simulation time 90674935360 ps
CPU time 97.48 seconds
Started Jun 04 12:29:19 PM PDT 24
Finished Jun 04 12:30:58 PM PDT 24
Peak memory 200064 kb
Host smart-6afb4384-c6e4-4e0c-8199-e6626fe939d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428852741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3428852741
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.931729215
Short name T51
Test name
Test status
Simulation time 10391098 ps
CPU time 0.56 seconds
Started Jun 04 12:29:26 PM PDT 24
Finished Jun 04 12:29:28 PM PDT 24
Peak memory 194748 kb
Host smart-f35d1de0-62a8-4a97-99f2-5f71d830e5cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931729215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.931729215
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3356972289
Short name T466
Test name
Test status
Simulation time 3387682740 ps
CPU time 35.89 seconds
Started Jun 04 12:29:21 PM PDT 24
Finished Jun 04 12:29:58 PM PDT 24
Peak memory 223364 kb
Host smart-15c53161-2140-4390-8013-c9ee73bade5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3356972289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3356972289
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1878005645
Short name T349
Test name
Test status
Simulation time 255049387 ps
CPU time 5.14 seconds
Started Jun 04 12:29:27 PM PDT 24
Finished Jun 04 12:29:34 PM PDT 24
Peak memory 199772 kb
Host smart-3adf0090-0717-482f-81ed-b32d214fe5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878005645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1878005645
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3821421223
Short name T190
Test name
Test status
Simulation time 1780818264 ps
CPU time 103.87 seconds
Started Jun 04 12:29:23 PM PDT 24
Finished Jun 04 12:31:07 PM PDT 24
Peak memory 436452 kb
Host smart-3c98d43e-74b6-42fa-84ca-d861c7960d9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3821421223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3821421223
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.300094631
Short name T137
Test name
Test status
Simulation time 556408326 ps
CPU time 3.59 seconds
Started Jun 04 12:29:27 PM PDT 24
Finished Jun 04 12:29:33 PM PDT 24
Peak memory 199816 kb
Host smart-a6981467-d52a-42b8-80ef-990432903bda
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300094631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.300094631
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1412502408
Short name T142
Test name
Test status
Simulation time 1688265053 ps
CPU time 97.52 seconds
Started Jun 04 12:29:23 PM PDT 24
Finished Jun 04 12:31:01 PM PDT 24
Peak memory 199856 kb
Host smart-32714f9d-fbe5-4b0b-a88e-6d031bffd96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412502408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1412502408
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3522468072
Short name T252
Test name
Test status
Simulation time 517937744 ps
CPU time 7.87 seconds
Started Jun 04 12:29:21 PM PDT 24
Finished Jun 04 12:29:29 PM PDT 24
Peak memory 199960 kb
Host smart-e2805d9a-30c0-4888-b086-fcfdba29d73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522468072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3522468072
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2349378854
Short name T105
Test name
Test status
Simulation time 37523405137 ps
CPU time 2510.17 seconds
Started Jun 04 12:29:27 PM PDT 24
Finished Jun 04 01:11:20 PM PDT 24
Peak memory 754748 kb
Host smart-789315f4-4be0-4be9-ae4b-7922cbb1b3f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349378854 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2349378854
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.254506833
Short name T548
Test name
Test status
Simulation time 49313077 ps
CPU time 1.04 seconds
Started Jun 04 12:29:27 PM PDT 24
Finished Jun 04 12:29:31 PM PDT 24
Peak memory 199692 kb
Host smart-3f235231-2cb4-423e-ab38-947cb35fba56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254506833 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_test_hmac_vectors.254506833
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.170304284
Short name T572
Test name
Test status
Simulation time 7888691942 ps
CPU time 441.42 seconds
Started Jun 04 12:29:30 PM PDT 24
Finished Jun 04 12:36:53 PM PDT 24
Peak memory 199884 kb
Host smart-f5b84af5-3792-42b7-b6a0-2508864e97d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170304284 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.170304284
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1080441853
Short name T458
Test name
Test status
Simulation time 21648416089 ps
CPU time 85.82 seconds
Started Jun 04 12:29:31 PM PDT 24
Finished Jun 04 12:30:58 PM PDT 24
Peak memory 199972 kb
Host smart-9d11802a-4165-4387-b12a-6f918f890421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080441853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1080441853
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3042186203
Short name T231
Test name
Test status
Simulation time 15512893 ps
CPU time 0.59 seconds
Started Jun 04 12:29:29 PM PDT 24
Finished Jun 04 12:29:32 PM PDT 24
Peak memory 194704 kb
Host smart-995cfdff-46c6-4166-8d00-5e56664396a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042186203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3042186203
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1748865389
Short name T254
Test name
Test status
Simulation time 615790730 ps
CPU time 29.39 seconds
Started Jun 04 12:29:28 PM PDT 24
Finished Jun 04 12:30:00 PM PDT 24
Peak memory 199908 kb
Host smart-4abe9ae7-719a-4c17-a9e7-cee43f19bd22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1748865389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1748865389
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.349778327
Short name T242
Test name
Test status
Simulation time 5007955220 ps
CPU time 64.27 seconds
Started Jun 04 12:29:27 PM PDT 24
Finished Jun 04 12:30:33 PM PDT 24
Peak memory 199872 kb
Host smart-1127a6b1-87e2-4fe6-ae3c-3d33780f0918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349778327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.349778327
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1429041807
Short name T212
Test name
Test status
Simulation time 9449840546 ps
CPU time 532.58 seconds
Started Jun 04 12:29:29 PM PDT 24
Finished Jun 04 12:38:24 PM PDT 24
Peak memory 645572 kb
Host smart-472a4779-1ae0-418c-873d-2c2d8712c8eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1429041807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1429041807
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2059896345
Short name T530
Test name
Test status
Simulation time 18982553713 ps
CPU time 250.77 seconds
Started Jun 04 12:29:29 PM PDT 24
Finished Jun 04 12:33:42 PM PDT 24
Peak memory 199984 kb
Host smart-958fb103-14ad-42cf-8825-4b408b67bd4d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059896345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2059896345
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.2404550170
Short name T347
Test name
Test status
Simulation time 236404412 ps
CPU time 4.06 seconds
Started Jun 04 12:29:29 PM PDT 24
Finished Jun 04 12:29:35 PM PDT 24
Peak memory 199948 kb
Host smart-68bc9555-a5b6-4d72-a40f-be721154baf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404550170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2404550170
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2881427142
Short name T356
Test name
Test status
Simulation time 4099050628 ps
CPU time 16.93 seconds
Started Jun 04 12:29:28 PM PDT 24
Finished Jun 04 12:29:47 PM PDT 24
Peak memory 199984 kb
Host smart-1288397f-53ce-4c34-afc7-2939c80c0538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881427142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2881427142
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.1919510187
Short name T74
Test name
Test status
Simulation time 829119079931 ps
CPU time 2578.46 seconds
Started Jun 04 12:29:35 PM PDT 24
Finished Jun 04 01:12:35 PM PDT 24
Peak memory 228864 kb
Host smart-e8c1ba5d-1f49-4e5d-ac23-bc81fe70d801
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919510187 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.1919510187
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.1961103675
Short name T144
Test name
Test status
Simulation time 35086494 ps
CPU time 1.18 seconds
Started Jun 04 12:29:29 PM PDT 24
Finished Jun 04 12:29:33 PM PDT 24
Peak memory 199884 kb
Host smart-4f7f32d6-28ac-4ba6-9299-b2d40baf6930
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961103675 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.1961103675
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.1257712694
Short name T563
Test name
Test status
Simulation time 18372543847 ps
CPU time 384.6 seconds
Started Jun 04 12:29:29 PM PDT 24
Finished Jun 04 12:35:56 PM PDT 24
Peak memory 199876 kb
Host smart-16b72c96-60bb-4d3d-870d-0636fb740feb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257712694 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.1257712694
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.2408348089
Short name T234
Test name
Test status
Simulation time 3992809665 ps
CPU time 18.27 seconds
Started Jun 04 12:29:29 PM PDT 24
Finished Jun 04 12:29:50 PM PDT 24
Peak memory 199948 kb
Host smart-b993811b-5ac4-4b1b-bd20-6ae336585b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408348089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2408348089
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3831146452
Short name T507
Test name
Test status
Simulation time 14123206 ps
CPU time 0.6 seconds
Started Jun 04 12:29:35 PM PDT 24
Finished Jun 04 12:29:37 PM PDT 24
Peak memory 196592 kb
Host smart-57fab921-3153-4634-8e66-476974016ba7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831146452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3831146452
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2500891984
Short name T445
Test name
Test status
Simulation time 1036677105 ps
CPU time 26.22 seconds
Started Jun 04 12:29:29 PM PDT 24
Finished Jun 04 12:29:58 PM PDT 24
Peak memory 216060 kb
Host smart-40910dc7-1cd8-4803-8c10-f67162979d46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2500891984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2500891984
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.2213977757
Short name T222
Test name
Test status
Simulation time 542388386 ps
CPU time 28.89 seconds
Started Jun 04 12:29:30 PM PDT 24
Finished Jun 04 12:30:01 PM PDT 24
Peak memory 199852 kb
Host smart-8b546d3b-f5c7-4638-a854-659fe90e4acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213977757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2213977757
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.1849601289
Short name T232
Test name
Test status
Simulation time 15142820763 ps
CPU time 884.56 seconds
Started Jun 04 12:29:30 PM PDT 24
Finished Jun 04 12:44:17 PM PDT 24
Peak memory 693924 kb
Host smart-1007358e-e579-4697-87d8-3a2599ef8a9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1849601289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1849601289
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.585642289
Short name T65
Test name
Test status
Simulation time 62830008474 ps
CPU time 204.96 seconds
Started Jun 04 12:29:27 PM PDT 24
Finished Jun 04 12:32:55 PM PDT 24
Peak memory 200060 kb
Host smart-f58ed27f-52f5-40bf-9039-a42faf2cb4ea
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585642289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.585642289
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.3592617382
Short name T400
Test name
Test status
Simulation time 7760642997 ps
CPU time 71.99 seconds
Started Jun 04 12:29:34 PM PDT 24
Finished Jun 04 12:30:47 PM PDT 24
Peak memory 200040 kb
Host smart-b4ae8ba9-e538-4ace-90c4-33ccf9d72d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592617382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3592617382
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.294708715
Short name T330
Test name
Test status
Simulation time 103100313 ps
CPU time 2.12 seconds
Started Jun 04 12:29:29 PM PDT 24
Finished Jun 04 12:29:34 PM PDT 24
Peak memory 199952 kb
Host smart-fd56b432-5903-49f6-95d8-4bb86d0fdef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294708715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.294708715
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.1166736269
Short name T406
Test name
Test status
Simulation time 140440480425 ps
CPU time 129.68 seconds
Started Jun 04 12:29:27 PM PDT 24
Finished Jun 04 12:31:40 PM PDT 24
Peak memory 200032 kb
Host smart-957368e9-7c9d-4b85-bdc6-8036d19f07f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166736269 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1166736269
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.3246286317
Short name T565
Test name
Test status
Simulation time 164268117 ps
CPU time 1.25 seconds
Started Jun 04 12:29:26 PM PDT 24
Finished Jun 04 12:29:29 PM PDT 24
Peak memory 199892 kb
Host smart-f6730564-dc5d-45e6-b3a7-ac8ee3d5d610
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246286317 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.3246286317
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.1202823071
Short name T389
Test name
Test status
Simulation time 78044517129 ps
CPU time 520.47 seconds
Started Jun 04 12:29:27 PM PDT 24
Finished Jun 04 12:38:11 PM PDT 24
Peak memory 199888 kb
Host smart-7345a444-a3cd-48ce-88ae-c8424a70a806
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202823071 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.1202823071
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.723844442
Short name T84
Test name
Test status
Simulation time 4209406542 ps
CPU time 89.5 seconds
Started Jun 04 12:29:35 PM PDT 24
Finished Jun 04 12:31:06 PM PDT 24
Peak memory 199992 kb
Host smart-44545921-fa21-43b7-a7cc-ec7fc5ddf1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723844442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.723844442
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3662093190
Short name T16
Test name
Test status
Simulation time 12299277 ps
CPU time 0.6 seconds
Started Jun 04 12:29:38 PM PDT 24
Finished Jun 04 12:29:40 PM PDT 24
Peak memory 195860 kb
Host smart-e42dcc2b-7304-4354-8a4b-949a38b21cb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662093190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3662093190
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1033435611
Short name T555
Test name
Test status
Simulation time 1026340616 ps
CPU time 17.2 seconds
Started Jun 04 12:29:27 PM PDT 24
Finished Jun 04 12:29:47 PM PDT 24
Peak memory 216364 kb
Host smart-b947000e-7983-4d2b-8dbd-b00674bc6e68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1033435611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1033435611
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1412227172
Short name T323
Test name
Test status
Simulation time 120662405 ps
CPU time 2.26 seconds
Started Jun 04 12:29:41 PM PDT 24
Finished Jun 04 12:29:44 PM PDT 24
Peak memory 199820 kb
Host smart-fad89a51-4fa2-4cea-b6fc-668bd3df3e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412227172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1412227172
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.1622102326
Short name T457
Test name
Test status
Simulation time 8092749711 ps
CPU time 134.27 seconds
Started Jun 04 12:29:29 PM PDT 24
Finished Jun 04 12:31:45 PM PDT 24
Peak memory 458800 kb
Host smart-533640a8-ade7-45d7-99ce-5c5db3ee6a7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1622102326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1622102326
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.4246526629
Short name T11
Test name
Test status
Simulation time 583206642 ps
CPU time 30.68 seconds
Started Jun 04 12:29:41 PM PDT 24
Finished Jun 04 12:30:12 PM PDT 24
Peak memory 199904 kb
Host smart-6f9066ce-143b-4230-9c01-0926d0fe0284
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246526629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.4246526629
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.65830514
Short name T475
Test name
Test status
Simulation time 5609161159 ps
CPU time 19.35 seconds
Started Jun 04 12:29:27 PM PDT 24
Finished Jun 04 12:29:49 PM PDT 24
Peak memory 199972 kb
Host smart-0439beb7-7ebe-4933-8c08-95a2d20c89a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65830514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.65830514
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.199903864
Short name T154
Test name
Test status
Simulation time 501332610 ps
CPU time 6.57 seconds
Started Jun 04 12:29:29 PM PDT 24
Finished Jun 04 12:29:38 PM PDT 24
Peak memory 199932 kb
Host smart-786f912d-5665-445b-b2fd-6cda7abcf46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199903864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.199903864
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.622109386
Short name T304
Test name
Test status
Simulation time 37161042988 ps
CPU time 927.31 seconds
Started Jun 04 12:29:40 PM PDT 24
Finished Jun 04 12:45:09 PM PDT 24
Peak memory 682784 kb
Host smart-02b79965-4798-4ca2-b7fe-3b1811ebad11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622109386 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.622109386
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.424003698
Short name T241
Test name
Test status
Simulation time 29400449 ps
CPU time 1.03 seconds
Started Jun 04 12:29:39 PM PDT 24
Finished Jun 04 12:29:42 PM PDT 24
Peak memory 199800 kb
Host smart-26b47b2c-ac87-4f70-ac2f-fad9cea8ae87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424003698 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_hmac_vectors.424003698
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.1938847394
Short name T584
Test name
Test status
Simulation time 46663138826 ps
CPU time 438.38 seconds
Started Jun 04 12:29:37 PM PDT 24
Finished Jun 04 12:36:57 PM PDT 24
Peak memory 199956 kb
Host smart-5c6a44d9-09df-40ff-a1d9-693b06ebb02f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938847394 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.1938847394
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1620030883
Short name T205
Test name
Test status
Simulation time 624008007 ps
CPU time 25.44 seconds
Started Jun 04 12:29:42 PM PDT 24
Finished Jun 04 12:30:08 PM PDT 24
Peak memory 199848 kb
Host smart-e3d19233-90a7-46e7-a63d-98c4c75e6640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620030883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1620030883
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.2153761215
Short name T419
Test name
Test status
Simulation time 88664757 ps
CPU time 0.57 seconds
Started Jun 04 12:27:27 PM PDT 24
Finished Jun 04 12:27:30 PM PDT 24
Peak memory 195800 kb
Host smart-1d441750-94f6-4399-8bf1-19ee95b664f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153761215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.2153761215
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.795374302
Short name T43
Test name
Test status
Simulation time 634880478 ps
CPU time 26.71 seconds
Started Jun 04 12:27:25 PM PDT 24
Finished Jun 04 12:27:54 PM PDT 24
Peak memory 221404 kb
Host smart-51799820-71d5-4764-a05c-db78f1ff46e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=795374302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.795374302
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1492388798
Short name T550
Test name
Test status
Simulation time 614782358 ps
CPU time 31.74 seconds
Started Jun 04 12:27:25 PM PDT 24
Finished Jun 04 12:27:59 PM PDT 24
Peak memory 199868 kb
Host smart-205352dc-a915-4c51-81a0-6a5e779c472a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492388798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1492388798
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2701353714
Short name T217
Test name
Test status
Simulation time 74529357 ps
CPU time 2.14 seconds
Started Jun 04 12:27:23 PM PDT 24
Finished Jun 04 12:27:26 PM PDT 24
Peak memory 199940 kb
Host smart-9c2c774d-164c-46e3-9fe3-fe142bbdd802
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2701353714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2701353714
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1865776543
Short name T192
Test name
Test status
Simulation time 3032569005 ps
CPU time 163.76 seconds
Started Jun 04 12:27:26 PM PDT 24
Finished Jun 04 12:30:12 PM PDT 24
Peak memory 199924 kb
Host smart-3141cd54-a5d4-4d3d-9627-163b2cd76f01
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865776543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1865776543
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3817562529
Short name T561
Test name
Test status
Simulation time 3793185998 ps
CPU time 71.37 seconds
Started Jun 04 12:27:25 PM PDT 24
Finished Jun 04 12:28:38 PM PDT 24
Peak memory 200000 kb
Host smart-f6b8b38e-78ff-4476-9d3b-e9871a61c7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817562529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3817562529
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.2581906517
Short name T290
Test name
Test status
Simulation time 620565478 ps
CPU time 5.94 seconds
Started Jun 04 12:27:28 PM PDT 24
Finished Jun 04 12:27:36 PM PDT 24
Peak memory 200000 kb
Host smart-5de1de75-95cf-4b6e-81f6-f91ee78575c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581906517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2581906517
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.4133261512
Short name T485
Test name
Test status
Simulation time 15382843988 ps
CPU time 886.73 seconds
Started Jun 04 12:27:29 PM PDT 24
Finished Jun 04 12:42:18 PM PDT 24
Peak memory 489952 kb
Host smart-ceec8326-5abc-4396-932c-321ef5634051
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133261512 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.4133261512
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.227920286
Short name T277
Test name
Test status
Simulation time 61900994 ps
CPU time 1.32 seconds
Started Jun 04 12:27:27 PM PDT 24
Finished Jun 04 12:27:31 PM PDT 24
Peak memory 199912 kb
Host smart-5c78df41-59f7-4bb7-acfd-adc0a3dbd7c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227920286 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_hmac_vectors.227920286
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.134845189
Short name T440
Test name
Test status
Simulation time 24316717026 ps
CPU time 418.38 seconds
Started Jun 04 12:27:28 PM PDT 24
Finished Jun 04 12:34:29 PM PDT 24
Peak memory 199952 kb
Host smart-e0a4ff57-a16d-440d-ba9b-9e341833b2bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134845189 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.134845189
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3351629022
Short name T508
Test name
Test status
Simulation time 9893954693 ps
CPU time 92.57 seconds
Started Jun 04 12:27:27 PM PDT 24
Finished Jun 04 12:29:02 PM PDT 24
Peak memory 199560 kb
Host smart-7397b97b-42f8-4f7d-8725-987cad6e6b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351629022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3351629022
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.711129739
Short name T308
Test name
Test status
Simulation time 24288609 ps
CPU time 0.6 seconds
Started Jun 04 12:27:28 PM PDT 24
Finished Jun 04 12:27:31 PM PDT 24
Peak memory 196588 kb
Host smart-caf9af19-9d0d-4f3f-affc-4c49c8e29540
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711129739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.711129739
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3627749855
Short name T29
Test name
Test status
Simulation time 2405027615 ps
CPU time 56.45 seconds
Started Jun 04 12:27:24 PM PDT 24
Finished Jun 04 12:28:22 PM PDT 24
Peak memory 228540 kb
Host smart-cc6ff8e1-2bc0-4cbe-9f96-c480e8a873b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3627749855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3627749855
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1870345353
Short name T345
Test name
Test status
Simulation time 5847513138 ps
CPU time 42.22 seconds
Started Jun 04 12:27:31 PM PDT 24
Finished Jun 04 12:28:14 PM PDT 24
Peak memory 199852 kb
Host smart-636191e6-7da4-4e6f-8db2-131e58ea876d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870345353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1870345353
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2975835145
Short name T381
Test name
Test status
Simulation time 2526900776 ps
CPU time 618.6 seconds
Started Jun 04 12:27:27 PM PDT 24
Finished Jun 04 12:37:48 PM PDT 24
Peak memory 712252 kb
Host smart-2f035e09-6e9b-4109-9d93-5443308bfe70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2975835145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2975835145
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.314024346
Short name T300
Test name
Test status
Simulation time 496449528 ps
CPU time 22.93 seconds
Started Jun 04 12:27:28 PM PDT 24
Finished Jun 04 12:27:53 PM PDT 24
Peak memory 199756 kb
Host smart-665fd654-ef91-4fb5-9049-f62e617f1404
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314024346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.314024346
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3804560758
Short name T373
Test name
Test status
Simulation time 8524280909 ps
CPU time 107.48 seconds
Started Jun 04 12:27:24 PM PDT 24
Finished Jun 04 12:29:13 PM PDT 24
Peak memory 199968 kb
Host smart-23697c8e-e254-43a1-8289-e127d9870608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804560758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3804560758
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.1111213822
Short name T150
Test name
Test status
Simulation time 509906871 ps
CPU time 3.23 seconds
Started Jun 04 12:27:22 PM PDT 24
Finished Jun 04 12:27:26 PM PDT 24
Peak memory 199940 kb
Host smart-2d744907-efa1-4758-b8e3-631341f8c30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111213822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1111213822
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.2476309761
Short name T126
Test name
Test status
Simulation time 3329413484 ps
CPU time 50.72 seconds
Started Jun 04 12:27:25 PM PDT 24
Finished Jun 04 12:28:18 PM PDT 24
Peak memory 208176 kb
Host smart-50e2e5a6-46a2-42ac-8fa8-a5265474f641
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476309761 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2476309761
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.2018407872
Short name T178
Test name
Test status
Simulation time 28989890 ps
CPU time 1.11 seconds
Started Jun 04 12:27:27 PM PDT 24
Finished Jun 04 12:27:31 PM PDT 24
Peak memory 199636 kb
Host smart-7f666217-f71f-41f5-a2b0-9361d6a0d216
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018407872 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.2018407872
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.1330037090
Short name T195
Test name
Test status
Simulation time 59450644517 ps
CPU time 521.89 seconds
Started Jun 04 12:27:24 PM PDT 24
Finished Jun 04 12:36:07 PM PDT 24
Peak memory 200008 kb
Host smart-0261bfcc-59d7-4b1c-993d-18be181282b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330037090 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.1330037090
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.3210066581
Short name T197
Test name
Test status
Simulation time 6693255277 ps
CPU time 57.43 seconds
Started Jun 04 12:27:25 PM PDT 24
Finished Jun 04 12:28:25 PM PDT 24
Peak memory 199964 kb
Host smart-c252a38f-5b65-441d-a893-15f42c522c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210066581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3210066581
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3221897472
Short name T580
Test name
Test status
Simulation time 34835567 ps
CPU time 0.63 seconds
Started Jun 04 12:27:26 PM PDT 24
Finished Jun 04 12:27:28 PM PDT 24
Peak memory 194612 kb
Host smart-8a5ae53b-123f-4896-ba8d-6234ead62fe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221897472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3221897472
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.802410004
Short name T474
Test name
Test status
Simulation time 2261771917 ps
CPU time 23.91 seconds
Started Jun 04 12:27:26 PM PDT 24
Finished Jun 04 12:27:52 PM PDT 24
Peak memory 199960 kb
Host smart-76938638-4da8-477d-b257-094aff1ba022
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=802410004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.802410004
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1394686407
Short name T279
Test name
Test status
Simulation time 596788783 ps
CPU time 21.33 seconds
Started Jun 04 12:27:25 PM PDT 24
Finished Jun 04 12:27:49 PM PDT 24
Peak memory 199904 kb
Host smart-63955dd1-9359-440f-a65b-36b4310f9eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394686407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1394686407
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.170336500
Short name T574
Test name
Test status
Simulation time 12860141416 ps
CPU time 622.53 seconds
Started Jun 04 12:27:26 PM PDT 24
Finished Jun 04 12:37:51 PM PDT 24
Peak memory 667784 kb
Host smart-4fef176d-804b-4004-84d9-bfb19e45cb7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=170336500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.170336500
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.4117426467
Short name T371
Test name
Test status
Simulation time 451992298 ps
CPU time 12.19 seconds
Started Jun 04 12:27:25 PM PDT 24
Finished Jun 04 12:27:39 PM PDT 24
Peak memory 199908 kb
Host smart-d1b2e8a9-6994-4aba-84c9-6d0decc98361
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117426467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.4117426467
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3841995206
Short name T276
Test name
Test status
Simulation time 17966944180 ps
CPU time 56.16 seconds
Started Jun 04 12:27:26 PM PDT 24
Finished Jun 04 12:28:25 PM PDT 24
Peak memory 200096 kb
Host smart-549ec178-8927-465a-a9a0-553ab6989dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841995206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3841995206
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.845324828
Short name T579
Test name
Test status
Simulation time 62679882 ps
CPU time 1.34 seconds
Started Jun 04 12:27:25 PM PDT 24
Finished Jun 04 12:27:28 PM PDT 24
Peak memory 199864 kb
Host smart-f9ff088e-b3cc-4c0e-a46c-d09cc1b80f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845324828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.845324828
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1506700314
Short name T75
Test name
Test status
Simulation time 284299724433 ps
CPU time 1223.45 seconds
Started Jun 04 12:27:26 PM PDT 24
Finished Jun 04 12:47:51 PM PDT 24
Peak memory 199836 kb
Host smart-d77510f7-a15e-4834-b773-df51ca15e8a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506700314 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1506700314
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.2082935114
Short name T438
Test name
Test status
Simulation time 51804040 ps
CPU time 1.07 seconds
Started Jun 04 12:27:27 PM PDT 24
Finished Jun 04 12:27:30 PM PDT 24
Peak memory 199812 kb
Host smart-0521cd05-8281-4265-81a0-7737d190f166
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082935114 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.2082935114
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.4025945651
Short name T537
Test name
Test status
Simulation time 37505048153 ps
CPU time 474.11 seconds
Started Jun 04 12:27:24 PM PDT 24
Finished Jun 04 12:35:19 PM PDT 24
Peak memory 199940 kb
Host smart-9041e010-6c13-448b-b8d5-70f5d6b044f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025945651 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.4025945651
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.3838872056
Short name T293
Test name
Test status
Simulation time 5338985247 ps
CPU time 66 seconds
Started Jun 04 12:27:26 PM PDT 24
Finished Jun 04 12:28:35 PM PDT 24
Peak memory 199952 kb
Host smart-be50c0a1-444f-4059-b502-ee0d75b5f004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838872056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3838872056
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/76.hmac_stress_all_with_rand_reset.3843965037
Short name T39
Test name
Test status
Simulation time 209095926395 ps
CPU time 3407.4 seconds
Started Jun 04 12:29:46 PM PDT 24
Finished Jun 04 01:26:35 PM PDT 24
Peak memory 780044 kb
Host smart-f6d5b531-c9d6-41e6-b543-a3c2555f3393
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3843965037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.hmac_stress_all_with_rand_reset.3843965037
Directory /workspace/76.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.436429583
Short name T221
Test name
Test status
Simulation time 11427327 ps
CPU time 0.64 seconds
Started Jun 04 12:27:27 PM PDT 24
Finished Jun 04 12:27:30 PM PDT 24
Peak memory 195536 kb
Host smart-7ffd7c6d-c954-4bad-a424-8026b6fc6596
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436429583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.436429583
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1224155855
Short name T274
Test name
Test status
Simulation time 1095075114 ps
CPU time 23.71 seconds
Started Jun 04 12:27:28 PM PDT 24
Finished Jun 04 12:27:54 PM PDT 24
Peak memory 208080 kb
Host smart-b754b6b8-b0af-46b8-8768-191cc578b5fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1224155855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1224155855
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3889782451
Short name T34
Test name
Test status
Simulation time 19690171250 ps
CPU time 47.28 seconds
Started Jun 04 12:27:26 PM PDT 24
Finished Jun 04 12:28:15 PM PDT 24
Peak memory 199980 kb
Host smart-d4b21792-4c07-4da5-9432-99f1a804695b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889782451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3889782451
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.1831050777
Short name T245
Test name
Test status
Simulation time 7385760392 ps
CPU time 418.97 seconds
Started Jun 04 12:27:28 PM PDT 24
Finished Jun 04 12:34:30 PM PDT 24
Peak memory 694648 kb
Host smart-61e0f1da-69a4-4f38-9725-4d1e2d789300
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1831050777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1831050777
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3243108555
Short name T224
Test name
Test status
Simulation time 13280843870 ps
CPU time 131.05 seconds
Started Jun 04 12:27:25 PM PDT 24
Finished Jun 04 12:29:38 PM PDT 24
Peak memory 199920 kb
Host smart-35fd7689-50e5-428f-b099-4a02915dba42
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243108555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3243108555
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1402093811
Short name T173
Test name
Test status
Simulation time 5776299357 ps
CPU time 115.75 seconds
Started Jun 04 12:27:27 PM PDT 24
Finished Jun 04 12:29:25 PM PDT 24
Peak memory 200068 kb
Host smart-946c0820-d1de-4aaa-ba2a-5ed4f1b3d378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402093811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1402093811
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3253645030
Short name T385
Test name
Test status
Simulation time 929162461 ps
CPU time 6.07 seconds
Started Jun 04 12:27:29 PM PDT 24
Finished Jun 04 12:27:37 PM PDT 24
Peak memory 199844 kb
Host smart-91d144ff-3b22-48ba-a489-57653f758841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253645030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3253645030
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.348178156
Short name T512
Test name
Test status
Simulation time 399987197599 ps
CPU time 3384.75 seconds
Started Jun 04 12:27:28 PM PDT 24
Finished Jun 04 01:23:55 PM PDT 24
Peak memory 839132 kb
Host smart-db4c5dbc-cd38-4f18-86a0-659e5a1f4215
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348178156 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.348178156
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.2987336373
Short name T149
Test name
Test status
Simulation time 29676182 ps
CPU time 1.02 seconds
Started Jun 04 12:27:28 PM PDT 24
Finished Jun 04 12:27:31 PM PDT 24
Peak memory 199640 kb
Host smart-2a6d7e4f-bacb-4448-9489-83c2d6a476dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987336373 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.2987336373
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.83066549
Short name T282
Test name
Test status
Simulation time 47388234262 ps
CPU time 538.59 seconds
Started Jun 04 12:27:27 PM PDT 24
Finished Jun 04 12:36:29 PM PDT 24
Peak memory 199904 kb
Host smart-f222a38a-3233-478b-aea0-e6397e5d167e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83066549 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.83066549
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.3107200812
Short name T8
Test name
Test status
Simulation time 10672244848 ps
CPU time 75.99 seconds
Started Jun 04 12:27:24 PM PDT 24
Finished Jun 04 12:28:41 PM PDT 24
Peak memory 199984 kb
Host smart-5c3796d1-bf47-4f69-9678-9eda699ba7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107200812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3107200812
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3294317522
Short name T591
Test name
Test status
Simulation time 29632425 ps
CPU time 0.58 seconds
Started Jun 04 12:27:32 PM PDT 24
Finished Jun 04 12:27:33 PM PDT 24
Peak memory 194712 kb
Host smart-e1569bd3-528b-4695-a074-2e678d425028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294317522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3294317522
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.3164300928
Short name T185
Test name
Test status
Simulation time 1137766117 ps
CPU time 62.2 seconds
Started Jun 04 12:27:39 PM PDT 24
Finished Jun 04 12:28:42 PM PDT 24
Peak memory 247964 kb
Host smart-fbbd9077-d6c3-4189-8be0-53711334b468
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3164300928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.3164300928
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.4148094427
Short name T305
Test name
Test status
Simulation time 865407535 ps
CPU time 43.07 seconds
Started Jun 04 12:27:39 PM PDT 24
Finished Jun 04 12:28:23 PM PDT 24
Peak memory 199932 kb
Host smart-6d436a41-165b-4215-a2ad-37a758b582dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148094427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.4148094427
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.482283656
Short name T581
Test name
Test status
Simulation time 1121401563 ps
CPU time 243.59 seconds
Started Jun 04 12:27:33 PM PDT 24
Finished Jun 04 12:31:38 PM PDT 24
Peak memory 479416 kb
Host smart-35f6a757-08e6-4f36-ba26-734375df1e7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=482283656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.482283656
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.1937139974
Short name T461
Test name
Test status
Simulation time 96931314452 ps
CPU time 89.73 seconds
Started Jun 04 12:27:32 PM PDT 24
Finished Jun 04 12:29:03 PM PDT 24
Peak memory 199944 kb
Host smart-69588a49-3565-488c-b513-720f356eb315
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937139974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1937139974
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.2900497290
Short name T225
Test name
Test status
Simulation time 1856793729 ps
CPU time 37.34 seconds
Started Jun 04 12:27:35 PM PDT 24
Finished Jun 04 12:28:14 PM PDT 24
Peak memory 199992 kb
Host smart-8a1dcce3-3966-47ad-add7-c044509e522b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900497290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2900497290
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1571593954
Short name T263
Test name
Test status
Simulation time 893658879 ps
CPU time 7.34 seconds
Started Jun 04 12:27:42 PM PDT 24
Finished Jun 04 12:27:51 PM PDT 24
Peak memory 199844 kb
Host smart-f6f46f93-b6c3-4b59-9766-8157a326b7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571593954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1571593954
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1461634401
Short name T101
Test name
Test status
Simulation time 301888915934 ps
CPU time 1662.3 seconds
Started Jun 04 12:27:33 PM PDT 24
Finished Jun 04 12:55:16 PM PDT 24
Peak memory 455752 kb
Host smart-5e5a694f-c1b1-4815-a66f-d0aa24f49bd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461634401 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1461634401
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.282000222
Short name T157
Test name
Test status
Simulation time 48294344 ps
CPU time 1.25 seconds
Started Jun 04 12:27:36 PM PDT 24
Finished Jun 04 12:27:38 PM PDT 24
Peak memory 199968 kb
Host smart-4836f154-808c-4346-839d-c7c919f42a7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282000222 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.hmac_test_hmac_vectors.282000222
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.3408048316
Short name T228
Test name
Test status
Simulation time 18516464657 ps
CPU time 419.94 seconds
Started Jun 04 12:27:33 PM PDT 24
Finished Jun 04 12:34:34 PM PDT 24
Peak memory 199944 kb
Host smart-d5a8c74f-0eaf-4d13-815d-dcab1ed13b91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408048316 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.3408048316
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3983133027
Short name T85
Test name
Test status
Simulation time 8534818245 ps
CPU time 10.65 seconds
Started Jun 04 12:27:34 PM PDT 24
Finished Jun 04 12:27:46 PM PDT 24
Peak memory 199976 kb
Host smart-bcd0329e-1534-45bb-83e1-c17e7a1c24b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983133027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3983133027
Directory /workspace/9.hmac_wipe_secret/latest
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