Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	13441888	1			T1	32		T2	79		T3	64082
all_values[1]	13441888	1			T1	32		T2	79		T3	64082
all_values[2]	13441888	1			T1	32		T2	79		T3	64082

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

119824

1

T14

102

T16

277

T8

3514

auto[1]

40205840

1

T1

96

T2

237

T3

192246

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33484680

1

T1

92

T2

186

T3

165470

auto[1]

6840984

1

T1

4

T2

51

T3

26776

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	41261	1			T14	100		T16	153		T8	1875
all_values[0]	auto[0]	auto[1]	320	1			T14	2		T16	4		T8	6
all_values[0]	auto[1]	auto[0]	13366179	1			T1	28		T2	75		T3	63888
all_values[0]	auto[1]	auto[1]	34128	1			T1	4		T2	4		T3	194
all_values[1]	auto[0]	auto[0]	35720	1			T16	60		T8	1595		T82	10
all_values[1]	auto[0]	auto[1]	145	1			T8	8		T24	1		T52	8
all_values[1]	auto[1]	auto[0]	13405801	1			T1	32		T2	79		T3	64082
all_values[1]	auto[1]	auto[1]	222	1			T8	6		T24	5		T52	1
all_values[2]	auto[0]	auto[0]	21520	1			T16	60		T8	11		T81	4
all_values[2]	auto[0]	auto[1]	20858	1			T8	19		T24	27		T52	233
all_values[2]	auto[1]	auto[0]	6614199	1			T1	32		T2	32		T3	37500
all_values[2]	auto[1]	auto[1]	6785311	1			T2	47		T3	26582		T4	454