Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6075826

1

T1

27

T2

27

T3

37305

auto[1]

2618975

1

T4

585

T5

3067

T6

83

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2569445

1

T4

1860

T17

1

T5

5041

auto[1]

6125356

1

T1

27

T2

27

T3

37305

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5057191

1

T3

37305

T4

1138

T17

276

auto[1]

3637610

1

T1

27

T2

27

T4

1097

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6932872	1			T1	8		T2	24		T3	21914
fifo_depth[1]	284577	1			T1	5		T2	3		T3	2505
fifo_depth[2]	229016	1			T1	2		T3	2473		T4	60
fifo_depth[3]	181823	1			T1	3		T3	2166		T4	38
fifo_depth[4]	150422	1			T1	2		T3	1814		T4	17
fifo_depth[5]	127326	1			T1	1		T3	1630		T4	8
fifo_depth[6]	117716	1			T1	3		T3	1355		T4	1
fifo_depth[7]	103713	1			T1	3		T3	1147		T5	230

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1761929

1

T1

19

T2

3

T3

15391

auto[1]

6932872

1

T1

8

T2

24

T3

21914

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8682152

1

T1

27

T2

27

T3

37305

auto[1]

12649

1

T14

1

T16

1

T8

1034

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

84670

1

T4

28

T7

1

T14

3

auto[0]

auto[0]

auto[0]

auto[1]

104753

1

T7

3

T14

1

T16

7

auto[0]

auto[0]

auto[1]

auto[0]

740417

1

T3

15391

T7

1

T14

3

auto[0]

auto[0]

auto[1]

auto[1]

91015

1

T4

49

T7

8

T14

1

auto[0]

auto[1]

auto[0]

auto[0]

197344

1

T4

107

T5

800

T6

6

auto[0]

auto[1]

auto[0]

auto[1]

182206

1

T4

22

T5

621

T6

5

auto[0]

auto[1]

auto[1]

auto[0]

172371

1

T1

19

T2

3

T5

998

auto[0]

auto[1]

auto[1]

auto[1]

189153

1

T6

4

T7

1

T16

6

auto[1]

auto[0]

auto[0]

auto[0]

268952

1

T4

736

T17

1

T6

25

auto[1]

auto[0]

auto[0]

auto[1]

281036

1

T6

20

T7

1

T15

9

auto[1]

auto[0]

auto[1]

auto[0]

3228816

1

T3

21914

T17

275

T6

35

auto[1]

auto[0]

auto[1]

auto[1]

257532

1

T4

325

T6

4

T15

11

auto[1]

auto[1]

auto[0]

auto[0]

685660

1

T4

779

T5

1176

T6

20

auto[1]

auto[1]

auto[0]

auto[1]

764824

1

T4

188

T5

2444

T6

40

auto[1]

auto[1]

auto[1]

auto[0]

697596

1

T1

8

T2

24

T5

2651

auto[1]

auto[1]

auto[1]

auto[1]

748456

1

T4

1

T5

2

T6

10

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

352260

1

T4

764

T17

1

T6

25

auto[0]

auto[0]

auto[0]

auto[1]

384119

1

T6

20

T7

4

T15

9

auto[0]

auto[0]

auto[1]

auto[0]

3967815

1

T3

37305

T17

275

T6

35

auto[0]

auto[0]

auto[1]

auto[1]

346277

1

T4

374

T6

4

T7

8

auto[0]

auto[1]

auto[0]

auto[0]

881610

1

T4

886

T5

1976

T6

26

auto[0]

auto[1]

auto[0]

auto[1]

945189

1

T4

210

T5

3065

T6

45

auto[0]

auto[1]

auto[1]

auto[0]

868870

1

T1

27

T2

27

T5

3649

auto[0]

auto[1]

auto[1]

auto[1]

936012

1

T4

1

T5

2

T6

14

auto[1]

auto[0]

auto[0]

auto[0]

1362

1

T8

121

T24

305

T41

1

auto[1]

auto[0]

auto[0]

auto[1]

1670

1

T8

89

T19

2

T24

27

auto[1]

auto[0]

auto[1]

auto[0]

1418

1

T8

138

T19

21

T24

21

auto[1]

auto[0]

auto[1]

auto[1]

2270

1

T8

71

T19

1

T24

55

auto[1]

auto[1]

auto[0]

auto[0]

1394

1

T16

1

T8

520

T25

28

auto[1]

auto[1]

auto[0]

auto[1]

1841

1

T14

1

T8

45

T24

136

auto[1]

auto[1]

auto[1]

auto[0]

1097

1

T8

42

T24

21

T25

17

auto[1]

auto[1]

auto[1]

auto[1]

1597

1

T8

8

T24

24

T115

3

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	268952	1			T4	736		T17	1		T6	25
fifo_depth[0]	auto[0]	auto[0]	auto[1]	281036	1			T6	20		T7	1		T15	9
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3228816	1			T3	21914		T17	275		T6	35
fifo_depth[0]	auto[0]	auto[1]	auto[1]	257532	1			T4	325		T6	4		T15	11
fifo_depth[0]	auto[1]	auto[0]	auto[0]	685660	1			T4	779		T5	1176		T6	20
fifo_depth[0]	auto[1]	auto[0]	auto[1]	764824	1			T4	188		T5	2444		T6	40
fifo_depth[0]	auto[1]	auto[1]	auto[0]	697596	1			T1	8		T2	24		T5	2651
fifo_depth[0]	auto[1]	auto[1]	auto[1]	748456	1			T4	1		T5	2		T6	10
fifo_depth[1]	auto[0]	auto[0]	auto[0]	8320	1			T4	9		T8	98		T45	110
fifo_depth[1]	auto[0]	auto[0]	auto[1]	10040	1			T8	164		T45	91		T18	18
fifo_depth[1]	auto[0]	auto[1]	auto[0]	180521	1			T3	2505		T8	5239		T45	105
fifo_depth[1]	auto[0]	auto[1]	auto[1]	8217	1			T4	23		T8	154		T45	73
fifo_depth[1]	auto[1]	auto[0]	auto[0]	20034	1			T4	43		T5	78		T6	1
fifo_depth[1]	auto[1]	auto[0]	auto[1]	18668	1			T4	7		T5	66		T6	3
fifo_depth[1]	auto[1]	auto[1]	auto[0]	19087	1			T1	5		T2	3		T5	93
fifo_depth[1]	auto[1]	auto[1]	auto[1]	19690	1			T6	2		T8	451		T45	130
fifo_depth[2]	auto[0]	auto[0]	auto[0]	7543	1			T4	8		T8	98		T45	98
fifo_depth[2]	auto[0]	auto[0]	auto[1]	8659	1			T8	156		T45	131		T18	8
fifo_depth[2]	auto[0]	auto[1]	auto[0]	134211	1			T3	2473		T8	4999		T45	97
fifo_depth[2]	auto[0]	auto[1]	auto[1]	7329	1			T4	13		T8	167		T45	78
fifo_depth[2]	auto[1]	auto[0]	auto[0]	18674	1			T4	31		T5	81		T6	2
fifo_depth[2]	auto[1]	auto[0]	auto[1]	17298	1			T4	8		T5	65		T6	1
fifo_depth[2]	auto[1]	auto[1]	auto[0]	17159	1			T1	2		T5	116		T6	4
fifo_depth[2]	auto[1]	auto[1]	auto[1]	18143	1			T8	534		T45	116		T82	2
fifo_depth[3]	auto[0]	auto[0]	auto[0]	5660	1			T4	5		T8	78		T45	104
fifo_depth[3]	auto[0]	auto[0]	auto[1]	6885	1			T8	148		T45	115		T18	2
fifo_depth[3]	auto[0]	auto[1]	auto[0]	100730	1			T3	2166		T8	4425		T45	108
fifo_depth[3]	auto[0]	auto[1]	auto[1]	5589	1			T4	11		T8	161		T45	70
fifo_depth[3]	auto[1]	auto[0]	auto[0]	16600	1			T4	16		T5	72		T8	603
fifo_depth[3]	auto[1]	auto[0]	auto[1]	15289	1			T4	6		T5	86		T8	825
fifo_depth[3]	auto[1]	auto[1]	auto[0]	14842	1			T1	3		T5	82		T8	453
fifo_depth[3]	auto[1]	auto[1]	auto[1]	16228	1			T6	1		T8	516		T45	132
fifo_depth[4]	auto[0]	auto[0]	auto[0]	5457	1			T4	2		T8	87		T45	90
fifo_depth[4]	auto[0]	auto[0]	auto[1]	6854	1			T8	155		T45	113		T18	3
fifo_depth[4]	auto[0]	auto[1]	auto[0]	72500	1			T3	1814		T8	3401		T45	111
fifo_depth[4]	auto[0]	auto[1]	auto[1]	5594	1			T4	2		T8	159		T45	72
fifo_depth[4]	auto[1]	auto[0]	auto[0]	15564	1			T4	12		T5	66		T6	2
fifo_depth[4]	auto[1]	auto[0]	auto[1]	14960	1			T4	1		T5	68		T8	954
fifo_depth[4]	auto[1]	auto[1]	auto[0]	14222	1			T1	2		T5	98		T6	1
fifo_depth[4]	auto[1]	auto[1]	auto[1]	15271	1			T6	1		T8	568		T45	123
fifo_depth[5]	auto[0]	auto[0]	auto[0]	4448	1			T4	3		T8	102		T45	109
fifo_depth[5]	auto[0]	auto[0]	auto[1]	5559	1			T8	156		T45	126		T18	1
fifo_depth[5]	auto[0]	auto[1]	auto[0]	57726	1			T3	1630		T8	2741		T45	101
fifo_depth[5]	auto[0]	auto[1]	auto[1]	4683	1			T8	150		T45	68		T26	110
fifo_depth[5]	auto[1]	auto[0]	auto[0]	14362	1			T4	5		T5	78		T6	1
fifo_depth[5]	auto[1]	auto[0]	auto[1]	13548	1			T5	54		T6	1		T8	820
fifo_depth[5]	auto[1]	auto[1]	auto[0]	12942	1			T1	1		T5	110		T6	1
fifo_depth[5]	auto[1]	auto[1]	auto[1]	14058	1			T8	539		T45	132		T82	2
fifo_depth[6]	auto[0]	auto[0]	auto[0]	4456	1			T4	1		T8	107		T45	114
fifo_depth[6]	auto[0]	auto[0]	auto[1]	5714	1			T8	157		T45	120		T26	48
fifo_depth[6]	auto[0]	auto[1]	auto[0]	49052	1			T3	1355		T8	2182		T45	110
fifo_depth[6]	auto[0]	auto[1]	auto[1]	4869	1			T8	156		T45	68		T26	96
fifo_depth[6]	auto[1]	auto[0]	auto[0]	13935	1			T5	70		T8	563		T45	53
fifo_depth[6]	auto[1]	auto[0]	auto[1]	13287	1			T5	71		T8	927		T45	15
fifo_depth[6]	auto[1]	auto[1]	auto[0]	12845	1			T1	3		T5	108		T8	491
fifo_depth[6]	auto[1]	auto[1]	auto[1]	13558	1			T8	533		T45	124		T82	3
fifo_depth[7]	auto[0]	auto[0]	auto[0]	4048	1			T8	102		T45	91		T26	44
fifo_depth[7]	auto[0]	auto[0]	auto[1]	4831	1			T8	157		T45	109		T26	43
fifo_depth[7]	auto[0]	auto[1]	auto[0]	39587	1			T3	1147		T8	1695		T45	104
fifo_depth[7]	auto[0]	auto[1]	auto[1]	4126	1			T8	153		T45	77		T26	83
fifo_depth[7]	auto[1]	auto[0]	auto[0]	13362	1			T5	67		T8	543		T45	41
fifo_depth[7]	auto[1]	auto[0]	auto[1]	12820	1			T5	58		T8	717		T45	14
fifo_depth[7]	auto[1]	auto[1]	auto[0]	11926	1			T1	3		T5	105		T8	431
fifo_depth[7]	auto[1]	auto[1]	auto[1]	13013	1			T8	567		T45	125		T82	4