Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	13441888	1			T1	32		T2	79		T3	64082
all_pins[1]	13441888	1			T1	32		T2	79		T3	64082
all_pins[2]	13441888	1			T1	32		T2	79		T3	64082

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	33505424	1			T1	92		T2	186		T3	165470
values[0x1]	6820240	1			T1	4		T2	51		T3	26776
transitions[0x0=>0x1]	6820105	1			T1	4		T2	51		T3	26776
transitions[0x1=>0x0]	6820119	1			T1	4		T2	51		T3	26776

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	13407194	1			T1	28		T2	75		T3	63888
all_pins[0]	values[0x1]	34694	1			T1	4		T2	4		T3	194
all_pins[0]	transitions[0x0=>0x1]	34621	1			T1	4		T2	4		T3	194
all_pins[0]	transitions[0x1=>0x0]	6785252	1			T2	47		T3	26582		T4	454
all_pins[1]	values[0x0]	13441653	1			T1	32		T2	79		T3	64082
all_pins[1]	values[0x1]	235	1			T8	6		T24	5		T52	1
all_pins[1]	transitions[0x0=>0x1]	202	1			T8	4		T24	5		T52	1
all_pins[1]	transitions[0x1=>0x0]	34661	1			T1	4		T2	4		T3	194
all_pins[2]	values[0x0]	6656577	1			T1	32		T2	32		T3	37500
all_pins[2]	values[0x1]	6785311	1			T2	47		T3	26582		T4	454
all_pins[2]	transitions[0x0=>0x1]	6785282	1			T2	47		T3	26582		T4	454
all_pins[2]	transitions[0x1=>0x0]	206	1			T8	6		T24	5		T52	1