Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 645 1 T8 24 T24 11 T52 28
all_values[1] 645 1 T8 24 T24 11 T52 28
all_values[2] 645 1 T8 24 T24 11 T52 28


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 994 1 T8 33 T24 18 T52 53
auto[1] 941 1 T8 39 T24 15 T52 31


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 722 1 T8 23 T24 16 T52 33
auto[1] 1213 1 T8 49 T24 17 T52 51


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1129 1 T8 44 T24 23 T52 48
auto[1] 806 1 T8 28 T24 10 T52 36


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 135 1 T8 4 T24 3 T52 6
all_values[0] auto[0] auto[0] auto[1] 55 1 T8 3 T24 2 T52 1
all_values[0] auto[0] auto[1] auto[0] 132 1 T8 1 T24 2 T52 5
all_values[0] auto[0] auto[1] auto[1] 65 1 T8 7 T52 2 T36 3
all_values[0] auto[1] auto[0] auto[1] 139 1 T8 4 T24 2 T52 11
all_values[0] auto[1] auto[1] auto[1] 119 1 T8 5 T24 2 T52 3
all_values[1] auto[0] auto[0] auto[0] 113 1 T8 3 T24 3 T52 7
all_values[1] auto[0] auto[0] auto[1] 77 1 T8 4 T52 5 T25 2
all_values[1] auto[0] auto[1] auto[0] 79 1 T8 4 T24 3 T52 5
all_values[1] auto[0] auto[1] auto[1] 84 1 T8 1 T24 2 T52 2
all_values[1] auto[1] auto[0] auto[1] 156 1 T8 7 T24 1 T52 7
all_values[1] auto[1] auto[1] auto[1] 136 1 T8 5 T24 2 T52 2
all_values[2] auto[0] auto[0] auto[0] 127 1 T8 2 T24 2 T52 6
all_values[2] auto[0] auto[0] auto[1] 60 1 T8 3 T24 3 T25 3
all_values[2] auto[0] auto[1] auto[0] 136 1 T8 9 T24 3 T52 4
all_values[2] auto[0] auto[1] auto[1] 66 1 T8 3 T52 5 T63 2
all_values[2] auto[1] auto[0] auto[1] 132 1 T8 3 T24 2 T52 10
all_values[2] auto[1] auto[1] auto[1] 124 1 T8 4 T24 1 T52 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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