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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.91 94.82 92.29 100.00 74.36 89.38 99.49 72.04


Total test records in report: 726
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T535 /workspace/coverage/default/33.hmac_smoke.159964033 Jun 05 04:22:20 PM PDT 24 Jun 05 04:22:33 PM PDT 24 2043131378 ps
T536 /workspace/coverage/default/9.hmac_error.491623596 Jun 05 04:21:16 PM PDT 24 Jun 05 04:23:18 PM PDT 24 46831041478 ps
T537 /workspace/coverage/default/24.hmac_test_hmac_vectors.1613405969 Jun 05 04:21:47 PM PDT 24 Jun 05 04:21:49 PM PDT 24 51312717 ps
T538 /workspace/coverage/default/28.hmac_burst_wr.1491676435 Jun 05 04:22:05 PM PDT 24 Jun 05 04:22:42 PM PDT 24 1898955109 ps
T105 /workspace/coverage/default/15.hmac_burst_wr.50191232 Jun 05 04:21:39 PM PDT 24 Jun 05 04:22:30 PM PDT 24 3119003293 ps
T539 /workspace/coverage/default/30.hmac_test_sha_vectors.2160638541 Jun 05 04:22:09 PM PDT 24 Jun 05 04:30:11 PM PDT 24 51496990520 ps
T540 /workspace/coverage/default/34.hmac_error.2074245971 Jun 05 04:22:20 PM PDT 24 Jun 05 04:24:25 PM PDT 24 31042518358 ps
T541 /workspace/coverage/default/46.hmac_back_pressure.2829880754 Jun 05 04:23:05 PM PDT 24 Jun 05 04:23:32 PM PDT 24 4872067362 ps
T542 /workspace/coverage/default/15.hmac_error.372297510 Jun 05 04:21:28 PM PDT 24 Jun 05 04:23:10 PM PDT 24 5925907270 ps
T543 /workspace/coverage/default/27.hmac_burst_wr.2179462241 Jun 05 04:21:53 PM PDT 24 Jun 05 04:22:56 PM PDT 24 12050127724 ps
T544 /workspace/coverage/default/8.hmac_datapath_stress.643919177 Jun 05 04:21:16 PM PDT 24 Jun 05 04:32:38 PM PDT 24 27331075454 ps
T545 /workspace/coverage/default/9.hmac_smoke.1898995472 Jun 05 04:21:18 PM PDT 24 Jun 05 04:21:22 PM PDT 24 85099296 ps
T546 /workspace/coverage/default/19.hmac_burst_wr.2698272984 Jun 05 04:21:36 PM PDT 24 Jun 05 04:21:40 PM PDT 24 60045958 ps
T547 /workspace/coverage/default/22.hmac_burst_wr.1685876964 Jun 05 04:21:38 PM PDT 24 Jun 05 04:22:27 PM PDT 24 3399574245 ps
T548 /workspace/coverage/default/32.hmac_wipe_secret.3563523102 Jun 05 04:22:20 PM PDT 24 Jun 05 04:22:55 PM PDT 24 857676372 ps
T549 /workspace/coverage/default/13.hmac_test_hmac_vectors.3548171122 Jun 05 04:21:42 PM PDT 24 Jun 05 04:21:44 PM PDT 24 52070654 ps
T550 /workspace/coverage/default/33.hmac_datapath_stress.2533359680 Jun 05 04:22:18 PM PDT 24 Jun 05 04:33:32 PM PDT 24 7103728137 ps
T551 /workspace/coverage/default/30.hmac_back_pressure.3420196212 Jun 05 04:22:09 PM PDT 24 Jun 05 04:22:59 PM PDT 24 1038417541 ps
T552 /workspace/coverage/default/49.hmac_burst_wr.3359565218 Jun 05 04:23:20 PM PDT 24 Jun 05 04:23:39 PM PDT 24 1678739066 ps
T11 /workspace/coverage/default/197.hmac_stress_all_with_rand_reset.3690157052 Jun 05 04:24:12 PM PDT 24 Jun 05 07:11:34 PM PDT 24 395632147512 ps
T553 /workspace/coverage/default/32.hmac_long_msg.161545179 Jun 05 04:22:20 PM PDT 24 Jun 05 04:23:30 PM PDT 24 19296108252 ps
T554 /workspace/coverage/default/20.hmac_alert_test.1844739909 Jun 05 04:21:38 PM PDT 24 Jun 05 04:21:39 PM PDT 24 23178704 ps
T555 /workspace/coverage/default/21.hmac_smoke.2373182327 Jun 05 04:21:39 PM PDT 24 Jun 05 04:21:44 PM PDT 24 827946905 ps
T556 /workspace/coverage/default/21.hmac_back_pressure.1115165703 Jun 05 04:21:37 PM PDT 24 Jun 05 04:22:35 PM PDT 24 1014883245 ps
T557 /workspace/coverage/default/49.hmac_back_pressure.1467498259 Jun 05 04:23:23 PM PDT 24 Jun 05 04:23:56 PM PDT 24 626178715 ps
T558 /workspace/coverage/default/35.hmac_smoke.2184941224 Jun 05 04:22:31 PM PDT 24 Jun 05 04:22:36 PM PDT 24 406915206 ps
T559 /workspace/coverage/default/32.hmac_test_hmac_vectors.1484774888 Jun 05 04:22:25 PM PDT 24 Jun 05 04:22:27 PM PDT 24 32507204 ps
T560 /workspace/coverage/default/8.hmac_error.3672565654 Jun 05 04:21:18 PM PDT 24 Jun 05 04:22:08 PM PDT 24 13427573043 ps
T561 /workspace/coverage/default/10.hmac_long_msg.1620679716 Jun 05 04:21:20 PM PDT 24 Jun 05 04:22:15 PM PDT 24 1901844821 ps
T562 /workspace/coverage/default/7.hmac_test_hmac_vectors.2461132359 Jun 05 04:21:15 PM PDT 24 Jun 05 04:21:17 PM PDT 24 51537436 ps
T563 /workspace/coverage/default/35.hmac_error.2040369280 Jun 05 04:22:32 PM PDT 24 Jun 05 04:24:10 PM PDT 24 5773610032 ps
T564 /workspace/coverage/default/36.hmac_burst_wr.1944736240 Jun 05 04:22:31 PM PDT 24 Jun 05 04:22:38 PM PDT 24 358191286 ps
T565 /workspace/coverage/default/25.hmac_test_sha_vectors.3004810335 Jun 05 04:21:48 PM PDT 24 Jun 05 04:28:25 PM PDT 24 7048768615 ps
T566 /workspace/coverage/default/37.hmac_datapath_stress.2445498344 Jun 05 04:22:31 PM PDT 24 Jun 05 04:29:44 PM PDT 24 8515457814 ps
T69 /workspace/coverage/default/45.hmac_stress_all.2237330170 Jun 05 04:23:04 PM PDT 24 Jun 05 04:47:08 PM PDT 24 102708015685 ps
T567 /workspace/coverage/default/1.hmac_test_hmac_vectors.1334850859 Jun 05 04:20:56 PM PDT 24 Jun 05 04:20:58 PM PDT 24 219294744 ps
T568 /workspace/coverage/default/6.hmac_error.1183077191 Jun 05 04:21:14 PM PDT 24 Jun 05 04:22:21 PM PDT 24 20871921555 ps
T569 /workspace/coverage/default/24.hmac_long_msg.3571100686 Jun 05 04:21:45 PM PDT 24 Jun 05 04:22:16 PM PDT 24 15194026145 ps
T570 /workspace/coverage/default/6.hmac_long_msg.629902237 Jun 05 04:21:15 PM PDT 24 Jun 05 04:22:23 PM PDT 24 17683024574 ps
T571 /workspace/coverage/default/43.hmac_error.143878872 Jun 05 04:22:59 PM PDT 24 Jun 05 04:25:42 PM PDT 24 8799514008 ps
T572 /workspace/coverage/default/5.hmac_burst_wr.3616003665 Jun 05 04:21:09 PM PDT 24 Jun 05 04:21:32 PM PDT 24 1434405695 ps
T573 /workspace/coverage/default/6.hmac_wipe_secret.3934340489 Jun 05 04:21:14 PM PDT 24 Jun 05 04:22:22 PM PDT 24 1828762943 ps
T574 /workspace/coverage/default/17.hmac_error.2396327773 Jun 05 04:21:36 PM PDT 24 Jun 05 04:23:56 PM PDT 24 52251640222 ps
T575 /workspace/coverage/default/45.hmac_test_hmac_vectors.321358933 Jun 05 04:23:04 PM PDT 24 Jun 05 04:23:07 PM PDT 24 33333752 ps
T576 /workspace/coverage/default/45.hmac_wipe_secret.2128344000 Jun 05 04:23:05 PM PDT 24 Jun 05 04:23:16 PM PDT 24 2339881029 ps
T577 /workspace/coverage/default/24.hmac_error.2084516551 Jun 05 04:21:49 PM PDT 24 Jun 05 04:22:33 PM PDT 24 2395060053 ps
T578 /workspace/coverage/default/35.hmac_burst_wr.3482095353 Jun 05 04:22:31 PM PDT 24 Jun 05 04:22:36 PM PDT 24 792072347 ps
T579 /workspace/coverage/default/5.hmac_long_msg.3116427474 Jun 05 04:21:05 PM PDT 24 Jun 05 04:22:22 PM PDT 24 7513417409 ps
T580 /workspace/coverage/default/10.hmac_error.1579085309 Jun 05 04:21:31 PM PDT 24 Jun 05 04:23:39 PM PDT 24 11735023589 ps
T581 /workspace/coverage/default/0.hmac_wipe_secret.2752826443 Jun 05 04:21:02 PM PDT 24 Jun 05 04:21:33 PM PDT 24 1980095315 ps
T582 /workspace/coverage/default/16.hmac_alert_test.1367525564 Jun 05 04:21:36 PM PDT 24 Jun 05 04:21:38 PM PDT 24 45647587 ps
T583 /workspace/coverage/default/12.hmac_alert_test.2734869191 Jun 05 04:21:34 PM PDT 24 Jun 05 04:21:35 PM PDT 24 14798860 ps
T584 /workspace/coverage/default/37.hmac_back_pressure.52669753 Jun 05 04:22:31 PM PDT 24 Jun 05 04:23:17 PM PDT 24 3937077722 ps
T585 /workspace/coverage/default/45.hmac_error.508858984 Jun 05 04:23:05 PM PDT 24 Jun 05 04:25:37 PM PDT 24 2701602539 ps
T586 /workspace/coverage/default/37.hmac_alert_test.2050179999 Jun 05 04:22:39 PM PDT 24 Jun 05 04:22:40 PM PDT 24 39979198 ps
T587 /workspace/coverage/default/19.hmac_alert_test.952533603 Jun 05 04:21:37 PM PDT 24 Jun 05 04:21:39 PM PDT 24 11970241 ps
T70 /workspace/coverage/default/22.hmac_stress_all.2641698725 Jun 05 04:21:38 PM PDT 24 Jun 05 04:44:39 PM PDT 24 303564156752 ps
T588 /workspace/coverage/default/2.hmac_stress_all.4169192166 Jun 05 04:21:06 PM PDT 24 Jun 05 05:07:04 PM PDT 24 86585240583 ps
T589 /workspace/coverage/default/11.hmac_error.678440867 Jun 05 04:21:30 PM PDT 24 Jun 05 04:24:14 PM PDT 24 12291275153 ps
T590 /workspace/coverage/default/16.hmac_back_pressure.3710757104 Jun 05 04:21:30 PM PDT 24 Jun 05 04:22:25 PM PDT 24 1069707184 ps
T591 /workspace/coverage/default/36.hmac_back_pressure.57832838 Jun 05 04:22:33 PM PDT 24 Jun 05 04:23:08 PM PDT 24 676586094 ps
T49 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3502058589 Jun 05 04:19:56 PM PDT 24 Jun 05 04:20:01 PM PDT 24 910676480 ps
T592 /workspace/coverage/cover_reg_top/35.hmac_intr_test.1238057721 Jun 05 04:20:00 PM PDT 24 Jun 05 04:20:01 PM PDT 24 10673636 ps
T54 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4242907721 Jun 05 04:19:45 PM PDT 24 Jun 05 04:19:48 PM PDT 24 51041449 ps
T50 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1424664923 Jun 05 04:19:44 PM PDT 24 Jun 05 04:19:47 PM PDT 24 364191284 ps
T593 /workspace/coverage/cover_reg_top/47.hmac_intr_test.465590431 Jun 05 04:20:03 PM PDT 24 Jun 05 04:20:04 PM PDT 24 12313599 ps
T83 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2039087121 Jun 05 04:19:53 PM PDT 24 Jun 05 04:19:55 PM PDT 24 16303295 ps
T594 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.78563534 Jun 05 04:19:44 PM PDT 24 Jun 05 04:19:46 PM PDT 24 150283380 ps
T71 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3573159700 Jun 05 04:19:34 PM PDT 24 Jun 05 04:19:44 PM PDT 24 533367695 ps
T84 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.275740750 Jun 05 04:19:19 PM PDT 24 Jun 05 04:19:28 PM PDT 24 1159100129 ps
T79 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1207124565 Jun 05 04:19:54 PM PDT 24 Jun 05 04:19:58 PM PDT 24 125524353 ps
T595 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3128278296 Jun 05 04:20:02 PM PDT 24 Jun 05 04:20:03 PM PDT 24 28150380 ps
T596 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1464208466 Jun 05 04:19:55 PM PDT 24 Jun 05 04:19:57 PM PDT 24 16598003 ps
T597 /workspace/coverage/cover_reg_top/44.hmac_intr_test.886880098 Jun 05 04:20:02 PM PDT 24 Jun 05 04:20:03 PM PDT 24 43653540 ps
T598 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1725353145 Jun 05 04:20:07 PM PDT 24 Jun 05 04:20:08 PM PDT 24 14515755 ps
T80 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.93086340 Jun 05 04:19:33 PM PDT 24 Jun 05 04:19:37 PM PDT 24 37794589 ps
T599 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2534101035 Jun 05 04:20:03 PM PDT 24 Jun 05 04:20:05 PM PDT 24 13681945 ps
T600 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3025426852 Jun 05 04:19:33 PM PDT 24 Jun 05 04:19:36 PM PDT 24 68064538 ps
T601 /workspace/coverage/cover_reg_top/14.hmac_intr_test.4033592632 Jun 05 04:19:53 PM PDT 24 Jun 05 04:19:54 PM PDT 24 40019484 ps
T602 /workspace/coverage/cover_reg_top/25.hmac_intr_test.1003225422 Jun 05 04:19:59 PM PDT 24 Jun 05 04:20:00 PM PDT 24 57274127 ps
T603 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1854548641 Jun 05 04:19:29 PM PDT 24 Jun 05 04:19:31 PM PDT 24 116017927 ps
T604 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1932513185 Jun 05 04:19:34 PM PDT 24 Jun 05 04:19:38 PM PDT 24 102680777 ps
T51 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2629957259 Jun 05 04:19:19 PM PDT 24 Jun 05 04:19:24 PM PDT 24 1518010944 ps
T605 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.559818076 Jun 05 04:19:34 PM PDT 24 Jun 05 04:19:37 PM PDT 24 209374594 ps
T85 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2118059966 Jun 05 04:19:28 PM PDT 24 Jun 05 04:19:30 PM PDT 24 207513319 ps
T606 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2820041854 Jun 05 04:19:50 PM PDT 24 Jun 05 04:19:52 PM PDT 24 603381051 ps
T607 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3779463250 Jun 05 04:19:47 PM PDT 24 Jun 05 04:19:48 PM PDT 24 141356056 ps
T86 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2038285622 Jun 05 04:19:36 PM PDT 24 Jun 05 04:19:38 PM PDT 24 84576906 ps
T92 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3877200897 Jun 05 04:19:15 PM PDT 24 Jun 05 04:19:27 PM PDT 24 11813091299 ps
T608 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2077200266 Jun 05 04:19:52 PM PDT 24 Jun 05 04:19:53 PM PDT 24 88968635 ps
T609 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.498763138 Jun 05 04:19:26 PM PDT 24 Jun 05 04:19:29 PM PDT 24 90370475 ps
T610 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.220531275 Jun 05 04:19:42 PM PDT 24 Jun 05 04:19:43 PM PDT 24 111876424 ps
T611 /workspace/coverage/cover_reg_top/48.hmac_intr_test.1759645228 Jun 05 04:20:03 PM PDT 24 Jun 05 04:20:05 PM PDT 24 21873469 ps
T109 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.131096442 Jun 05 04:20:07 PM PDT 24 Jun 05 04:20:12 PM PDT 24 133422219 ps
T612 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4098585863 Jun 05 04:19:43 PM PDT 24 Jun 05 04:19:47 PM PDT 24 180044759 ps
T613 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2880376412 Jun 05 04:19:35 PM PDT 24 Jun 05 04:19:38 PM PDT 24 217342207 ps
T614 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.357673826 Jun 05 04:19:18 PM PDT 24 Jun 05 04:19:21 PM PDT 24 126757065 ps
T615 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3447714220 Jun 05 04:20:00 PM PDT 24 Jun 05 04:20:01 PM PDT 24 45359152 ps
T616 /workspace/coverage/cover_reg_top/27.hmac_intr_test.2199275451 Jun 05 04:20:03 PM PDT 24 Jun 05 04:20:05 PM PDT 24 24075640 ps
T114 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2461258422 Jun 05 04:19:26 PM PDT 24 Jun 05 04:19:30 PM PDT 24 374837402 ps
T617 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2884149822 Jun 05 04:19:26 PM PDT 24 Jun 05 04:19:29 PM PDT 24 102769994 ps
T618 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3364606458 Jun 05 04:19:43 PM PDT 24 Jun 05 04:19:44 PM PDT 24 88163028 ps
T619 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.270452769 Jun 05 04:19:44 PM PDT 24 Jun 05 04:19:46 PM PDT 24 253303774 ps
T620 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2701699517 Jun 05 04:19:56 PM PDT 24 Jun 05 04:19:58 PM PDT 24 208483456 ps
T621 /workspace/coverage/cover_reg_top/12.hmac_intr_test.987631133 Jun 05 04:19:43 PM PDT 24 Jun 05 04:19:44 PM PDT 24 164354361 ps
T107 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3493115627 Jun 05 04:19:35 PM PDT 24 Jun 05 04:19:38 PM PDT 24 91911526 ps
T108 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2344829893 Jun 05 04:19:36 PM PDT 24 Jun 05 04:19:40 PM PDT 24 165029934 ps
T87 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1380833806 Jun 05 04:20:03 PM PDT 24 Jun 05 04:20:05 PM PDT 24 109286716 ps
T622 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.792747819 Jun 05 04:19:51 PM PDT 24 Jun 05 04:19:54 PM PDT 24 178630870 ps
T623 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1792196252 Jun 05 04:19:26 PM PDT 24 Jun 05 04:19:28 PM PDT 24 32127409 ps
T624 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2504264229 Jun 05 04:19:43 PM PDT 24 Jun 05 04:19:45 PM PDT 24 86373313 ps
T625 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.178042604 Jun 05 04:20:00 PM PDT 24 Jun 05 04:20:03 PM PDT 24 104948790 ps
T626 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.876244048 Jun 05 04:19:55 PM PDT 24 Jun 05 04:19:58 PM PDT 24 55722736 ps
T627 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3416116102 Jun 05 04:19:19 PM PDT 24 Jun 05 04:19:21 PM PDT 24 75392661 ps
T628 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1575430327 Jun 05 04:19:19 PM PDT 24 Jun 05 04:19:22 PM PDT 24 64383557 ps
T629 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1480959486 Jun 05 04:19:54 PM PDT 24 Jun 05 04:19:55 PM PDT 24 30667079 ps
T630 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.502268922 Jun 05 04:19:28 PM PDT 24 Jun 05 04:19:34 PM PDT 24 218002095 ps
T631 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3468857835 Jun 05 04:19:33 PM PDT 24 Jun 05 04:19:36 PM PDT 24 103441849 ps
T632 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2831317651 Jun 05 04:19:54 PM PDT 24 Jun 05 04:19:57 PM PDT 24 413113035 ps
T633 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.4294751118 Jun 05 04:19:55 PM PDT 24 Jun 05 04:22:02 PM PDT 24 46996706918 ps
T634 /workspace/coverage/cover_reg_top/45.hmac_intr_test.402434672 Jun 05 04:20:02 PM PDT 24 Jun 05 04:20:03 PM PDT 24 20379074 ps
T88 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3841271038 Jun 05 04:19:34 PM PDT 24 Jun 05 04:19:36 PM PDT 24 33494770 ps
T635 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1060066150 Jun 05 04:20:03 PM PDT 24 Jun 05 04:20:05 PM PDT 24 15443047 ps
T636 /workspace/coverage/cover_reg_top/2.hmac_intr_test.1811482239 Jun 05 04:19:27 PM PDT 24 Jun 05 04:19:28 PM PDT 24 19493373 ps
T637 /workspace/coverage/cover_reg_top/36.hmac_intr_test.3223802732 Jun 05 04:20:04 PM PDT 24 Jun 05 04:20:05 PM PDT 24 31117751 ps
T638 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.787472456 Jun 05 04:19:44 PM PDT 24 Jun 05 04:19:48 PM PDT 24 181607335 ps
T639 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2101307323 Jun 05 04:20:02 PM PDT 24 Jun 05 04:20:04 PM PDT 24 17870396 ps
T89 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.784891769 Jun 05 04:19:54 PM PDT 24 Jun 05 04:19:55 PM PDT 24 15007399 ps
T640 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2716034823 Jun 05 04:19:43 PM PDT 24 Jun 05 04:36:36 PM PDT 24 289638212613 ps
T641 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.608897429 Jun 05 04:19:54 PM PDT 24 Jun 05 04:19:57 PM PDT 24 87626736 ps
T642 /workspace/coverage/cover_reg_top/24.hmac_intr_test.267938606 Jun 05 04:20:01 PM PDT 24 Jun 05 04:20:03 PM PDT 24 47460491 ps
T643 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.984742294 Jun 05 04:19:26 PM PDT 24 Jun 05 04:19:32 PM PDT 24 1471614628 ps
T90 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2512887655 Jun 05 04:19:19 PM PDT 24 Jun 05 04:19:21 PM PDT 24 39097150 ps
T644 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.882547499 Jun 05 04:20:03 PM PDT 24 Jun 05 04:20:07 PM PDT 24 1197044328 ps
T645 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.698031219 Jun 05 04:19:37 PM PDT 24 Jun 05 04:29:38 PM PDT 24 154688477462 ps
T111 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1361523959 Jun 05 04:19:56 PM PDT 24 Jun 05 04:20:00 PM PDT 24 90591254 ps
T646 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3270463558 Jun 05 04:20:01 PM PDT 24 Jun 05 04:43:44 PM PDT 24 131668985237 ps
T647 /workspace/coverage/cover_reg_top/6.hmac_intr_test.1223133730 Jun 05 04:19:36 PM PDT 24 Jun 05 04:19:37 PM PDT 24 14229927 ps
T648 /workspace/coverage/cover_reg_top/4.hmac_intr_test.1942482947 Jun 05 04:19:35 PM PDT 24 Jun 05 04:19:36 PM PDT 24 35605849 ps
T649 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1406805970 Jun 05 04:19:44 PM PDT 24 Jun 05 04:19:46 PM PDT 24 79310536 ps
T650 /workspace/coverage/cover_reg_top/22.hmac_intr_test.418983530 Jun 05 04:20:01 PM PDT 24 Jun 05 04:20:03 PM PDT 24 48194370 ps
T91 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1691656837 Jun 05 04:19:44 PM PDT 24 Jun 05 04:19:46 PM PDT 24 42537400 ps
T651 /workspace/coverage/cover_reg_top/9.hmac_intr_test.108046931 Jun 05 04:19:45 PM PDT 24 Jun 05 04:19:46 PM PDT 24 42327127 ps
T652 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2594466063 Jun 05 04:20:11 PM PDT 24 Jun 05 04:20:13 PM PDT 24 24317922 ps
T653 /workspace/coverage/cover_reg_top/5.hmac_intr_test.1737217237 Jun 05 04:19:35 PM PDT 24 Jun 05 04:19:36 PM PDT 24 55760826 ps
T654 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.4023427006 Jun 05 04:19:55 PM PDT 24 Jun 05 04:19:59 PM PDT 24 798477583 ps
T655 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.807614098 Jun 05 04:19:35 PM PDT 24 Jun 05 04:19:37 PM PDT 24 60631709 ps
T656 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.256724533 Jun 05 04:19:44 PM PDT 24 Jun 05 04:19:47 PM PDT 24 86427218 ps
T93 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1587171534 Jun 05 04:19:33 PM PDT 24 Jun 05 04:19:37 PM PDT 24 59260476 ps
T112 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2994434136 Jun 05 04:19:59 PM PDT 24 Jun 05 04:20:04 PM PDT 24 264811495 ps
T657 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3316763788 Jun 05 04:19:36 PM PDT 24 Jun 05 04:19:38 PM PDT 24 50312534 ps
T110 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2835041160 Jun 05 04:19:37 PM PDT 24 Jun 05 04:19:40 PM PDT 24 93189685 ps
T658 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3681096995 Jun 05 04:19:34 PM PDT 24 Jun 05 04:21:04 PM PDT 24 11289522399 ps
T659 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.4000010664 Jun 05 04:19:16 PM PDT 24 Jun 05 04:19:19 PM PDT 24 141534628 ps
T660 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3150137971 Jun 05 04:19:42 PM PDT 24 Jun 05 04:19:45 PM PDT 24 124273757 ps
T661 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1431857119 Jun 05 04:19:53 PM PDT 24 Jun 05 04:19:55 PM PDT 24 81675981 ps
T662 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1805620998 Jun 05 04:19:37 PM PDT 24 Jun 05 04:19:41 PM PDT 24 220848274 ps
T663 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2661816991 Jun 05 04:20:01 PM PDT 24 Jun 05 04:20:03 PM PDT 24 32484530 ps
T664 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1528479317 Jun 05 04:19:45 PM PDT 24 Jun 05 04:19:49 PM PDT 24 1076999984 ps
T665 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1464330272 Jun 05 04:19:56 PM PDT 24 Jun 05 04:19:59 PM PDT 24 183400990 ps
T666 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.195157425 Jun 05 04:19:18 PM PDT 24 Jun 05 04:19:20 PM PDT 24 63955068 ps
T667 /workspace/coverage/cover_reg_top/38.hmac_intr_test.1396538969 Jun 05 04:20:02 PM PDT 24 Jun 05 04:20:04 PM PDT 24 16178965 ps
T668 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.874841306 Jun 05 04:19:18 PM PDT 24 Jun 05 04:19:21 PM PDT 24 423511076 ps
T669 /workspace/coverage/cover_reg_top/3.hmac_intr_test.4052949316 Jun 05 04:19:34 PM PDT 24 Jun 05 04:19:35 PM PDT 24 14155816 ps
T670 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.4274446547 Jun 05 04:19:34 PM PDT 24 Jun 05 04:19:37 PM PDT 24 109332373 ps
T671 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2909341139 Jun 05 04:19:22 PM PDT 24 Jun 05 04:19:25 PM PDT 24 112501725 ps
T672 /workspace/coverage/cover_reg_top/7.hmac_intr_test.3638943468 Jun 05 04:19:36 PM PDT 24 Jun 05 04:19:38 PM PDT 24 14361957 ps
T673 /workspace/coverage/cover_reg_top/16.hmac_intr_test.2350861374 Jun 05 04:19:56 PM PDT 24 Jun 05 04:19:58 PM PDT 24 104021286 ps
T674 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3590418235 Jun 05 04:19:22 PM PDT 24 Jun 05 04:19:24 PM PDT 24 61382985 ps
T675 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.753142323 Jun 05 04:20:00 PM PDT 24 Jun 05 04:20:03 PM PDT 24 75187008 ps
T676 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1265313375 Jun 05 04:19:22 PM PDT 24 Jun 05 04:19:23 PM PDT 24 71595175 ps
T677 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1593636788 Jun 05 04:19:52 PM PDT 24 Jun 05 04:19:55 PM PDT 24 87461925 ps
T678 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3384349018 Jun 05 04:19:53 PM PDT 24 Jun 05 04:19:55 PM PDT 24 157357662 ps
T94 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.324353598 Jun 05 04:20:07 PM PDT 24 Jun 05 04:20:09 PM PDT 24 19337058 ps
T679 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1097450681 Jun 05 04:19:36 PM PDT 24 Jun 05 04:19:39 PM PDT 24 189309705 ps
T680 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.800786203 Jun 05 04:19:31 PM PDT 24 Jun 05 04:19:33 PM PDT 24 27446032 ps
T681 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3996578162 Jun 05 04:20:00 PM PDT 24 Jun 05 04:20:02 PM PDT 24 64475280 ps
T682 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1763529281 Jun 05 04:19:55 PM PDT 24 Jun 05 04:19:59 PM PDT 24 186707873 ps
T683 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2692538283 Jun 05 04:19:25 PM PDT 24 Jun 05 04:19:30 PM PDT 24 130215904 ps
T684 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3048457113 Jun 05 04:19:49 PM PDT 24 Jun 05 04:30:17 PM PDT 24 134729561458 ps
T685 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.344932566 Jun 05 04:19:55 PM PDT 24 Jun 05 04:19:57 PM PDT 24 171314754 ps
T686 /workspace/coverage/cover_reg_top/21.hmac_intr_test.2576963994 Jun 05 04:20:00 PM PDT 24 Jun 05 04:20:02 PM PDT 24 11911124 ps
T687 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3949796094 Jun 05 04:19:45 PM PDT 24 Jun 05 04:19:51 PM PDT 24 554736742 ps
T688 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.718346492 Jun 05 04:19:56 PM PDT 24 Jun 05 04:19:59 PM PDT 24 270842369 ps
T689 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4064284227 Jun 05 04:19:58 PM PDT 24 Jun 05 04:20:01 PM PDT 24 93025813 ps
T690 /workspace/coverage/cover_reg_top/18.hmac_intr_test.3808953080 Jun 05 04:20:01 PM PDT 24 Jun 05 04:20:02 PM PDT 24 12802017 ps
T95 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.26121973 Jun 05 04:19:35 PM PDT 24 Jun 05 04:19:36 PM PDT 24 14736642 ps
T691 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1614720101 Jun 05 04:19:43 PM PDT 24 Jun 05 04:19:45 PM PDT 24 63922952 ps
T692 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1825634985 Jun 05 04:19:16 PM PDT 24 Jun 05 04:19:20 PM PDT 24 381416143 ps
T693 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1615771155 Jun 05 04:19:56 PM PDT 24 Jun 05 04:19:59 PM PDT 24 442292792 ps
T694 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.162266123 Jun 05 04:19:35 PM PDT 24 Jun 05 04:19:37 PM PDT 24 22881272 ps
T695 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2327130087 Jun 05 04:19:44 PM PDT 24 Jun 05 04:19:45 PM PDT 24 14687421 ps
T696 /workspace/coverage/cover_reg_top/19.hmac_intr_test.3982204698 Jun 05 04:20:04 PM PDT 24 Jun 05 04:20:06 PM PDT 24 23566077 ps
T697 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1534059203 Jun 05 04:19:27 PM PDT 24 Jun 05 04:19:30 PM PDT 24 222234620 ps
T698 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2536879751 Jun 05 04:20:03 PM PDT 24 Jun 05 04:20:05 PM PDT 24 22440546 ps
T699 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2659307 Jun 05 04:20:07 PM PDT 24 Jun 05 04:20:08 PM PDT 24 14662772 ps
T700 /workspace/coverage/cover_reg_top/13.hmac_intr_test.1347226853 Jun 05 04:19:53 PM PDT 24 Jun 05 04:19:54 PM PDT 24 13326678 ps
T701 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1287131212 Jun 05 04:20:01 PM PDT 24 Jun 05 04:20:03 PM PDT 24 44948375 ps
T113 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1979535167 Jun 05 04:19:34 PM PDT 24 Jun 05 04:19:39 PM PDT 24 468150602 ps
T702 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.4251324526 Jun 05 04:19:18 PM PDT 24 Jun 05 04:19:28 PM PDT 24 210498205 ps
T703 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2994822055 Jun 05 04:19:44 PM PDT 24 Jun 05 04:19:47 PM PDT 24 52604194 ps
T96 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1455740123 Jun 05 04:19:56 PM PDT 24 Jun 05 04:19:58 PM PDT 24 59621388 ps
T704 /workspace/coverage/cover_reg_top/30.hmac_intr_test.242099225 Jun 05 04:20:00 PM PDT 24 Jun 05 04:20:02 PM PDT 24 31148011 ps
T705 /workspace/coverage/cover_reg_top/46.hmac_intr_test.506413465 Jun 05 04:20:04 PM PDT 24 Jun 05 04:20:06 PM PDT 24 61950024 ps
T53 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3572185072 Jun 05 04:19:45 PM PDT 24 Jun 05 04:19:50 PM PDT 24 437741059 ps
T706 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.68775418 Jun 05 04:19:55 PM PDT 24 Jun 05 04:19:59 PM PDT 24 159572063 ps
T707 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2753901392 Jun 05 04:19:46 PM PDT 24 Jun 05 04:19:48 PM PDT 24 296810663 ps
T708 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.121748373 Jun 05 04:19:27 PM PDT 24 Jun 05 04:19:36 PM PDT 24 1576906418 ps
T709 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1891128890 Jun 05 04:19:35 PM PDT 24 Jun 05 04:19:38 PM PDT 24 213249458 ps
T710 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1000188342 Jun 05 04:19:35 PM PDT 24 Jun 05 04:19:37 PM PDT 24 72133258 ps
T711 /workspace/coverage/cover_reg_top/31.hmac_intr_test.4276506128 Jun 05 04:20:01 PM PDT 24 Jun 05 04:20:03 PM PDT 24 41827347 ps
T712 /workspace/coverage/cover_reg_top/40.hmac_intr_test.3055351193 Jun 05 04:20:00 PM PDT 24 Jun 05 04:20:02 PM PDT 24 13914945 ps
T713 /workspace/coverage/cover_reg_top/26.hmac_intr_test.3410770754 Jun 05 04:20:00 PM PDT 24 Jun 05 04:20:02 PM PDT 24 139929092 ps
T714 /workspace/coverage/cover_reg_top/0.hmac_intr_test.469020047 Jun 05 04:19:18 PM PDT 24 Jun 05 04:19:20 PM PDT 24 12174476 ps
T715 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1367333115 Jun 05 04:19:53 PM PDT 24 Jun 05 04:19:56 PM PDT 24 469085465 ps
T716 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.784550551 Jun 05 04:19:34 PM PDT 24 Jun 05 04:19:38 PM PDT 24 262849185 ps
T717 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1335487613 Jun 05 04:20:00 PM PDT 24 Jun 05 04:20:01 PM PDT 24 15382689 ps
T718 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2379990725 Jun 05 04:20:02 PM PDT 24 Jun 05 04:20:05 PM PDT 24 66416042 ps
T719 /workspace/coverage/cover_reg_top/1.hmac_intr_test.201855560 Jun 05 04:19:17 PM PDT 24 Jun 05 04:19:18 PM PDT 24 60548394 ps
T720 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2909182761 Jun 05 04:19:19 PM PDT 24 Jun 05 04:19:21 PM PDT 24 146751147 ps
T721 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3925107004 Jun 05 04:20:01 PM PDT 24 Jun 05 04:20:03 PM PDT 24 24276820 ps
T722 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1138503413 Jun 05 04:19:45 PM PDT 24 Jun 05 04:19:46 PM PDT 24 13510706 ps
T723 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3596624112 Jun 05 04:19:34 PM PDT 24 Jun 05 04:19:36 PM PDT 24 107980198 ps
T724 /workspace/coverage/cover_reg_top/8.hmac_intr_test.2248906913 Jun 05 04:19:44 PM PDT 24 Jun 05 04:19:45 PM PDT 24 14239154 ps
T725 /workspace/coverage/cover_reg_top/17.hmac_intr_test.4138656116 Jun 05 04:19:57 PM PDT 24 Jun 05 04:19:59 PM PDT 24 13843581 ps
T726 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3437020337 Jun 05 04:19:35 PM PDT 24 Jun 05 04:19:48 PM PDT 24 4227985727 ps

Test location /workspace/coverage/default/32.hmac_back_pressure.2999467096
Short name T7
Test name
Test status
Simulation time 874811360 ps
CPU time 20.33 seconds
Started Jun 05 04:22:18 PM PDT 24
Finished Jun 05 04:22:39 PM PDT 24
Peak memory 216356 kb
Host smart-608464db-f6f9-48e7-8d51-83b982f09493
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2999467096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2999467096
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/142.hmac_stress_all_with_rand_reset.1009638197
Short name T19
Test name
Test status
Simulation time 15029650274 ps
CPU time 1309.25 seconds
Started Jun 05 04:23:44 PM PDT 24
Finished Jun 05 04:45:35 PM PDT 24
Peak memory 705588 kb
Host smart-10c844ca-2508-48ca-853c-7369c79d87fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1009638197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.hmac_stress_all_with_rand_reset.1009638197
Directory /workspace/142.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_stress_all.987065080
Short name T8
Test name
Test status
Simulation time 121489671179 ps
CPU time 3145.2 seconds
Started Jun 05 04:21:32 PM PDT 24
Finished Jun 05 05:13:59 PM PDT 24
Peak memory 761188 kb
Host smart-772b67be-f029-41e8-9f25-e8ff262198f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987065080 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.987065080
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3109625308
Short name T27
Test name
Test status
Simulation time 92176285 ps
CPU time 0.8 seconds
Started Jun 05 04:21:00 PM PDT 24
Finished Jun 05 04:21:01 PM PDT 24
Peak memory 218476 kb
Host smart-f9b59eba-d238-4de7-b93a-be2f37b9be7e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109625308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3109625308
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/197.hmac_stress_all_with_rand_reset.3690157052
Short name T11
Test name
Test status
Simulation time 395632147512 ps
CPU time 10040 seconds
Started Jun 05 04:24:12 PM PDT 24
Finished Jun 05 07:11:34 PM PDT 24
Peak memory 985180 kb
Host smart-4184947b-0249-46f9-861f-61cce9f63ec4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3690157052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.hmac_stress_all_with_rand_reset.3690157052
Directory /workspace/197.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3502058589
Short name T49
Test name
Test status
Simulation time 910676480 ps
CPU time 4.48 seconds
Started Jun 05 04:19:56 PM PDT 24
Finished Jun 05 04:20:01 PM PDT 24
Peak memory 199436 kb
Host smart-c94261cd-418c-45fc-801b-d3d2c2640ce5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502058589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3502058589
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/124.hmac_stress_all_with_rand_reset.290275201
Short name T12
Test name
Test status
Simulation time 22962401412 ps
CPU time 377.07 seconds
Started Jun 05 04:23:39 PM PDT 24
Finished Jun 05 04:29:56 PM PDT 24
Peak memory 208460 kb
Host smart-4a6334c8-289d-43d3-853c-49cd0f9437c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=290275201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.hmac_stress_all_with_rand_reset.290275201
Directory /workspace/124.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3573159700
Short name T71
Test name
Test status
Simulation time 533367695 ps
CPU time 8.91 seconds
Started Jun 05 04:19:34 PM PDT 24
Finished Jun 05 04:19:44 PM PDT 24
Peak memory 199380 kb
Host smart-f0ba49d5-8339-41e1-9392-425fc41030dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573159700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3573159700
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2906536660
Short name T22
Test name
Test status
Simulation time 46329684 ps
CPU time 0.58 seconds
Started Jun 05 04:22:14 PM PDT 24
Finished Jun 05 04:22:15 PM PDT 24
Peak memory 194976 kb
Host smart-3a8c05b2-5620-4d85-9102-e46b99c37f17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906536660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2906536660
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1251216570
Short name T29
Test name
Test status
Simulation time 52233484 ps
CPU time 0.83 seconds
Started Jun 05 04:20:58 PM PDT 24
Finished Jun 05 04:21:00 PM PDT 24
Peak memory 218556 kb
Host smart-54f738cd-b4cd-4154-8955-7defbee11308
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251216570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1251216570
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2835041160
Short name T110
Test name
Test status
Simulation time 93189685 ps
CPU time 2.75 seconds
Started Jun 05 04:19:37 PM PDT 24
Finished Jun 05 04:19:40 PM PDT 24
Peak memory 199440 kb
Host smart-3dfdb4c7-77cf-4764-813d-f9b9a97ae97d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835041160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.2835041160
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/188.hmac_stress_all_with_rand_reset.4014692099
Short name T25
Test name
Test status
Simulation time 26468958478 ps
CPU time 2034.61 seconds
Started Jun 05 04:24:01 PM PDT 24
Finished Jun 05 04:57:56 PM PDT 24
Peak memory 733648 kb
Host smart-432d7ff7-fd0f-4921-851a-b784cd24f5e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4014692099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.hmac_stress_all_with_rand_reset.4014692099
Directory /workspace/188.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.399045410
Short name T102
Test name
Test status
Simulation time 4700037661 ps
CPU time 56.84 seconds
Started Jun 05 04:21:23 PM PDT 24
Finished Jun 05 04:22:20 PM PDT 24
Peak memory 230824 kb
Host smart-3326bca6-0624-4f64-b166-45776c854ce7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=399045410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.399045410
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_error.473073071
Short name T99
Test name
Test status
Simulation time 22299487032 ps
CPU time 104.52 seconds
Started Jun 05 04:21:23 PM PDT 24
Finished Jun 05 04:23:08 PM PDT 24
Peak memory 200080 kb
Host smart-e192de60-c285-4784-bd39-76466682ca71
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473073071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.473073071
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1619831216
Short name T68
Test name
Test status
Simulation time 16001213915 ps
CPU time 229.02 seconds
Started Jun 05 04:21:22 PM PDT 24
Finished Jun 05 04:25:12 PM PDT 24
Peak memory 216436 kb
Host smart-065ecdb2-c76c-464b-8c35-3dba315c1866
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619831216 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1619831216
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2070957095
Short name T100
Test name
Test status
Simulation time 6743266568 ps
CPU time 89.53 seconds
Started Jun 05 04:21:28 PM PDT 24
Finished Jun 05 04:22:58 PM PDT 24
Peak memory 200100 kb
Host smart-b2a66bc9-6a7d-4a5b-ae1a-65858f7d76a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070957095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2070957095
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.3746557419
Short name T103
Test name
Test status
Simulation time 2889024515 ps
CPU time 59.09 seconds
Started Jun 05 04:22:59 PM PDT 24
Finished Jun 05 04:23:59 PM PDT 24
Peak memory 200248 kb
Host smart-c2c1d5f2-2192-4cd9-a13d-8bc391205ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746557419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3746557419
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3572185072
Short name T53
Test name
Test status
Simulation time 437741059 ps
CPU time 4.1 seconds
Started Jun 05 04:19:45 PM PDT 24
Finished Jun 05 04:19:50 PM PDT 24
Peak memory 199392 kb
Host smart-a8c8d5dc-0556-49ea-9b2d-2c1f7e6d71c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572185072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3572185072
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2909341139
Short name T671
Test name
Test status
Simulation time 112501725 ps
CPU time 3.09 seconds
Started Jun 05 04:19:22 PM PDT 24
Finished Jun 05 04:19:25 PM PDT 24
Peak memory 199320 kb
Host smart-421ae38d-eafb-454d-b6c6-1406feb46e37
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909341139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2909341139
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.4251324526
Short name T702
Test name
Test status
Simulation time 210498205 ps
CPU time 9.64 seconds
Started Jun 05 04:19:18 PM PDT 24
Finished Jun 05 04:19:28 PM PDT 24
Peak memory 198404 kb
Host smart-06d55403-26ee-4ea4-94c1-ce519cbf36b3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251324526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.4251324526
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1265313375
Short name T676
Test name
Test status
Simulation time 71595175 ps
CPU time 0.74 seconds
Started Jun 05 04:19:22 PM PDT 24
Finished Jun 05 04:19:23 PM PDT 24
Peak memory 197200 kb
Host smart-8811f863-7ad0-4197-9c07-0a23de2cb611
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265313375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1265313375
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1575430327
Short name T628
Test name
Test status
Simulation time 64383557 ps
CPU time 1.96 seconds
Started Jun 05 04:19:19 PM PDT 24
Finished Jun 05 04:19:22 PM PDT 24
Peak memory 199468 kb
Host smart-1c8c234d-a146-4530-89fe-eb3ef35ac209
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575430327 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1575430327
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2909182761
Short name T720
Test name
Test status
Simulation time 146751147 ps
CPU time 0.67 seconds
Started Jun 05 04:19:19 PM PDT 24
Finished Jun 05 04:19:21 PM PDT 24
Peak memory 197044 kb
Host smart-17409d38-74f8-47a5-8dcf-26fd01634173
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909182761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2909182761
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.469020047
Short name T714
Test name
Test status
Simulation time 12174476 ps
CPU time 0.6 seconds
Started Jun 05 04:19:18 PM PDT 24
Finished Jun 05 04:19:20 PM PDT 24
Peak memory 194292 kb
Host smart-e702aed7-d02c-4408-a902-5e81b579b732
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469020047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.469020047
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.4000010664
Short name T659
Test name
Test status
Simulation time 141534628 ps
CPU time 2.45 seconds
Started Jun 05 04:19:16 PM PDT 24
Finished Jun 05 04:19:19 PM PDT 24
Peak memory 199244 kb
Host smart-166b9c1e-fb09-468e-bd24-391372d46bc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000010664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.4000010664
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3590418235
Short name T674
Test name
Test status
Simulation time 61382985 ps
CPU time 1.53 seconds
Started Jun 05 04:19:22 PM PDT 24
Finished Jun 05 04:19:24 PM PDT 24
Peak memory 199432 kb
Host smart-500374c4-70ad-4394-a071-980568b9ea6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590418235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.3590418235
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1825634985
Short name T692
Test name
Test status
Simulation time 381416143 ps
CPU time 2.95 seconds
Started Jun 05 04:19:16 PM PDT 24
Finished Jun 05 04:19:20 PM PDT 24
Peak memory 199368 kb
Host smart-b93cfa83-d050-48d3-99a5-7d4d22f19fe1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825634985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1825634985
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.275740750
Short name T84
Test name
Test status
Simulation time 1159100129 ps
CPU time 8.93 seconds
Started Jun 05 04:19:19 PM PDT 24
Finished Jun 05 04:19:28 PM PDT 24
Peak memory 199424 kb
Host smart-1da548cf-275b-4282-a8d0-9b583b5315f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275740750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.275740750
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3877200897
Short name T92
Test name
Test status
Simulation time 11813091299 ps
CPU time 11.5 seconds
Started Jun 05 04:19:15 PM PDT 24
Finished Jun 05 04:19:27 PM PDT 24
Peak memory 199368 kb
Host smart-857c5077-23b3-4c1b-8c07-d36ebb4b6ac5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877200897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3877200897
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2512887655
Short name T90
Test name
Test status
Simulation time 39097150 ps
CPU time 0.99 seconds
Started Jun 05 04:19:19 PM PDT 24
Finished Jun 05 04:19:21 PM PDT 24
Peak memory 199096 kb
Host smart-016734a3-84ae-410c-b629-e502a8bd4999
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512887655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2512887655
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.357673826
Short name T614
Test name
Test status
Simulation time 126757065 ps
CPU time 1.71 seconds
Started Jun 05 04:19:18 PM PDT 24
Finished Jun 05 04:19:21 PM PDT 24
Peak memory 199492 kb
Host smart-badb6994-8cba-40a4-882b-60b904c78c64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357673826 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.357673826
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.195157425
Short name T666
Test name
Test status
Simulation time 63955068 ps
CPU time 0.93 seconds
Started Jun 05 04:19:18 PM PDT 24
Finished Jun 05 04:19:20 PM PDT 24
Peak memory 198784 kb
Host smart-08642476-d70a-4ca4-91e1-b638277257e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195157425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.195157425
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.201855560
Short name T719
Test name
Test status
Simulation time 60548394 ps
CPU time 0.62 seconds
Started Jun 05 04:19:17 PM PDT 24
Finished Jun 05 04:19:18 PM PDT 24
Peak memory 194296 kb
Host smart-fb7d6839-c8ef-41a6-8f47-ccb79caf30b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201855560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.201855560
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3416116102
Short name T627
Test name
Test status
Simulation time 75392661 ps
CPU time 1.04 seconds
Started Jun 05 04:19:19 PM PDT 24
Finished Jun 05 04:19:21 PM PDT 24
Peak memory 199116 kb
Host smart-d8093913-01e1-4b71-8e9a-65c7a4c1f5dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416116102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.3416116102
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.874841306
Short name T668
Test name
Test status
Simulation time 423511076 ps
CPU time 2.77 seconds
Started Jun 05 04:19:18 PM PDT 24
Finished Jun 05 04:19:21 PM PDT 24
Peak memory 199472 kb
Host smart-0d6af200-f8bd-4c47-9d21-b256495724bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874841306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.874841306
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2629957259
Short name T51
Test name
Test status
Simulation time 1518010944 ps
CPU time 3.88 seconds
Started Jun 05 04:19:19 PM PDT 24
Finished Jun 05 04:19:24 PM PDT 24
Peak memory 199440 kb
Host smart-31666415-bdda-4020-bb3f-af94c835002b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629957259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2629957259
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.270452769
Short name T619
Test name
Test status
Simulation time 253303774 ps
CPU time 1.73 seconds
Started Jun 05 04:19:44 PM PDT 24
Finished Jun 05 04:19:46 PM PDT 24
Peak memory 199436 kb
Host smart-e5d26908-5acc-47cc-8f25-6cdf95cb3f43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270452769 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.270452769
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2753901392
Short name T707
Test name
Test status
Simulation time 296810663 ps
CPU time 0.97 seconds
Started Jun 05 04:19:46 PM PDT 24
Finished Jun 05 04:19:48 PM PDT 24
Peak memory 198880 kb
Host smart-92dbe329-7f9d-4039-a7ee-783b498e5c14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753901392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2753901392
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1138503413
Short name T722
Test name
Test status
Simulation time 13510706 ps
CPU time 0.57 seconds
Started Jun 05 04:19:45 PM PDT 24
Finished Jun 05 04:19:46 PM PDT 24
Peak memory 194196 kb
Host smart-dde9d578-7fb0-4aa5-afd4-abe98b7da1e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138503413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1138503413
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1406805970
Short name T649
Test name
Test status
Simulation time 79310536 ps
CPU time 1.65 seconds
Started Jun 05 04:19:44 PM PDT 24
Finished Jun 05 04:19:46 PM PDT 24
Peak memory 199344 kb
Host smart-3f51188b-44e6-430d-9f6e-5e4ba4a0b4bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406805970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1406805970
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1528479317
Short name T664
Test name
Test status
Simulation time 1076999984 ps
CPU time 3.16 seconds
Started Jun 05 04:19:45 PM PDT 24
Finished Jun 05 04:19:49 PM PDT 24
Peak memory 199468 kb
Host smart-80526fe0-be94-45a2-bc7f-03e5032e0464
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528479317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1528479317
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3949796094
Short name T687
Test name
Test status
Simulation time 554736742 ps
CPU time 4.81 seconds
Started Jun 05 04:19:45 PM PDT 24
Finished Jun 05 04:19:51 PM PDT 24
Peak memory 199472 kb
Host smart-3fa964bb-6200-4445-acb6-117faafe4e7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949796094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3949796094
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2994822055
Short name T703
Test name
Test status
Simulation time 52604194 ps
CPU time 1.64 seconds
Started Jun 05 04:19:44 PM PDT 24
Finished Jun 05 04:19:47 PM PDT 24
Peak memory 199508 kb
Host smart-6e8fa575-341a-4422-9068-c29b19edd2d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994822055 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.2994822055
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.220531275
Short name T610
Test name
Test status
Simulation time 111876424 ps
CPU time 0.94 seconds
Started Jun 05 04:19:42 PM PDT 24
Finished Jun 05 04:19:43 PM PDT 24
Peak memory 198608 kb
Host smart-734e4457-a5ca-4a1c-886a-f7fe9e74eea9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220531275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.220531275
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1614720101
Short name T691
Test name
Test status
Simulation time 63922952 ps
CPU time 0.61 seconds
Started Jun 05 04:19:43 PM PDT 24
Finished Jun 05 04:19:45 PM PDT 24
Peak memory 194228 kb
Host smart-546bee3f-af7c-4d22-8819-5894e2311958
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614720101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1614720101
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.256724533
Short name T656
Test name
Test status
Simulation time 86427218 ps
CPU time 2.1 seconds
Started Jun 05 04:19:44 PM PDT 24
Finished Jun 05 04:19:47 PM PDT 24
Peak memory 199348 kb
Host smart-d58c8f67-20dd-49b5-82fe-cbdea80c758f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256724533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.256724533
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4098585863
Short name T612
Test name
Test status
Simulation time 180044759 ps
CPU time 3.68 seconds
Started Jun 05 04:19:43 PM PDT 24
Finished Jun 05 04:19:47 PM PDT 24
Peak memory 199380 kb
Host smart-c31c8301-e020-4a7d-b190-7149514af91a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098585863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.4098585863
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2716034823
Short name T640
Test name
Test status
Simulation time 289638212613 ps
CPU time 1012.83 seconds
Started Jun 05 04:19:43 PM PDT 24
Finished Jun 05 04:36:36 PM PDT 24
Peak memory 215940 kb
Host smart-91c0cf63-b960-454d-8c00-9cd51f3ecece
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716034823 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.2716034823
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1691656837
Short name T91
Test name
Test status
Simulation time 42537400 ps
CPU time 0.83 seconds
Started Jun 05 04:19:44 PM PDT 24
Finished Jun 05 04:19:46 PM PDT 24
Peak memory 197100 kb
Host smart-d9aa157a-0427-424b-b498-df6a7470692e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691656837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1691656837
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.987631133
Short name T621
Test name
Test status
Simulation time 164354361 ps
CPU time 0.6 seconds
Started Jun 05 04:19:43 PM PDT 24
Finished Jun 05 04:19:44 PM PDT 24
Peak memory 194264 kb
Host smart-dfde904d-5046-49e7-a760-f0aa83864504
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987631133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.987631133
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2504264229
Short name T624
Test name
Test status
Simulation time 86373313 ps
CPU time 1.1 seconds
Started Jun 05 04:19:43 PM PDT 24
Finished Jun 05 04:19:45 PM PDT 24
Peak memory 199432 kb
Host smart-29dbd1cb-6d23-447d-a480-2856c14a29e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504264229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2504264229
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.787472456
Short name T638
Test name
Test status
Simulation time 181607335 ps
CPU time 3.83 seconds
Started Jun 05 04:19:44 PM PDT 24
Finished Jun 05 04:19:48 PM PDT 24
Peak memory 199492 kb
Host smart-7482df19-1926-45d1-bc33-6cd1cdb287e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787472456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.787472456
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3150137971
Short name T660
Test name
Test status
Simulation time 124273757 ps
CPU time 2.85 seconds
Started Jun 05 04:19:42 PM PDT 24
Finished Jun 05 04:19:45 PM PDT 24
Peak memory 199476 kb
Host smart-a587322a-53bd-4250-a97d-983fb2f9743a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150137971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3150137971
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1763529281
Short name T682
Test name
Test status
Simulation time 186707873 ps
CPU time 3.05 seconds
Started Jun 05 04:19:55 PM PDT 24
Finished Jun 05 04:19:59 PM PDT 24
Peak memory 207672 kb
Host smart-597f5642-341b-424f-bcd0-c42f42b287b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763529281 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1763529281
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2039087121
Short name T83
Test name
Test status
Simulation time 16303295 ps
CPU time 0.8 seconds
Started Jun 05 04:19:53 PM PDT 24
Finished Jun 05 04:19:55 PM PDT 24
Peak memory 198904 kb
Host smart-0e6ccd4d-59ef-41cc-9d04-76dffa19155c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039087121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2039087121
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.1347226853
Short name T700
Test name
Test status
Simulation time 13326678 ps
CPU time 0.6 seconds
Started Jun 05 04:19:53 PM PDT 24
Finished Jun 05 04:19:54 PM PDT 24
Peak memory 194200 kb
Host smart-7d018825-fc34-4814-b2f4-0de4726ec1f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347226853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1347226853
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2077200266
Short name T608
Test name
Test status
Simulation time 88968635 ps
CPU time 1.15 seconds
Started Jun 05 04:19:52 PM PDT 24
Finished Jun 05 04:19:53 PM PDT 24
Peak memory 197616 kb
Host smart-9d4dd220-c434-4605-a803-10e3f7a29efd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077200266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2077200266
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1615771155
Short name T693
Test name
Test status
Simulation time 442292792 ps
CPU time 2.12 seconds
Started Jun 05 04:19:56 PM PDT 24
Finished Jun 05 04:19:59 PM PDT 24
Peak memory 199524 kb
Host smart-92a7bac6-0860-486d-b9de-5c2c21a27e72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615771155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1615771155
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3384349018
Short name T678
Test name
Test status
Simulation time 157357662 ps
CPU time 1.92 seconds
Started Jun 05 04:19:53 PM PDT 24
Finished Jun 05 04:19:55 PM PDT 24
Peak memory 199440 kb
Host smart-fd6768bb-378d-4b12-a4f7-0f21a55ba3c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384349018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3384349018
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1207124565
Short name T79
Test name
Test status
Simulation time 125524353 ps
CPU time 2.3 seconds
Started Jun 05 04:19:54 PM PDT 24
Finished Jun 05 04:19:58 PM PDT 24
Peak memory 207708 kb
Host smart-a6b4fd17-c8c6-4721-baa8-8ea635956582
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207124565 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1207124565
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.784891769
Short name T89
Test name
Test status
Simulation time 15007399 ps
CPU time 0.81 seconds
Started Jun 05 04:19:54 PM PDT 24
Finished Jun 05 04:19:55 PM PDT 24
Peak memory 198884 kb
Host smart-db3ceba0-ead3-4aca-88ad-616fd5cdbb48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784891769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.784891769
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.4033592632
Short name T601
Test name
Test status
Simulation time 40019484 ps
CPU time 0.6 seconds
Started Jun 05 04:19:53 PM PDT 24
Finished Jun 05 04:19:54 PM PDT 24
Peak memory 194200 kb
Host smart-8558ef50-6677-47cb-b9be-7f7b391a005b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033592632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.4033592632
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1593636788
Short name T677
Test name
Test status
Simulation time 87461925 ps
CPU time 1.7 seconds
Started Jun 05 04:19:52 PM PDT 24
Finished Jun 05 04:19:55 PM PDT 24
Peak memory 199612 kb
Host smart-fe9aa603-6a9a-443c-bd99-e0ab59d490cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593636788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1593636788
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2831317651
Short name T632
Test name
Test status
Simulation time 413113035 ps
CPU time 1.36 seconds
Started Jun 05 04:19:54 PM PDT 24
Finished Jun 05 04:19:57 PM PDT 24
Peak memory 199436 kb
Host smart-9a850f1f-cd9e-4271-ad5f-866a6f137064
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831317651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2831317651
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.4294751118
Short name T633
Test name
Test status
Simulation time 46996706918 ps
CPU time 126.52 seconds
Started Jun 05 04:19:55 PM PDT 24
Finished Jun 05 04:22:02 PM PDT 24
Peak memory 215936 kb
Host smart-405e9d27-f1d6-4897-a786-8440a8e527f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294751118 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.4294751118
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1480959486
Short name T629
Test name
Test status
Simulation time 30667079 ps
CPU time 0.83 seconds
Started Jun 05 04:19:54 PM PDT 24
Finished Jun 05 04:19:55 PM PDT 24
Peak memory 198332 kb
Host smart-2f510dd9-2a85-4d94-b03d-eeffd1117620
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480959486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1480959486
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1464208466
Short name T596
Test name
Test status
Simulation time 16598003 ps
CPU time 0.56 seconds
Started Jun 05 04:19:55 PM PDT 24
Finished Jun 05 04:19:57 PM PDT 24
Peak memory 194204 kb
Host smart-e0674c78-59d4-432c-ac3a-b648452aefe3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464208466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1464208466
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2701699517
Short name T620
Test name
Test status
Simulation time 208483456 ps
CPU time 1.26 seconds
Started Jun 05 04:19:56 PM PDT 24
Finished Jun 05 04:19:58 PM PDT 24
Peak memory 199400 kb
Host smart-67b9d722-796a-4783-ace9-26633d73801e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701699517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2701699517
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1367333115
Short name T715
Test name
Test status
Simulation time 469085465 ps
CPU time 2.34 seconds
Started Jun 05 04:19:53 PM PDT 24
Finished Jun 05 04:19:56 PM PDT 24
Peak memory 199448 kb
Host smart-402e6be2-074e-4f2c-bb8c-9ae6acbce058
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367333115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1367333115
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1361523959
Short name T111
Test name
Test status
Simulation time 90591254 ps
CPU time 2.85 seconds
Started Jun 05 04:19:56 PM PDT 24
Finished Jun 05 04:20:00 PM PDT 24
Peak memory 199416 kb
Host smart-739ea57d-ab4d-4595-8e46-3728ca5e175a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361523959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1361523959
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1464330272
Short name T665
Test name
Test status
Simulation time 183400990 ps
CPU time 2.6 seconds
Started Jun 05 04:19:56 PM PDT 24
Finished Jun 05 04:19:59 PM PDT 24
Peak memory 199500 kb
Host smart-cc4bcf03-d753-463a-bb9f-c4797b8b1397
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464330272 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.1464330272
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1431857119
Short name T661
Test name
Test status
Simulation time 81675981 ps
CPU time 0.81 seconds
Started Jun 05 04:19:53 PM PDT 24
Finished Jun 05 04:19:55 PM PDT 24
Peak memory 198128 kb
Host smart-5803ea3b-574d-4c3b-a341-cafa98397dc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431857119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1431857119
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.2350861374
Short name T673
Test name
Test status
Simulation time 104021286 ps
CPU time 0.58 seconds
Started Jun 05 04:19:56 PM PDT 24
Finished Jun 05 04:19:58 PM PDT 24
Peak memory 194200 kb
Host smart-aa43af1b-d347-448e-9ab2-41e9c63ac437
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350861374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2350861374
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.344932566
Short name T685
Test name
Test status
Simulation time 171314754 ps
CPU time 1.7 seconds
Started Jun 05 04:19:55 PM PDT 24
Finished Jun 05 04:19:57 PM PDT 24
Peak memory 199416 kb
Host smart-70b8c439-c4b9-4317-9605-7c7d82852e59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344932566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr
_outstanding.344932566
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.4023427006
Short name T654
Test name
Test status
Simulation time 798477583 ps
CPU time 2.92 seconds
Started Jun 05 04:19:55 PM PDT 24
Finished Jun 05 04:19:59 PM PDT 24
Peak memory 199464 kb
Host smart-79e84143-917f-4d83-9e41-e5918cabec62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023427006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.4023427006
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.608897429
Short name T641
Test name
Test status
Simulation time 87626736 ps
CPU time 1.88 seconds
Started Jun 05 04:19:54 PM PDT 24
Finished Jun 05 04:19:57 PM PDT 24
Peak memory 199440 kb
Host smart-a85f1ee6-bd34-4e7e-a54f-1ea3f388b465
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608897429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.608897429
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2379990725
Short name T718
Test name
Test status
Simulation time 66416042 ps
CPU time 1.15 seconds
Started Jun 05 04:20:02 PM PDT 24
Finished Jun 05 04:20:05 PM PDT 24
Peak memory 199244 kb
Host smart-4e1dc808-e364-424b-a854-9fd14a4c4edc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379990725 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2379990725
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1455740123
Short name T96
Test name
Test status
Simulation time 59621388 ps
CPU time 0.83 seconds
Started Jun 05 04:19:56 PM PDT 24
Finished Jun 05 04:19:58 PM PDT 24
Peak memory 198824 kb
Host smart-f620e7ff-1bcd-4e7e-be3e-cf6645069101
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455740123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1455740123
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.4138656116
Short name T725
Test name
Test status
Simulation time 13843581 ps
CPU time 0.56 seconds
Started Jun 05 04:19:57 PM PDT 24
Finished Jun 05 04:19:59 PM PDT 24
Peak memory 194200 kb
Host smart-17740c52-8477-47ee-a23e-ef4c12176122
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138656116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.4138656116
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.876244048
Short name T626
Test name
Test status
Simulation time 55722736 ps
CPU time 1.5 seconds
Started Jun 05 04:19:55 PM PDT 24
Finished Jun 05 04:19:58 PM PDT 24
Peak memory 199432 kb
Host smart-440f34e5-aa81-4f2d-b33a-da51505114f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876244048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr
_outstanding.876244048
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.68775418
Short name T706
Test name
Test status
Simulation time 159572063 ps
CPU time 3.22 seconds
Started Jun 05 04:19:55 PM PDT 24
Finished Jun 05 04:19:59 PM PDT 24
Peak memory 199508 kb
Host smart-753762f0-91bf-43dd-8b87-1660cf379f31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68775418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.68775418
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.718346492
Short name T688
Test name
Test status
Simulation time 270842369 ps
CPU time 1.73 seconds
Started Jun 05 04:19:56 PM PDT 24
Finished Jun 05 04:19:59 PM PDT 24
Peak memory 199440 kb
Host smart-daaaff86-5ce4-46a1-98db-d2bac522093c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718346492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.718346492
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3996578162
Short name T681
Test name
Test status
Simulation time 64475280 ps
CPU time 1.2 seconds
Started Jun 05 04:20:00 PM PDT 24
Finished Jun 05 04:20:02 PM PDT 24
Peak memory 199292 kb
Host smart-1427bf75-db81-48a1-a477-0a20fed8ee22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996578162 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3996578162
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1380833806
Short name T87
Test name
Test status
Simulation time 109286716 ps
CPU time 0.91 seconds
Started Jun 05 04:20:03 PM PDT 24
Finished Jun 05 04:20:05 PM PDT 24
Peak memory 199120 kb
Host smart-14f9156e-a9b6-460b-8e60-67399c4f195b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380833806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1380833806
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3808953080
Short name T690
Test name
Test status
Simulation time 12802017 ps
CPU time 0.61 seconds
Started Jun 05 04:20:01 PM PDT 24
Finished Jun 05 04:20:02 PM PDT 24
Peak memory 194124 kb
Host smart-27593f42-45d9-4434-b991-df787d24148f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808953080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3808953080
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.753142323
Short name T675
Test name
Test status
Simulation time 75187008 ps
CPU time 1.72 seconds
Started Jun 05 04:20:00 PM PDT 24
Finished Jun 05 04:20:03 PM PDT 24
Peak memory 199476 kb
Host smart-187b47cf-43d6-4e7a-9e59-0df00171f7f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753142323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.753142323
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4064284227
Short name T689
Test name
Test status
Simulation time 93025813 ps
CPU time 2.35 seconds
Started Jun 05 04:19:58 PM PDT 24
Finished Jun 05 04:20:01 PM PDT 24
Peak memory 199528 kb
Host smart-57f71e3e-8af7-4d34-9f18-cd62f9f11f63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064284227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.4064284227
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2994434136
Short name T112
Test name
Test status
Simulation time 264811495 ps
CPU time 4.32 seconds
Started Jun 05 04:19:59 PM PDT 24
Finished Jun 05 04:20:04 PM PDT 24
Peak memory 199476 kb
Host smart-7b4b715c-1d6c-4762-9167-20f0b21f98b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994434136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2994434136
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3270463558
Short name T646
Test name
Test status
Simulation time 131668985237 ps
CPU time 1422.01 seconds
Started Jun 05 04:20:01 PM PDT 24
Finished Jun 05 04:43:44 PM PDT 24
Peak memory 218976 kb
Host smart-fe95c3ac-1638-4895-b03d-a24f2fa0ba6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270463558 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3270463558
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.324353598
Short name T94
Test name
Test status
Simulation time 19337058 ps
CPU time 0.95 seconds
Started Jun 05 04:20:07 PM PDT 24
Finished Jun 05 04:20:09 PM PDT 24
Peak memory 198868 kb
Host smart-79874d5f-0baf-41ae-b203-9601606836db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324353598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.324353598
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.3982204698
Short name T696
Test name
Test status
Simulation time 23566077 ps
CPU time 0.62 seconds
Started Jun 05 04:20:04 PM PDT 24
Finished Jun 05 04:20:06 PM PDT 24
Peak memory 194264 kb
Host smart-2a7c5cfb-ad90-49d3-9653-8fe9e6699b7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982204698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3982204698
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.178042604
Short name T625
Test name
Test status
Simulation time 104948790 ps
CPU time 1.72 seconds
Started Jun 05 04:20:00 PM PDT 24
Finished Jun 05 04:20:03 PM PDT 24
Peak memory 199432 kb
Host smart-248d3759-5b0f-4926-bdfc-e04d6a3d4a0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178042604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.178042604
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.882547499
Short name T644
Test name
Test status
Simulation time 1197044328 ps
CPU time 3.38 seconds
Started Jun 05 04:20:03 PM PDT 24
Finished Jun 05 04:20:07 PM PDT 24
Peak memory 199424 kb
Host smart-2b6a7d6c-f600-4958-83f2-ebd0eb59b656
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882547499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.882547499
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.131096442
Short name T109
Test name
Test status
Simulation time 133422219 ps
CPU time 4.08 seconds
Started Jun 05 04:20:07 PM PDT 24
Finished Jun 05 04:20:12 PM PDT 24
Peak memory 199444 kb
Host smart-17a8f9e9-edfa-4e15-b3f9-6aaa8c38ebd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131096442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.131096442
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1587171534
Short name T93
Test name
Test status
Simulation time 59260476 ps
CPU time 3.08 seconds
Started Jun 05 04:19:33 PM PDT 24
Finished Jun 05 04:19:37 PM PDT 24
Peak memory 199404 kb
Host smart-7bc806b2-ca42-475d-998f-341b678a2404
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587171534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1587171534
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.502268922
Short name T630
Test name
Test status
Simulation time 218002095 ps
CPU time 5.18 seconds
Started Jun 05 04:19:28 PM PDT 24
Finished Jun 05 04:19:34 PM PDT 24
Peak memory 199252 kb
Host smart-593630eb-9af8-460b-bcd1-639930e8b736
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502268922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.502268922
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2118059966
Short name T85
Test name
Test status
Simulation time 207513319 ps
CPU time 1 seconds
Started Jun 05 04:19:28 PM PDT 24
Finished Jun 05 04:19:30 PM PDT 24
Peak memory 199140 kb
Host smart-7e505c60-799d-4584-b35f-9838d4f746e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118059966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2118059966
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3681096995
Short name T658
Test name
Test status
Simulation time 11289522399 ps
CPU time 88.91 seconds
Started Jun 05 04:19:34 PM PDT 24
Finished Jun 05 04:21:04 PM PDT 24
Peak memory 215212 kb
Host smart-51edb162-e4ab-4a40-a889-ce7d94e216c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681096995 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3681096995
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.800786203
Short name T680
Test name
Test status
Simulation time 27446032 ps
CPU time 0.82 seconds
Started Jun 05 04:19:31 PM PDT 24
Finished Jun 05 04:19:33 PM PDT 24
Peak memory 199104 kb
Host smart-521aed62-9784-451a-973a-4f6faf10bcf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800786203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.800786203
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.1811482239
Short name T636
Test name
Test status
Simulation time 19493373 ps
CPU time 0.56 seconds
Started Jun 05 04:19:27 PM PDT 24
Finished Jun 05 04:19:28 PM PDT 24
Peak memory 194268 kb
Host smart-9ded645b-fa98-43ce-bbd1-2a52e47236cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811482239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1811482239
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2884149822
Short name T617
Test name
Test status
Simulation time 102769994 ps
CPU time 1.78 seconds
Started Jun 05 04:19:26 PM PDT 24
Finished Jun 05 04:19:29 PM PDT 24
Peak memory 199368 kb
Host smart-fe9c43d1-21f9-48b2-8f76-36bfaa78f2e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884149822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2884149822
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3468857835
Short name T631
Test name
Test status
Simulation time 103441849 ps
CPU time 2.37 seconds
Started Jun 05 04:19:33 PM PDT 24
Finished Jun 05 04:19:36 PM PDT 24
Peak memory 199544 kb
Host smart-ac8db250-cc93-4d32-85ce-01954013ca4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468857835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3468857835
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2461258422
Short name T114
Test name
Test status
Simulation time 374837402 ps
CPU time 3.04 seconds
Started Jun 05 04:19:26 PM PDT 24
Finished Jun 05 04:19:30 PM PDT 24
Peak memory 199356 kb
Host smart-f00778de-7dc3-4938-b79c-409f1cedb8a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461258422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2461258422
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1060066150
Short name T635
Test name
Test status
Simulation time 15443047 ps
CPU time 0.57 seconds
Started Jun 05 04:20:03 PM PDT 24
Finished Jun 05 04:20:05 PM PDT 24
Peak memory 194216 kb
Host smart-dce4409f-5abb-4548-ace7-1c3bae8f1b3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060066150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1060066150
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2576963994
Short name T686
Test name
Test status
Simulation time 11911124 ps
CPU time 0.57 seconds
Started Jun 05 04:20:00 PM PDT 24
Finished Jun 05 04:20:02 PM PDT 24
Peak memory 194200 kb
Host smart-138e28e8-32b1-4afc-b231-a5906a1ef654
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576963994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2576963994
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.418983530
Short name T650
Test name
Test status
Simulation time 48194370 ps
CPU time 0.62 seconds
Started Jun 05 04:20:01 PM PDT 24
Finished Jun 05 04:20:03 PM PDT 24
Peak memory 194276 kb
Host smart-d58dc468-84d7-42ea-a300-f5e32dc823af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418983530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.418983530
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2101307323
Short name T639
Test name
Test status
Simulation time 17870396 ps
CPU time 0.6 seconds
Started Jun 05 04:20:02 PM PDT 24
Finished Jun 05 04:20:04 PM PDT 24
Peak memory 194184 kb
Host smart-1aa5679f-c211-415c-a647-35ff60d610c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101307323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2101307323
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.267938606
Short name T642
Test name
Test status
Simulation time 47460491 ps
CPU time 0.62 seconds
Started Jun 05 04:20:01 PM PDT 24
Finished Jun 05 04:20:03 PM PDT 24
Peak memory 194264 kb
Host smart-c2486afd-a211-4a3f-909a-6e61cf529c06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267938606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.267938606
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1003225422
Short name T602
Test name
Test status
Simulation time 57274127 ps
CPU time 0.62 seconds
Started Jun 05 04:19:59 PM PDT 24
Finished Jun 05 04:20:00 PM PDT 24
Peak memory 194192 kb
Host smart-9ae19f84-0c82-4b3b-840c-765e3b3370a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003225422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1003225422
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3410770754
Short name T713
Test name
Test status
Simulation time 139929092 ps
CPU time 0.67 seconds
Started Jun 05 04:20:00 PM PDT 24
Finished Jun 05 04:20:02 PM PDT 24
Peak memory 194128 kb
Host smart-c5ac6ce3-389d-4ab8-b1ed-c899937389ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410770754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3410770754
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2199275451
Short name T616
Test name
Test status
Simulation time 24075640 ps
CPU time 0.63 seconds
Started Jun 05 04:20:03 PM PDT 24
Finished Jun 05 04:20:05 PM PDT 24
Peak memory 194080 kb
Host smart-5f52ca5a-975b-4494-9ef7-15a0aac5b450
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199275451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2199275451
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2536879751
Short name T698
Test name
Test status
Simulation time 22440546 ps
CPU time 0.64 seconds
Started Jun 05 04:20:03 PM PDT 24
Finished Jun 05 04:20:05 PM PDT 24
Peak memory 194292 kb
Host smart-20b01ac1-e8c8-4bf0-9f9f-0df42c470b5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536879751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2536879751
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2534101035
Short name T599
Test name
Test status
Simulation time 13681945 ps
CPU time 0.63 seconds
Started Jun 05 04:20:03 PM PDT 24
Finished Jun 05 04:20:05 PM PDT 24
Peak memory 194264 kb
Host smart-8ddabd6e-699c-4770-a2a1-fd37c36a3111
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534101035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2534101035
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.121748373
Short name T708
Test name
Test status
Simulation time 1576906418 ps
CPU time 8.84 seconds
Started Jun 05 04:19:27 PM PDT 24
Finished Jun 05 04:19:36 PM PDT 24
Peak memory 199372 kb
Host smart-0f6ed4ae-0b4d-4daf-bdc9-7250bae04ceb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121748373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.121748373
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.984742294
Short name T643
Test name
Test status
Simulation time 1471614628 ps
CPU time 5.75 seconds
Started Jun 05 04:19:26 PM PDT 24
Finished Jun 05 04:19:32 PM PDT 24
Peak memory 199316 kb
Host smart-76c0b448-d8c9-49f6-b8e0-4416d78fd320
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984742294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.984742294
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1854548641
Short name T603
Test name
Test status
Simulation time 116017927 ps
CPU time 0.96 seconds
Started Jun 05 04:19:29 PM PDT 24
Finished Jun 05 04:19:31 PM PDT 24
Peak memory 198652 kb
Host smart-b939d82b-a95e-49d8-b7f7-ebf80457c5aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854548641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1854548641
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3025426852
Short name T600
Test name
Test status
Simulation time 68064538 ps
CPU time 2.02 seconds
Started Jun 05 04:19:33 PM PDT 24
Finished Jun 05 04:19:36 PM PDT 24
Peak memory 199500 kb
Host smart-b8f26aa1-b9d9-43ba-b915-dab1e5e3465d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025426852 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.3025426852
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3841271038
Short name T88
Test name
Test status
Simulation time 33494770 ps
CPU time 0.95 seconds
Started Jun 05 04:19:34 PM PDT 24
Finished Jun 05 04:19:36 PM PDT 24
Peak memory 198896 kb
Host smart-14bf99eb-9cae-4cb0-870b-122c571dda2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841271038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3841271038
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.4052949316
Short name T669
Test name
Test status
Simulation time 14155816 ps
CPU time 0.6 seconds
Started Jun 05 04:19:34 PM PDT 24
Finished Jun 05 04:19:35 PM PDT 24
Peak memory 194236 kb
Host smart-e9514aa2-c410-47ee-956c-de6623faccc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052949316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.4052949316
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1534059203
Short name T697
Test name
Test status
Simulation time 222234620 ps
CPU time 1.16 seconds
Started Jun 05 04:19:27 PM PDT 24
Finished Jun 05 04:19:30 PM PDT 24
Peak memory 197916 kb
Host smart-772671a9-fd8c-4aff-b414-b5d9ad862be1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534059203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.1534059203
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1792196252
Short name T623
Test name
Test status
Simulation time 32127409 ps
CPU time 1.51 seconds
Started Jun 05 04:19:26 PM PDT 24
Finished Jun 05 04:19:28 PM PDT 24
Peak memory 199504 kb
Host smart-3bb14d04-28c8-473c-b395-e5e726a73263
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792196252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1792196252
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2692538283
Short name T683
Test name
Test status
Simulation time 130215904 ps
CPU time 3.97 seconds
Started Jun 05 04:19:25 PM PDT 24
Finished Jun 05 04:19:30 PM PDT 24
Peak memory 199452 kb
Host smart-181f510b-8864-4116-a24c-e9bd6917a0e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692538283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2692538283
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.242099225
Short name T704
Test name
Test status
Simulation time 31148011 ps
CPU time 0.67 seconds
Started Jun 05 04:20:00 PM PDT 24
Finished Jun 05 04:20:02 PM PDT 24
Peak memory 194264 kb
Host smart-8539c2c8-2519-40fa-b61a-121358e96c1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242099225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.242099225
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.4276506128
Short name T711
Test name
Test status
Simulation time 41827347 ps
CPU time 0.64 seconds
Started Jun 05 04:20:01 PM PDT 24
Finished Jun 05 04:20:03 PM PDT 24
Peak memory 194260 kb
Host smart-30a78610-bed2-49d6-bb5c-22224c6e78d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276506128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.4276506128
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3925107004
Short name T721
Test name
Test status
Simulation time 24276820 ps
CPU time 0.61 seconds
Started Jun 05 04:20:01 PM PDT 24
Finished Jun 05 04:20:03 PM PDT 24
Peak memory 194268 kb
Host smart-7253babb-c7f7-42ca-a1fa-11a7ce897af4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925107004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3925107004
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2661816991
Short name T663
Test name
Test status
Simulation time 32484530 ps
CPU time 0.61 seconds
Started Jun 05 04:20:01 PM PDT 24
Finished Jun 05 04:20:03 PM PDT 24
Peak memory 194200 kb
Host smart-3d6a852a-fc2a-433e-bafb-62540f3cf094
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661816991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2661816991
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1335487613
Short name T717
Test name
Test status
Simulation time 15382689 ps
CPU time 0.61 seconds
Started Jun 05 04:20:00 PM PDT 24
Finished Jun 05 04:20:01 PM PDT 24
Peak memory 194200 kb
Host smart-db0f7dd7-a75d-4e85-a38d-71abd9406fba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335487613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1335487613
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1238057721
Short name T592
Test name
Test status
Simulation time 10673636 ps
CPU time 0.59 seconds
Started Jun 05 04:20:00 PM PDT 24
Finished Jun 05 04:20:01 PM PDT 24
Peak memory 194264 kb
Host smart-e84f72af-3276-4319-aa2b-d1e8b699e9ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238057721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1238057721
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3223802732
Short name T637
Test name
Test status
Simulation time 31117751 ps
CPU time 0.64 seconds
Started Jun 05 04:20:04 PM PDT 24
Finished Jun 05 04:20:05 PM PDT 24
Peak memory 194264 kb
Host smart-a1f74de0-6b14-4d91-908e-e9ed5e32eafe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223802732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3223802732
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1725353145
Short name T598
Test name
Test status
Simulation time 14515755 ps
CPU time 0.63 seconds
Started Jun 05 04:20:07 PM PDT 24
Finished Jun 05 04:20:08 PM PDT 24
Peak memory 194204 kb
Host smart-7a82b9c4-18e6-44f6-85d8-70bc641cbc7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725353145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1725353145
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.1396538969
Short name T667
Test name
Test status
Simulation time 16178965 ps
CPU time 0.6 seconds
Started Jun 05 04:20:02 PM PDT 24
Finished Jun 05 04:20:04 PM PDT 24
Peak memory 194200 kb
Host smart-4d89610a-03cd-4acc-95b8-663747102f21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396538969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1396538969
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1287131212
Short name T701
Test name
Test status
Simulation time 44948375 ps
CPU time 0.63 seconds
Started Jun 05 04:20:01 PM PDT 24
Finished Jun 05 04:20:03 PM PDT 24
Peak memory 194196 kb
Host smart-a2b45cfd-3ac1-4439-a5ac-50534c47d609
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287131212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1287131212
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3437020337
Short name T726
Test name
Test status
Simulation time 4227985727 ps
CPU time 11.23 seconds
Started Jun 05 04:19:35 PM PDT 24
Finished Jun 05 04:19:48 PM PDT 24
Peak memory 198824 kb
Host smart-30377427-d4d9-401e-a998-1cdfda14d137
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437020337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3437020337
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1000188342
Short name T710
Test name
Test status
Simulation time 72133258 ps
CPU time 0.81 seconds
Started Jun 05 04:19:35 PM PDT 24
Finished Jun 05 04:19:37 PM PDT 24
Peak memory 197192 kb
Host smart-914c2783-ea7b-4bda-b644-8707dc4ee5c7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000188342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1000188342
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.162266123
Short name T694
Test name
Test status
Simulation time 22881272 ps
CPU time 1.44 seconds
Started Jun 05 04:19:35 PM PDT 24
Finished Jun 05 04:19:37 PM PDT 24
Peak memory 199488 kb
Host smart-de680c7c-6216-406f-839a-5fd6f295957a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162266123 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.162266123
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2038285622
Short name T86
Test name
Test status
Simulation time 84576906 ps
CPU time 1.01 seconds
Started Jun 05 04:19:36 PM PDT 24
Finished Jun 05 04:19:38 PM PDT 24
Peak memory 198956 kb
Host smart-e9ca29be-48e3-44da-954e-715a444c2eaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038285622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2038285622
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.1942482947
Short name T648
Test name
Test status
Simulation time 35605849 ps
CPU time 0.6 seconds
Started Jun 05 04:19:35 PM PDT 24
Finished Jun 05 04:19:36 PM PDT 24
Peak memory 194200 kb
Host smart-e76803f0-d708-4ee5-b480-d93d5c91f88d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942482947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1942482947
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.4274446547
Short name T670
Test name
Test status
Simulation time 109332373 ps
CPU time 1.83 seconds
Started Jun 05 04:19:34 PM PDT 24
Finished Jun 05 04:19:37 PM PDT 24
Peak memory 199432 kb
Host smart-48e883af-4304-484d-bf36-67b03d8b9c59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274446547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.4274446547
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.498763138
Short name T609
Test name
Test status
Simulation time 90370475 ps
CPU time 1.84 seconds
Started Jun 05 04:19:26 PM PDT 24
Finished Jun 05 04:19:29 PM PDT 24
Peak memory 199524 kb
Host smart-2f9585db-9a71-443c-b950-8bab63f4de45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498763138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.498763138
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2344829893
Short name T108
Test name
Test status
Simulation time 165029934 ps
CPU time 3.15 seconds
Started Jun 05 04:19:36 PM PDT 24
Finished Jun 05 04:19:40 PM PDT 24
Peak memory 199436 kb
Host smart-d95bb7ee-fc3d-4849-a973-baef40747357
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344829893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2344829893
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.3055351193
Short name T712
Test name
Test status
Simulation time 13914945 ps
CPU time 0.58 seconds
Started Jun 05 04:20:00 PM PDT 24
Finished Jun 05 04:20:02 PM PDT 24
Peak memory 194260 kb
Host smart-a1e6c0e9-50dc-4d62-915e-ad7f76957cc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055351193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3055351193
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2659307
Short name T699
Test name
Test status
Simulation time 14662772 ps
CPU time 0.61 seconds
Started Jun 05 04:20:07 PM PDT 24
Finished Jun 05 04:20:08 PM PDT 24
Peak memory 194196 kb
Host smart-c8eebf32-c1b2-4911-b0df-fc25a2693502
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2659307
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3447714220
Short name T615
Test name
Test status
Simulation time 45359152 ps
CPU time 0.58 seconds
Started Jun 05 04:20:00 PM PDT 24
Finished Jun 05 04:20:01 PM PDT 24
Peak memory 194212 kb
Host smart-57a32191-d6dc-4d0b-b519-e5b2ea909adf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447714220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3447714220
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3128278296
Short name T595
Test name
Test status
Simulation time 28150380 ps
CPU time 0.62 seconds
Started Jun 05 04:20:02 PM PDT 24
Finished Jun 05 04:20:03 PM PDT 24
Peak memory 193816 kb
Host smart-b998008c-3615-45e6-8a01-25f5d1e8fc0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128278296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3128278296
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.886880098
Short name T597
Test name
Test status
Simulation time 43653540 ps
CPU time 0.64 seconds
Started Jun 05 04:20:02 PM PDT 24
Finished Jun 05 04:20:03 PM PDT 24
Peak memory 194272 kb
Host smart-0cff61d6-611c-42de-9103-ad28d85cfce9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886880098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.886880098
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.402434672
Short name T634
Test name
Test status
Simulation time 20379074 ps
CPU time 0.6 seconds
Started Jun 05 04:20:02 PM PDT 24
Finished Jun 05 04:20:03 PM PDT 24
Peak memory 193740 kb
Host smart-4c954bb1-a78c-492f-bfec-2c7acf02a6e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402434672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.402434672
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.506413465
Short name T705
Test name
Test status
Simulation time 61950024 ps
CPU time 0.6 seconds
Started Jun 05 04:20:04 PM PDT 24
Finished Jun 05 04:20:06 PM PDT 24
Peak memory 194204 kb
Host smart-f03d56de-dd8a-4a55-8452-5d81de28565e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506413465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.506413465
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.465590431
Short name T593
Test name
Test status
Simulation time 12313599 ps
CPU time 0.6 seconds
Started Jun 05 04:20:03 PM PDT 24
Finished Jun 05 04:20:04 PM PDT 24
Peak memory 194084 kb
Host smart-ea76187d-01f2-4241-8296-e32a188f37e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465590431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.465590431
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1759645228
Short name T611
Test name
Test status
Simulation time 21873469 ps
CPU time 0.64 seconds
Started Jun 05 04:20:03 PM PDT 24
Finished Jun 05 04:20:05 PM PDT 24
Peak memory 194268 kb
Host smart-f3786416-7c21-4b1a-862e-9da243b85356
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759645228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1759645228
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2594466063
Short name T652
Test name
Test status
Simulation time 24317922 ps
CPU time 0.61 seconds
Started Jun 05 04:20:11 PM PDT 24
Finished Jun 05 04:20:13 PM PDT 24
Peak memory 194208 kb
Host smart-61b49475-a5c4-454c-91bf-bf6b414f2377
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594466063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2594466063
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.698031219
Short name T645
Test name
Test status
Simulation time 154688477462 ps
CPU time 599.59 seconds
Started Jun 05 04:19:37 PM PDT 24
Finished Jun 05 04:29:38 PM PDT 24
Peak memory 215904 kb
Host smart-5c4f1558-820c-432b-8122-c8e7dabb1816
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698031219 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.698031219
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.807614098
Short name T655
Test name
Test status
Simulation time 60631709 ps
CPU time 0.72 seconds
Started Jun 05 04:19:35 PM PDT 24
Finished Jun 05 04:19:37 PM PDT 24
Peak memory 197368 kb
Host smart-dbc0e463-8584-4c83-9f95-51ff643ed106
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807614098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.807614098
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1737217237
Short name T653
Test name
Test status
Simulation time 55760826 ps
CPU time 0.6 seconds
Started Jun 05 04:19:35 PM PDT 24
Finished Jun 05 04:19:36 PM PDT 24
Peak memory 194212 kb
Host smart-59ef996e-c4c5-4100-be1f-efb132c9ffe6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737217237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1737217237
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1891128890
Short name T709
Test name
Test status
Simulation time 213249458 ps
CPU time 2.18 seconds
Started Jun 05 04:19:35 PM PDT 24
Finished Jun 05 04:19:38 PM PDT 24
Peak memory 199400 kb
Host smart-58e8bfb7-715f-4010-9143-31fbbe8613d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891128890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1891128890
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.784550551
Short name T716
Test name
Test status
Simulation time 262849185 ps
CPU time 3.57 seconds
Started Jun 05 04:19:34 PM PDT 24
Finished Jun 05 04:19:38 PM PDT 24
Peak memory 199348 kb
Host smart-60661f65-c37d-4b93-b581-e957c58ca441
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784550551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.784550551
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3493115627
Short name T107
Test name
Test status
Simulation time 91911526 ps
CPU time 1.89 seconds
Started Jun 05 04:19:35 PM PDT 24
Finished Jun 05 04:19:38 PM PDT 24
Peak memory 199444 kb
Host smart-a7e0eb26-0030-4889-a046-269d4e738520
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493115627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3493115627
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.93086340
Short name T80
Test name
Test status
Simulation time 37794589 ps
CPU time 2.34 seconds
Started Jun 05 04:19:33 PM PDT 24
Finished Jun 05 04:19:37 PM PDT 24
Peak memory 199492 kb
Host smart-b5b4ed45-0edf-448c-93b5-295750c27fa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93086340 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.93086340
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2327130087
Short name T695
Test name
Test status
Simulation time 14687421 ps
CPU time 0.69 seconds
Started Jun 05 04:19:44 PM PDT 24
Finished Jun 05 04:19:45 PM PDT 24
Peak memory 196404 kb
Host smart-ebaf3af2-39b6-46c4-8f69-a9d244a52a0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327130087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2327130087
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.1223133730
Short name T647
Test name
Test status
Simulation time 14229927 ps
CPU time 0.6 seconds
Started Jun 05 04:19:36 PM PDT 24
Finished Jun 05 04:19:37 PM PDT 24
Peak memory 194268 kb
Host smart-2a6570c2-a09a-480c-a192-006679b1f529
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223133730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1223133730
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2880376412
Short name T613
Test name
Test status
Simulation time 217342207 ps
CPU time 2.24 seconds
Started Jun 05 04:19:35 PM PDT 24
Finished Jun 05 04:19:38 PM PDT 24
Peak memory 199380 kb
Host smart-c5e2f3a4-73df-4efd-81e5-b7fa85e46102
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880376412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2880376412
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1932513185
Short name T604
Test name
Test status
Simulation time 102680777 ps
CPU time 2.79 seconds
Started Jun 05 04:19:34 PM PDT 24
Finished Jun 05 04:19:38 PM PDT 24
Peak memory 199540 kb
Host smart-3659488f-313f-431b-b448-e5a20ffe9350
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932513185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1932513185
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3596624112
Short name T723
Test name
Test status
Simulation time 107980198 ps
CPU time 1.87 seconds
Started Jun 05 04:19:34 PM PDT 24
Finished Jun 05 04:19:36 PM PDT 24
Peak memory 199612 kb
Host smart-1d7c7c10-610c-4c18-831e-37300afe70ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596624112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3596624112
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4242907721
Short name T54
Test name
Test status
Simulation time 51041449 ps
CPU time 1.61 seconds
Started Jun 05 04:19:45 PM PDT 24
Finished Jun 05 04:19:48 PM PDT 24
Peak memory 199072 kb
Host smart-8c048d3b-d51c-49fe-9e79-f69dcf62af21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242907721 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.4242907721
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2820041854
Short name T606
Test name
Test status
Simulation time 603381051 ps
CPU time 0.91 seconds
Started Jun 05 04:19:50 PM PDT 24
Finished Jun 05 04:19:52 PM PDT 24
Peak memory 198680 kb
Host smart-c8cff157-1a65-4f8b-886c-525de01ef39c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820041854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2820041854
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.3638943468
Short name T672
Test name
Test status
Simulation time 14361957 ps
CPU time 0.58 seconds
Started Jun 05 04:19:36 PM PDT 24
Finished Jun 05 04:19:38 PM PDT 24
Peak memory 194252 kb
Host smart-dc95bca5-9ed2-421c-8088-829a0073a633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638943468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3638943468
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1097450681
Short name T679
Test name
Test status
Simulation time 189309705 ps
CPU time 1.69 seconds
Started Jun 05 04:19:36 PM PDT 24
Finished Jun 05 04:19:39 PM PDT 24
Peak memory 199440 kb
Host smart-0b4b3c62-33bb-45db-9020-0b9e3a6e809d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097450681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.1097450681
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1805620998
Short name T662
Test name
Test status
Simulation time 220848274 ps
CPU time 2.44 seconds
Started Jun 05 04:19:37 PM PDT 24
Finished Jun 05 04:19:41 PM PDT 24
Peak memory 199468 kb
Host smart-f8a2d0ed-3f0f-4e9e-b6b1-2d268f0b67fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805620998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1805620998
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1979535167
Short name T113
Test name
Test status
Simulation time 468150602 ps
CPU time 4.19 seconds
Started Jun 05 04:19:34 PM PDT 24
Finished Jun 05 04:19:39 PM PDT 24
Peak memory 199432 kb
Host smart-cc1ba942-0777-49a5-93dc-052384efdecf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979535167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1979535167
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3048457113
Short name T684
Test name
Test status
Simulation time 134729561458 ps
CPU time 626.4 seconds
Started Jun 05 04:19:49 PM PDT 24
Finished Jun 05 04:30:17 PM PDT 24
Peak memory 215664 kb
Host smart-13137f73-ea28-4bd9-9a0c-c6f1eda7f1d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048457113 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3048457113
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.26121973
Short name T95
Test name
Test status
Simulation time 14736642 ps
CPU time 0.8 seconds
Started Jun 05 04:19:35 PM PDT 24
Finished Jun 05 04:19:36 PM PDT 24
Peak memory 199324 kb
Host smart-84339300-55fd-4477-995c-2d654a88ab34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26121973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.26121973
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.2248906913
Short name T724
Test name
Test status
Simulation time 14239154 ps
CPU time 0.62 seconds
Started Jun 05 04:19:44 PM PDT 24
Finished Jun 05 04:19:45 PM PDT 24
Peak memory 192592 kb
Host smart-6a178d62-da7b-4a95-b152-b44e20200131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248906913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2248906913
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3316763788
Short name T657
Test name
Test status
Simulation time 50312534 ps
CPU time 1.25 seconds
Started Jun 05 04:19:36 PM PDT 24
Finished Jun 05 04:19:38 PM PDT 24
Peak memory 199120 kb
Host smart-54e7a7aa-9f2a-49b6-b2f2-fe9eca197461
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316763788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3316763788
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.559818076
Short name T605
Test name
Test status
Simulation time 209374594 ps
CPU time 2.79 seconds
Started Jun 05 04:19:34 PM PDT 24
Finished Jun 05 04:19:37 PM PDT 24
Peak memory 199496 kb
Host smart-4c909dcc-b5b9-4ab2-97c3-3aeec18eb1c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559818076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.559818076
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3779463250
Short name T607
Test name
Test status
Simulation time 141356056 ps
CPU time 1.14 seconds
Started Jun 05 04:19:47 PM PDT 24
Finished Jun 05 04:19:48 PM PDT 24
Peak memory 199268 kb
Host smart-3a687098-a972-4801-8724-4c3837b335d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779463250 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3779463250
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3364606458
Short name T618
Test name
Test status
Simulation time 88163028 ps
CPU time 0.83 seconds
Started Jun 05 04:19:43 PM PDT 24
Finished Jun 05 04:19:44 PM PDT 24
Peak memory 198940 kb
Host smart-3f5f370e-5bae-4f04-a53c-bb6daf13692c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364606458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3364606458
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.108046931
Short name T651
Test name
Test status
Simulation time 42327127 ps
CPU time 0.63 seconds
Started Jun 05 04:19:45 PM PDT 24
Finished Jun 05 04:19:46 PM PDT 24
Peak memory 194280 kb
Host smart-27103aea-bf72-4751-9238-a27e4bab2cac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108046931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.108046931
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.78563534
Short name T594
Test name
Test status
Simulation time 150283380 ps
CPU time 1.69 seconds
Started Jun 05 04:19:44 PM PDT 24
Finished Jun 05 04:19:46 PM PDT 24
Peak memory 199460 kb
Host smart-7e1f641e-0821-41a5-be45-62c555fe626b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78563534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_o
utstanding.78563534
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.792747819
Short name T622
Test name
Test status
Simulation time 178630870 ps
CPU time 1.95 seconds
Started Jun 05 04:19:51 PM PDT 24
Finished Jun 05 04:19:54 PM PDT 24
Peak memory 199232 kb
Host smart-7116e111-6f87-4a07-8cb2-dd6fe69d69bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792747819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.792747819
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1424664923
Short name T50
Test name
Test status
Simulation time 364191284 ps
CPU time 1.97 seconds
Started Jun 05 04:19:44 PM PDT 24
Finished Jun 05 04:19:47 PM PDT 24
Peak memory 199368 kb
Host smart-95db19cf-3326-43a9-b683-6b6e0a6293bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424664923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1424664923
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3726888389
Short name T345
Test name
Test status
Simulation time 11867344 ps
CPU time 0.57 seconds
Started Jun 05 04:20:57 PM PDT 24
Finished Jun 05 04:20:58 PM PDT 24
Peak memory 194932 kb
Host smart-e364b38d-590f-4f52-9211-b68270bee9c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726888389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3726888389
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3612809693
Short name T212
Test name
Test status
Simulation time 2089347126 ps
CPU time 43.94 seconds
Started Jun 05 04:21:02 PM PDT 24
Finished Jun 05 04:21:47 PM PDT 24
Peak memory 232832 kb
Host smart-086e4c1c-4537-48c4-a9ca-e5a2c4837559
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3612809693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3612809693
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3452034552
Short name T268
Test name
Test status
Simulation time 2180466852 ps
CPU time 41.8 seconds
Started Jun 05 04:20:55 PM PDT 24
Finished Jun 05 04:21:37 PM PDT 24
Peak memory 200172 kb
Host smart-036c0e69-6e73-4194-8cb5-e4b400226e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452034552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3452034552
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1507009099
Short name T259
Test name
Test status
Simulation time 4005927827 ps
CPU time 1137.2 seconds
Started Jun 05 04:20:58 PM PDT 24
Finished Jun 05 04:39:56 PM PDT 24
Peak memory 774588 kb
Host smart-57dff08d-e2c2-4ce4-a842-ad89b5db851e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1507009099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1507009099
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2334271683
Short name T39
Test name
Test status
Simulation time 10100913335 ps
CPU time 91.6 seconds
Started Jun 05 04:20:57 PM PDT 24
Finished Jun 05 04:22:29 PM PDT 24
Peak memory 200160 kb
Host smart-e54449c6-baf1-4498-a06b-698c487a4559
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334271683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2334271683
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.2554153125
Short name T432
Test name
Test status
Simulation time 15755470519 ps
CPU time 62.31 seconds
Started Jun 05 04:20:57 PM PDT 24
Finished Jun 05 04:22:00 PM PDT 24
Peak memory 200192 kb
Host smart-b701a14f-a346-4f72-a6ff-3327c60f7ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554153125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.2554153125
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.1231634002
Short name T134
Test name
Test status
Simulation time 3512272450 ps
CPU time 14.63 seconds
Started Jun 05 04:20:56 PM PDT 24
Finished Jun 05 04:21:12 PM PDT 24
Peak memory 200148 kb
Host smart-30054bab-9966-4e26-a1b4-96b91202ee60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231634002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1231634002
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3914171563
Short name T532
Test name
Test status
Simulation time 67571064794 ps
CPU time 2153.25 seconds
Started Jun 05 04:20:56 PM PDT 24
Finished Jun 05 04:56:51 PM PDT 24
Peak memory 774652 kb
Host smart-5f6b142d-fb66-4b38-9f53-1b3e52aadc38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914171563 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3914171563
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.1525076572
Short name T2
Test name
Test status
Simulation time 119573025 ps
CPU time 1.39 seconds
Started Jun 05 04:20:58 PM PDT 24
Finished Jun 05 04:21:00 PM PDT 24
Peak memory 200172 kb
Host smart-7c218d51-e7af-4ae5-bd2d-daab60c50f33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525076572 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.1525076572
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.968926125
Short name T196
Test name
Test status
Simulation time 7701085836 ps
CPU time 461.32 seconds
Started Jun 05 04:21:01 PM PDT 24
Finished Jun 05 04:28:42 PM PDT 24
Peak memory 200160 kb
Host smart-2704fa4c-194f-4bd6-a712-17e77f33db26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968926125 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.968926125
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.2752826443
Short name T581
Test name
Test status
Simulation time 1980095315 ps
CPU time 30.51 seconds
Started Jun 05 04:21:02 PM PDT 24
Finished Jun 05 04:21:33 PM PDT 24
Peak memory 200164 kb
Host smart-18733e27-5bef-49ee-a792-a3992bf4daef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752826443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.2752826443
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3742084315
Short name T456
Test name
Test status
Simulation time 17472270 ps
CPU time 0.64 seconds
Started Jun 05 04:21:01 PM PDT 24
Finished Jun 05 04:21:02 PM PDT 24
Peak memory 195060 kb
Host smart-f329dc4f-4db2-4912-9ca3-9f9997364aec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742084315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3742084315
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3237983482
Short name T473
Test name
Test status
Simulation time 622710172 ps
CPU time 27.76 seconds
Started Jun 05 04:20:55 PM PDT 24
Finished Jun 05 04:21:23 PM PDT 24
Peak memory 208284 kb
Host smart-62510e0f-448b-4dc9-a52a-06ccb1806702
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3237983482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3237983482
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.1902892182
Short name T349
Test name
Test status
Simulation time 552023664 ps
CPU time 9.49 seconds
Started Jun 05 04:21:02 PM PDT 24
Finished Jun 05 04:21:12 PM PDT 24
Peak memory 200112 kb
Host smart-1845fe25-632c-47ad-9830-f80096800869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902892182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1902892182
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.453641771
Short name T494
Test name
Test status
Simulation time 3085609812 ps
CPU time 703.28 seconds
Started Jun 05 04:21:02 PM PDT 24
Finished Jun 05 04:32:46 PM PDT 24
Peak memory 618156 kb
Host smart-08ed9d04-c81a-472f-9300-7528706cce89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=453641771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.453641771
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.1296837412
Short name T461
Test name
Test status
Simulation time 33191971517 ps
CPU time 116.13 seconds
Started Jun 05 04:20:57 PM PDT 24
Finished Jun 05 04:22:54 PM PDT 24
Peak memory 200116 kb
Host smart-a8c309c6-5f78-450d-a460-0c4f20f070e9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296837412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1296837412
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2117745341
Short name T353
Test name
Test status
Simulation time 28721344059 ps
CPU time 29.79 seconds
Started Jun 05 04:20:56 PM PDT 24
Finished Jun 05 04:21:27 PM PDT 24
Peak memory 200148 kb
Host smart-3f8ddf54-ea12-4bfe-99cf-a649298e6e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117745341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2117745341
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_smoke.1731791900
Short name T341
Test name
Test status
Simulation time 730848532 ps
CPU time 6.71 seconds
Started Jun 05 04:20:55 PM PDT 24
Finished Jun 05 04:21:03 PM PDT 24
Peak memory 200092 kb
Host smart-6297a8e5-0a04-4283-84f2-6c493425d3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731791900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1731791900
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3238369893
Short name T270
Test name
Test status
Simulation time 22210902310 ps
CPU time 1921.27 seconds
Started Jun 05 04:21:01 PM PDT 24
Finished Jun 05 04:53:03 PM PDT 24
Peak memory 762328 kb
Host smart-eecc7cd5-b750-4404-9ae8-99a9e83fc27d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238369893 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3238369893
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.1334850859
Short name T567
Test name
Test status
Simulation time 219294744 ps
CPU time 1.42 seconds
Started Jun 05 04:20:56 PM PDT 24
Finished Jun 05 04:20:58 PM PDT 24
Peak memory 200024 kb
Host smart-6a95abff-18f3-4d30-a634-51ed92323f63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334850859 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.1334850859
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.1061167566
Short name T388
Test name
Test status
Simulation time 35332367543 ps
CPU time 509.12 seconds
Started Jun 05 04:20:57 PM PDT 24
Finished Jun 05 04:29:27 PM PDT 24
Peak memory 200128 kb
Host smart-79ae4cc5-9909-41ec-b81f-c045c15f55e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061167566 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.1061167566
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.777804142
Short name T174
Test name
Test status
Simulation time 15214605305 ps
CPU time 95.99 seconds
Started Jun 05 04:21:01 PM PDT 24
Finished Jun 05 04:22:37 PM PDT 24
Peak memory 200136 kb
Host smart-a628c631-657a-4dae-a3b7-835609575078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777804142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.777804142
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2477464220
Short name T485
Test name
Test status
Simulation time 12932946 ps
CPU time 0.58 seconds
Started Jun 05 04:21:21 PM PDT 24
Finished Jun 05 04:21:22 PM PDT 24
Peak memory 196604 kb
Host smart-2cf5a3fe-8edf-4308-870f-a88bae63db06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477464220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2477464220
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2246417791
Short name T344
Test name
Test status
Simulation time 2210630589 ps
CPU time 8.95 seconds
Started Jun 05 04:21:27 PM PDT 24
Finished Jun 05 04:21:37 PM PDT 24
Peak memory 200196 kb
Host smart-c0ff1a52-fa45-4946-93ca-00f12429b2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246417791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2246417791
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1481609105
Short name T101
Test name
Test status
Simulation time 51008774274 ps
CPU time 749.43 seconds
Started Jun 05 04:21:25 PM PDT 24
Finished Jun 05 04:33:56 PM PDT 24
Peak memory 689052 kb
Host smart-f1ab9957-da71-42be-aafe-786700b27c4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1481609105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1481609105
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.1579085309
Short name T580
Test name
Test status
Simulation time 11735023589 ps
CPU time 127.03 seconds
Started Jun 05 04:21:31 PM PDT 24
Finished Jun 05 04:23:39 PM PDT 24
Peak memory 200144 kb
Host smart-11868216-8c24-4968-a0a4-ce45b0b42e87
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579085309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1579085309
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.1620679716
Short name T561
Test name
Test status
Simulation time 1901844821 ps
CPU time 54.13 seconds
Started Jun 05 04:21:20 PM PDT 24
Finished Jun 05 04:22:15 PM PDT 24
Peak memory 200020 kb
Host smart-1d6226ec-bf36-4dfc-88a2-3406b8f30d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620679716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1620679716
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.2160456614
Short name T262
Test name
Test status
Simulation time 1173175202 ps
CPU time 9.32 seconds
Started Jun 05 04:21:20 PM PDT 24
Finished Jun 05 04:21:30 PM PDT 24
Peak memory 200132 kb
Host smart-edc0449c-ab64-4346-9d23-16cc43ed815b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160456614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.2160456614
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.670594770
Short name T482
Test name
Test status
Simulation time 244608405249 ps
CPU time 1398.29 seconds
Started Jun 05 04:21:27 PM PDT 24
Finished Jun 05 04:44:47 PM PDT 24
Peak memory 693792 kb
Host smart-bb5e1cdb-5e7b-400c-89f2-69af87287951
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670594770 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.670594770
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.3555336119
Short name T527
Test name
Test status
Simulation time 55789034 ps
CPU time 1.09 seconds
Started Jun 05 04:21:21 PM PDT 24
Finished Jun 05 04:21:23 PM PDT 24
Peak memory 199912 kb
Host smart-752d96e8-ace2-43b4-a95c-23ed11c79e59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555336119 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.3555336119
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.177778808
Short name T144
Test name
Test status
Simulation time 29269756157 ps
CPU time 436.46 seconds
Started Jun 05 04:21:19 PM PDT 24
Finished Jun 05 04:28:37 PM PDT 24
Peak memory 200112 kb
Host smart-03c58484-bcf1-49f1-9d3f-f9b7c5640880
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177778808 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.177778808
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.1584986216
Short name T72
Test name
Test status
Simulation time 3009174280 ps
CPU time 59.18 seconds
Started Jun 05 04:21:24 PM PDT 24
Finished Jun 05 04:22:24 PM PDT 24
Peak memory 200108 kb
Host smart-39c70ca9-4bec-427e-bb3e-c5f2c806fae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584986216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1584986216
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2211655685
Short name T302
Test name
Test status
Simulation time 51228221 ps
CPU time 0.58 seconds
Started Jun 05 04:21:30 PM PDT 24
Finished Jun 05 04:21:32 PM PDT 24
Peak memory 195636 kb
Host smart-dbc1816e-804c-475e-9f48-29ba3dd55d9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211655685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2211655685
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1566392961
Short name T520
Test name
Test status
Simulation time 3717626191 ps
CPU time 44.77 seconds
Started Jun 05 04:21:22 PM PDT 24
Finished Jun 05 04:22:08 PM PDT 24
Peak memory 215868 kb
Host smart-78c55e85-71b7-48fd-817a-27ce4ce02b37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1566392961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1566392961
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3843583835
Short name T389
Test name
Test status
Simulation time 3313133045 ps
CPU time 18.44 seconds
Started Jun 05 04:21:25 PM PDT 24
Finished Jun 05 04:21:45 PM PDT 24
Peak memory 200160 kb
Host smart-4357174a-e91d-4d40-aceb-fee6a422b888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843583835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3843583835
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1499321526
Short name T481
Test name
Test status
Simulation time 1247706857 ps
CPU time 286.99 seconds
Started Jun 05 04:21:26 PM PDT 24
Finished Jun 05 04:26:14 PM PDT 24
Peak memory 459084 kb
Host smart-3a723751-024b-4ac7-9793-dd902d2952bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1499321526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1499321526
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.678440867
Short name T589
Test name
Test status
Simulation time 12291275153 ps
CPU time 162.16 seconds
Started Jun 05 04:21:30 PM PDT 24
Finished Jun 05 04:24:14 PM PDT 24
Peak memory 200196 kb
Host smart-341dfd13-3ed2-48ae-9e19-a767c0ce2f67
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678440867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.678440867
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2812749804
Short name T243
Test name
Test status
Simulation time 513560926 ps
CPU time 30.5 seconds
Started Jun 05 04:21:19 PM PDT 24
Finished Jun 05 04:21:50 PM PDT 24
Peak memory 200128 kb
Host smart-7a50315f-ffb4-402f-858a-26864a913c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812749804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2812749804
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.444381717
Short name T193
Test name
Test status
Simulation time 1842437460 ps
CPU time 11.4 seconds
Started Jun 05 04:21:26 PM PDT 24
Finished Jun 05 04:21:39 PM PDT 24
Peak memory 200188 kb
Host smart-13e79d88-21e4-464f-95c8-a8c6179b83da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444381717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.444381717
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3830788141
Short name T299
Test name
Test status
Simulation time 92318503262 ps
CPU time 620.58 seconds
Started Jun 05 04:21:22 PM PDT 24
Finished Jun 05 04:31:43 PM PDT 24
Peak memory 227880 kb
Host smart-86c2ebf1-7802-497a-8dbe-c41e18b43530
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830788141 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3830788141
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.3943369701
Short name T475
Test name
Test status
Simulation time 107906843 ps
CPU time 1.41 seconds
Started Jun 05 04:21:32 PM PDT 24
Finished Jun 05 04:21:34 PM PDT 24
Peak memory 200076 kb
Host smart-405884ec-81ac-408c-aae2-81347f4767e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943369701 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.3943369701
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.3705901467
Short name T300
Test name
Test status
Simulation time 31422949811 ps
CPU time 444.83 seconds
Started Jun 05 04:21:21 PM PDT 24
Finished Jun 05 04:28:47 PM PDT 24
Peak memory 200080 kb
Host smart-4a497e6b-dbc6-4c29-9481-f192b498575b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705901467 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.3705901467
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.1751769270
Short name T453
Test name
Test status
Simulation time 13868389232 ps
CPU time 50.41 seconds
Started Jun 05 04:21:32 PM PDT 24
Finished Jun 05 04:22:24 PM PDT 24
Peak memory 200200 kb
Host smart-11a7028e-8f09-4b28-a6cd-bb6a0c65b456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751769270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1751769270
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2734869191
Short name T583
Test name
Test status
Simulation time 14798860 ps
CPU time 0.58 seconds
Started Jun 05 04:21:34 PM PDT 24
Finished Jun 05 04:21:35 PM PDT 24
Peak memory 195812 kb
Host smart-f236a773-627f-4015-8b08-154be5579152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734869191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2734869191
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.962812678
Short name T405
Test name
Test status
Simulation time 225309592 ps
CPU time 9.45 seconds
Started Jun 05 04:21:20 PM PDT 24
Finished Jun 05 04:21:30 PM PDT 24
Peak memory 208248 kb
Host smart-1c10b9a2-c4a0-4d63-8c2e-27d5ce736724
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=962812678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.962812678
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1813178552
Short name T335
Test name
Test status
Simulation time 14872865073 ps
CPU time 58.14 seconds
Started Jun 05 04:21:27 PM PDT 24
Finished Jun 05 04:22:26 PM PDT 24
Peak memory 200064 kb
Host smart-4740de87-e388-49b4-8e71-29abe331fc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813178552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1813178552
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.654424422
Short name T534
Test name
Test status
Simulation time 11399960783 ps
CPU time 575.07 seconds
Started Jun 05 04:21:31 PM PDT 24
Finished Jun 05 04:31:08 PM PDT 24
Peak memory 705784 kb
Host smart-2a005831-4522-4cd4-bdfc-c19fb8a156eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=654424422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.654424422
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2863210019
Short name T18
Test name
Test status
Simulation time 13320865406 ps
CPU time 86.29 seconds
Started Jun 05 04:21:33 PM PDT 24
Finished Jun 05 04:23:01 PM PDT 24
Peak memory 200164 kb
Host smart-f9ae6700-1ca3-4dd7-bbc3-7e6331fd238e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863210019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2863210019
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.4000569241
Short name T233
Test name
Test status
Simulation time 13781746396 ps
CPU time 79.78 seconds
Started Jun 05 04:21:27 PM PDT 24
Finished Jun 05 04:22:47 PM PDT 24
Peak memory 200108 kb
Host smart-0ca96215-7063-4691-851e-2fe05e2bebfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000569241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.4000569241
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3843877370
Short name T252
Test name
Test status
Simulation time 173187940 ps
CPU time 3.09 seconds
Started Jun 05 04:21:21 PM PDT 24
Finished Jun 05 04:21:25 PM PDT 24
Peak memory 200092 kb
Host smart-51ca9dd6-5ecc-4b35-a0f0-5c7ea7ac87a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843877370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3843877370
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.1200160550
Short name T306
Test name
Test status
Simulation time 109659616 ps
CPU time 1.1 seconds
Started Jun 05 04:21:23 PM PDT 24
Finished Jun 05 04:21:24 PM PDT 24
Peak memory 199952 kb
Host smart-36ac8b7a-1ede-4fd2-a76f-e8248963f430
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200160550 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.1200160550
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.1958655659
Short name T256
Test name
Test status
Simulation time 8123176582 ps
CPU time 454.1 seconds
Started Jun 05 04:21:36 PM PDT 24
Finished Jun 05 04:29:11 PM PDT 24
Peak memory 199932 kb
Host smart-f473cf26-77b0-4259-91d0-6ee2839aec06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958655659 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.1958655659
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2675671821
Short name T407
Test name
Test status
Simulation time 61997391870 ps
CPU time 72.47 seconds
Started Jun 05 04:21:19 PM PDT 24
Finished Jun 05 04:22:33 PM PDT 24
Peak memory 200160 kb
Host smart-405bd62b-7de3-440e-af58-a7c29c9716ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675671821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2675671821
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/126.hmac_stress_all_with_rand_reset.976291989
Short name T13
Test name
Test status
Simulation time 2176936852 ps
CPU time 57.8 seconds
Started Jun 05 04:23:36 PM PDT 24
Finished Jun 05 04:24:34 PM PDT 24
Peak memory 216568 kb
Host smart-9c5cdd2a-8a9b-47a1-86b2-ec16077636d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=976291989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.hmac_stress_all_with_rand_reset.976291989
Directory /workspace/126.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2046671590
Short name T502
Test name
Test status
Simulation time 54341541 ps
CPU time 0.57 seconds
Started Jun 05 04:21:35 PM PDT 24
Finished Jun 05 04:21:37 PM PDT 24
Peak memory 195436 kb
Host smart-8437dfea-02bc-49e0-8999-fdbb94f0b645
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046671590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2046671590
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.795680788
Short name T75
Test name
Test status
Simulation time 2395428055 ps
CPU time 65.57 seconds
Started Jun 05 04:21:26 PM PDT 24
Finished Jun 05 04:22:32 PM PDT 24
Peak memory 223472 kb
Host smart-6cf3e7d0-d35b-42cc-b607-e5d737cfdaad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=795680788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.795680788
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.4241069780
Short name T483
Test name
Test status
Simulation time 14682521221 ps
CPU time 52.36 seconds
Started Jun 05 04:21:28 PM PDT 24
Finished Jun 05 04:22:21 PM PDT 24
Peak memory 200140 kb
Host smart-a0849f47-fea3-48db-b27a-377149452baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241069780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.4241069780
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.3877105134
Short name T505
Test name
Test status
Simulation time 825061833 ps
CPU time 199.37 seconds
Started Jun 05 04:21:26 PM PDT 24
Finished Jun 05 04:24:46 PM PDT 24
Peak memory 611468 kb
Host smart-62cc803c-5332-4bea-b29b-a15dbb855fac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3877105134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.3877105134
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1956166609
Short name T480
Test name
Test status
Simulation time 1836976182 ps
CPU time 111.28 seconds
Started Jun 05 04:21:25 PM PDT 24
Finished Jun 05 04:23:17 PM PDT 24
Peak memory 200172 kb
Host smart-4df2e955-235d-4713-8044-9f0155009687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956166609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1956166609
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.126308195
Short name T15
Test name
Test status
Simulation time 424242301 ps
CPU time 2.89 seconds
Started Jun 05 04:21:27 PM PDT 24
Finished Jun 05 04:21:31 PM PDT 24
Peak memory 200120 kb
Host smart-9c4cc38e-c782-4e56-9321-d1a1c5fce5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126308195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.126308195
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.1017254748
Short name T381
Test name
Test status
Simulation time 9591751571 ps
CPU time 322.04 seconds
Started Jun 05 04:21:27 PM PDT 24
Finished Jun 05 04:26:50 PM PDT 24
Peak memory 420520 kb
Host smart-0802c194-ec67-4142-bff5-e6a4c49e3266
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017254748 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1017254748
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.3548171122
Short name T549
Test name
Test status
Simulation time 52070654 ps
CPU time 1.08 seconds
Started Jun 05 04:21:42 PM PDT 24
Finished Jun 05 04:21:44 PM PDT 24
Peak memory 199880 kb
Host smart-b52cd357-2799-491f-b578-70a2a91ddd58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548171122 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.3548171122
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.3575316157
Short name T120
Test name
Test status
Simulation time 149294534970 ps
CPU time 541.54 seconds
Started Jun 05 04:21:31 PM PDT 24
Finished Jun 05 04:30:34 PM PDT 24
Peak memory 200160 kb
Host smart-b68e016a-016b-4a22-ae30-8cb9cac0193d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575316157 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.3575316157
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3466225750
Short name T429
Test name
Test status
Simulation time 4363683311 ps
CPU time 56.03 seconds
Started Jun 05 04:21:27 PM PDT 24
Finished Jun 05 04:22:24 PM PDT 24
Peak memory 200120 kb
Host smart-386ba62d-70d5-400e-b877-6c7bb371b13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466225750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3466225750
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1363504726
Short name T161
Test name
Test status
Simulation time 77257411 ps
CPU time 0.61 seconds
Started Jun 05 04:21:30 PM PDT 24
Finished Jun 05 04:21:31 PM PDT 24
Peak memory 194940 kb
Host smart-4dc6fb4a-e0cd-4018-b83b-0f786a2342f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363504726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1363504726
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1626461206
Short name T491
Test name
Test status
Simulation time 1835955620 ps
CPU time 28.86 seconds
Started Jun 05 04:21:25 PM PDT 24
Finished Jun 05 04:21:54 PM PDT 24
Peak memory 208260 kb
Host smart-629ffafb-e49c-491e-9999-b064b9d0f619
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1626461206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1626461206
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.1667085801
Short name T81
Test name
Test status
Simulation time 7465103945 ps
CPU time 17.18 seconds
Started Jun 05 04:21:36 PM PDT 24
Finished Jun 05 04:21:55 PM PDT 24
Peak memory 199860 kb
Host smart-3cfc4d70-00ec-4403-93ec-5e5f00ace7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667085801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.1667085801
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.1565454301
Short name T254
Test name
Test status
Simulation time 4293746478 ps
CPU time 303.56 seconds
Started Jun 05 04:21:25 PM PDT 24
Finished Jun 05 04:26:29 PM PDT 24
Peak memory 682536 kb
Host smart-08dd0500-0220-4aba-b718-59b72e8b63f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1565454301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1565454301
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3812360000
Short name T287
Test name
Test status
Simulation time 22810210859 ps
CPU time 95.2 seconds
Started Jun 05 04:21:36 PM PDT 24
Finished Jun 05 04:23:12 PM PDT 24
Peak memory 199964 kb
Host smart-839137b9-6ca9-41bc-b533-c790f5402cd2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812360000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3812360000
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.3063448466
Short name T187
Test name
Test status
Simulation time 1274938351 ps
CPU time 19.58 seconds
Started Jun 05 04:21:35 PM PDT 24
Finished Jun 05 04:21:56 PM PDT 24
Peak memory 199976 kb
Host smart-7300b7ce-2207-49eb-9016-6d2a1337aaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063448466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3063448466
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3063578191
Short name T421
Test name
Test status
Simulation time 616132075 ps
CPU time 6.11 seconds
Started Jun 05 04:21:36 PM PDT 24
Finished Jun 05 04:21:44 PM PDT 24
Peak memory 199848 kb
Host smart-bd1c7a1b-5435-4c18-b169-7ed4049731b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063578191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3063578191
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.1967545205
Short name T74
Test name
Test status
Simulation time 59354367 ps
CPU time 1.31 seconds
Started Jun 05 04:21:27 PM PDT 24
Finished Jun 05 04:21:29 PM PDT 24
Peak memory 200080 kb
Host smart-8f33f595-4605-420b-b4e0-cb4e8ca0fac1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967545205 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.1967545205
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.1886287352
Short name T303
Test name
Test status
Simulation time 35269509665 ps
CPU time 493.6 seconds
Started Jun 05 04:21:37 PM PDT 24
Finished Jun 05 04:29:52 PM PDT 24
Peak memory 200084 kb
Host smart-3e5c7848-65ec-4707-a36c-3ada3475afa6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886287352 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.1886287352
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3952122925
Short name T447
Test name
Test status
Simulation time 7609794533 ps
CPU time 82.61 seconds
Started Jun 05 04:21:42 PM PDT 24
Finished Jun 05 04:23:06 PM PDT 24
Peak memory 199872 kb
Host smart-153230a0-e2a8-4476-a3f5-84e86241a1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952122925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3952122925
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.2633518710
Short name T154
Test name
Test status
Simulation time 77504468 ps
CPU time 0.57 seconds
Started Jun 05 04:21:26 PM PDT 24
Finished Jun 05 04:21:27 PM PDT 24
Peak memory 194968 kb
Host smart-22034f0a-eb01-4f09-b001-ccd4bdf57ce1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633518710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2633518710
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.2485951434
Short name T366
Test name
Test status
Simulation time 1868787873 ps
CPU time 24.66 seconds
Started Jun 05 04:21:30 PM PDT 24
Finished Jun 05 04:21:56 PM PDT 24
Peak memory 208324 kb
Host smart-6a18635c-c922-49db-aa58-4dec15db93f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2485951434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2485951434
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.50191232
Short name T105
Test name
Test status
Simulation time 3119003293 ps
CPU time 50.09 seconds
Started Jun 05 04:21:39 PM PDT 24
Finished Jun 05 04:22:30 PM PDT 24
Peak memory 200144 kb
Host smart-4a17d6fd-89f8-4d0a-bf9f-e60cdec15744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50191232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.50191232
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1988233149
Short name T223
Test name
Test status
Simulation time 1181841742 ps
CPU time 268.97 seconds
Started Jun 05 04:21:30 PM PDT 24
Finished Jun 05 04:25:59 PM PDT 24
Peak memory 626900 kb
Host smart-35e65243-088e-489b-b4e6-9ea5e438da88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1988233149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1988233149
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.372297510
Short name T542
Test name
Test status
Simulation time 5925907270 ps
CPU time 100.82 seconds
Started Jun 05 04:21:28 PM PDT 24
Finished Jun 05 04:23:10 PM PDT 24
Peak memory 200120 kb
Host smart-e0eaaae3-e115-4cfa-a029-b6b8cfc11d7f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372297510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.372297510
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3174485276
Short name T477
Test name
Test status
Simulation time 678355682 ps
CPU time 41.98 seconds
Started Jun 05 04:21:27 PM PDT 24
Finished Jun 05 04:22:10 PM PDT 24
Peak memory 200188 kb
Host smart-0fa1d36c-cdb4-4b0c-ae07-e82ecf2e385c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174485276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3174485276
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1470778881
Short name T237
Test name
Test status
Simulation time 473404599 ps
CPU time 6.34 seconds
Started Jun 05 04:21:35 PM PDT 24
Finished Jun 05 04:21:42 PM PDT 24
Peak memory 200112 kb
Host smart-013ed7d8-2d14-43e1-a6ff-ec4f6523f33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470778881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1470778881
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.602671084
Short name T386
Test name
Test status
Simulation time 38619674440 ps
CPU time 2356.51 seconds
Started Jun 05 04:21:39 PM PDT 24
Finished Jun 05 05:00:57 PM PDT 24
Peak memory 663016 kb
Host smart-c8d97cbe-d81a-41fb-ba69-6c5127d198ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602671084 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.602671084
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.4251833994
Short name T342
Test name
Test status
Simulation time 56299324 ps
CPU time 1.13 seconds
Started Jun 05 04:21:31 PM PDT 24
Finished Jun 05 04:21:33 PM PDT 24
Peak memory 199952 kb
Host smart-117dff16-1e83-41a4-8350-09f25482c438
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251833994 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.4251833994
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.2423231490
Short name T354
Test name
Test status
Simulation time 222459883198 ps
CPU time 492.22 seconds
Started Jun 05 04:21:41 PM PDT 24
Finished Jun 05 04:29:55 PM PDT 24
Peak memory 200084 kb
Host smart-8fffd805-2d25-4791-bddd-702e794a706f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423231490 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.2423231490
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.2102274040
Short name T156
Test name
Test status
Simulation time 3525142095 ps
CPU time 87.23 seconds
Started Jun 05 04:21:29 PM PDT 24
Finished Jun 05 04:22:57 PM PDT 24
Peak memory 200160 kb
Host smart-cc6f3b32-f58b-41af-b5d4-9a1a51df66a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102274040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.2102274040
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/154.hmac_stress_all_with_rand_reset.1110454565
Short name T10
Test name
Test status
Simulation time 5738577835 ps
CPU time 508.06 seconds
Started Jun 05 04:23:59 PM PDT 24
Finished Jun 05 04:32:27 PM PDT 24
Peak memory 650384 kb
Host smart-4f4e736f-efff-46c1-878e-8f7fa7b2ff2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1110454565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.hmac_stress_all_with_rand_reset.1110454565
Directory /workspace/154.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_alert_test.1367525564
Short name T582
Test name
Test status
Simulation time 45647587 ps
CPU time 0.64 seconds
Started Jun 05 04:21:36 PM PDT 24
Finished Jun 05 04:21:38 PM PDT 24
Peak memory 195968 kb
Host smart-e18a69d5-2afc-45e0-834c-845d14000a9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367525564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.1367525564
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.3710757104
Short name T590
Test name
Test status
Simulation time 1069707184 ps
CPU time 54.63 seconds
Started Jun 05 04:21:30 PM PDT 24
Finished Jun 05 04:22:25 PM PDT 24
Peak memory 233080 kb
Host smart-f740eb67-310d-4e72-8f58-bbc501737e50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3710757104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.3710757104
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1755004039
Short name T412
Test name
Test status
Simulation time 10775323450 ps
CPU time 41.39 seconds
Started Jun 05 04:21:28 PM PDT 24
Finished Jun 05 04:22:10 PM PDT 24
Peak memory 200116 kb
Host smart-7b375a36-6cc8-4373-aa51-560db989aa21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755004039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1755004039
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.1927211702
Short name T152
Test name
Test status
Simulation time 5300218885 ps
CPU time 667.34 seconds
Started Jun 05 04:21:27 PM PDT 24
Finished Jun 05 04:32:36 PM PDT 24
Peak memory 740832 kb
Host smart-7dd7f10d-da0a-4f53-b668-7e77f357b162
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1927211702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1927211702
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.4005967884
Short name T200
Test name
Test status
Simulation time 3004480900 ps
CPU time 25.45 seconds
Started Jun 05 04:21:28 PM PDT 24
Finished Jun 05 04:21:55 PM PDT 24
Peak memory 200052 kb
Host smart-efcdc0d0-3de9-4211-82ac-746090c5d2e5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005967884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.4005967884
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.783857554
Short name T511
Test name
Test status
Simulation time 1797139799 ps
CPU time 105.71 seconds
Started Jun 05 04:21:27 PM PDT 24
Finished Jun 05 04:23:13 PM PDT 24
Peak memory 200088 kb
Host smart-cdbbeb06-1fe4-4a2f-b601-c59aa1bfd597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783857554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.783857554
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.3049272960
Short name T374
Test name
Test status
Simulation time 130093637 ps
CPU time 4.82 seconds
Started Jun 05 04:21:27 PM PDT 24
Finished Jun 05 04:21:32 PM PDT 24
Peak memory 200084 kb
Host smart-d2595640-9258-4d75-9666-54c5f9799811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049272960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.3049272960
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.4099823614
Short name T459
Test name
Test status
Simulation time 699755082 ps
CPU time 31.68 seconds
Started Jun 05 04:21:27 PM PDT 24
Finished Jun 05 04:22:00 PM PDT 24
Peak memory 200072 kb
Host smart-0ffbfe77-7291-4366-a36f-b0afe61dc847
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099823614 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.4099823614
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.3787578389
Short name T125
Test name
Test status
Simulation time 32918460 ps
CPU time 1.27 seconds
Started Jun 05 04:21:30 PM PDT 24
Finished Jun 05 04:21:32 PM PDT 24
Peak memory 200064 kb
Host smart-2a79aaf8-4034-414c-a555-7f0dfb7c14ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787578389 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.3787578389
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.3573009194
Short name T496
Test name
Test status
Simulation time 47816735918 ps
CPU time 404.98 seconds
Started Jun 05 04:21:32 PM PDT 24
Finished Jun 05 04:28:18 PM PDT 24
Peak memory 200080 kb
Host smart-c383d893-1594-49ff-9818-ab71ea15656f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573009194 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.3573009194
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2574784955
Short name T510
Test name
Test status
Simulation time 53070470 ps
CPU time 0.6 seconds
Started Jun 05 04:21:35 PM PDT 24
Finished Jun 05 04:21:36 PM PDT 24
Peak memory 195952 kb
Host smart-03bcdc10-d270-4857-ac1d-af6190f2b744
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574784955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2574784955
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3224160555
Short name T210
Test name
Test status
Simulation time 1039998454 ps
CPU time 30.04 seconds
Started Jun 05 04:21:39 PM PDT 24
Finished Jun 05 04:22:10 PM PDT 24
Peak memory 216440 kb
Host smart-fdf4b1b5-e422-4af7-abe6-f1b67cc6cee6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3224160555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3224160555
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1714551067
Short name T241
Test name
Test status
Simulation time 1071944171 ps
CPU time 21.73 seconds
Started Jun 05 04:21:31 PM PDT 24
Finished Jun 05 04:21:53 PM PDT 24
Peak memory 200104 kb
Host smart-ca87f5be-c5e7-4d49-9548-a20c9882eb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714551067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1714551067
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2905431688
Short name T203
Test name
Test status
Simulation time 1954153158 ps
CPU time 235.12 seconds
Started Jun 05 04:21:29 PM PDT 24
Finished Jun 05 04:25:24 PM PDT 24
Peak memory 584040 kb
Host smart-bffe4a9e-ee03-4244-ad83-01ab8708c892
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2905431688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2905431688
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.2396327773
Short name T574
Test name
Test status
Simulation time 52251640222 ps
CPU time 139.1 seconds
Started Jun 05 04:21:36 PM PDT 24
Finished Jun 05 04:23:56 PM PDT 24
Peak memory 200112 kb
Host smart-d9926255-2a24-4e0d-b232-f3102b069417
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396327773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2396327773
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.1203837832
Short name T424
Test name
Test status
Simulation time 938835642 ps
CPU time 44.09 seconds
Started Jun 05 04:21:30 PM PDT 24
Finished Jun 05 04:22:15 PM PDT 24
Peak memory 200052 kb
Host smart-a48f7010-d404-4eb2-bb09-155dbb7501e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203837832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1203837832
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.528618355
Short name T82
Test name
Test status
Simulation time 600055558 ps
CPU time 7.06 seconds
Started Jun 05 04:21:31 PM PDT 24
Finished Jun 05 04:21:39 PM PDT 24
Peak memory 200124 kb
Host smart-0f6ca4d2-19e9-4d91-a8e6-61da90d6fbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528618355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.528618355
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.497161455
Short name T67
Test name
Test status
Simulation time 132755730961 ps
CPU time 2608.98 seconds
Started Jun 05 04:21:35 PM PDT 24
Finished Jun 05 05:05:05 PM PDT 24
Peak memory 753796 kb
Host smart-485079df-109b-4e79-b336-493b5cf5e947
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497161455 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.497161455
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.1882667894
Short name T116
Test name
Test status
Simulation time 99199955 ps
CPU time 1.18 seconds
Started Jun 05 04:21:31 PM PDT 24
Finished Jun 05 04:21:34 PM PDT 24
Peak memory 200104 kb
Host smart-8b8d594f-7b6d-4923-9418-ad2a2ee15701
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882667894 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.1882667894
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.3110223724
Short name T73
Test name
Test status
Simulation time 108966478479 ps
CPU time 530.92 seconds
Started Jun 05 04:21:30 PM PDT 24
Finished Jun 05 04:30:21 PM PDT 24
Peak memory 200084 kb
Host smart-43081089-307d-480b-96a2-8280a7f8380c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110223724 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.3110223724
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.646281194
Short name T509
Test name
Test status
Simulation time 7937672053 ps
CPU time 57.64 seconds
Started Jun 05 04:21:28 PM PDT 24
Finished Jun 05 04:22:26 PM PDT 24
Peak memory 200112 kb
Host smart-df163440-74af-40b0-ad94-d1d3f1e6edc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646281194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.646281194
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2565472915
Short name T400
Test name
Test status
Simulation time 20394780 ps
CPU time 0.58 seconds
Started Jun 05 04:21:31 PM PDT 24
Finished Jun 05 04:21:32 PM PDT 24
Peak memory 195664 kb
Host smart-14aae03a-fdad-455f-988f-9ef5c5ee5b46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565472915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2565472915
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.140894041
Short name T181
Test name
Test status
Simulation time 1273078484 ps
CPU time 48.64 seconds
Started Jun 05 04:21:31 PM PDT 24
Finished Jun 05 04:22:21 PM PDT 24
Peak memory 231724 kb
Host smart-ac5b63cc-c822-4083-b42a-56be2ae402f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=140894041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.140894041
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1348311783
Short name T427
Test name
Test status
Simulation time 1000761371 ps
CPU time 15.52 seconds
Started Jun 05 04:21:38 PM PDT 24
Finished Jun 05 04:21:55 PM PDT 24
Peak memory 200088 kb
Host smart-029ec7db-36c7-45c9-bc62-100f51aba264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348311783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1348311783
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1491402238
Short name T5
Test name
Test status
Simulation time 948207394 ps
CPU time 193.29 seconds
Started Jun 05 04:21:32 PM PDT 24
Finished Jun 05 04:24:46 PM PDT 24
Peak memory 416488 kb
Host smart-6891abb4-7ec9-4649-a1aa-971f08f65596
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1491402238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1491402238
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.1511605535
Short name T208
Test name
Test status
Simulation time 15942717774 ps
CPU time 133.12 seconds
Started Jun 05 04:21:29 PM PDT 24
Finished Jun 05 04:23:43 PM PDT 24
Peak memory 200204 kb
Host smart-22d82a87-9c3b-4d73-a04b-c4225f74939b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511605535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1511605535
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1392453450
Short name T123
Test name
Test status
Simulation time 126412131 ps
CPU time 3.87 seconds
Started Jun 05 04:21:35 PM PDT 24
Finished Jun 05 04:21:40 PM PDT 24
Peak memory 200060 kb
Host smart-8fbd45b8-d7a7-4a79-910e-17eccfc88c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392453450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1392453450
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3456110311
Short name T149
Test name
Test status
Simulation time 123399213 ps
CPU time 4.51 seconds
Started Jun 05 04:21:32 PM PDT 24
Finished Jun 05 04:21:37 PM PDT 24
Peak memory 200132 kb
Host smart-03e07961-c8e7-4387-9419-7b7177701bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456110311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3456110311
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.2032711771
Short name T322
Test name
Test status
Simulation time 108445488259 ps
CPU time 525.95 seconds
Started Jun 05 04:21:35 PM PDT 24
Finished Jun 05 04:30:22 PM PDT 24
Peak memory 200168 kb
Host smart-c7f17999-1bf9-477f-a62a-aba9be3c5941
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032711771 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2032711771
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.398650276
Short name T360
Test name
Test status
Simulation time 63349443 ps
CPU time 1.4 seconds
Started Jun 05 04:21:31 PM PDT 24
Finished Jun 05 04:21:33 PM PDT 24
Peak memory 199920 kb
Host smart-23dc28f1-8ba7-45e8-b6e9-51c30017aef2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398650276 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_hmac_vectors.398650276
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.935465721
Short name T3
Test name
Test status
Simulation time 27032830353 ps
CPU time 403.52 seconds
Started Jun 05 04:21:35 PM PDT 24
Finished Jun 05 04:28:20 PM PDT 24
Peak memory 200084 kb
Host smart-16826e94-4cc4-4259-b18a-f76ec80487be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935465721 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.935465721
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.781173709
Short name T347
Test name
Test status
Simulation time 18447067853 ps
CPU time 69.84 seconds
Started Jun 05 04:21:40 PM PDT 24
Finished Jun 05 04:22:51 PM PDT 24
Peak memory 200168 kb
Host smart-3dd92ac3-2350-472a-9ef9-166e75bad508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781173709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.781173709
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.952533603
Short name T587
Test name
Test status
Simulation time 11970241 ps
CPU time 0.65 seconds
Started Jun 05 04:21:37 PM PDT 24
Finished Jun 05 04:21:39 PM PDT 24
Peak memory 195680 kb
Host smart-2e06dbc4-5d31-412b-9e77-b28f67aac2ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952533603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.952533603
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.1052547027
Short name T321
Test name
Test status
Simulation time 1592786137 ps
CPU time 18.02 seconds
Started Jun 05 04:21:38 PM PDT 24
Finished Jun 05 04:21:57 PM PDT 24
Peak memory 208204 kb
Host smart-aff92150-8bb9-475e-b4ba-e5b002cc621f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1052547027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.1052547027
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2698272984
Short name T546
Test name
Test status
Simulation time 60045958 ps
CPU time 2.2 seconds
Started Jun 05 04:21:36 PM PDT 24
Finished Jun 05 04:21:40 PM PDT 24
Peak memory 199972 kb
Host smart-34fa683d-00f6-4682-8540-b18b7a9017e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698272984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2698272984
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1482607354
Short name T379
Test name
Test status
Simulation time 4223631680 ps
CPU time 114.23 seconds
Started Jun 05 04:21:37 PM PDT 24
Finished Jun 05 04:23:32 PM PDT 24
Peak memory 582716 kb
Host smart-7be1709d-fa28-4aa7-8be1-635bc32cdd93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1482607354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1482607354
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.600298371
Short name T318
Test name
Test status
Simulation time 5518878678 ps
CPU time 40.23 seconds
Started Jun 05 04:21:40 PM PDT 24
Finished Jun 05 04:22:22 PM PDT 24
Peak memory 200164 kb
Host smart-f1f3aaba-478b-4894-90ba-a2ab72781922
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600298371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.600298371
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.613521982
Short name T519
Test name
Test status
Simulation time 9108503109 ps
CPU time 130.66 seconds
Started Jun 05 04:21:34 PM PDT 24
Finished Jun 05 04:23:45 PM PDT 24
Peak memory 200108 kb
Host smart-6c850f41-c93d-4c30-aae2-c436fd1c8d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613521982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.613521982
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.85855092
Short name T222
Test name
Test status
Simulation time 317753281 ps
CPU time 4.55 seconds
Started Jun 05 04:21:36 PM PDT 24
Finished Jun 05 04:21:42 PM PDT 24
Peak memory 200044 kb
Host smart-fc85b863-8b6d-4b27-9639-9bbed9b19f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85855092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.85855092
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1921009095
Short name T66
Test name
Test status
Simulation time 364231240615 ps
CPU time 2532.02 seconds
Started Jun 05 04:21:40 PM PDT 24
Finished Jun 05 05:03:53 PM PDT 24
Peak memory 764344 kb
Host smart-aa74f5cf-3f5f-43fd-b099-9c6cf14e6700
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921009095 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1921009095
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.2911234778
Short name T375
Test name
Test status
Simulation time 380318851 ps
CPU time 1.43 seconds
Started Jun 05 04:21:39 PM PDT 24
Finished Jun 05 04:21:42 PM PDT 24
Peak memory 200144 kb
Host smart-1e8808c7-e742-4c96-916c-9ded7c60f3f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911234778 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.2911234778
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.4212085142
Short name T157
Test name
Test status
Simulation time 31350563676 ps
CPU time 477.02 seconds
Started Jun 05 04:21:37 PM PDT 24
Finished Jun 05 04:29:35 PM PDT 24
Peak memory 200056 kb
Host smart-a7de9a2e-8d0b-453d-abb9-3e0a6b3e7b90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212085142 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.4212085142
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.296993084
Short name T26
Test name
Test status
Simulation time 4803609516 ps
CPU time 61.14 seconds
Started Jun 05 04:21:37 PM PDT 24
Finished Jun 05 04:22:39 PM PDT 24
Peak memory 200116 kb
Host smart-6da192b1-941a-49b8-a335-a8801d11accd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296993084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.296993084
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2457219410
Short name T279
Test name
Test status
Simulation time 50945512 ps
CPU time 0.61 seconds
Started Jun 05 04:21:06 PM PDT 24
Finished Jun 05 04:21:08 PM PDT 24
Peak memory 196696 kb
Host smart-6083be59-22e0-4da8-85af-46b263a570d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457219410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2457219410
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1873219699
Short name T191
Test name
Test status
Simulation time 3436193317 ps
CPU time 45.39 seconds
Started Jun 05 04:21:00 PM PDT 24
Finished Jun 05 04:21:46 PM PDT 24
Peak memory 242228 kb
Host smart-9030436b-88f5-48ba-bbad-7998ee8cf54b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1873219699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1873219699
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2642331129
Short name T115
Test name
Test status
Simulation time 333883229 ps
CPU time 4.39 seconds
Started Jun 05 04:21:04 PM PDT 24
Finished Jun 05 04:21:09 PM PDT 24
Peak memory 200020 kb
Host smart-569bff85-ebec-4338-9f63-d811db21f10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642331129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2642331129
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.2126098245
Short name T231
Test name
Test status
Simulation time 4435037726 ps
CPU time 1414.41 seconds
Started Jun 05 04:21:04 PM PDT 24
Finished Jun 05 04:44:39 PM PDT 24
Peak memory 776576 kb
Host smart-0d35d942-90c1-4a9a-a55b-1135bc87a40c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2126098245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2126098245
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.2225191495
Short name T411
Test name
Test status
Simulation time 36023693851 ps
CPU time 150.8 seconds
Started Jun 05 04:21:04 PM PDT 24
Finished Jun 05 04:23:35 PM PDT 24
Peak memory 200348 kb
Host smart-d2fb256f-be34-4a53-821b-d61358912a62
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225191495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2225191495
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3004796795
Short name T211
Test name
Test status
Simulation time 13774550257 ps
CPU time 91.51 seconds
Started Jun 05 04:21:02 PM PDT 24
Finished Jun 05 04:22:34 PM PDT 24
Peak memory 200204 kb
Host smart-19484012-ee01-490b-9214-e0fc836adfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004796795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3004796795
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2387624113
Short name T30
Test name
Test status
Simulation time 182366958 ps
CPU time 1.12 seconds
Started Jun 05 04:21:05 PM PDT 24
Finished Jun 05 04:21:07 PM PDT 24
Peak memory 219576 kb
Host smart-07057e8a-6400-45e7-845f-1b185bb36c30
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387624113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2387624113
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.1954634181
Short name T330
Test name
Test status
Simulation time 115719926 ps
CPU time 2.02 seconds
Started Jun 05 04:21:01 PM PDT 24
Finished Jun 05 04:21:03 PM PDT 24
Peak memory 200144 kb
Host smart-270037fe-f422-489e-a5cb-77de9380646f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954634181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1954634181
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.4169192166
Short name T588
Test name
Test status
Simulation time 86585240583 ps
CPU time 2756.51 seconds
Started Jun 05 04:21:06 PM PDT 24
Finished Jun 05 05:07:04 PM PDT 24
Peak memory 857668 kb
Host smart-00e43a2f-cbbc-4dea-99df-5477b110e928
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169192166 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.4169192166
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.526868169
Short name T403
Test name
Test status
Simulation time 521481499 ps
CPU time 1.14 seconds
Started Jun 05 04:21:03 PM PDT 24
Finished Jun 05 04:21:04 PM PDT 24
Peak memory 200128 kb
Host smart-8a0b7cea-cdde-4770-ab67-f6891fe95494
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526868169 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.hmac_test_hmac_vectors.526868169
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.930687964
Short name T298
Test name
Test status
Simulation time 32999256351 ps
CPU time 477.34 seconds
Started Jun 05 04:21:06 PM PDT 24
Finished Jun 05 04:29:04 PM PDT 24
Peak memory 200088 kb
Host smart-25aa7cb7-ffc2-40c6-b62b-4be7fab7ebdd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930687964 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.930687964
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.530076241
Short name T471
Test name
Test status
Simulation time 3675021746 ps
CPU time 35.94 seconds
Started Jun 05 04:21:03 PM PDT 24
Finished Jun 05 04:21:40 PM PDT 24
Peak memory 200200 kb
Host smart-62967f9e-0090-4bf0-9f05-e5ef18bcc746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530076241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.530076241
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1844739909
Short name T554
Test name
Test status
Simulation time 23178704 ps
CPU time 0.57 seconds
Started Jun 05 04:21:38 PM PDT 24
Finished Jun 05 04:21:39 PM PDT 24
Peak memory 194940 kb
Host smart-360021b2-a6dc-4c54-9364-f8ba48ad727b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844739909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1844739909
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.108657058
Short name T515
Test name
Test status
Simulation time 1242245651 ps
CPU time 61.08 seconds
Started Jun 05 04:21:42 PM PDT 24
Finished Jun 05 04:22:44 PM PDT 24
Peak memory 235096 kb
Host smart-87336088-bd99-4e4a-a49e-b2b8e326ceee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=108657058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.108657058
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.509664271
Short name T495
Test name
Test status
Simulation time 4123317518 ps
CPU time 59.47 seconds
Started Jun 05 04:21:40 PM PDT 24
Finished Jun 05 04:22:41 PM PDT 24
Peak memory 200192 kb
Host smart-fdc80950-48d4-480c-a19f-668b4b850739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509664271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.509664271
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.2692505345
Short name T228
Test name
Test status
Simulation time 4770446592 ps
CPU time 727.87 seconds
Started Jun 05 04:21:40 PM PDT 24
Finished Jun 05 04:33:49 PM PDT 24
Peak memory 734848 kb
Host smart-6a687f1e-7fb6-4aa4-8647-29895327cc52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2692505345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2692505345
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.2063060227
Short name T61
Test name
Test status
Simulation time 9109479977 ps
CPU time 109.42 seconds
Started Jun 05 04:21:39 PM PDT 24
Finished Jun 05 04:23:30 PM PDT 24
Peak memory 200112 kb
Host smart-c5570fca-e575-4b1a-b782-ceaa46e7647d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063060227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2063060227
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.544335112
Short name T240
Test name
Test status
Simulation time 894113573 ps
CPU time 13.69 seconds
Started Jun 05 04:21:38 PM PDT 24
Finished Jun 05 04:21:52 PM PDT 24
Peak memory 200100 kb
Host smart-c8720eac-3161-435f-810a-163876a486ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544335112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.544335112
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.3191038005
Short name T145
Test name
Test status
Simulation time 995587292 ps
CPU time 8 seconds
Started Jun 05 04:21:38 PM PDT 24
Finished Jun 05 04:21:47 PM PDT 24
Peak memory 200176 kb
Host smart-c8aa4486-d0c0-4d13-a1c4-e360f0ef0a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191038005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3191038005
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2049808364
Short name T98
Test name
Test status
Simulation time 859057678074 ps
CPU time 1043.47 seconds
Started Jun 05 04:21:42 PM PDT 24
Finished Jun 05 04:39:06 PM PDT 24
Peak memory 242112 kb
Host smart-bb0a452e-97aa-42a6-8800-05ed10ffa1c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049808364 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2049808364
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.4221951183
Short name T170
Test name
Test status
Simulation time 197415627 ps
CPU time 1.41 seconds
Started Jun 05 04:21:39 PM PDT 24
Finished Jun 05 04:21:42 PM PDT 24
Peak memory 200184 kb
Host smart-32b4f563-5179-4b57-a7f2-d22dff8642ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221951183 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.4221951183
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.3635351333
Short name T307
Test name
Test status
Simulation time 14516143215 ps
CPU time 407.64 seconds
Started Jun 05 04:21:35 PM PDT 24
Finished Jun 05 04:28:23 PM PDT 24
Peak memory 200060 kb
Host smart-0b606263-3975-4bae-9a1a-709ebf1037d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635351333 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.3635351333
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.2146552900
Short name T266
Test name
Test status
Simulation time 43091181 ps
CPU time 1.58 seconds
Started Jun 05 04:21:39 PM PDT 24
Finished Jun 05 04:21:41 PM PDT 24
Peak memory 199968 kb
Host smart-57f22ef7-9fc0-4bcd-9e38-42efd8f8a0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146552900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2146552900
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3479962635
Short name T399
Test name
Test status
Simulation time 41139277 ps
CPU time 0.59 seconds
Started Jun 05 04:21:38 PM PDT 24
Finished Jun 05 04:21:39 PM PDT 24
Peak memory 195956 kb
Host smart-3b221803-a608-447d-9bc1-a5e7a2de9dfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479962635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3479962635
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1115165703
Short name T556
Test name
Test status
Simulation time 1014883245 ps
CPU time 56.74 seconds
Started Jun 05 04:21:37 PM PDT 24
Finished Jun 05 04:22:35 PM PDT 24
Peak memory 216512 kb
Host smart-4d2e9977-20bd-4f03-91e0-ed22ffedc252
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1115165703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1115165703
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.667391139
Short name T415
Test name
Test status
Simulation time 1682137724 ps
CPU time 45.77 seconds
Started Jun 05 04:21:36 PM PDT 24
Finished Jun 05 04:22:22 PM PDT 24
Peak memory 200136 kb
Host smart-0618451b-5fea-49c0-b7b9-8a39938511e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667391139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.667391139
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.2472142953
Short name T310
Test name
Test status
Simulation time 5114347967 ps
CPU time 675.33 seconds
Started Jun 05 04:21:36 PM PDT 24
Finished Jun 05 04:32:52 PM PDT 24
Peak memory 756912 kb
Host smart-7590eeee-2143-40c0-b2c3-6543d6edae2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2472142953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2472142953
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1448942922
Short name T172
Test name
Test status
Simulation time 38084377342 ps
CPU time 153.04 seconds
Started Jun 05 04:21:38 PM PDT 24
Finished Jun 05 04:24:12 PM PDT 24
Peak memory 200160 kb
Host smart-cd2bc14f-c1ae-41a2-99c2-8df2c47a4504
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448942922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1448942922
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2686940051
Short name T486
Test name
Test status
Simulation time 5556935506 ps
CPU time 86.78 seconds
Started Jun 05 04:21:38 PM PDT 24
Finished Jun 05 04:23:05 PM PDT 24
Peak memory 200152 kb
Host smart-18f2c806-72b5-4004-a9e2-fee5dfc3b870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686940051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2686940051
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2373182327
Short name T555
Test name
Test status
Simulation time 827946905 ps
CPU time 4.48 seconds
Started Jun 05 04:21:39 PM PDT 24
Finished Jun 05 04:21:44 PM PDT 24
Peak memory 200136 kb
Host smart-152dbbd7-1804-47a2-b605-9a1ca90e2cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373182327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2373182327
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2215663116
Short name T213
Test name
Test status
Simulation time 15523659771 ps
CPU time 974.53 seconds
Started Jun 05 04:21:45 PM PDT 24
Finished Jun 05 04:38:00 PM PDT 24
Peak memory 713764 kb
Host smart-f5b96f46-abbe-4797-8fc4-81c2cc5bfc80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215663116 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2215663116
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.2407696992
Short name T1
Test name
Test status
Simulation time 58921282 ps
CPU time 1.11 seconds
Started Jun 05 04:21:39 PM PDT 24
Finished Jun 05 04:21:42 PM PDT 24
Peak memory 200100 kb
Host smart-4ac2249f-f11d-488e-8adc-b1436497fef3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407696992 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.2407696992
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.1254737961
Short name T380
Test name
Test status
Simulation time 97553568201 ps
CPU time 453.85 seconds
Started Jun 05 04:21:39 PM PDT 24
Finished Jun 05 04:29:14 PM PDT 24
Peak memory 200096 kb
Host smart-21aa4be9-ac39-48ff-b6a4-21375b768486
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254737961 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.1254737961
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2860975286
Short name T334
Test name
Test status
Simulation time 554929591 ps
CPU time 11.07 seconds
Started Jun 05 04:21:36 PM PDT 24
Finished Jun 05 04:21:49 PM PDT 24
Peak memory 200032 kb
Host smart-d92d2087-49fb-4ef2-9a74-8fcda7d719ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860975286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2860975286
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3235639056
Short name T173
Test name
Test status
Simulation time 14481401 ps
CPU time 0.58 seconds
Started Jun 05 04:21:40 PM PDT 24
Finished Jun 05 04:21:42 PM PDT 24
Peak memory 195968 kb
Host smart-a4e3f501-9517-4405-99e6-c38233124437
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235639056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3235639056
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2115734998
Short name T419
Test name
Test status
Simulation time 703971298 ps
CPU time 8.31 seconds
Started Jun 05 04:21:40 PM PDT 24
Finished Jun 05 04:21:50 PM PDT 24
Peak memory 200048 kb
Host smart-737f8f79-8e8d-438c-9ba4-283dfca8f68f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2115734998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2115734998
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1685876964
Short name T547
Test name
Test status
Simulation time 3399574245 ps
CPU time 48.15 seconds
Started Jun 05 04:21:38 PM PDT 24
Finished Jun 05 04:22:27 PM PDT 24
Peak memory 200180 kb
Host smart-b34fd9fa-b22b-4b52-82d7-bfbed06bfc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685876964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1685876964
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.2201583746
Short name T423
Test name
Test status
Simulation time 806920775 ps
CPU time 216.89 seconds
Started Jun 05 04:21:35 PM PDT 24
Finished Jun 05 04:25:13 PM PDT 24
Peak memory 650504 kb
Host smart-acf5b0a0-a5ea-4a29-abf4-408fe482b10c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2201583746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2201583746
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.3971968382
Short name T40
Test name
Test status
Simulation time 23552647840 ps
CPU time 153.39 seconds
Started Jun 05 04:21:38 PM PDT 24
Finished Jun 05 04:24:12 PM PDT 24
Peak memory 200176 kb
Host smart-c1b3bc1c-44c9-4ff7-a191-a4ca4d5c10f0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971968382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3971968382
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3038874338
Short name T458
Test name
Test status
Simulation time 1155767747 ps
CPU time 70.04 seconds
Started Jun 05 04:21:37 PM PDT 24
Finished Jun 05 04:22:48 PM PDT 24
Peak memory 200128 kb
Host smart-1c5a2ce3-5fcf-44f6-8254-c69165395ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038874338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3038874338
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.4052225568
Short name T162
Test name
Test status
Simulation time 179961690 ps
CPU time 2.77 seconds
Started Jun 05 04:21:36 PM PDT 24
Finished Jun 05 04:21:40 PM PDT 24
Peak memory 200040 kb
Host smart-80e72c61-f277-45a7-94fe-7a58c3e07964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052225568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.4052225568
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2641698725
Short name T70
Test name
Test status
Simulation time 303564156752 ps
CPU time 1380.29 seconds
Started Jun 05 04:21:38 PM PDT 24
Finished Jun 05 04:44:39 PM PDT 24
Peak memory 236020 kb
Host smart-6dd37394-bd48-4be3-8a78-9f98a0aa4245
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641698725 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2641698725
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.953959208
Short name T503
Test name
Test status
Simulation time 122178141 ps
CPU time 1.36 seconds
Started Jun 05 04:21:40 PM PDT 24
Finished Jun 05 04:21:43 PM PDT 24
Peak memory 200116 kb
Host smart-a3901d62-bee6-49d1-aa32-9c056ce5bdb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953959208 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_hmac_vectors.953959208
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.2426257273
Short name T275
Test name
Test status
Simulation time 165451571612 ps
CPU time 530.2 seconds
Started Jun 05 04:21:39 PM PDT 24
Finished Jun 05 04:30:31 PM PDT 24
Peak memory 200088 kb
Host smart-99b14e40-b15a-48fe-b2d0-f56a397208a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426257273 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.2426257273
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.1597727872
Short name T280
Test name
Test status
Simulation time 4730490582 ps
CPU time 78.63 seconds
Started Jun 05 04:21:38 PM PDT 24
Finished Jun 05 04:22:58 PM PDT 24
Peak memory 200176 kb
Host smart-1666582c-a80a-4b86-a0f9-7c65a7a08ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597727872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1597727872
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2738880735
Short name T356
Test name
Test status
Simulation time 21743965 ps
CPU time 0.58 seconds
Started Jun 05 04:21:41 PM PDT 24
Finished Jun 05 04:21:43 PM PDT 24
Peak memory 195696 kb
Host smart-caababc0-940c-450b-b35c-c8c8119f1bf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738880735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2738880735
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2068069531
Short name T264
Test name
Test status
Simulation time 1128115242 ps
CPU time 49.99 seconds
Started Jun 05 04:21:40 PM PDT 24
Finished Jun 05 04:22:31 PM PDT 24
Peak memory 231176 kb
Host smart-85f5d552-aea4-43eb-996c-7660270d50fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2068069531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2068069531
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.3385982497
Short name T522
Test name
Test status
Simulation time 423502341 ps
CPU time 25.39 seconds
Started Jun 05 04:21:38 PM PDT 24
Finished Jun 05 04:22:04 PM PDT 24
Peak memory 200100 kb
Host smart-a04bce38-fb44-444a-b956-b15de6261ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385982497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3385982497
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1880866894
Short name T244
Test name
Test status
Simulation time 2540968097 ps
CPU time 580.58 seconds
Started Jun 05 04:21:38 PM PDT 24
Finished Jun 05 04:31:19 PM PDT 24
Peak memory 692160 kb
Host smart-f9d24837-be9b-4e4b-8ee2-9581f0d3a06b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1880866894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1880866894
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3058874024
Short name T163
Test name
Test status
Simulation time 1919514141 ps
CPU time 8.81 seconds
Started Jun 05 04:21:40 PM PDT 24
Finished Jun 05 04:21:50 PM PDT 24
Peak memory 199968 kb
Host smart-057cb4a8-fba2-4977-9be5-87056a5eb939
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058874024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3058874024
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3907585972
Short name T346
Test name
Test status
Simulation time 7079986648 ps
CPU time 109.59 seconds
Started Jun 05 04:21:41 PM PDT 24
Finished Jun 05 04:23:31 PM PDT 24
Peak memory 200156 kb
Host smart-db86d00f-dfa2-4e2d-8e95-05ef69aa4930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907585972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3907585972
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.461424339
Short name T460
Test name
Test status
Simulation time 706500429 ps
CPU time 6.48 seconds
Started Jun 05 04:21:42 PM PDT 24
Finished Jun 05 04:21:49 PM PDT 24
Peak memory 200072 kb
Host smart-716879be-5327-47f3-bb66-0737a67bd5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461424339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.461424339
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.1052378035
Short name T476
Test name
Test status
Simulation time 4877209425 ps
CPU time 68.61 seconds
Started Jun 05 04:21:38 PM PDT 24
Finished Jun 05 04:22:48 PM PDT 24
Peak memory 200184 kb
Host smart-ce215f00-a9f5-4cab-bf1a-76f7fd3535ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052378035 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1052378035
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.3415958160
Short name T467
Test name
Test status
Simulation time 30939002 ps
CPU time 1.04 seconds
Started Jun 05 04:21:40 PM PDT 24
Finished Jun 05 04:21:43 PM PDT 24
Peak memory 199932 kb
Host smart-2545275a-96a2-4955-90c9-68690534886f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415958160 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.3415958160
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.3309113507
Short name T167
Test name
Test status
Simulation time 13261558884 ps
CPU time 451.75 seconds
Started Jun 05 04:21:45 PM PDT 24
Finished Jun 05 04:29:18 PM PDT 24
Peak memory 200040 kb
Host smart-f34753f7-3ba5-4787-80f2-ca44954a206e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309113507 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.3309113507
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3121685055
Short name T531
Test name
Test status
Simulation time 2002387775 ps
CPU time 38.5 seconds
Started Jun 05 04:21:43 PM PDT 24
Finished Jun 05 04:22:22 PM PDT 24
Peak memory 200144 kb
Host smart-0dde4eaa-5761-469f-8cf9-3bb3b1c3cac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121685055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3121685055
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2628331267
Short name T390
Test name
Test status
Simulation time 13125102 ps
CPU time 0.62 seconds
Started Jun 05 04:21:45 PM PDT 24
Finished Jun 05 04:21:47 PM PDT 24
Peak memory 195964 kb
Host smart-f355ce02-976e-4e00-a853-c113fedea276
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628331267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2628331267
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.538420332
Short name T16
Test name
Test status
Simulation time 2140310672 ps
CPU time 49.7 seconds
Started Jun 05 04:21:49 PM PDT 24
Finished Jun 05 04:22:40 PM PDT 24
Peak memory 218556 kb
Host smart-00adef03-2137-4ed5-83d8-3cb126323561
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=538420332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.538420332
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1253960013
Short name T523
Test name
Test status
Simulation time 3366643137 ps
CPU time 54.42 seconds
Started Jun 05 04:21:47 PM PDT 24
Finished Jun 05 04:22:43 PM PDT 24
Peak memory 200244 kb
Host smart-c0b53009-1f22-452e-96bb-d0fb86cc0f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253960013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1253960013
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.4149336303
Short name T186
Test name
Test status
Simulation time 6397151499 ps
CPU time 811.17 seconds
Started Jun 05 04:21:46 PM PDT 24
Finished Jun 05 04:35:18 PM PDT 24
Peak memory 727372 kb
Host smart-1814737c-a8e1-4d69-98ab-ef5a0a6b269e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4149336303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.4149336303
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2084516551
Short name T577
Test name
Test status
Simulation time 2395060053 ps
CPU time 43.05 seconds
Started Jun 05 04:21:49 PM PDT 24
Finished Jun 05 04:22:33 PM PDT 24
Peak memory 200116 kb
Host smart-e40ee01b-3949-4f83-89bc-243ff1481a75
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084516551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2084516551
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.3571100686
Short name T569
Test name
Test status
Simulation time 15194026145 ps
CPU time 29.61 seconds
Started Jun 05 04:21:45 PM PDT 24
Finished Jun 05 04:22:16 PM PDT 24
Peak memory 200188 kb
Host smart-98527903-eb17-46fc-9ddf-23bf90568add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571100686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3571100686
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.3652682879
Short name T524
Test name
Test status
Simulation time 209859781 ps
CPU time 2.01 seconds
Started Jun 05 04:21:39 PM PDT 24
Finished Jun 05 04:21:43 PM PDT 24
Peak memory 200072 kb
Host smart-680c784c-3466-4b2a-9569-b83d5a5abb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652682879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3652682879
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3461496295
Short name T65
Test name
Test status
Simulation time 197320503924 ps
CPU time 1285.99 seconds
Started Jun 05 04:21:49 PM PDT 24
Finished Jun 05 04:43:17 PM PDT 24
Peak memory 216608 kb
Host smart-3ceef8d5-8016-42bf-a952-45a8a6d0cd0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461496295 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3461496295
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.1613405969
Short name T537
Test name
Test status
Simulation time 51312717 ps
CPU time 1.02 seconds
Started Jun 05 04:21:47 PM PDT 24
Finished Jun 05 04:21:49 PM PDT 24
Peak memory 199824 kb
Host smart-2ad23a93-e785-4c9c-9658-1bb9fc46a8b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613405969 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.1613405969
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.1901986642
Short name T365
Test name
Test status
Simulation time 33647900539 ps
CPU time 486.65 seconds
Started Jun 05 04:21:48 PM PDT 24
Finished Jun 05 04:29:56 PM PDT 24
Peak memory 200100 kb
Host smart-d12276af-8414-4925-81f0-745897ba724d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901986642 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.1901986642
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.1153970778
Short name T337
Test name
Test status
Simulation time 28075997077 ps
CPU time 75.62 seconds
Started Jun 05 04:21:46 PM PDT 24
Finished Jun 05 04:23:03 PM PDT 24
Peak memory 200164 kb
Host smart-e64c6cef-5f7a-44a3-a956-a67729fcb9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153970778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1153970778
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3633645493
Short name T489
Test name
Test status
Simulation time 43615447 ps
CPU time 0.59 seconds
Started Jun 05 04:21:45 PM PDT 24
Finished Jun 05 04:21:46 PM PDT 24
Peak memory 194968 kb
Host smart-a7a4c440-34da-4397-9f0c-0258722d73c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633645493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3633645493
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.2731275084
Short name T234
Test name
Test status
Simulation time 2909572494 ps
CPU time 37.16 seconds
Started Jun 05 04:21:48 PM PDT 24
Finished Jun 05 04:22:27 PM PDT 24
Peak memory 229088 kb
Host smart-044d0643-e2a2-4c60-94f7-9fbbe3f84fd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2731275084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2731275084
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1439384787
Short name T235
Test name
Test status
Simulation time 1877317768 ps
CPU time 31.83 seconds
Started Jun 05 04:21:45 PM PDT 24
Finished Jun 05 04:22:17 PM PDT 24
Peak memory 200084 kb
Host smart-aca6b940-065d-421f-bcaf-07283eb523cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439384787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1439384787
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.23814865
Short name T192
Test name
Test status
Simulation time 21531190867 ps
CPU time 1500.42 seconds
Started Jun 05 04:21:45 PM PDT 24
Finished Jun 05 04:46:46 PM PDT 24
Peak memory 764068 kb
Host smart-4ccb8a7c-c124-4434-b74a-e96eeb037ee1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=23814865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.23814865
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2015455201
Short name T492
Test name
Test status
Simulation time 48552956606 ps
CPU time 170.83 seconds
Started Jun 05 04:21:49 PM PDT 24
Finished Jun 05 04:24:41 PM PDT 24
Peak memory 200224 kb
Host smart-07ec2656-5b20-4b4d-8070-10a93b4bec9f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015455201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2015455201
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.4154114458
Short name T56
Test name
Test status
Simulation time 17961531553 ps
CPU time 43.72 seconds
Started Jun 05 04:21:46 PM PDT 24
Finished Jun 05 04:22:31 PM PDT 24
Peak memory 200140 kb
Host smart-d400d178-430f-4e4c-8b2f-aec8ae3a932c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154114458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.4154114458
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.1196065966
Short name T166
Test name
Test status
Simulation time 176083574 ps
CPU time 5.96 seconds
Started Jun 05 04:21:47 PM PDT 24
Finished Jun 05 04:21:55 PM PDT 24
Peak memory 200140 kb
Host smart-2dbc31bd-8e2b-41c7-9976-552eb244951b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196065966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1196065966
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.1609896673
Short name T276
Test name
Test status
Simulation time 55766144454 ps
CPU time 1046.89 seconds
Started Jun 05 04:21:47 PM PDT 24
Finished Jun 05 04:39:15 PM PDT 24
Peak memory 229368 kb
Host smart-262ae5be-d359-46c8-b81d-c5440cdbf8d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609896673 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1609896673
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.4294214528
Short name T514
Test name
Test status
Simulation time 227263322 ps
CPU time 1.16 seconds
Started Jun 05 04:21:45 PM PDT 24
Finished Jun 05 04:21:47 PM PDT 24
Peak memory 200096 kb
Host smart-978a0515-b0cc-4baa-9e69-20479789d5d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294214528 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.4294214528
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.3004810335
Short name T565
Test name
Test status
Simulation time 7048768615 ps
CPU time 395.15 seconds
Started Jun 05 04:21:48 PM PDT 24
Finished Jun 05 04:28:25 PM PDT 24
Peak memory 200184 kb
Host smart-4ab7beb8-f99f-450b-a5ea-af471038dc29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004810335 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.3004810335
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2356332991
Short name T420
Test name
Test status
Simulation time 1869656177 ps
CPU time 79.25 seconds
Started Jun 05 04:21:45 PM PDT 24
Finished Jun 05 04:23:05 PM PDT 24
Peak memory 200112 kb
Host smart-0eac23b4-816f-43c0-9b42-81e84729eaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356332991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2356332991
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.3003686318
Short name T20
Test name
Test status
Simulation time 42152149 ps
CPU time 0.65 seconds
Started Jun 05 04:21:54 PM PDT 24
Finished Jun 05 04:21:56 PM PDT 24
Peak memory 195968 kb
Host smart-7051511b-e69f-4243-b926-256ca078b129
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003686318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3003686318
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.936637866
Short name T247
Test name
Test status
Simulation time 1114430529 ps
CPU time 55.56 seconds
Started Jun 05 04:21:48 PM PDT 24
Finished Jun 05 04:22:45 PM PDT 24
Peak memory 216548 kb
Host smart-f10fc200-021a-4757-8173-f47747c82638
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=936637866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.936637866
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1858701915
Short name T289
Test name
Test status
Simulation time 2762368903 ps
CPU time 27.27 seconds
Started Jun 05 04:21:46 PM PDT 24
Finished Jun 05 04:22:14 PM PDT 24
Peak memory 200224 kb
Host smart-e62f52de-ccda-4a24-a838-96865b5c9b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858701915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1858701915
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.2032280369
Short name T319
Test name
Test status
Simulation time 4831188235 ps
CPU time 301.96 seconds
Started Jun 05 04:21:48 PM PDT 24
Finished Jun 05 04:26:51 PM PDT 24
Peak memory 481976 kb
Host smart-31a31b4d-9a97-4c41-ada7-264564f5764a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2032280369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2032280369
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.388863969
Short name T286
Test name
Test status
Simulation time 4987417304 ps
CPU time 155.51 seconds
Started Jun 05 04:21:54 PM PDT 24
Finished Jun 05 04:24:30 PM PDT 24
Peak memory 200108 kb
Host smart-1ee8af39-c395-466d-93e0-6867d8c36052
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388863969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.388863969
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3674785861
Short name T183
Test name
Test status
Simulation time 12190793885 ps
CPU time 42.23 seconds
Started Jun 05 04:21:46 PM PDT 24
Finished Jun 05 04:22:30 PM PDT 24
Peak memory 200192 kb
Host smart-b617f021-fe22-4a86-858b-6a4e669b18ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674785861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3674785861
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.858427817
Short name T497
Test name
Test status
Simulation time 159718765 ps
CPU time 5.59 seconds
Started Jun 05 04:21:49 PM PDT 24
Finished Jun 05 04:21:56 PM PDT 24
Peak memory 200124 kb
Host smart-c4d4ab6a-a275-464f-83a8-6e8e4e0bb990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858427817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.858427817
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.1404602020
Short name T428
Test name
Test status
Simulation time 459600958725 ps
CPU time 1922.82 seconds
Started Jun 05 04:21:52 PM PDT 24
Finished Jun 05 04:53:56 PM PDT 24
Peak memory 694292 kb
Host smart-1d1b6912-d081-42f6-8451-cc08ad5aed5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404602020 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1404602020
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.2229182911
Short name T148
Test name
Test status
Simulation time 58271465 ps
CPU time 1.22 seconds
Started Jun 05 04:21:53 PM PDT 24
Finished Jun 05 04:21:54 PM PDT 24
Peak memory 200088 kb
Host smart-b2f0252c-f5dc-4a40-8686-6bbd3c0e610c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229182911 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.2229182911
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.744207315
Short name T232
Test name
Test status
Simulation time 202271850237 ps
CPU time 583.24 seconds
Started Jun 05 04:21:55 PM PDT 24
Finished Jun 05 04:31:39 PM PDT 24
Peak memory 200100 kb
Host smart-f95dd97f-ce9e-43d5-a5ca-cb4c5e0d7458
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744207315 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.744207315
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.4084511418
Short name T513
Test name
Test status
Simulation time 4149723203 ps
CPU time 51.58 seconds
Started Jun 05 04:21:53 PM PDT 24
Finished Jun 05 04:22:45 PM PDT 24
Peak memory 200152 kb
Host smart-c5cc1cee-51fe-433d-a539-c5422a4bcef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084511418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.4084511418
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1612768771
Short name T281
Test name
Test status
Simulation time 59415542 ps
CPU time 0.58 seconds
Started Jun 05 04:21:54 PM PDT 24
Finished Jun 05 04:21:55 PM PDT 24
Peak memory 195648 kb
Host smart-89cc2d07-891e-438e-a2c6-e7c09bbd9102
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612768771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1612768771
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.251853875
Short name T371
Test name
Test status
Simulation time 418135461 ps
CPU time 19.14 seconds
Started Jun 05 04:21:53 PM PDT 24
Finished Jun 05 04:22:13 PM PDT 24
Peak memory 221376 kb
Host smart-a1da0f74-b09e-4a18-8f02-7cdc260b7ed4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=251853875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.251853875
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.2179462241
Short name T543
Test name
Test status
Simulation time 12050127724 ps
CPU time 62.35 seconds
Started Jun 05 04:21:53 PM PDT 24
Finished Jun 05 04:22:56 PM PDT 24
Peak memory 200176 kb
Host smart-43b49f05-cc2e-477a-850b-bef4b6102b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179462241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2179462241
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3564221802
Short name T124
Test name
Test status
Simulation time 2651624182 ps
CPU time 553.59 seconds
Started Jun 05 04:21:54 PM PDT 24
Finished Jun 05 04:31:08 PM PDT 24
Peak memory 693144 kb
Host smart-a8cdb520-becc-44dd-9065-636a8b7262cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3564221802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3564221802
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2850302103
Short name T132
Test name
Test status
Simulation time 52338402581 ps
CPU time 159.39 seconds
Started Jun 05 04:21:56 PM PDT 24
Finished Jun 05 04:24:36 PM PDT 24
Peak memory 200112 kb
Host smart-fea0e784-553c-4dd9-83ff-2415e817872e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850302103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2850302103
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.143318656
Short name T474
Test name
Test status
Simulation time 865198025 ps
CPU time 45.95 seconds
Started Jun 05 04:21:55 PM PDT 24
Finished Jun 05 04:22:42 PM PDT 24
Peak memory 200048 kb
Host smart-2e5527d9-2699-4026-826d-58c50c1d457b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143318656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.143318656
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.566381765
Short name T470
Test name
Test status
Simulation time 1762526639 ps
CPU time 8.08 seconds
Started Jun 05 04:21:54 PM PDT 24
Finished Jun 05 04:22:02 PM PDT 24
Peak memory 200088 kb
Host smart-8446c036-9f4a-40eb-889f-79fffd45a5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566381765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.566381765
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3730554693
Short name T305
Test name
Test status
Simulation time 34418102884 ps
CPU time 937.31 seconds
Started Jun 05 04:21:55 PM PDT 24
Finished Jun 05 04:37:32 PM PDT 24
Peak memory 224728 kb
Host smart-39b3e04c-c7e2-45b4-a0ca-bc4a3da6f1c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730554693 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3730554693
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.596537448
Short name T263
Test name
Test status
Simulation time 171030186 ps
CPU time 1.07 seconds
Started Jun 05 04:21:54 PM PDT 24
Finished Jun 05 04:21:55 PM PDT 24
Peak memory 199876 kb
Host smart-484630e7-f5b7-4891-9f6d-d7f33683a175
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596537448 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_hmac_vectors.596537448
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.2292451753
Short name T143
Test name
Test status
Simulation time 35043023202 ps
CPU time 478.94 seconds
Started Jun 05 04:21:52 PM PDT 24
Finished Jun 05 04:29:52 PM PDT 24
Peak memory 200132 kb
Host smart-d9928796-bae1-48b8-972d-c6fc99ebd55f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292451753 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.2292451753
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.4157866851
Short name T325
Test name
Test status
Simulation time 2971750792 ps
CPU time 29.75 seconds
Started Jun 05 04:21:56 PM PDT 24
Finished Jun 05 04:22:27 PM PDT 24
Peak memory 200116 kb
Host smart-294a4df8-aa6b-4095-9213-4a8a87dd175c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157866851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.4157866851
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2691337482
Short name T296
Test name
Test status
Simulation time 12522959 ps
CPU time 0.62 seconds
Started Jun 05 04:22:02 PM PDT 24
Finished Jun 05 04:22:03 PM PDT 24
Peak memory 194936 kb
Host smart-cc07f772-1649-449e-a80c-ffb1f7b6ee29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691337482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2691337482
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2132958364
Short name T42
Test name
Test status
Simulation time 215432529 ps
CPU time 3.32 seconds
Started Jun 05 04:22:04 PM PDT 24
Finished Jun 05 04:22:08 PM PDT 24
Peak memory 216036 kb
Host smart-dd91cae7-00a7-4e30-b650-b656482e1174
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2132958364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2132958364
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1491676435
Short name T538
Test name
Test status
Simulation time 1898955109 ps
CPU time 36.21 seconds
Started Jun 05 04:22:05 PM PDT 24
Finished Jun 05 04:22:42 PM PDT 24
Peak memory 200164 kb
Host smart-dfb24e88-adc0-4f5e-b97f-c03b48de32de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491676435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1491676435
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.161330803
Short name T506
Test name
Test status
Simulation time 11693567587 ps
CPU time 706.82 seconds
Started Jun 05 04:22:01 PM PDT 24
Finished Jun 05 04:33:49 PM PDT 24
Peak memory 690012 kb
Host smart-820bbf2d-dbe9-41a0-87a1-cd41445af9c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=161330803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.161330803
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1563855791
Short name T294
Test name
Test status
Simulation time 9358226540 ps
CPU time 31.55 seconds
Started Jun 05 04:22:03 PM PDT 24
Finished Jun 05 04:22:35 PM PDT 24
Peak memory 199992 kb
Host smart-dc5618ac-9a35-406f-9ff5-e3f2fbac3784
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563855791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1563855791
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.3571007514
Short name T179
Test name
Test status
Simulation time 4779146044 ps
CPU time 62.5 seconds
Started Jun 05 04:22:04 PM PDT 24
Finished Jun 05 04:23:07 PM PDT 24
Peak memory 200136 kb
Host smart-057cb6f1-0e78-44ec-ab6c-4a9db34a675c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571007514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3571007514
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1094623804
Short name T516
Test name
Test status
Simulation time 139134575 ps
CPU time 2.33 seconds
Started Jun 05 04:21:53 PM PDT 24
Finished Jun 05 04:21:56 PM PDT 24
Peak memory 200124 kb
Host smart-75d98c93-bdc4-4a03-b163-e13aef3e436a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094623804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1094623804
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.4229857965
Short name T446
Test name
Test status
Simulation time 389256756802 ps
CPU time 952.76 seconds
Started Jun 05 04:22:05 PM PDT 24
Finished Jun 05 04:37:59 PM PDT 24
Peak memory 361944 kb
Host smart-6aef7a36-b328-4983-bea9-01cb3701de05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229857965 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.4229857965
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.1458132901
Short name T117
Test name
Test status
Simulation time 227685847 ps
CPU time 1.2 seconds
Started Jun 05 04:22:05 PM PDT 24
Finished Jun 05 04:22:07 PM PDT 24
Peak memory 200068 kb
Host smart-985af551-64bd-4561-b8c0-0e4be4719b51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458132901 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.1458132901
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.4277084405
Short name T209
Test name
Test status
Simulation time 98495038890 ps
CPU time 458.54 seconds
Started Jun 05 04:22:03 PM PDT 24
Finished Jun 05 04:29:42 PM PDT 24
Peak memory 200100 kb
Host smart-83842ef7-6213-45a4-85bf-ef4ee98520fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277084405 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.4277084405
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3298789247
Short name T4
Test name
Test status
Simulation time 901599981 ps
CPU time 17.93 seconds
Started Jun 05 04:22:04 PM PDT 24
Finished Jun 05 04:22:22 PM PDT 24
Peak memory 200072 kb
Host smart-d03a20bf-08af-4fc6-83b2-90427418bb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298789247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3298789247
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.2649233381
Short name T490
Test name
Test status
Simulation time 36978574 ps
CPU time 0.58 seconds
Started Jun 05 04:22:11 PM PDT 24
Finished Jun 05 04:22:12 PM PDT 24
Peak memory 196692 kb
Host smart-1b5704f7-87a9-43b2-ad70-de93ac01ce85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649233381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2649233381
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1443427666
Short name T14
Test name
Test status
Simulation time 1467634522 ps
CPU time 16.49 seconds
Started Jun 05 04:22:04 PM PDT 24
Finished Jun 05 04:22:21 PM PDT 24
Peak memory 216052 kb
Host smart-53432d0d-fc1f-485f-8c0f-5029f8ff2c5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1443427666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1443427666
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.3993323747
Short name T246
Test name
Test status
Simulation time 1774094893 ps
CPU time 26.21 seconds
Started Jun 05 04:22:04 PM PDT 24
Finished Jun 05 04:22:31 PM PDT 24
Peak memory 200112 kb
Host smart-b9aec96b-cd9d-4932-9474-eff69f2978a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993323747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3993323747
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1398469947
Short name T126
Test name
Test status
Simulation time 5720576315 ps
CPU time 475.67 seconds
Started Jun 05 04:22:04 PM PDT 24
Finished Jun 05 04:30:01 PM PDT 24
Peak memory 690496 kb
Host smart-f10a67d8-ed2e-49d9-b555-51c036546a6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1398469947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1398469947
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2539471980
Short name T395
Test name
Test status
Simulation time 6595842603 ps
CPU time 90.72 seconds
Started Jun 05 04:22:02 PM PDT 24
Finished Jun 05 04:23:33 PM PDT 24
Peak memory 200216 kb
Host smart-f0a86413-8c95-4691-a93c-f04681696bf0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539471980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2539471980
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2854269742
Short name T62
Test name
Test status
Simulation time 965059218 ps
CPU time 18.98 seconds
Started Jun 05 04:22:03 PM PDT 24
Finished Jun 05 04:22:22 PM PDT 24
Peak memory 200280 kb
Host smart-ec877e04-4e67-410a-aa2f-460cd4b7b452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854269742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2854269742
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2651378602
Short name T361
Test name
Test status
Simulation time 1693872790 ps
CPU time 11.2 seconds
Started Jun 05 04:22:03 PM PDT 24
Finished Jun 05 04:22:14 PM PDT 24
Peak memory 200176 kb
Host smart-4e83e491-1e8a-463a-b1a8-cdbe9de87380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651378602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2651378602
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.855477688
Short name T219
Test name
Test status
Simulation time 1695108792 ps
CPU time 24.37 seconds
Started Jun 05 04:22:12 PM PDT 24
Finished Jun 05 04:22:36 PM PDT 24
Peak memory 200036 kb
Host smart-af2c673a-8ca5-48d0-82e9-7a1b1dae52af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855477688 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.855477688
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.391806975
Short name T171
Test name
Test status
Simulation time 60163970 ps
CPU time 1.17 seconds
Started Jun 05 04:22:04 PM PDT 24
Finished Jun 05 04:22:06 PM PDT 24
Peak memory 200028 kb
Host smart-48afe072-7dd3-40a6-9eaf-b0ff36bbbd0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391806975 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_hmac_vectors.391806975
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.1778129422
Short name T488
Test name
Test status
Simulation time 9197802799 ps
CPU time 502.42 seconds
Started Jun 05 04:22:04 PM PDT 24
Finished Jun 05 04:30:27 PM PDT 24
Peak memory 200080 kb
Host smart-b7d92ab4-37ae-42ee-a230-630aaed16734
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778129422 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.1778129422
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2077455279
Short name T387
Test name
Test status
Simulation time 1855590620 ps
CPU time 89.31 seconds
Started Jun 05 04:22:04 PM PDT 24
Finished Jun 05 04:23:34 PM PDT 24
Peak memory 200052 kb
Host smart-b138d71a-6b2f-4b30-b95e-8763f514b373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077455279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2077455279
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3024217142
Short name T526
Test name
Test status
Simulation time 19675166 ps
CPU time 0.56 seconds
Started Jun 05 04:21:04 PM PDT 24
Finished Jun 05 04:21:06 PM PDT 24
Peak memory 195640 kb
Host smart-4acbdaaf-7108-4c14-8f27-9ab4b825d4d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024217142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3024217142
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3060199753
Short name T413
Test name
Test status
Simulation time 3803929110 ps
CPU time 47.63 seconds
Started Jun 05 04:21:04 PM PDT 24
Finished Jun 05 04:21:52 PM PDT 24
Peak memory 208268 kb
Host smart-a0cfbe53-4208-4f37-8e4f-d2634d635ce7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3060199753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3060199753
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1164224232
Short name T106
Test name
Test status
Simulation time 913666120 ps
CPU time 49.53 seconds
Started Jun 05 04:21:03 PM PDT 24
Finished Jun 05 04:21:53 PM PDT 24
Peak memory 200084 kb
Host smart-e6a41967-bc77-487f-b33e-2fcfdf2238c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164224232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1164224232
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1748001268
Short name T317
Test name
Test status
Simulation time 8589365489 ps
CPU time 499.78 seconds
Started Jun 05 04:21:05 PM PDT 24
Finished Jun 05 04:29:26 PM PDT 24
Peak memory 674164 kb
Host smart-8152197c-f1ef-4fe7-9346-f76a72752822
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1748001268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1748001268
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.286429958
Short name T267
Test name
Test status
Simulation time 392089251 ps
CPU time 6.45 seconds
Started Jun 05 04:21:03 PM PDT 24
Finished Jun 05 04:21:11 PM PDT 24
Peak memory 200024 kb
Host smart-e9108b7e-13e1-4a66-9532-d0cddbc3726d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286429958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.286429958
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.981188295
Short name T404
Test name
Test status
Simulation time 107953652 ps
CPU time 6.1 seconds
Started Jun 05 04:21:04 PM PDT 24
Finished Jun 05 04:21:11 PM PDT 24
Peak memory 200020 kb
Host smart-71b13251-23f4-4784-8c8c-137ccc68aafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981188295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.981188295
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1625638875
Short name T28
Test name
Test status
Simulation time 85445009 ps
CPU time 0.97 seconds
Started Jun 05 04:21:05 PM PDT 24
Finished Jun 05 04:21:07 PM PDT 24
Peak memory 219528 kb
Host smart-96e9416e-0739-4634-bcdd-d30b1325cc64
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625638875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1625638875
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.1895420817
Short name T416
Test name
Test status
Simulation time 361233096 ps
CPU time 6.32 seconds
Started Jun 05 04:21:04 PM PDT 24
Finished Jun 05 04:21:11 PM PDT 24
Peak memory 200132 kb
Host smart-da5a303b-cb17-4f75-88c5-7dc1811ea428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895420817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1895420817
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.54964667
Short name T452
Test name
Test status
Simulation time 16059941129 ps
CPU time 1025.72 seconds
Started Jun 05 04:21:08 PM PDT 24
Finished Jun 05 04:38:14 PM PDT 24
Peak memory 691840 kb
Host smart-b482dd27-aa44-4ce3-8d5b-2dfa6895dbb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54964667 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.54964667
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.1094279134
Short name T498
Test name
Test status
Simulation time 449608535 ps
CPU time 1.11 seconds
Started Jun 05 04:21:06 PM PDT 24
Finished Jun 05 04:21:08 PM PDT 24
Peak memory 199688 kb
Host smart-08c24f31-d210-48dd-98f1-17bce2fe2698
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094279134 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.1094279134
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.2397075519
Short name T33
Test name
Test status
Simulation time 94893729375 ps
CPU time 571.07 seconds
Started Jun 05 04:21:08 PM PDT 24
Finished Jun 05 04:30:40 PM PDT 24
Peak memory 200088 kb
Host smart-412e0521-97d4-4fe1-b240-da84f73843cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397075519 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.2397075519
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1205717235
Short name T357
Test name
Test status
Simulation time 7461594712 ps
CPU time 71.97 seconds
Started Jun 05 04:21:05 PM PDT 24
Finished Jun 05 04:22:18 PM PDT 24
Peak memory 200100 kb
Host smart-487f9031-18e8-4f9e-a0f8-147f86d1d7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205717235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1205717235
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.2806455996
Short name T433
Test name
Test status
Simulation time 12527451 ps
CPU time 0.61 seconds
Started Jun 05 04:22:14 PM PDT 24
Finished Jun 05 04:22:15 PM PDT 24
Peak memory 194764 kb
Host smart-ddf7424c-5f15-42f4-a60d-dcb5b590bbbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806455996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2806455996
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.3420196212
Short name T551
Test name
Test status
Simulation time 1038417541 ps
CPU time 49.63 seconds
Started Jun 05 04:22:09 PM PDT 24
Finished Jun 05 04:22:59 PM PDT 24
Peak memory 216516 kb
Host smart-26e13da8-b9db-4c8f-93dc-bb6c32676e2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3420196212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3420196212
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3852940715
Short name T291
Test name
Test status
Simulation time 728295479 ps
CPU time 14.5 seconds
Started Jun 05 04:22:10 PM PDT 24
Finished Jun 05 04:22:25 PM PDT 24
Peak memory 200148 kb
Host smart-7cc1d09c-b9ac-44cb-a98a-53489d735923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852940715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3852940715
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.1675126540
Short name T454
Test name
Test status
Simulation time 3608499978 ps
CPU time 435.05 seconds
Started Jun 05 04:22:11 PM PDT 24
Finished Jun 05 04:29:27 PM PDT 24
Peak memory 707500 kb
Host smart-ed01162d-ce32-4bb0-9deb-5146ecfc93a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1675126540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1675126540
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3617975991
Short name T355
Test name
Test status
Simulation time 37227812234 ps
CPU time 152.47 seconds
Started Jun 05 04:22:09 PM PDT 24
Finished Jun 05 04:24:42 PM PDT 24
Peak memory 200160 kb
Host smart-517fa9bc-ebc5-4db0-8848-8fe2ce7523f6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617975991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3617975991
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2833257279
Short name T129
Test name
Test status
Simulation time 10415958691 ps
CPU time 95.04 seconds
Started Jun 05 04:22:16 PM PDT 24
Finished Jun 05 04:23:51 PM PDT 24
Peak memory 200024 kb
Host smart-72121322-1da2-4fa1-9912-df4b28251892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833257279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2833257279
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.1983025855
Short name T493
Test name
Test status
Simulation time 460266387 ps
CPU time 4.35 seconds
Started Jun 05 04:22:12 PM PDT 24
Finished Jun 05 04:22:17 PM PDT 24
Peak memory 200008 kb
Host smart-06c3fa87-ed8a-4633-986f-38ab1c21e7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983025855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1983025855
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.3584093043
Short name T177
Test name
Test status
Simulation time 3131288433 ps
CPU time 172.79 seconds
Started Jun 05 04:22:11 PM PDT 24
Finished Jun 05 04:25:05 PM PDT 24
Peak memory 215544 kb
Host smart-3a9ddb19-1609-48ee-ba98-44b72c05abde
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584093043 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.3584093043
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.1144193047
Short name T147
Test name
Test status
Simulation time 124034728 ps
CPU time 1.17 seconds
Started Jun 05 04:22:11 PM PDT 24
Finished Jun 05 04:22:13 PM PDT 24
Peak memory 200080 kb
Host smart-e4182d77-e41f-42cf-b7a2-1dce4a7ac0aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144193047 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.1144193047
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.2160638541
Short name T539
Test name
Test status
Simulation time 51496990520 ps
CPU time 481.34 seconds
Started Jun 05 04:22:09 PM PDT 24
Finished Jun 05 04:30:11 PM PDT 24
Peak memory 200124 kb
Host smart-e4e0380c-d142-45c6-a9c2-ed1395d64d89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160638541 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.2160638541
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.254568967
Short name T37
Test name
Test status
Simulation time 1785501238 ps
CPU time 8.76 seconds
Started Jun 05 04:22:15 PM PDT 24
Finished Jun 05 04:22:24 PM PDT 24
Peak memory 199632 kb
Host smart-2dea8202-1109-4858-a0a4-1f292ade18ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254568967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.254568967
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2241834086
Short name T372
Test name
Test status
Simulation time 651117907 ps
CPU time 30.36 seconds
Started Jun 05 04:22:10 PM PDT 24
Finished Jun 05 04:22:41 PM PDT 24
Peak memory 231260 kb
Host smart-2f8d0f9c-1d09-496c-99b4-446d0afc0017
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2241834086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2241834086
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.420003534
Short name T297
Test name
Test status
Simulation time 845287818 ps
CPU time 44.32 seconds
Started Jun 05 04:22:12 PM PDT 24
Finished Jun 05 04:22:57 PM PDT 24
Peak memory 200132 kb
Host smart-e2cad205-6096-4a07-87ae-a2aaf040a03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420003534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.420003534
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3325395591
Short name T409
Test name
Test status
Simulation time 8909054940 ps
CPU time 307.28 seconds
Started Jun 05 04:22:10 PM PDT 24
Finished Jun 05 04:27:18 PM PDT 24
Peak memory 626684 kb
Host smart-79c407f3-f4ab-4c63-82fd-26b7764e3ff5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3325395591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3325395591
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3627585413
Short name T292
Test name
Test status
Simulation time 1655036633 ps
CPU time 87.28 seconds
Started Jun 05 04:22:09 PM PDT 24
Finished Jun 05 04:23:38 PM PDT 24
Peak memory 200056 kb
Host smart-52ab6c18-bf55-409d-94c6-5dd81662c8e5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627585413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3627585413
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.2430641508
Short name T139
Test name
Test status
Simulation time 25859000831 ps
CPU time 82.57 seconds
Started Jun 05 04:22:08 PM PDT 24
Finished Jun 05 04:23:31 PM PDT 24
Peak memory 200136 kb
Host smart-de2378f0-f045-409e-9ef5-8682a23a319e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430641508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.2430641508
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.4212055
Short name T55
Test name
Test status
Simulation time 1680042745 ps
CPU time 9.19 seconds
Started Jun 05 04:22:11 PM PDT 24
Finished Jun 05 04:22:21 PM PDT 24
Peak memory 200064 kb
Host smart-65cf11fb-244b-455f-92a0-ba33b33753eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.4212055
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2889445018
Short name T63
Test name
Test status
Simulation time 23996383219 ps
CPU time 880.9 seconds
Started Jun 05 04:22:10 PM PDT 24
Finished Jun 05 04:36:52 PM PDT 24
Peak memory 740116 kb
Host smart-dd4b3143-362d-4599-9a84-b9a7aa4959ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889445018 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2889445018
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.3527861605
Short name T367
Test name
Test status
Simulation time 62371611 ps
CPU time 1.18 seconds
Started Jun 05 04:22:09 PM PDT 24
Finished Jun 05 04:22:11 PM PDT 24
Peak memory 200084 kb
Host smart-6202b588-f373-43c6-ad2f-13be79eb8432
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527861605 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.3527861605
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.2751537896
Short name T323
Test name
Test status
Simulation time 165290839151 ps
CPU time 464.5 seconds
Started Jun 05 04:22:15 PM PDT 24
Finished Jun 05 04:30:00 PM PDT 24
Peak memory 199804 kb
Host smart-280a7d0a-24ad-460b-b2ef-967a7a8303e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751537896 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.2751537896
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1275441172
Short name T359
Test name
Test status
Simulation time 69276653393 ps
CPU time 72.39 seconds
Started Jun 05 04:22:12 PM PDT 24
Finished Jun 05 04:23:25 PM PDT 24
Peak memory 200168 kb
Host smart-af52e5fc-5795-4cf1-b0cb-61ac6016e68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275441172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1275441172
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2720680942
Short name T469
Test name
Test status
Simulation time 15551036 ps
CPU time 0.62 seconds
Started Jun 05 04:22:20 PM PDT 24
Finished Jun 05 04:22:22 PM PDT 24
Peak memory 196700 kb
Host smart-c4fa61d7-3bac-4119-aaed-11ce33d6f236
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720680942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2720680942
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1644284600
Short name T205
Test name
Test status
Simulation time 474543573 ps
CPU time 25.7 seconds
Started Jun 05 04:22:21 PM PDT 24
Finished Jun 05 04:22:47 PM PDT 24
Peak memory 200124 kb
Host smart-0f7bf17f-f76c-42c5-810c-1e199c29cfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644284600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1644284600
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.4288000594
Short name T391
Test name
Test status
Simulation time 749806172 ps
CPU time 125.67 seconds
Started Jun 05 04:22:18 PM PDT 24
Finished Jun 05 04:24:25 PM PDT 24
Peak memory 466652 kb
Host smart-19d4dcf9-e9bd-4952-b38f-2864d6351c9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4288000594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.4288000594
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.4223733601
Short name T443
Test name
Test status
Simulation time 2901089679 ps
CPU time 51.78 seconds
Started Jun 05 04:22:20 PM PDT 24
Finished Jun 05 04:23:14 PM PDT 24
Peak memory 200164 kb
Host smart-94862b98-3c16-473b-84c5-2894f2113034
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223733601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.4223733601
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.161545179
Short name T553
Test name
Test status
Simulation time 19296108252 ps
CPU time 68.3 seconds
Started Jun 05 04:22:20 PM PDT 24
Finished Jun 05 04:23:30 PM PDT 24
Peak memory 200104 kb
Host smart-0d6936c2-f228-41c5-89dd-7b32226fd9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161545179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.161545179
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1740279104
Short name T406
Test name
Test status
Simulation time 16781586 ps
CPU time 0.83 seconds
Started Jun 05 04:22:20 PM PDT 24
Finished Jun 05 04:22:22 PM PDT 24
Peak memory 198532 kb
Host smart-50cee7b3-be8b-408e-b550-aef42a780c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740279104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1740279104
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.306677919
Short name T224
Test name
Test status
Simulation time 30656486211 ps
CPU time 1230.14 seconds
Started Jun 05 04:22:19 PM PDT 24
Finished Jun 05 04:42:50 PM PDT 24
Peak memory 728216 kb
Host smart-470e12fa-2458-4b1e-85a0-99a4760f9074
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306677919 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.306677919
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.1484774888
Short name T559
Test name
Test status
Simulation time 32507204 ps
CPU time 1.19 seconds
Started Jun 05 04:22:25 PM PDT 24
Finished Jun 05 04:22:27 PM PDT 24
Peak memory 200108 kb
Host smart-550a2549-cc57-40d6-a95e-39ce6025f101
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484774888 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.1484774888
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.4004369283
Short name T265
Test name
Test status
Simulation time 160870322692 ps
CPU time 568.46 seconds
Started Jun 05 04:22:18 PM PDT 24
Finished Jun 05 04:31:48 PM PDT 24
Peak memory 200072 kb
Host smart-2ff5d9d7-116f-4a90-be67-c1c8501b2d9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004369283 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.4004369283
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3563523102
Short name T548
Test name
Test status
Simulation time 857676372 ps
CPU time 34.11 seconds
Started Jun 05 04:22:20 PM PDT 24
Finished Jun 05 04:22:55 PM PDT 24
Peak memory 200052 kb
Host smart-cee3bd1a-d884-4b1f-bc2d-1e26d4b4d233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563523102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3563523102
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.3936612102
Short name T214
Test name
Test status
Simulation time 43241660 ps
CPU time 0.59 seconds
Started Jun 05 04:22:19 PM PDT 24
Finished Jun 05 04:22:21 PM PDT 24
Peak memory 194972 kb
Host smart-f7424b69-419a-4b1f-8bb8-f291938f8c5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936612102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3936612102
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.2416002329
Short name T189
Test name
Test status
Simulation time 2068407236 ps
CPU time 26.15 seconds
Started Jun 05 04:22:17 PM PDT 24
Finished Jun 05 04:22:44 PM PDT 24
Peak memory 232648 kb
Host smart-20f838e4-b3c9-4e0d-b705-37dba35ad69c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2416002329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2416002329
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.478076040
Short name T364
Test name
Test status
Simulation time 283761011 ps
CPU time 15.56 seconds
Started Jun 05 04:22:20 PM PDT 24
Finished Jun 05 04:22:36 PM PDT 24
Peak memory 200160 kb
Host smart-40f4caf5-f8df-408e-ade4-3f396cc5d9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478076040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.478076040
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2533359680
Short name T550
Test name
Test status
Simulation time 7103728137 ps
CPU time 672.96 seconds
Started Jun 05 04:22:18 PM PDT 24
Finished Jun 05 04:33:32 PM PDT 24
Peak memory 729056 kb
Host smart-e4657108-c816-496c-bb49-59ef63ac1ce0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2533359680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2533359680
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1280739679
Short name T373
Test name
Test status
Simulation time 15506904357 ps
CPU time 69.5 seconds
Started Jun 05 04:22:19 PM PDT 24
Finished Jun 05 04:23:29 PM PDT 24
Peak memory 200116 kb
Host smart-ab43f07e-c8fc-4992-bb4e-0e44087c933d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280739679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1280739679
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3484007218
Short name T445
Test name
Test status
Simulation time 2052541091 ps
CPU time 29.37 seconds
Started Jun 05 04:22:20 PM PDT 24
Finished Jun 05 04:22:51 PM PDT 24
Peak memory 200080 kb
Host smart-910699b9-846a-4657-8d44-2ce48a9be5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484007218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3484007218
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.159964033
Short name T535
Test name
Test status
Simulation time 2043131378 ps
CPU time 11.02 seconds
Started Jun 05 04:22:20 PM PDT 24
Finished Jun 05 04:22:33 PM PDT 24
Peak memory 200084 kb
Host smart-52b2d4ce-9d77-4f72-8efb-575df43d8184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159964033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.159964033
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.925652848
Short name T236
Test name
Test status
Simulation time 1371117654 ps
CPU time 71.87 seconds
Started Jun 05 04:22:20 PM PDT 24
Finished Jun 05 04:23:33 PM PDT 24
Peak memory 200084 kb
Host smart-59c9ba85-0200-4c2f-85ab-82f9503b4bb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925652848 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.925652848
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.3596844451
Short name T529
Test name
Test status
Simulation time 83506029 ps
CPU time 1.37 seconds
Started Jun 05 04:22:20 PM PDT 24
Finished Jun 05 04:22:23 PM PDT 24
Peak memory 200148 kb
Host smart-19f648fe-d78e-424b-936e-d8163d8b30b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596844451 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.3596844451
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.1095428788
Short name T333
Test name
Test status
Simulation time 7710300256 ps
CPU time 419.58 seconds
Started Jun 05 04:22:20 PM PDT 24
Finished Jun 05 04:29:21 PM PDT 24
Peak memory 200124 kb
Host smart-b96d7238-a964-4ba1-82cf-89b611fd4e4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095428788 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.1095428788
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.1070147992
Short name T479
Test name
Test status
Simulation time 10357296203 ps
CPU time 93.79 seconds
Started Jun 05 04:22:18 PM PDT 24
Finished Jun 05 04:23:53 PM PDT 24
Peak memory 200128 kb
Host smart-3fb2e93c-019a-4a19-ae14-0c91b3c91e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070147992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1070147992
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2777133911
Short name T248
Test name
Test status
Simulation time 14714894 ps
CPU time 0.57 seconds
Started Jun 05 04:22:34 PM PDT 24
Finished Jun 05 04:22:35 PM PDT 24
Peak memory 194936 kb
Host smart-d29784ba-661b-4c29-ad95-6369460238e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777133911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2777133911
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3739637483
Short name T43
Test name
Test status
Simulation time 857878229 ps
CPU time 46.87 seconds
Started Jun 05 04:22:18 PM PDT 24
Finished Jun 05 04:23:06 PM PDT 24
Peak memory 232676 kb
Host smart-a74b1341-8603-4027-82a5-402dbab3faf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3739637483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3739637483
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1824125811
Short name T518
Test name
Test status
Simulation time 13670893362 ps
CPU time 39.23 seconds
Started Jun 05 04:22:25 PM PDT 24
Finished Jun 05 04:23:05 PM PDT 24
Peak memory 200148 kb
Host smart-308ef209-4bff-456f-9344-fe640cb48c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824125811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1824125811
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3137900477
Short name T340
Test name
Test status
Simulation time 2705619269 ps
CPU time 560.7 seconds
Started Jun 05 04:22:20 PM PDT 24
Finished Jun 05 04:31:42 PM PDT 24
Peak memory 734964 kb
Host smart-74021bfd-d292-494a-bb52-c9130663b4ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3137900477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3137900477
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.2074245971
Short name T540
Test name
Test status
Simulation time 31042518358 ps
CPU time 124.14 seconds
Started Jun 05 04:22:20 PM PDT 24
Finished Jun 05 04:24:25 PM PDT 24
Peak memory 200160 kb
Host smart-b53c7e30-b8fe-4e8c-b5d3-0934afd9018d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074245971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2074245971
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.2817085387
Short name T160
Test name
Test status
Simulation time 4285052828 ps
CPU time 76.45 seconds
Started Jun 05 04:22:18 PM PDT 24
Finished Jun 05 04:23:36 PM PDT 24
Peak memory 200196 kb
Host smart-ef345f72-f698-4c42-ae9c-aeb487cbf15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817085387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.2817085387
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1604877799
Short name T332
Test name
Test status
Simulation time 30131572 ps
CPU time 0.88 seconds
Started Jun 05 04:22:21 PM PDT 24
Finished Jun 05 04:22:23 PM PDT 24
Peak memory 198952 kb
Host smart-f7c9a5a2-ce32-45df-8943-6aabb91e6e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604877799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1604877799
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.1107344840
Short name T430
Test name
Test status
Simulation time 50975014520 ps
CPU time 1311.52 seconds
Started Jun 05 04:22:20 PM PDT 24
Finished Jun 05 04:44:13 PM PDT 24
Peak memory 649680 kb
Host smart-11c5a3a6-3701-4717-a323-977d6d6d1cef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107344840 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1107344840
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_stress_all_with_rand_reset.3213100727
Short name T9
Test name
Test status
Simulation time 17255744624 ps
CPU time 3473.36 seconds
Started Jun 05 04:22:30 PM PDT 24
Finished Jun 05 05:20:24 PM PDT 24
Peak memory 846892 kb
Host smart-80738da3-6dd4-4434-a68e-6541dd93cd43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3213100727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all_with_rand_reset.3213100727
Directory /workspace/34.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.2463649896
Short name T58
Test name
Test status
Simulation time 30211333 ps
CPU time 0.99 seconds
Started Jun 05 04:22:18 PM PDT 24
Finished Jun 05 04:22:20 PM PDT 24
Peak memory 199948 kb
Host smart-7b881acb-1881-4eb4-9b9f-c7db52e151a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463649896 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.2463649896
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.1211471706
Short name T46
Test name
Test status
Simulation time 100449021858 ps
CPU time 492.4 seconds
Started Jun 05 04:22:19 PM PDT 24
Finished Jun 05 04:30:33 PM PDT 24
Peak memory 200124 kb
Host smart-81d579fa-ab50-4859-9a83-16f05c8eec49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211471706 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.1211471706
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1671118610
Short name T230
Test name
Test status
Simulation time 874288381 ps
CPU time 44.61 seconds
Started Jun 05 04:22:20 PM PDT 24
Finished Jun 05 04:23:05 PM PDT 24
Peak memory 200072 kb
Host smart-a05a9cff-6acd-4204-a8f5-c33fde48ff07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671118610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1671118610
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.1564127837
Short name T207
Test name
Test status
Simulation time 11904713 ps
CPU time 0.6 seconds
Started Jun 05 04:22:31 PM PDT 24
Finished Jun 05 04:22:33 PM PDT 24
Peak memory 195964 kb
Host smart-0c963a9f-cd64-47a8-868e-cdc245a8b962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564127837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.1564127837
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.4059716128
Short name T190
Test name
Test status
Simulation time 3639977057 ps
CPU time 48.13 seconds
Started Jun 05 04:22:32 PM PDT 24
Finished Jun 05 04:23:21 PM PDT 24
Peak memory 233944 kb
Host smart-51a8fa62-18ea-4e86-a961-34205c47f527
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4059716128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.4059716128
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3482095353
Short name T578
Test name
Test status
Simulation time 792072347 ps
CPU time 3.55 seconds
Started Jun 05 04:22:31 PM PDT 24
Finished Jun 05 04:22:36 PM PDT 24
Peak memory 200024 kb
Host smart-76dd5ce3-b690-4863-a9a6-77cf4611a415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482095353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3482095353
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2694142060
Short name T436
Test name
Test status
Simulation time 2322475172 ps
CPU time 345.25 seconds
Started Jun 05 04:22:30 PM PDT 24
Finished Jun 05 04:28:16 PM PDT 24
Peak memory 667252 kb
Host smart-550dfffe-96ba-4ec9-bb4a-6a767c751001
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2694142060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2694142060
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.2040369280
Short name T563
Test name
Test status
Simulation time 5773610032 ps
CPU time 96.45 seconds
Started Jun 05 04:22:32 PM PDT 24
Finished Jun 05 04:24:10 PM PDT 24
Peak memory 200164 kb
Host smart-b646186f-eeef-4c95-b1be-6d3f95fadafc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040369280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2040369280
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.886800647
Short name T444
Test name
Test status
Simulation time 1260144152 ps
CPU time 22.72 seconds
Started Jun 05 04:22:32 PM PDT 24
Finished Jun 05 04:22:55 PM PDT 24
Peak memory 200180 kb
Host smart-3c6e04e6-3ee8-4d9e-9c0e-29c0795d7adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886800647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.886800647
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2184941224
Short name T558
Test name
Test status
Simulation time 406915206 ps
CPU time 3.33 seconds
Started Jun 05 04:22:31 PM PDT 24
Finished Jun 05 04:22:36 PM PDT 24
Peak memory 199832 kb
Host smart-a4b0636c-084c-4d07-aa8c-dcc95141a448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184941224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2184941224
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.4055798333
Short name T238
Test name
Test status
Simulation time 74219007465 ps
CPU time 1219.71 seconds
Started Jun 05 04:22:31 PM PDT 24
Finished Jun 05 04:42:51 PM PDT 24
Peak memory 511948 kb
Host smart-69add8fa-5297-40b2-b256-f3c7506d3641
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055798333 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.4055798333
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.1699389142
Short name T206
Test name
Test status
Simulation time 31261842 ps
CPU time 1.13 seconds
Started Jun 05 04:22:31 PM PDT 24
Finished Jun 05 04:22:33 PM PDT 24
Peak memory 199924 kb
Host smart-788687af-4ae4-4c62-ab32-e808835b70e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699389142 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.1699389142
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.229273622
Short name T169
Test name
Test status
Simulation time 8015708967 ps
CPU time 469.49 seconds
Started Jun 05 04:22:31 PM PDT 24
Finished Jun 05 04:30:22 PM PDT 24
Peak memory 199996 kb
Host smart-212d54a2-ea39-4434-869b-b396550290f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229273622 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.229273622
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.3546405484
Short name T329
Test name
Test status
Simulation time 4249974318 ps
CPU time 39.71 seconds
Started Jun 05 04:22:32 PM PDT 24
Finished Jun 05 04:23:13 PM PDT 24
Peak memory 200168 kb
Host smart-f8ee0f0a-0394-4301-b49d-f18278f6c7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546405484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3546405484
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.4053675252
Short name T315
Test name
Test status
Simulation time 25383369 ps
CPU time 0.59 seconds
Started Jun 05 04:22:31 PM PDT 24
Finished Jun 05 04:22:32 PM PDT 24
Peak memory 195960 kb
Host smart-c683d0b2-b3fb-461b-8721-31eef527210a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053675252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.4053675252
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.57832838
Short name T591
Test name
Test status
Simulation time 676586094 ps
CPU time 33.9 seconds
Started Jun 05 04:22:33 PM PDT 24
Finished Jun 05 04:23:08 PM PDT 24
Peak memory 232900 kb
Host smart-df2e585e-3532-4672-aa52-48d7cb0b8cb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=57832838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.57832838
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1944736240
Short name T564
Test name
Test status
Simulation time 358191286 ps
CPU time 5.44 seconds
Started Jun 05 04:22:31 PM PDT 24
Finished Jun 05 04:22:38 PM PDT 24
Peak memory 200064 kb
Host smart-98635223-16e0-48f0-ac13-e8f3b6fb9702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944736240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1944736240
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.800324548
Short name T184
Test name
Test status
Simulation time 469246128 ps
CPU time 24.69 seconds
Started Jun 05 04:22:32 PM PDT 24
Finished Jun 05 04:22:58 PM PDT 24
Peak memory 241552 kb
Host smart-563cdc36-04bb-4d5a-97d1-43faba321c2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=800324548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.800324548
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3969671249
Short name T284
Test name
Test status
Simulation time 27168337134 ps
CPU time 138.02 seconds
Started Jun 05 04:22:31 PM PDT 24
Finished Jun 05 04:24:49 PM PDT 24
Peak memory 200168 kb
Host smart-dc0db4f7-4fc7-4a50-8a5e-cae6c10b39c7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969671249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3969671249
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.1719125510
Short name T442
Test name
Test status
Simulation time 2201442865 ps
CPU time 62.44 seconds
Started Jun 05 04:22:34 PM PDT 24
Finished Jun 05 04:23:37 PM PDT 24
Peak memory 200168 kb
Host smart-bb0db478-93bd-4b0d-8066-4b56126d2d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719125510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1719125510
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.1661943252
Short name T425
Test name
Test status
Simulation time 1815628293 ps
CPU time 8.6 seconds
Started Jun 05 04:22:33 PM PDT 24
Finished Jun 05 04:22:42 PM PDT 24
Peak memory 200072 kb
Host smart-e4cc46ae-b670-4cfb-8495-3579173f14cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661943252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1661943252
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.3725598235
Short name T38
Test name
Test status
Simulation time 551163268345 ps
CPU time 4448.08 seconds
Started Jun 05 04:22:32 PM PDT 24
Finished Jun 05 05:36:42 PM PDT 24
Peak memory 849020 kb
Host smart-5a4c0792-18e1-4c56-ac77-5cc1b6d5617a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725598235 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.3725598235
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.2421801062
Short name T500
Test name
Test status
Simulation time 102346552 ps
CPU time 1.12 seconds
Started Jun 05 04:22:31 PM PDT 24
Finished Jun 05 04:22:33 PM PDT 24
Peak memory 200148 kb
Host smart-556e9f02-9567-4375-a8a5-3e88de6a2a6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421801062 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.2421801062
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.2878005694
Short name T227
Test name
Test status
Simulation time 26795064996 ps
CPU time 442.14 seconds
Started Jun 05 04:22:31 PM PDT 24
Finished Jun 05 04:29:54 PM PDT 24
Peak memory 200140 kb
Host smart-d19e5579-227f-475d-bf83-28ee6ecf21f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878005694 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.2878005694
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1700156688
Short name T316
Test name
Test status
Simulation time 1914310607 ps
CPU time 24.83 seconds
Started Jun 05 04:22:30 PM PDT 24
Finished Jun 05 04:22:56 PM PDT 24
Peak memory 200056 kb
Host smart-29f48b51-963f-44a7-b19f-bbe78975d8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700156688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1700156688
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.2050179999
Short name T586
Test name
Test status
Simulation time 39979198 ps
CPU time 0.56 seconds
Started Jun 05 04:22:39 PM PDT 24
Finished Jun 05 04:22:40 PM PDT 24
Peak memory 196000 kb
Host smart-b442eecc-2ba7-4c6f-bfe4-8dbc28cd4504
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050179999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2050179999
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.52669753
Short name T584
Test name
Test status
Simulation time 3937077722 ps
CPU time 44.98 seconds
Started Jun 05 04:22:31 PM PDT 24
Finished Jun 05 04:23:17 PM PDT 24
Peak memory 217620 kb
Host smart-f99da866-50ae-4c2a-9d6a-53c49a903411
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=52669753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.52669753
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.476951783
Short name T178
Test name
Test status
Simulation time 8548029702 ps
CPU time 59.97 seconds
Started Jun 05 04:22:31 PM PDT 24
Finished Jun 05 04:23:32 PM PDT 24
Peak memory 200144 kb
Host smart-5776c4ef-a744-456f-9f0c-75d93c46c175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476951783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.476951783
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2445498344
Short name T566
Test name
Test status
Simulation time 8515457814 ps
CPU time 432.33 seconds
Started Jun 05 04:22:31 PM PDT 24
Finished Jun 05 04:29:44 PM PDT 24
Peak memory 684648 kb
Host smart-1d85f218-459c-4b4b-96bf-e10025f001c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2445498344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2445498344
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1851205653
Short name T249
Test name
Test status
Simulation time 14621354837 ps
CPU time 52.21 seconds
Started Jun 05 04:22:31 PM PDT 24
Finished Jun 05 04:23:25 PM PDT 24
Peak memory 200168 kb
Host smart-4a1c8657-3c15-4a1b-9bbd-b8bb1682e3de
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851205653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1851205653
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.885603183
Short name T327
Test name
Test status
Simulation time 260388195 ps
CPU time 4.58 seconds
Started Jun 05 04:22:31 PM PDT 24
Finished Jun 05 04:22:36 PM PDT 24
Peak memory 200076 kb
Host smart-a162ef58-6ac8-4e9f-9286-fe7ccd150ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885603183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.885603183
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.1732989578
Short name T220
Test name
Test status
Simulation time 1448536064 ps
CPU time 7.36 seconds
Started Jun 05 04:22:31 PM PDT 24
Finished Jun 05 04:22:39 PM PDT 24
Peak memory 200176 kb
Host smart-99a612ed-9023-43c1-ba85-c2188090d9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732989578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1732989578
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2975208111
Short name T24
Test name
Test status
Simulation time 109067941017 ps
CPU time 2162.95 seconds
Started Jun 05 04:22:38 PM PDT 24
Finished Jun 05 04:58:42 PM PDT 24
Peak memory 672516 kb
Host smart-f609ef0f-97eb-40d0-84e7-a71191d26932
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975208111 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2975208111
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.140937060
Short name T78
Test name
Test status
Simulation time 188971552 ps
CPU time 1.05 seconds
Started Jun 05 04:22:38 PM PDT 24
Finished Jun 05 04:22:40 PM PDT 24
Peak memory 199892 kb
Host smart-b1b5fd0c-d508-490d-b746-0147784e48fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140937060 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_hmac_vectors.140937060
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.3368639889
Short name T392
Test name
Test status
Simulation time 33918238443 ps
CPU time 533.35 seconds
Started Jun 05 04:22:40 PM PDT 24
Finished Jun 05 04:31:34 PM PDT 24
Peak memory 200140 kb
Host smart-c4d5a51e-f9ad-46c3-9464-0d106e7f5fa6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368639889 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.3368639889
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.783709658
Short name T158
Test name
Test status
Simulation time 6590938315 ps
CPU time 30.8 seconds
Started Jun 05 04:22:31 PM PDT 24
Finished Jun 05 04:23:03 PM PDT 24
Peak memory 200200 kb
Host smart-a952454a-6c37-4542-8385-02ed54963f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783709658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.783709658
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.4203443062
Short name T21
Test name
Test status
Simulation time 12907786 ps
CPU time 0.58 seconds
Started Jun 05 04:22:49 PM PDT 24
Finished Jun 05 04:22:50 PM PDT 24
Peak memory 195140 kb
Host smart-b05e5685-99e3-41e5-880d-999ab699cb62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203443062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.4203443062
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.4179917403
Short name T328
Test name
Test status
Simulation time 520090571 ps
CPU time 26.04 seconds
Started Jun 05 04:22:40 PM PDT 24
Finished Jun 05 04:23:06 PM PDT 24
Peak memory 208300 kb
Host smart-601977d7-e762-4a0a-8b5d-52c9db6e581c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4179917403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.4179917403
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1620037599
Short name T229
Test name
Test status
Simulation time 307888063 ps
CPU time 4.18 seconds
Started Jun 05 04:22:40 PM PDT 24
Finished Jun 05 04:22:45 PM PDT 24
Peak memory 200132 kb
Host smart-6a1d1418-b8bc-4f43-8348-f3cc3add2c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620037599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1620037599
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.1222713024
Short name T146
Test name
Test status
Simulation time 802657799 ps
CPU time 187.57 seconds
Started Jun 05 04:22:42 PM PDT 24
Finished Jun 05 04:25:50 PM PDT 24
Peak memory 620392 kb
Host smart-3dd55c20-681b-49e5-b403-5fb58c028f01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1222713024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.1222713024
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2684854145
Short name T260
Test name
Test status
Simulation time 3936283857 ps
CPU time 109.85 seconds
Started Jun 05 04:22:42 PM PDT 24
Finished Jun 05 04:24:32 PM PDT 24
Peak memory 200104 kb
Host smart-bf2ee882-7ee3-4904-80c0-593d43ac1160
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684854145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2684854145
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.39378887
Short name T45
Test name
Test status
Simulation time 11505943296 ps
CPU time 120.78 seconds
Started Jun 05 04:22:42 PM PDT 24
Finished Jun 05 04:24:43 PM PDT 24
Peak memory 200104 kb
Host smart-be9a7fe5-0db1-491c-b8b3-8aa8595d57e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39378887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.39378887
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.299585233
Short name T462
Test name
Test status
Simulation time 337288673 ps
CPU time 2.5 seconds
Started Jun 05 04:22:40 PM PDT 24
Finished Jun 05 04:22:43 PM PDT 24
Peak memory 200100 kb
Host smart-ad1b2508-6fa2-47a2-915c-59093e999614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299585233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.299585233
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.422943074
Short name T507
Test name
Test status
Simulation time 32408399236 ps
CPU time 43.76 seconds
Started Jun 05 04:22:39 PM PDT 24
Finished Jun 05 04:23:24 PM PDT 24
Peak memory 200152 kb
Host smart-e04bb5a5-18e4-4fe7-a0f8-7878f9bc4ff5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422943074 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.422943074
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.503736464
Short name T478
Test name
Test status
Simulation time 303022520 ps
CPU time 1.46 seconds
Started Jun 05 04:22:49 PM PDT 24
Finished Jun 05 04:22:52 PM PDT 24
Peak memory 200168 kb
Host smart-c9e6402f-e3b7-4017-af42-e004e636fda5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503736464 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_test_hmac_vectors.503736464
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.3226012836
Short name T204
Test name
Test status
Simulation time 146971124986 ps
CPU time 508.85 seconds
Started Jun 05 04:22:40 PM PDT 24
Finished Jun 05 04:31:10 PM PDT 24
Peak memory 200124 kb
Host smart-3bfc7366-9615-4a6f-a956-d2fd5c0757d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226012836 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.3226012836
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.2502822071
Short name T282
Test name
Test status
Simulation time 1678628531 ps
CPU time 24.36 seconds
Started Jun 05 04:22:40 PM PDT 24
Finished Jun 05 04:23:05 PM PDT 24
Peak memory 200100 kb
Host smart-4e28121f-57b8-46f8-a56f-434f3be48b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502822071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2502822071
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.894688948
Short name T417
Test name
Test status
Simulation time 71740546 ps
CPU time 0.59 seconds
Started Jun 05 04:22:40 PM PDT 24
Finished Jun 05 04:22:41 PM PDT 24
Peak memory 195608 kb
Host smart-cd1ab0ad-a17d-4621-ab9d-1ee514706994
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894688948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.894688948
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3102105888
Short name T277
Test name
Test status
Simulation time 1082660794 ps
CPU time 49.54 seconds
Started Jun 05 04:22:43 PM PDT 24
Finished Jun 05 04:23:33 PM PDT 24
Peak memory 215508 kb
Host smart-90e37f76-5197-4d95-b5f2-63a448b82882
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3102105888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3102105888
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.58220027
Short name T151
Test name
Test status
Simulation time 436788068 ps
CPU time 8.46 seconds
Started Jun 05 04:22:43 PM PDT 24
Finished Jun 05 04:22:52 PM PDT 24
Peak memory 200116 kb
Host smart-7641e2e4-59d4-4fc8-8219-c1d9b3a7f5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58220027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.58220027
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3452941245
Short name T437
Test name
Test status
Simulation time 5102164506 ps
CPU time 670.9 seconds
Started Jun 05 04:22:40 PM PDT 24
Finished Jun 05 04:33:52 PM PDT 24
Peak memory 671248 kb
Host smart-cd0d994e-28ce-40ec-a1cd-6bf138aa0fd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3452941245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3452941245
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3557416765
Short name T435
Test name
Test status
Simulation time 13104841008 ps
CPU time 121.63 seconds
Started Jun 05 04:22:47 PM PDT 24
Finished Jun 05 04:24:49 PM PDT 24
Peak memory 200120 kb
Host smart-6108c0bd-113a-4f2d-8039-2c3fb7933293
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557416765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3557416765
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.4226491459
Short name T119
Test name
Test status
Simulation time 200012085 ps
CPU time 3.56 seconds
Started Jun 05 04:22:43 PM PDT 24
Finished Jun 05 04:22:47 PM PDT 24
Peak memory 200104 kb
Host smart-b9d48e79-d2fb-4f55-9f55-4521bcbfebf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226491459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.4226491459
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1056190028
Short name T525
Test name
Test status
Simulation time 1043406611 ps
CPU time 5.88 seconds
Started Jun 05 04:22:41 PM PDT 24
Finished Jun 05 04:22:47 PM PDT 24
Peak memory 200084 kb
Host smart-149d3d3b-cbba-4109-88bd-403f9b81e96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056190028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1056190028
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.2081714474
Short name T59
Test name
Test status
Simulation time 147095273 ps
CPU time 1.11 seconds
Started Jun 05 04:22:48 PM PDT 24
Finished Jun 05 04:22:50 PM PDT 24
Peak memory 200060 kb
Host smart-c958ed43-c201-45bf-acf3-d65b77237d88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081714474 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.2081714474
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.3478983917
Short name T378
Test name
Test status
Simulation time 27776169438 ps
CPU time 479.07 seconds
Started Jun 05 04:22:42 PM PDT 24
Finished Jun 05 04:30:41 PM PDT 24
Peak memory 200016 kb
Host smart-47d89ea8-d308-4265-8e7b-87a9149779dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478983917 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.3478983917
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.950443977
Short name T484
Test name
Test status
Simulation time 4086679472 ps
CPU time 33.39 seconds
Started Jun 05 04:22:48 PM PDT 24
Finished Jun 05 04:23:22 PM PDT 24
Peak memory 200168 kb
Host smart-6358759b-0841-49d1-b258-c18a9478a0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950443977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.950443977
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2045646672
Short name T217
Test name
Test status
Simulation time 144152716 ps
CPU time 0.59 seconds
Started Jun 05 04:21:06 PM PDT 24
Finished Jun 05 04:21:08 PM PDT 24
Peak memory 196680 kb
Host smart-f5fa5e42-db37-4b5e-9e2f-5911dac7f60c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045646672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2045646672
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.893255908
Short name T393
Test name
Test status
Simulation time 3519938977 ps
CPU time 43.42 seconds
Started Jun 05 04:21:04 PM PDT 24
Finished Jun 05 04:21:49 PM PDT 24
Peak memory 210392 kb
Host smart-229280b5-bab7-4186-be33-d4c8ed99ef72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=893255908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.893255908
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3103461169
Short name T283
Test name
Test status
Simulation time 1426716314 ps
CPU time 21.57 seconds
Started Jun 05 04:21:04 PM PDT 24
Finished Jun 05 04:21:26 PM PDT 24
Peak memory 200124 kb
Host smart-fd03ba11-fb10-492e-94ce-90e0232400a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103461169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3103461169
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2033133458
Short name T221
Test name
Test status
Simulation time 53885311653 ps
CPU time 842.17 seconds
Started Jun 05 04:21:04 PM PDT 24
Finished Jun 05 04:35:08 PM PDT 24
Peak memory 740060 kb
Host smart-ea3d8bf6-d39f-45c6-8ac8-244685f35295
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2033133458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2033133458
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1407187142
Short name T273
Test name
Test status
Simulation time 3470495949 ps
CPU time 17.07 seconds
Started Jun 05 04:21:06 PM PDT 24
Finished Jun 05 04:21:23 PM PDT 24
Peak memory 200112 kb
Host smart-a398aaaa-eb53-432d-90ca-d204b5363a07
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407187142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1407187142
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1826252635
Short name T314
Test name
Test status
Simulation time 21508687792 ps
CPU time 111.58 seconds
Started Jun 05 04:21:05 PM PDT 24
Finished Jun 05 04:22:57 PM PDT 24
Peak memory 200116 kb
Host smart-b48d353b-6311-427a-8645-6b707dd498a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826252635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1826252635
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2579707848
Short name T31
Test name
Test status
Simulation time 494613342 ps
CPU time 1.25 seconds
Started Jun 05 04:21:06 PM PDT 24
Finished Jun 05 04:21:08 PM PDT 24
Peak memory 219488 kb
Host smart-8f1b55c2-086a-4cb8-8901-20a23673a384
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579707848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2579707848
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.3146555836
Short name T159
Test name
Test status
Simulation time 709068758 ps
CPU time 5.79 seconds
Started Jun 05 04:21:05 PM PDT 24
Finished Jun 05 04:21:11 PM PDT 24
Peak memory 200092 kb
Host smart-7bf8e4d8-9bb9-4054-9384-e252256f6b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146555836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.3146555836
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1478065009
Short name T368
Test name
Test status
Simulation time 18444694424 ps
CPU time 1591.43 seconds
Started Jun 05 04:21:04 PM PDT 24
Finished Jun 05 04:47:37 PM PDT 24
Peak memory 778616 kb
Host smart-5ae7e8f1-1258-4167-8cf3-ec3cde4ab3fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478065009 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1478065009
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.4101337380
Short name T202
Test name
Test status
Simulation time 253832366 ps
CPU time 1.34 seconds
Started Jun 05 04:21:07 PM PDT 24
Finished Jun 05 04:21:09 PM PDT 24
Peak memory 199972 kb
Host smart-414aa3b4-690c-4f79-9d86-3a36e2e4b4aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101337380 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.4101337380
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.283974383
Short name T225
Test name
Test status
Simulation time 230462744264 ps
CPU time 458.95 seconds
Started Jun 05 04:21:07 PM PDT 24
Finished Jun 05 04:28:47 PM PDT 24
Peak memory 200072 kb
Host smart-2f8ec237-f2d7-42df-b29f-82faeb166350
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283974383 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.283974383
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.553842028
Short name T320
Test name
Test status
Simulation time 1350141528 ps
CPU time 51.96 seconds
Started Jun 05 04:21:07 PM PDT 24
Finished Jun 05 04:21:59 PM PDT 24
Peak memory 200100 kb
Host smart-5cd3dbdb-0f19-43f1-bdf7-9602b05383f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553842028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.553842028
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3077120995
Short name T487
Test name
Test status
Simulation time 46267716 ps
CPU time 0.59 seconds
Started Jun 05 04:22:40 PM PDT 24
Finished Jun 05 04:22:41 PM PDT 24
Peak memory 195920 kb
Host smart-0f44dec9-1d1b-460e-8722-9fc823fb2211
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077120995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3077120995
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.3464353607
Short name T199
Test name
Test status
Simulation time 371453370 ps
CPU time 5.23 seconds
Started Jun 05 04:22:49 PM PDT 24
Finished Jun 05 04:22:55 PM PDT 24
Peak memory 200296 kb
Host smart-ca12cfc2-72c2-474d-be32-c9f3c44d7833
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3464353607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3464353607
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3406300467
Short name T226
Test name
Test status
Simulation time 3629334103 ps
CPU time 37.91 seconds
Started Jun 05 04:22:43 PM PDT 24
Finished Jun 05 04:23:21 PM PDT 24
Peak memory 200144 kb
Host smart-571808a1-00c0-4566-8ec0-7e3d7c08824a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406300467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3406300467
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.4097967931
Short name T153
Test name
Test status
Simulation time 1145800228 ps
CPU time 121.23 seconds
Started Jun 05 04:22:42 PM PDT 24
Finished Jun 05 04:24:43 PM PDT 24
Peak memory 435756 kb
Host smart-d25d9432-032b-4ca7-9d07-ba9509630fd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4097967931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.4097967931
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.3527033107
Short name T351
Test name
Test status
Simulation time 921442506 ps
CPU time 5.63 seconds
Started Jun 05 04:22:43 PM PDT 24
Finished Jun 05 04:22:50 PM PDT 24
Peak memory 200144 kb
Host smart-0d6dc2cc-6f14-4855-8847-49b74f01a349
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527033107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3527033107
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.643024104
Short name T438
Test name
Test status
Simulation time 148597948 ps
CPU time 9.24 seconds
Started Jun 05 04:22:42 PM PDT 24
Finished Jun 05 04:22:52 PM PDT 24
Peak memory 199976 kb
Host smart-061111f7-5f5b-441b-a481-5dc55beabe45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643024104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.643024104
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.3795831757
Short name T402
Test name
Test status
Simulation time 3094551976 ps
CPU time 11.7 seconds
Started Jun 05 04:22:50 PM PDT 24
Finished Jun 05 04:23:02 PM PDT 24
Peak memory 200332 kb
Host smart-e2d56133-a716-450c-bac4-4f988180a5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795831757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.3795831757
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1326853564
Short name T41
Test name
Test status
Simulation time 13434148505 ps
CPU time 385.43 seconds
Started Jun 05 04:22:39 PM PDT 24
Finished Jun 05 04:29:05 PM PDT 24
Peak memory 208276 kb
Host smart-0feeefa7-0b56-48a0-b3a9-253f8dc44141
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326853564 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1326853564
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.4181164075
Short name T466
Test name
Test status
Simulation time 35269650 ps
CPU time 1.4 seconds
Started Jun 05 04:22:46 PM PDT 24
Finished Jun 05 04:22:48 PM PDT 24
Peak memory 200048 kb
Host smart-990ce72f-bda0-4445-a567-07575e6b48f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181164075 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.4181164075
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.614419544
Short name T382
Test name
Test status
Simulation time 9138591435 ps
CPU time 442.99 seconds
Started Jun 05 04:22:42 PM PDT 24
Finished Jun 05 04:30:05 PM PDT 24
Peak memory 199996 kb
Host smart-8532407c-652f-4b9d-8e74-464ca589f54f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614419544 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.614419544
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.743599222
Short name T128
Test name
Test status
Simulation time 5687904797 ps
CPU time 52.04 seconds
Started Jun 05 04:22:48 PM PDT 24
Finished Jun 05 04:23:41 PM PDT 24
Peak memory 200288 kb
Host smart-db6b67ee-c85a-4794-b9c8-d24da0df2710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743599222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.743599222
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1554111540
Short name T370
Test name
Test status
Simulation time 11789856 ps
CPU time 0.6 seconds
Started Jun 05 04:22:45 PM PDT 24
Finished Jun 05 04:22:46 PM PDT 24
Peak memory 195684 kb
Host smart-365ca7b7-4cfd-44ab-91d5-cddf9f234246
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554111540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1554111540
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.256796490
Short name T272
Test name
Test status
Simulation time 1049117956 ps
CPU time 50.34 seconds
Started Jun 05 04:22:52 PM PDT 24
Finished Jun 05 04:23:42 PM PDT 24
Peak memory 218516 kb
Host smart-f6c48da7-ca03-42d5-b34a-87e1c61147d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=256796490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.256796490
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.4206845898
Short name T348
Test name
Test status
Simulation time 4212908774 ps
CPU time 56.96 seconds
Started Jun 05 04:22:48 PM PDT 24
Finished Jun 05 04:23:45 PM PDT 24
Peak memory 200148 kb
Host smart-18b8619e-920c-4572-9766-8bc9b41ef911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206845898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.4206845898
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.3649156354
Short name T261
Test name
Test status
Simulation time 24602579133 ps
CPU time 422.04 seconds
Started Jun 05 04:22:50 PM PDT 24
Finished Jun 05 04:29:53 PM PDT 24
Peak memory 618380 kb
Host smart-81433147-5129-485a-8475-9186e6f0d802
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3649156354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.3649156354
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2127825287
Short name T122
Test name
Test status
Simulation time 12928608671 ps
CPU time 55.87 seconds
Started Jun 05 04:22:49 PM PDT 24
Finished Jun 05 04:23:45 PM PDT 24
Peak memory 200112 kb
Host smart-207fef52-3254-4e14-8f5a-7a932ad178b5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127825287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2127825287
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.2165746270
Short name T533
Test name
Test status
Simulation time 33830591264 ps
CPU time 124.75 seconds
Started Jun 05 04:22:48 PM PDT 24
Finished Jun 05 04:24:54 PM PDT 24
Peak memory 200192 kb
Host smart-736dd197-cb93-4f8c-9a2b-7c808d52760a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165746270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.2165746270
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.2595796088
Short name T150
Test name
Test status
Simulation time 286191861 ps
CPU time 3.16 seconds
Started Jun 05 04:22:40 PM PDT 24
Finished Jun 05 04:22:44 PM PDT 24
Peak memory 200092 kb
Host smart-41befa42-4728-4ced-915e-bc6e6178a16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595796088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.2595796088
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1938149418
Short name T76
Test name
Test status
Simulation time 100389167131 ps
CPU time 1020.97 seconds
Started Jun 05 04:22:46 PM PDT 24
Finished Jun 05 04:39:48 PM PDT 24
Peak memory 700536 kb
Host smart-b0302e3f-abd8-480a-9e6b-3c5e25e47ff0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938149418 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1938149418
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.2794548153
Short name T242
Test name
Test status
Simulation time 42660858 ps
CPU time 1.1 seconds
Started Jun 05 04:22:49 PM PDT 24
Finished Jun 05 04:22:51 PM PDT 24
Peak memory 199760 kb
Host smart-f9439d7a-6b6b-4864-9451-7e9e4dc04bcc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794548153 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.2794548153
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.3919637513
Short name T137
Test name
Test status
Simulation time 312359789070 ps
CPU time 466.78 seconds
Started Jun 05 04:22:52 PM PDT 24
Finished Jun 05 04:30:39 PM PDT 24
Peak memory 200092 kb
Host smart-b6c75628-c205-45c4-922f-c75882888f11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919637513 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.3919637513
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.2237625086
Short name T521
Test name
Test status
Simulation time 7831001100 ps
CPU time 36.69 seconds
Started Jun 05 04:22:46 PM PDT 24
Finished Jun 05 04:23:24 PM PDT 24
Peak memory 200104 kb
Host smart-706f5745-dc0d-4cec-a6a3-248352b71a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237625086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2237625086
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3495651020
Short name T180
Test name
Test status
Simulation time 28042513 ps
CPU time 0.69 seconds
Started Jun 05 04:22:56 PM PDT 24
Finished Jun 05 04:22:58 PM PDT 24
Peak memory 195980 kb
Host smart-1f861e88-a86d-49a2-8843-c80f4736a2ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495651020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3495651020
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2184197579
Short name T34
Test name
Test status
Simulation time 1227714959 ps
CPU time 58.16 seconds
Started Jun 05 04:22:50 PM PDT 24
Finished Jun 05 04:23:49 PM PDT 24
Peak memory 211404 kb
Host smart-a9bf41f6-7743-48b4-8117-b52e3ffff6f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2184197579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2184197579
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.646423615
Short name T369
Test name
Test status
Simulation time 2653984931 ps
CPU time 664.44 seconds
Started Jun 05 04:22:54 PM PDT 24
Finished Jun 05 04:33:59 PM PDT 24
Peak memory 661312 kb
Host smart-3e7123d4-066c-4dde-a262-f46bf8ff8da6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=646423615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.646423615
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3599103985
Short name T17
Test name
Test status
Simulation time 732736534 ps
CPU time 2.99 seconds
Started Jun 05 04:22:56 PM PDT 24
Finished Jun 05 04:22:59 PM PDT 24
Peak memory 199900 kb
Host smart-6d06fa6c-6d3c-4b14-a904-d15fbbbd31c1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599103985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3599103985
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2422301108
Short name T418
Test name
Test status
Simulation time 3777918978 ps
CPU time 55.72 seconds
Started Jun 05 04:22:49 PM PDT 24
Finished Jun 05 04:23:45 PM PDT 24
Peak memory 200192 kb
Host smart-460acfba-f9fe-44db-870d-336e69618422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422301108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2422301108
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3402356728
Short name T336
Test name
Test status
Simulation time 695000841 ps
CPU time 6.59 seconds
Started Jun 05 04:22:46 PM PDT 24
Finished Jun 05 04:22:53 PM PDT 24
Peak memory 200092 kb
Host smart-fcbd931a-63c3-493f-8223-4a76c0c755e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402356728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3402356728
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.125869037
Short name T36
Test name
Test status
Simulation time 138392619052 ps
CPU time 1384.55 seconds
Started Jun 05 04:22:58 PM PDT 24
Finished Jun 05 04:46:04 PM PDT 24
Peak memory 692908 kb
Host smart-67984aec-be25-477d-a05f-99c87ead3da3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125869037 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.125869037
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.411198238
Short name T57
Test name
Test status
Simulation time 216660736 ps
CPU time 1.1 seconds
Started Jun 05 04:22:54 PM PDT 24
Finished Jun 05 04:22:56 PM PDT 24
Peak memory 199884 kb
Host smart-091c4083-75b6-4437-b351-001f4b36390f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411198238 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_test_hmac_vectors.411198238
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.2593399255
Short name T414
Test name
Test status
Simulation time 26127928939 ps
CPU time 495.71 seconds
Started Jun 05 04:22:54 PM PDT 24
Finished Jun 05 04:31:11 PM PDT 24
Peak memory 200092 kb
Host smart-4711e7d6-6877-4a50-9a78-db393f5c7f0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593399255 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.2593399255
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.1363241760
Short name T408
Test name
Test status
Simulation time 5229151374 ps
CPU time 55.45 seconds
Started Jun 05 04:22:55 PM PDT 24
Finished Jun 05 04:23:51 PM PDT 24
Peak memory 200220 kb
Host smart-d7bd008b-58cb-4a04-bb04-4f5961d981b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363241760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1363241760
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.609948332
Short name T376
Test name
Test status
Simulation time 69603077 ps
CPU time 0.61 seconds
Started Jun 05 04:22:58 PM PDT 24
Finished Jun 05 04:23:00 PM PDT 24
Peak memory 196744 kb
Host smart-c9c84aca-b211-4751-b66a-ba55b5568fb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609948332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.609948332
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.707471485
Short name T431
Test name
Test status
Simulation time 994439423 ps
CPU time 20.9 seconds
Started Jun 05 04:22:55 PM PDT 24
Finished Jun 05 04:23:17 PM PDT 24
Peak memory 215564 kb
Host smart-a3896e72-a411-49de-8160-8edf42ae9d9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=707471485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.707471485
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3221667943
Short name T288
Test name
Test status
Simulation time 1244730544 ps
CPU time 18.74 seconds
Started Jun 05 04:22:57 PM PDT 24
Finished Jun 05 04:23:17 PM PDT 24
Peak memory 200100 kb
Host smart-3f6d3a60-011f-46d8-87b6-5037edc1c24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221667943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3221667943
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2236531368
Short name T97
Test name
Test status
Simulation time 4110455971 ps
CPU time 1046.64 seconds
Started Jun 05 04:22:55 PM PDT 24
Finished Jun 05 04:40:22 PM PDT 24
Peak memory 684240 kb
Host smart-0f81be57-dca0-4415-a237-ce8018d3c405
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2236531368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2236531368
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.143878872
Short name T571
Test name
Test status
Simulation time 8799514008 ps
CPU time 161.62 seconds
Started Jun 05 04:22:59 PM PDT 24
Finished Jun 05 04:25:42 PM PDT 24
Peak memory 200116 kb
Host smart-d677a901-4154-4415-8fb4-8c1481bfa073
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143878872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.143878872
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3789403431
Short name T293
Test name
Test status
Simulation time 280383978 ps
CPU time 7.22 seconds
Started Jun 05 04:22:54 PM PDT 24
Finished Jun 05 04:23:01 PM PDT 24
Peak memory 200152 kb
Host smart-08eda247-247d-4c3b-ac13-1f7ed261f7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789403431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3789403431
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2086896007
Short name T255
Test name
Test status
Simulation time 291394623 ps
CPU time 4.85 seconds
Started Jun 05 04:22:54 PM PDT 24
Finished Jun 05 04:22:59 PM PDT 24
Peak memory 200176 kb
Host smart-bc2a35c7-7425-4b2a-823b-c288230134e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086896007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2086896007
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.820705274
Short name T195
Test name
Test status
Simulation time 23270109713 ps
CPU time 3480.96 seconds
Started Jun 05 04:22:54 PM PDT 24
Finished Jun 05 05:20:56 PM PDT 24
Peak memory 844456 kb
Host smart-5fe4a13c-2f41-4d13-ad87-2236fc7368d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820705274 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.820705274
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.726640106
Short name T185
Test name
Test status
Simulation time 516541298 ps
CPU time 1.19 seconds
Started Jun 05 04:22:54 PM PDT 24
Finished Jun 05 04:22:56 PM PDT 24
Peak memory 199880 kb
Host smart-7bc00cef-edf3-4c77-b67d-0f33f880c5f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726640106 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_hmac_vectors.726640106
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.3676917423
Short name T194
Test name
Test status
Simulation time 96862291733 ps
CPU time 445.64 seconds
Started Jun 05 04:22:57 PM PDT 24
Finished Jun 05 04:30:23 PM PDT 24
Peak memory 200088 kb
Host smart-2d10dd0f-9208-4aef-9c37-45d013a412ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676917423 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.3676917423
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1034413977
Short name T472
Test name
Test status
Simulation time 4222192214 ps
CPU time 25.57 seconds
Started Jun 05 04:22:56 PM PDT 24
Finished Jun 05 04:23:23 PM PDT 24
Peak memory 200124 kb
Host smart-019918d4-4aed-4a30-b89f-f1b0057810e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034413977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1034413977
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3359421097
Short name T517
Test name
Test status
Simulation time 12833689 ps
CPU time 0.61 seconds
Started Jun 05 04:23:07 PM PDT 24
Finished Jun 05 04:23:08 PM PDT 24
Peak memory 195996 kb
Host smart-b54eef75-874e-48e4-a8e4-5580277a28e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359421097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3359421097
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3936552560
Short name T440
Test name
Test status
Simulation time 1879045647 ps
CPU time 21.99 seconds
Started Jun 05 04:22:56 PM PDT 24
Finished Jun 05 04:23:18 PM PDT 24
Peak memory 208356 kb
Host smart-646afc5c-8603-499a-90d4-97ee3db92a6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3936552560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3936552560
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.961755583
Short name T512
Test name
Test status
Simulation time 2968170862 ps
CPU time 8.34 seconds
Started Jun 05 04:23:06 PM PDT 24
Finished Jun 05 04:23:15 PM PDT 24
Peak memory 200180 kb
Host smart-165ba166-8d46-45f4-92e2-80a223c97691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961755583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.961755583
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1575694787
Short name T278
Test name
Test status
Simulation time 628929433 ps
CPU time 153.73 seconds
Started Jun 05 04:22:57 PM PDT 24
Finished Jun 05 04:25:32 PM PDT 24
Peak memory 616248 kb
Host smart-61c2c070-73ca-467f-b3eb-3985c46273f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1575694787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1575694787
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.2780221071
Short name T250
Test name
Test status
Simulation time 62105810386 ps
CPU time 204.93 seconds
Started Jun 05 04:23:12 PM PDT 24
Finished Jun 05 04:26:38 PM PDT 24
Peak memory 200168 kb
Host smart-735ab557-ba3d-48df-b1c2-47abd626cefc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780221071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.2780221071
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.4209523787
Short name T135
Test name
Test status
Simulation time 18504053646 ps
CPU time 105.71 seconds
Started Jun 05 04:22:58 PM PDT 24
Finished Jun 05 04:24:45 PM PDT 24
Peak memory 200144 kb
Host smart-e784dfa0-f10c-4932-bf44-5043ffd950ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209523787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.4209523787
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2373400597
Short name T450
Test name
Test status
Simulation time 157875174 ps
CPU time 5.99 seconds
Started Jun 05 04:22:57 PM PDT 24
Finished Jun 05 04:23:04 PM PDT 24
Peak memory 200076 kb
Host smart-8313e850-a9c4-4ca3-b83a-44bd794a11d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373400597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2373400597
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3148344474
Short name T530
Test name
Test status
Simulation time 54287688945 ps
CPU time 1587.65 seconds
Started Jun 05 04:23:04 PM PDT 24
Finished Jun 05 04:49:33 PM PDT 24
Peak memory 709592 kb
Host smart-c65058e9-8701-461f-aa47-de7c4d4359be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148344474 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3148344474
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.1978846407
Short name T48
Test name
Test status
Simulation time 54263453 ps
CPU time 1.11 seconds
Started Jun 05 04:23:02 PM PDT 24
Finished Jun 05 04:23:04 PM PDT 24
Peak memory 199928 kb
Host smart-e4272bb6-2c15-45af-bc90-2127130e31a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978846407 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.1978846407
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.3272707273
Short name T47
Test name
Test status
Simulation time 24923298548 ps
CPU time 466.26 seconds
Started Jun 05 04:23:04 PM PDT 24
Finished Jun 05 04:30:51 PM PDT 24
Peak memory 200080 kb
Host smart-00beddf0-feae-4b06-8834-eca92fe831b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272707273 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.3272707273
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.3937663888
Short name T313
Test name
Test status
Simulation time 7992806643 ps
CPU time 35.63 seconds
Started Jun 05 04:23:06 PM PDT 24
Finished Jun 05 04:23:42 PM PDT 24
Peak memory 200168 kb
Host smart-79ba4702-dce4-418e-bfbc-e5a16cf50aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937663888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.3937663888
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.1850344587
Short name T127
Test name
Test status
Simulation time 11201543 ps
CPU time 0.58 seconds
Started Jun 05 04:23:04 PM PDT 24
Finished Jun 05 04:23:05 PM PDT 24
Peak memory 194956 kb
Host smart-655d7658-7c64-4308-8a3c-9c5c56257656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850344587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1850344587
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.2216005967
Short name T168
Test name
Test status
Simulation time 1783450378 ps
CPU time 22.7 seconds
Started Jun 05 04:23:05 PM PDT 24
Finished Jun 05 04:23:29 PM PDT 24
Peak memory 226824 kb
Host smart-fc5fa5f6-004b-4797-a49c-f73f0a9f4243
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2216005967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.2216005967
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2536539162
Short name T499
Test name
Test status
Simulation time 152435806 ps
CPU time 3.43 seconds
Started Jun 05 04:23:07 PM PDT 24
Finished Jun 05 04:23:11 PM PDT 24
Peak memory 200112 kb
Host smart-e0a3fec7-3991-42f3-81e7-c1b512d06695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536539162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2536539162
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1481273736
Short name T363
Test name
Test status
Simulation time 456126254 ps
CPU time 11.51 seconds
Started Jun 05 04:23:07 PM PDT 24
Finished Jun 05 04:23:19 PM PDT 24
Peak memory 205196 kb
Host smart-6ef3008d-8527-432b-8c8a-e6ddf1a47788
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1481273736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1481273736
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.508858984
Short name T585
Test name
Test status
Simulation time 2701602539 ps
CPU time 151.51 seconds
Started Jun 05 04:23:05 PM PDT 24
Finished Jun 05 04:25:37 PM PDT 24
Peak memory 200120 kb
Host smart-7a077469-11a7-4273-a046-7ee3169d5363
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508858984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.508858984
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1699107261
Short name T164
Test name
Test status
Simulation time 11397477905 ps
CPU time 82.62 seconds
Started Jun 05 04:23:03 PM PDT 24
Finished Jun 05 04:24:27 PM PDT 24
Peak memory 200176 kb
Host smart-cabbf51d-eaf4-40ca-92c6-f7edbfa5e888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699107261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1699107261
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2819152163
Short name T201
Test name
Test status
Simulation time 170174912 ps
CPU time 3.39 seconds
Started Jun 05 04:23:06 PM PDT 24
Finished Jun 05 04:23:10 PM PDT 24
Peak memory 200168 kb
Host smart-f3c7adcf-9558-4b0e-9f30-3c2611c1faeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819152163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2819152163
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2237330170
Short name T69
Test name
Test status
Simulation time 102708015685 ps
CPU time 1442.16 seconds
Started Jun 05 04:23:04 PM PDT 24
Finished Jun 05 04:47:08 PM PDT 24
Peak memory 460072 kb
Host smart-6de67f04-6472-4f2f-804e-d062b7f133c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237330170 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2237330170
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.321358933
Short name T575
Test name
Test status
Simulation time 33333752 ps
CPU time 1.31 seconds
Started Jun 05 04:23:04 PM PDT 24
Finished Jun 05 04:23:07 PM PDT 24
Peak memory 200072 kb
Host smart-5576621c-5fbe-4b64-a357-2ebe13b3020b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321358933 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_hmac_vectors.321358933
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.2433189641
Short name T422
Test name
Test status
Simulation time 8417988597 ps
CPU time 471.88 seconds
Started Jun 05 04:23:05 PM PDT 24
Finished Jun 05 04:30:57 PM PDT 24
Peak memory 200084 kb
Host smart-3dc5a2ae-6b56-4c17-8823-ab277808d287
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433189641 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.2433189641
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.2128344000
Short name T576
Test name
Test status
Simulation time 2339881029 ps
CPU time 10.38 seconds
Started Jun 05 04:23:05 PM PDT 24
Finished Jun 05 04:23:16 PM PDT 24
Peak memory 200068 kb
Host smart-0513e8c6-99d5-4a90-af35-3bf3c14ac86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128344000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2128344000
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3060590963
Short name T339
Test name
Test status
Simulation time 26144726 ps
CPU time 0.61 seconds
Started Jun 05 04:23:15 PM PDT 24
Finished Jun 05 04:23:16 PM PDT 24
Peak memory 195924 kb
Host smart-5e7919ea-b160-499b-a709-63399d8ab091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060590963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3060590963
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.2829880754
Short name T541
Test name
Test status
Simulation time 4872067362 ps
CPU time 26.55 seconds
Started Jun 05 04:23:05 PM PDT 24
Finished Jun 05 04:23:32 PM PDT 24
Peak memory 208428 kb
Host smart-f784083e-6f07-4fcb-bab9-61f040c1a068
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2829880754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2829880754
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.246630532
Short name T311
Test name
Test status
Simulation time 12786638578 ps
CPU time 58.14 seconds
Started Jun 05 04:23:06 PM PDT 24
Finished Jun 05 04:24:05 PM PDT 24
Peak memory 200196 kb
Host smart-cfa41016-d4fc-43b7-9e12-d11400d82767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246630532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.246630532
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.1450097019
Short name T271
Test name
Test status
Simulation time 6491687199 ps
CPU time 1030.21 seconds
Started Jun 05 04:23:04 PM PDT 24
Finished Jun 05 04:40:15 PM PDT 24
Peak memory 719276 kb
Host smart-4fdb2ccd-6045-4fb1-8aeb-16ddd8d2bd92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1450097019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1450097019
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.390047787
Short name T331
Test name
Test status
Simulation time 56682030678 ps
CPU time 198.49 seconds
Started Jun 05 04:23:06 PM PDT 24
Finished Jun 05 04:26:25 PM PDT 24
Peak memory 200112 kb
Host smart-03386295-0387-44f6-b330-55acb26c4e63
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390047787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.390047787
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.241880867
Short name T350
Test name
Test status
Simulation time 7143221567 ps
CPU time 35.23 seconds
Started Jun 05 04:23:03 PM PDT 24
Finished Jun 05 04:23:39 PM PDT 24
Peak memory 200144 kb
Host smart-7e54a5f6-fb5f-4bd0-8eeb-75a5f923f697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241880867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.241880867
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.58504282
Short name T175
Test name
Test status
Simulation time 57016652 ps
CPU time 1.97 seconds
Started Jun 05 04:23:06 PM PDT 24
Finished Jun 05 04:23:08 PM PDT 24
Peak memory 200084 kb
Host smart-429790d9-557d-4adb-89a3-42695feb37e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58504282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.58504282
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3001365564
Short name T253
Test name
Test status
Simulation time 53262766876 ps
CPU time 1670.63 seconds
Started Jun 05 04:23:13 PM PDT 24
Finished Jun 05 04:51:05 PM PDT 24
Peak memory 728428 kb
Host smart-1c9332b6-558e-4513-9cd8-c641990bb37b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001365564 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3001365564
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.2833464017
Short name T449
Test name
Test status
Simulation time 33775584 ps
CPU time 1.14 seconds
Started Jun 05 04:23:03 PM PDT 24
Finished Jun 05 04:23:05 PM PDT 24
Peak memory 200040 kb
Host smart-de728341-af00-4ec8-95d0-486d99a06c95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833464017 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.2833464017
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.2959095095
Short name T182
Test name
Test status
Simulation time 35579211336 ps
CPU time 512.45 seconds
Started Jun 05 04:23:05 PM PDT 24
Finished Jun 05 04:31:38 PM PDT 24
Peak memory 200040 kb
Host smart-5542dccc-d5d7-4c66-b424-8c1cc36c6238
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959095095 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.2959095095
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1033675244
Short name T434
Test name
Test status
Simulation time 7111054416 ps
CPU time 33.02 seconds
Started Jun 05 04:23:03 PM PDT 24
Finished Jun 05 04:23:36 PM PDT 24
Peak memory 200152 kb
Host smart-e24727c5-0d55-465f-bdbb-14af9a4cd83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033675244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1033675244
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.895498912
Short name T394
Test name
Test status
Simulation time 25398578 ps
CPU time 0.59 seconds
Started Jun 05 04:23:11 PM PDT 24
Finished Jun 05 04:23:12 PM PDT 24
Peak memory 195752 kb
Host smart-907d54e3-92e7-42ee-9489-9b23a7175878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895498912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.895498912
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1155173271
Short name T362
Test name
Test status
Simulation time 3788648591 ps
CPU time 46.06 seconds
Started Jun 05 04:23:14 PM PDT 24
Finished Jun 05 04:24:01 PM PDT 24
Peak memory 226760 kb
Host smart-e7a4db97-fae3-4342-976a-3c1eb59f33c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1155173271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1155173271
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.4125068981
Short name T385
Test name
Test status
Simulation time 3020424427 ps
CPU time 52.17 seconds
Started Jun 05 04:23:12 PM PDT 24
Finished Jun 05 04:24:05 PM PDT 24
Peak memory 200196 kb
Host smart-61a16808-b012-4cab-965f-aff1705fdfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125068981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.4125068981
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1114730177
Short name T216
Test name
Test status
Simulation time 3628949748 ps
CPU time 920.11 seconds
Started Jun 05 04:23:13 PM PDT 24
Finished Jun 05 04:38:33 PM PDT 24
Peak memory 702208 kb
Host smart-322f6671-05ad-4062-99f3-1048186f956b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1114730177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1114730177
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2603969600
Short name T383
Test name
Test status
Simulation time 7691492372 ps
CPU time 61.18 seconds
Started Jun 05 04:23:13 PM PDT 24
Finished Jun 05 04:24:15 PM PDT 24
Peak memory 200124 kb
Host smart-2b341bd8-9139-47e1-b87e-b25249cc4e0f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603969600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2603969600
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3908005974
Short name T508
Test name
Test status
Simulation time 2398827150 ps
CPU time 6.24 seconds
Started Jun 05 04:23:12 PM PDT 24
Finished Jun 05 04:23:19 PM PDT 24
Peak memory 200184 kb
Host smart-73b77a49-57e3-4b09-b69e-b39cc5dc3001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908005974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3908005974
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3987774653
Short name T6
Test name
Test status
Simulation time 411064128 ps
CPU time 6.23 seconds
Started Jun 05 04:23:12 PM PDT 24
Finished Jun 05 04:23:19 PM PDT 24
Peak memory 200052 kb
Host smart-10611c3f-9e75-469b-a8e1-117856289cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987774653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3987774653
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.4206615771
Short name T384
Test name
Test status
Simulation time 61164969309 ps
CPU time 1737.94 seconds
Started Jun 05 04:23:15 PM PDT 24
Finished Jun 05 04:52:13 PM PDT 24
Peak memory 761992 kb
Host smart-ae1fd988-c43d-40b3-bd4f-94af95f78b3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206615771 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.4206615771
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.2360489919
Short name T133
Test name
Test status
Simulation time 146888466 ps
CPU time 1.27 seconds
Started Jun 05 04:23:10 PM PDT 24
Finished Jun 05 04:23:11 PM PDT 24
Peak memory 200112 kb
Host smart-63a51a38-af7a-4da7-ac3c-748c534666a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360489919 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.2360489919
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.2312381950
Short name T245
Test name
Test status
Simulation time 65416641783 ps
CPU time 497.97 seconds
Started Jun 05 04:23:15 PM PDT 24
Finished Jun 05 04:31:33 PM PDT 24
Peak memory 200080 kb
Host smart-72a4f0b4-52a1-4cc4-bf51-b92677059a26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312381950 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.2312381950
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3516512882
Short name T77
Test name
Test status
Simulation time 16817385392 ps
CPU time 83.13 seconds
Started Jun 05 04:23:12 PM PDT 24
Finished Jun 05 04:24:36 PM PDT 24
Peak memory 200124 kb
Host smart-1bd0d5f8-5534-4949-878c-36bc816630ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516512882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3516512882
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.206452040
Short name T401
Test name
Test status
Simulation time 36203848 ps
CPU time 0.6 seconds
Started Jun 05 04:23:15 PM PDT 24
Finished Jun 05 04:23:16 PM PDT 24
Peak memory 195712 kb
Host smart-a69ce3a8-9c3b-409d-8e1c-80243905a868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206452040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.206452040
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2892863252
Short name T448
Test name
Test status
Simulation time 7704300704 ps
CPU time 27.31 seconds
Started Jun 05 04:23:11 PM PDT 24
Finished Jun 05 04:23:39 PM PDT 24
Peak memory 224756 kb
Host smart-d3e8b8f3-b42e-46d1-a9aa-04a392a7226e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2892863252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2892863252
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.335183097
Short name T501
Test name
Test status
Simulation time 5641217688 ps
CPU time 33.56 seconds
Started Jun 05 04:23:12 PM PDT 24
Finished Jun 05 04:23:46 PM PDT 24
Peak memory 200148 kb
Host smart-858b0643-c082-447e-b83c-4142b95f31e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335183097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.335183097
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2763875302
Short name T308
Test name
Test status
Simulation time 5432127836 ps
CPU time 669.51 seconds
Started Jun 05 04:23:12 PM PDT 24
Finished Jun 05 04:34:22 PM PDT 24
Peak memory 690032 kb
Host smart-7bf50491-290f-4ff3-91e9-2c280cfd9eab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2763875302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2763875302
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1692318450
Short name T136
Test name
Test status
Simulation time 5460476289 ps
CPU time 109.6 seconds
Started Jun 05 04:23:13 PM PDT 24
Finished Jun 05 04:25:03 PM PDT 24
Peak memory 200124 kb
Host smart-ad6915ff-24b1-4ecc-b3cd-a1e86a30ad7c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692318450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1692318450
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.770374876
Short name T140
Test name
Test status
Simulation time 1211185107 ps
CPU time 4.52 seconds
Started Jun 05 04:23:11 PM PDT 24
Finished Jun 05 04:23:16 PM PDT 24
Peak memory 200056 kb
Host smart-58c05bd8-9acc-45b3-8f3f-f62491a7cefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770374876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.770374876
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2499732793
Short name T468
Test name
Test status
Simulation time 3992590607 ps
CPU time 11.93 seconds
Started Jun 05 04:23:16 PM PDT 24
Finished Jun 05 04:23:28 PM PDT 24
Peak memory 200192 kb
Host smart-8c92acc5-1cd9-4d26-98d5-e34e9f3610db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499732793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2499732793
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.667668152
Short name T64
Test name
Test status
Simulation time 158213379150 ps
CPU time 1212.59 seconds
Started Jun 05 04:23:16 PM PDT 24
Finished Jun 05 04:43:29 PM PDT 24
Peak memory 449016 kb
Host smart-9de4ba93-d23c-4b9e-b23c-5b261007ac27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667668152 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.667668152
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.3978798478
Short name T426
Test name
Test status
Simulation time 66379486 ps
CPU time 1.17 seconds
Started Jun 05 04:23:12 PM PDT 24
Finished Jun 05 04:23:14 PM PDT 24
Peak memory 199988 kb
Host smart-cd948e81-aec1-4820-afa9-f64017412b70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978798478 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.3978798478
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.1817468119
Short name T301
Test name
Test status
Simulation time 113733449192 ps
CPU time 513.4 seconds
Started Jun 05 04:23:12 PM PDT 24
Finished Jun 05 04:31:47 PM PDT 24
Peak memory 200132 kb
Host smart-4b4a309a-9a2c-4daa-95cd-72e44077db55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817468119 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.1817468119
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2799185940
Short name T304
Test name
Test status
Simulation time 2626848546 ps
CPU time 45.91 seconds
Started Jun 05 04:23:10 PM PDT 24
Finished Jun 05 04:23:56 PM PDT 24
Peak memory 200164 kb
Host smart-383f544a-6b54-4b17-92fe-3be732641cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799185940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2799185940
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3691084863
Short name T23
Test name
Test status
Simulation time 16032219 ps
CPU time 0.56 seconds
Started Jun 05 04:23:24 PM PDT 24
Finished Jun 05 04:23:25 PM PDT 24
Peak memory 194940 kb
Host smart-97272bf0-e464-4d33-a5b6-7a3e265aed69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691084863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3691084863
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1467498259
Short name T557
Test name
Test status
Simulation time 626178715 ps
CPU time 32.45 seconds
Started Jun 05 04:23:23 PM PDT 24
Finished Jun 05 04:23:56 PM PDT 24
Peak memory 216260 kb
Host smart-e5d97f33-f632-42fc-b7c0-76af8a5a673f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1467498259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1467498259
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3359565218
Short name T552
Test name
Test status
Simulation time 1678739066 ps
CPU time 17.98 seconds
Started Jun 05 04:23:20 PM PDT 24
Finished Jun 05 04:23:39 PM PDT 24
Peak memory 200036 kb
Host smart-9db48274-8004-49d9-bf0e-ef9fb35ede9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359565218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3359565218
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.508625574
Short name T410
Test name
Test status
Simulation time 2313736300 ps
CPU time 118.94 seconds
Started Jun 05 04:23:22 PM PDT 24
Finished Jun 05 04:25:21 PM PDT 24
Peak memory 573588 kb
Host smart-4c002798-402f-417c-ad14-225e7f53ad4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=508625574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.508625574
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3574702579
Short name T338
Test name
Test status
Simulation time 1757328757 ps
CPU time 98.43 seconds
Started Jun 05 04:23:21 PM PDT 24
Finished Jun 05 04:25:00 PM PDT 24
Peak memory 200060 kb
Host smart-46aa621a-7924-4731-9a6b-80bc2384acab
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574702579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3574702579
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.3955372654
Short name T309
Test name
Test status
Simulation time 15290131851 ps
CPU time 51.07 seconds
Started Jun 05 04:23:21 PM PDT 24
Finished Jun 05 04:24:13 PM PDT 24
Peak memory 200140 kb
Host smart-c49bc4c5-c656-44a8-a879-a53accff4ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955372654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3955372654
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2447354897
Short name T441
Test name
Test status
Simulation time 98350772 ps
CPU time 2.32 seconds
Started Jun 05 04:23:22 PM PDT 24
Finished Jun 05 04:23:25 PM PDT 24
Peak memory 200064 kb
Host smart-21751031-1695-473d-972a-6370a2f0cb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447354897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2447354897
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1614879537
Short name T52
Test name
Test status
Simulation time 32741785353 ps
CPU time 1422.61 seconds
Started Jun 05 04:23:20 PM PDT 24
Finished Jun 05 04:47:04 PM PDT 24
Peak memory 618156 kb
Host smart-83e9b251-3164-4e55-8ad2-ea8ac47b68e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614879537 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1614879537
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.2789721227
Short name T258
Test name
Test status
Simulation time 122042598 ps
CPU time 1.41 seconds
Started Jun 05 04:23:22 PM PDT 24
Finished Jun 05 04:23:24 PM PDT 24
Peak memory 200072 kb
Host smart-63a4fb79-142e-4791-bd6f-25b87d178103
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789721227 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.2789721227
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.1951063795
Short name T290
Test name
Test status
Simulation time 7834941707 ps
CPU time 415.86 seconds
Started Jun 05 04:23:21 PM PDT 24
Finished Jun 05 04:30:17 PM PDT 24
Peak memory 200096 kb
Host smart-195e6385-565f-4d3c-89ed-9e4eb899bda9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951063795 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.1951063795
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.2091714905
Short name T455
Test name
Test status
Simulation time 2142895266 ps
CPU time 47.63 seconds
Started Jun 05 04:23:22 PM PDT 24
Finished Jun 05 04:24:11 PM PDT 24
Peak memory 200152 kb
Host smart-bf2a6780-6bcd-4b98-ac8a-9b4a6950b627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091714905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.2091714905
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.2552868399
Short name T352
Test name
Test status
Simulation time 25351538 ps
CPU time 0.58 seconds
Started Jun 05 04:21:17 PM PDT 24
Finished Jun 05 04:21:20 PM PDT 24
Peak memory 195956 kb
Host smart-3e559fcb-e9ae-4611-bf44-fdc834b351cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552868399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.2552868399
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2429227546
Short name T528
Test name
Test status
Simulation time 1056293651 ps
CPU time 26.16 seconds
Started Jun 05 04:21:06 PM PDT 24
Finished Jun 05 04:21:33 PM PDT 24
Peak memory 212316 kb
Host smart-10717822-bd98-471f-9ba1-8bc4d74149ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2429227546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2429227546
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3616003665
Short name T572
Test name
Test status
Simulation time 1434405695 ps
CPU time 22.04 seconds
Started Jun 05 04:21:09 PM PDT 24
Finished Jun 05 04:21:32 PM PDT 24
Peak memory 200128 kb
Host smart-828e9a9e-8f03-432d-9185-8a98f6fbdd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616003665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3616003665
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.143126443
Short name T465
Test name
Test status
Simulation time 211516671 ps
CPU time 38.27 seconds
Started Jun 05 04:21:05 PM PDT 24
Finished Jun 05 04:21:44 PM PDT 24
Peak memory 321192 kb
Host smart-300f7ed2-36ce-4ea7-bf24-58dbf7d960cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=143126443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.143126443
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.3960643857
Short name T464
Test name
Test status
Simulation time 10653179471 ps
CPU time 95.11 seconds
Started Jun 05 04:21:07 PM PDT 24
Finished Jun 05 04:22:43 PM PDT 24
Peak memory 200108 kb
Host smart-14790400-6ec6-4bb7-9b76-582e96859f47
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960643857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3960643857
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3116427474
Short name T579
Test name
Test status
Simulation time 7513417409 ps
CPU time 75.63 seconds
Started Jun 05 04:21:05 PM PDT 24
Finished Jun 05 04:22:22 PM PDT 24
Peak memory 200252 kb
Host smart-a312d77e-5ec1-4268-84ee-e0df296c9828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116427474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3116427474
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.2710535667
Short name T326
Test name
Test status
Simulation time 116153963 ps
CPU time 4.16 seconds
Started Jun 05 04:21:05 PM PDT 24
Finished Jun 05 04:21:09 PM PDT 24
Peak memory 200136 kb
Host smart-959df981-2fb7-4ff6-9183-f4aadedb0362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710535667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2710535667
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.2804243712
Short name T269
Test name
Test status
Simulation time 4372309652 ps
CPU time 110.28 seconds
Started Jun 05 04:21:08 PM PDT 24
Finished Jun 05 04:22:59 PM PDT 24
Peak memory 215760 kb
Host smart-ce8582ba-fba4-4cc1-8083-743afc95cb19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804243712 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.2804243712
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.2288418164
Short name T312
Test name
Test status
Simulation time 31089817 ps
CPU time 1.17 seconds
Started Jun 05 04:21:09 PM PDT 24
Finished Jun 05 04:21:11 PM PDT 24
Peak memory 199736 kb
Host smart-e8867271-c0e9-449c-aa52-fc2aa9b9e66a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288418164 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.2288418164
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.3340171903
Short name T251
Test name
Test status
Simulation time 17560603158 ps
CPU time 499.18 seconds
Started Jun 05 04:21:07 PM PDT 24
Finished Jun 05 04:29:27 PM PDT 24
Peak memory 200060 kb
Host smart-c7face71-785e-4d84-8da7-c7060c6eb017
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340171903 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.3340171903
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.2028586165
Short name T138
Test name
Test status
Simulation time 1705449876 ps
CPU time 24.7 seconds
Started Jun 05 04:21:09 PM PDT 24
Finished Jun 05 04:21:34 PM PDT 24
Peak memory 200120 kb
Host smart-47b8a83e-840f-4f9a-a7ad-67e128eaddc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028586165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.2028586165
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.3375498840
Short name T398
Test name
Test status
Simulation time 14027206 ps
CPU time 0.6 seconds
Started Jun 05 04:21:14 PM PDT 24
Finished Jun 05 04:21:15 PM PDT 24
Peak memory 194972 kb
Host smart-fc6f94a1-07e5-4b91-8dd5-c3323dbb8b85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375498840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.3375498840
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3498130966
Short name T457
Test name
Test status
Simulation time 1272186250 ps
CPU time 14.88 seconds
Started Jun 05 04:21:14 PM PDT 24
Finished Jun 05 04:21:30 PM PDT 24
Peak memory 208312 kb
Host smart-b9315644-67dd-44b7-b5b6-36fc0a594af9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3498130966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3498130966
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3529371875
Short name T131
Test name
Test status
Simulation time 11185487244 ps
CPU time 12.9 seconds
Started Jun 05 04:21:21 PM PDT 24
Finished Jun 05 04:21:35 PM PDT 24
Peak memory 200088 kb
Host smart-e4c133b5-e8f7-468a-8a40-deed128b4e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529371875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3529371875
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2051459209
Short name T141
Test name
Test status
Simulation time 17241507182 ps
CPU time 268.3 seconds
Started Jun 05 04:21:15 PM PDT 24
Finished Jun 05 04:25:44 PM PDT 24
Peak memory 494992 kb
Host smart-589a3a97-05cb-40e7-ad03-29d5f7c0038b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2051459209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2051459209
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1183077191
Short name T568
Test name
Test status
Simulation time 20871921555 ps
CPU time 66.73 seconds
Started Jun 05 04:21:14 PM PDT 24
Finished Jun 05 04:22:21 PM PDT 24
Peak memory 200120 kb
Host smart-5c183237-68cb-47fc-92fb-73dd6d0fc163
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183077191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1183077191
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.629902237
Short name T570
Test name
Test status
Simulation time 17683024574 ps
CPU time 67.73 seconds
Started Jun 05 04:21:15 PM PDT 24
Finished Jun 05 04:22:23 PM PDT 24
Peak memory 200164 kb
Host smart-b1e75a1a-e350-4773-b4a1-4b61a942df28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629902237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.629902237
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.1258446755
Short name T218
Test name
Test status
Simulation time 270245606 ps
CPU time 3.25 seconds
Started Jun 05 04:21:13 PM PDT 24
Finished Jun 05 04:21:17 PM PDT 24
Peak memory 200280 kb
Host smart-8299039b-c999-4d03-aad5-b605fab0a98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258446755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1258446755
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.3123247852
Short name T451
Test name
Test status
Simulation time 182005055791 ps
CPU time 1193.2 seconds
Started Jun 05 04:21:17 PM PDT 24
Finished Jun 05 04:41:12 PM PDT 24
Peak memory 225808 kb
Host smart-2fc2ae89-7c7b-4ad8-bbea-23211bd5b0c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123247852 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3123247852
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.4211344436
Short name T257
Test name
Test status
Simulation time 217102218 ps
CPU time 1.09 seconds
Started Jun 05 04:21:16 PM PDT 24
Finished Jun 05 04:21:18 PM PDT 24
Peak memory 200072 kb
Host smart-fe2ad8dd-80c4-4a2d-9ee3-102f76a2bf50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211344436 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.4211344436
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.3479070605
Short name T32
Test name
Test status
Simulation time 102959158107 ps
CPU time 491.63 seconds
Started Jun 05 04:21:15 PM PDT 24
Finished Jun 05 04:29:28 PM PDT 24
Peak memory 200136 kb
Host smart-774daa29-cef6-42c1-a851-cd42fb6edc82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479070605 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.3479070605
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.3934340489
Short name T573
Test name
Test status
Simulation time 1828762943 ps
CPU time 66.48 seconds
Started Jun 05 04:21:14 PM PDT 24
Finished Jun 05 04:22:22 PM PDT 24
Peak memory 200096 kb
Host smart-555981d7-a471-401f-98b4-a9ce06f40b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934340489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3934340489
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3903415839
Short name T439
Test name
Test status
Simulation time 16014055 ps
CPU time 0.63 seconds
Started Jun 05 04:21:17 PM PDT 24
Finished Jun 05 04:21:19 PM PDT 24
Peak memory 195956 kb
Host smart-1855a870-72ff-45a4-9eaf-a5b701995195
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903415839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3903415839
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1086118249
Short name T295
Test name
Test status
Simulation time 1931592341 ps
CPU time 27.27 seconds
Started Jun 05 04:21:19 PM PDT 24
Finished Jun 05 04:21:47 PM PDT 24
Peak memory 219588 kb
Host smart-7f709743-99f0-46d3-a2ed-f5a2b5dfa645
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1086118249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1086118249
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1275992309
Short name T397
Test name
Test status
Simulation time 644082589 ps
CPU time 16.78 seconds
Started Jun 05 04:21:17 PM PDT 24
Finished Jun 05 04:21:36 PM PDT 24
Peak memory 200044 kb
Host smart-55b24549-67de-4aa3-99bd-e13542355bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275992309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1275992309
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.4218903277
Short name T118
Test name
Test status
Simulation time 102731790 ps
CPU time 10.59 seconds
Started Jun 05 04:21:14 PM PDT 24
Finished Jun 05 04:21:25 PM PDT 24
Peak memory 224172 kb
Host smart-6915dc82-28c3-43ce-ad3b-33a8a013fc93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4218903277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.4218903277
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1987571744
Short name T142
Test name
Test status
Simulation time 5866852192 ps
CPU time 75.1 seconds
Started Jun 05 04:21:16 PM PDT 24
Finished Jun 05 04:22:32 PM PDT 24
Peak memory 200076 kb
Host smart-28c3d22b-cd11-480b-8979-b745163b24e1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987571744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1987571744
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.1702078702
Short name T343
Test name
Test status
Simulation time 10278035484 ps
CPU time 133.05 seconds
Started Jun 05 04:21:18 PM PDT 24
Finished Jun 05 04:23:33 PM PDT 24
Peak memory 200164 kb
Host smart-850c48d6-a3b9-43a4-960e-89ca5af2ac93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702078702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1702078702
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.3457236335
Short name T130
Test name
Test status
Simulation time 1196991596 ps
CPU time 6.1 seconds
Started Jun 05 04:21:14 PM PDT 24
Finished Jun 05 04:21:21 PM PDT 24
Peak memory 200004 kb
Host smart-4b5c55a9-0fe6-4320-9dd2-161801d5f310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457236335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3457236335
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.2744767776
Short name T188
Test name
Test status
Simulation time 83697790468 ps
CPU time 1082.07 seconds
Started Jun 05 04:21:16 PM PDT 24
Finished Jun 05 04:39:19 PM PDT 24
Peak memory 200212 kb
Host smart-f9513e7a-f774-4b10-81cb-e6b2dc8441cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744767776 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.2744767776
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.2461132359
Short name T562
Test name
Test status
Simulation time 51537436 ps
CPU time 1.11 seconds
Started Jun 05 04:21:15 PM PDT 24
Finished Jun 05 04:21:17 PM PDT 24
Peak memory 199900 kb
Host smart-63097c70-0e41-416c-94dd-8424ee879e2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461132359 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.2461132359
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.3584278683
Short name T504
Test name
Test status
Simulation time 132164921563 ps
CPU time 557.49 seconds
Started Jun 05 04:21:15 PM PDT 24
Finished Jun 05 04:30:33 PM PDT 24
Peak memory 200080 kb
Host smart-00d6645b-cb77-47c9-a859-a53128324760
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584278683 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.3584278683
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.160491567
Short name T274
Test name
Test status
Simulation time 9752260319 ps
CPU time 48.2 seconds
Started Jun 05 04:21:17 PM PDT 24
Finished Jun 05 04:22:06 PM PDT 24
Peak memory 200192 kb
Host smart-21f5e0ee-1742-4ac1-8bae-8f49ec0c0f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160491567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.160491567
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1536686851
Short name T165
Test name
Test status
Simulation time 14181296 ps
CPU time 0.6 seconds
Started Jun 05 04:21:18 PM PDT 24
Finished Jun 05 04:21:20 PM PDT 24
Peak memory 195980 kb
Host smart-95de0865-84ac-40ba-9a9c-e4d36a32a0a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536686851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1536686851
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1698745743
Short name T44
Test name
Test status
Simulation time 3639352546 ps
CPU time 39.24 seconds
Started Jun 05 04:21:19 PM PDT 24
Finished Jun 05 04:21:59 PM PDT 24
Peak memory 216436 kb
Host smart-0c65d663-540b-4fab-b535-9a93d04eae4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1698745743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1698745743
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3695116790
Short name T35
Test name
Test status
Simulation time 1899721244 ps
CPU time 25.76 seconds
Started Jun 05 04:21:17 PM PDT 24
Finished Jun 05 04:21:43 PM PDT 24
Peak memory 200088 kb
Host smart-16bf8937-6f0d-4eb5-a7b5-928b601ba1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695116790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3695116790
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.643919177
Short name T544
Test name
Test status
Simulation time 27331075454 ps
CPU time 680.37 seconds
Started Jun 05 04:21:16 PM PDT 24
Finished Jun 05 04:32:38 PM PDT 24
Peak memory 686408 kb
Host smart-6ff6fe81-3227-4919-b3b1-5493754efd92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=643919177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.643919177
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3672565654
Short name T560
Test name
Test status
Simulation time 13427573043 ps
CPU time 48.94 seconds
Started Jun 05 04:21:18 PM PDT 24
Finished Jun 05 04:22:08 PM PDT 24
Peak memory 200112 kb
Host smart-c93d3345-24bc-4456-bee9-2d945987d7f8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672565654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3672565654
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3982337287
Short name T155
Test name
Test status
Simulation time 4287046294 ps
CPU time 79.11 seconds
Started Jun 05 04:21:14 PM PDT 24
Finished Jun 05 04:22:34 PM PDT 24
Peak memory 200128 kb
Host smart-9a9628f8-ef53-4584-950d-3940c87a4396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982337287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3982337287
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.651301420
Short name T239
Test name
Test status
Simulation time 185811707 ps
CPU time 1.75 seconds
Started Jun 05 04:21:14 PM PDT 24
Finished Jun 05 04:21:17 PM PDT 24
Peak memory 200100 kb
Host smart-d1bdddfa-a588-44e7-a367-d7269a828400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651301420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.651301420
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.3143593071
Short name T104
Test name
Test status
Simulation time 2679297311 ps
CPU time 32.45 seconds
Started Jun 05 04:21:19 PM PDT 24
Finished Jun 05 04:21:53 PM PDT 24
Peak memory 216460 kb
Host smart-93747f28-48e8-4f7a-b56a-98a3b8dd7899
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143593071 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3143593071
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.3563370793
Short name T121
Test name
Test status
Simulation time 30646587 ps
CPU time 1.07 seconds
Started Jun 05 04:21:19 PM PDT 24
Finished Jun 05 04:21:21 PM PDT 24
Peak memory 199888 kb
Host smart-db1c94c6-9d39-4205-bff6-7b6eebcc0f3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563370793 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.3563370793
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.3041220208
Short name T396
Test name
Test status
Simulation time 36077723108 ps
CPU time 489.59 seconds
Started Jun 05 04:21:15 PM PDT 24
Finished Jun 05 04:29:25 PM PDT 24
Peak memory 200088 kb
Host smart-92fdbf36-3e01-4097-866d-fed0a7bfb385
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041220208 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.3041220208
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.794853681
Short name T60
Test name
Test status
Simulation time 11212594588 ps
CPU time 78.43 seconds
Started Jun 05 04:21:15 PM PDT 24
Finished Jun 05 04:22:34 PM PDT 24
Peak memory 200156 kb
Host smart-8740a8b0-0f98-422b-b5c3-45044debf5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794853681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.794853681
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.684493477
Short name T358
Test name
Test status
Simulation time 13819038 ps
CPU time 0.61 seconds
Started Jun 05 04:21:27 PM PDT 24
Finished Jun 05 04:21:28 PM PDT 24
Peak memory 195628 kb
Host smart-e6dedbbc-d336-42c3-9dd9-62a2ec75c955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684493477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.684493477
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2419930869
Short name T285
Test name
Test status
Simulation time 961813831 ps
CPU time 54.98 seconds
Started Jun 05 04:21:18 PM PDT 24
Finished Jun 05 04:22:14 PM PDT 24
Peak memory 222616 kb
Host smart-d57cbf3d-654f-43a0-83a4-3e58784f704b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2419930869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2419930869
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2637264696
Short name T176
Test name
Test status
Simulation time 5897520874 ps
CPU time 23.79 seconds
Started Jun 05 04:21:16 PM PDT 24
Finished Jun 05 04:21:40 PM PDT 24
Peak memory 200144 kb
Host smart-0f1fe1e0-7f46-4962-8476-6669fad97daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637264696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2637264696
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.939626050
Short name T324
Test name
Test status
Simulation time 17759128483 ps
CPU time 1259.36 seconds
Started Jun 05 04:21:16 PM PDT 24
Finished Jun 05 04:42:17 PM PDT 24
Peak memory 728948 kb
Host smart-b5ce9084-ec58-4383-9f6d-c56a6e8ec805
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=939626050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.939626050
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.491623596
Short name T536
Test name
Test status
Simulation time 46831041478 ps
CPU time 120.51 seconds
Started Jun 05 04:21:16 PM PDT 24
Finished Jun 05 04:23:18 PM PDT 24
Peak memory 200080 kb
Host smart-465be0af-3999-4094-a068-8024801675d9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491623596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.491623596
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.4224283266
Short name T197
Test name
Test status
Simulation time 39965775080 ps
CPU time 138.84 seconds
Started Jun 05 04:21:16 PM PDT 24
Finished Jun 05 04:23:36 PM PDT 24
Peak memory 200144 kb
Host smart-f232c9d3-4b6d-4b92-aba7-b4439a986bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224283266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.4224283266
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1898995472
Short name T545
Test name
Test status
Simulation time 85099296 ps
CPU time 1.93 seconds
Started Jun 05 04:21:18 PM PDT 24
Finished Jun 05 04:21:22 PM PDT 24
Peak memory 200104 kb
Host smart-4182cafc-d8b8-4b05-ac0b-a01f76ff4b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898995472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1898995472
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1755974023
Short name T377
Test name
Test status
Simulation time 78689573553 ps
CPU time 1534.55 seconds
Started Jun 05 04:21:21 PM PDT 24
Finished Jun 05 04:46:57 PM PDT 24
Peak memory 348376 kb
Host smart-a595f0db-b649-4c19-b5c2-f1afae575728
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755974023 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1755974023
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.4215204885
Short name T215
Test name
Test status
Simulation time 32777379 ps
CPU time 1.19 seconds
Started Jun 05 04:21:15 PM PDT 24
Finished Jun 05 04:21:17 PM PDT 24
Peak memory 200064 kb
Host smart-ba5333cb-aec3-412d-89c5-a2b5f24a4f52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215204885 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.4215204885
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.225331995
Short name T198
Test name
Test status
Simulation time 114189679707 ps
CPU time 535.14 seconds
Started Jun 05 04:21:15 PM PDT 24
Finished Jun 05 04:30:11 PM PDT 24
Peak memory 200288 kb
Host smart-74e7062c-9fff-4cec-9b73-82170ee32f79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225331995 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.225331995
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.2619630823
Short name T463
Test name
Test status
Simulation time 3503415131 ps
CPU time 14.63 seconds
Started Jun 05 04:21:15 PM PDT 24
Finished Jun 05 04:21:31 PM PDT 24
Peak memory 200344 kb
Host smart-5f84d025-48e1-47a3-b9c2-af6276c80008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619630823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2619630823
Directory /workspace/9.hmac_wipe_secret/latest
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