Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15398367	1			T1	11036		T2	316		T3	958
all_values[1]	15398367	1			T1	11036		T2	316		T3	958
all_values[2]	15398367	1			T1	11036		T2	316		T3	958

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

117344

1

T1

423

T2

2

T4

1682

auto[1]

46077757

1

T1

32685

T2

946

T3

2874

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38456654

1

T1

30231

T2

900

T3

2589

auto[1]

7738447

1

T1

2877

T2

48

T3

285

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	37226	1			T17	713		T40	83		T18	94
all_values[0]	auto[0]	auto[1]	415	1			T4	1		T40	4		T7	4
all_values[0]	auto[1]	auto[0]	15320760	1			T1	11010		T2	292		T3	955
all_values[0]	auto[1]	auto[1]	39966	1			T1	26		T2	24		T3	3
all_values[1]	auto[0]	auto[0]	38787	1			T1	423		T4	1676		T7	85
all_values[1]	auto[0]	auto[1]	217	1			T4	2		T23	2		T50	4
all_values[1]	auto[1]	auto[0]	15358981	1			T1	10613		T2	316		T3	958
all_values[1]	auto[1]	auto[1]	382	1			T4	4		T15	1		T7	2
all_values[2]	auto[0]	auto[0]	20472	1			T4	3		T7	2923		T82	2
all_values[2]	auto[0]	auto[1]	20227	1			T2	2		T7	3324		T23	561
all_values[2]	auto[1]	auto[0]	7680428	1			T1	8185		T2	292		T3	676
all_values[2]	auto[1]	auto[1]	7677240	1			T1	2851		T2	22		T3	282