Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
18.62	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	50	14	21.88
Crosses	124	103	21	16.94

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	61	49	12	19.67	100	1	1	0
msg_len_upper_cp	1	1	0	0.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	122	101	21	17.21	100	1	1	0
msg_len_upper_cross	2	2	0	0.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

136790

1

T1

32

T2

22

T3

2

auto[1]

108350

1

T1

26

T2

20

T3

2

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	61	49	12	19.67

User Defined Bins for msg_len_lower_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto_lens[1]	0	1	1
auto_lens[2]	0	1	1
auto_lens[3]	0	1	1
auto_lens[4]	0	1	1
auto_lens[5]	0	1	1
auto_lens[6]	0	1	1
auto_lens[7]	0	1	1
auto_lens[8]	0	1	1
auto_lens[9]	0	1	1
auto_lens[10]	0	1	1
auto_lens[11]	0	1	1
auto_lens[12]	0	1	1
auto_lens[13]	0	1	1
auto_lens[14]	0	1	1
auto_lens[15]	0	1	1
auto_lens[16]	0	1	1
auto_lens[17]	0	1	1
auto_lens[18]	0	1	1
auto_lens[19]	0	1	1
auto_lens[20]	0	1	1
auto_lens[21]	0	1	1
auto_lens[22]	0	1	1
auto_lens[23]	0	1	1
auto_lens[24]	0	1	1
auto_lens[25]	0	1	1
auto_lens[26]	0	1	1
auto_lens[27]	0	1	1
auto_lens[28]	0	1	1
auto_lens[29]	0	1	1
auto_lens[30]	0	1	1
auto_lens[31]	0	1	1
auto_lens[32]	0	1	1
auto_lens[33]	0	1	1
auto_lens[34]	0	1	1
auto_lens[35]	0	1	1
auto_lens[36]	0	1	1
auto_lens[37]	0	1	1
auto_lens[38]	0	1	1
auto_lens[39]	0	1	1
auto_lens[40]	0	1	1
auto_lens[41]	0	1	1
auto_lens[42]	0	1	1
auto_lens[43]	0	1	1
auto_lens[44]	0	1	1
auto_lens[45]	0	1	1
auto_lens[46]	0	1	1
auto_lens[47]	0	1	1
auto_lens[48]	0	1	1
auto_lens[49]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto_lens[0]	114966	1			T1	26		T2	20		T3	1
len_2049	14	1			T24	1		T101	1		T102	1
len_2048	87	1			T4	2		T7	5		T23	1
len_2047	2	1			T103	2		-	-		-	-
len_1025	15	1			T4	1		T7	2		T104	2
len_1024	152	1			T4	4		T7	7		T23	2
len_1023	1	1			T105	1		-	-		-	-
len_513	21	1			T106	3		T107	13		T108	2
len_512	173	1			T4	4		T7	6		T23	2
len_511	6	1			T104	2		T109	1		T110	3
len_1	1360	1			T4	8		T6	2		T7	32
len_0	5773	1			T1	3		T2	1		T3	1

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for msg_len_upper_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
len_upper	0	1	1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	122	101	21	17.21	101

Automatically Generated Cross Bins for msg_len_lower_cross

Uncovered bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto_lens[1] , auto_lens[2] , auto_lens[3] , auto_lens[4] , auto_lens[5] , auto_lens[6] , auto_lens[7] , auto_lens[8] , auto_lens[9] , auto_lens[10] , auto_lens[11] , auto_lens[12] , auto_lens[13] , auto_lens[14] , auto_lens[15] , auto_lens[16] , auto_lens[17] , auto_lens[18] , auto_lens[19] , auto_lens[20] , auto_lens[21] , auto_lens[22] , auto_lens[23] , auto_lens[24] , auto_lens[25] , auto_lens[26] , auto_lens[27] , auto_lens[28] , auto_lens[29] , auto_lens[30] , auto_lens[31] , auto_lens[32] , auto_lens[33] , auto_lens[34] , auto_lens[35] , auto_lens[36] , auto_lens[37] , auto_lens[38] , auto_lens[39] , auto_lens[40] , auto_lens[41] , auto_lens[42] , auto_lens[43] , auto_lens[44] , auto_lens[45] , auto_lens[46] , auto_lens[47] , auto_lens[48] , auto_lens[49]]	--	--	49
[auto[0]]	[len_2047]	0	1	1
[auto[0]]	[len_513]	0	1	1
[auto[1]]	[auto_lens[1] , auto_lens[2] , auto_lens[3] , auto_lens[4] , auto_lens[5] , auto_lens[6] , auto_lens[7] , auto_lens[8] , auto_lens[9] , auto_lens[10] , auto_lens[11] , auto_lens[12] , auto_lens[13] , auto_lens[14] , auto_lens[15] , auto_lens[16] , auto_lens[17] , auto_lens[18] , auto_lens[19] , auto_lens[20] , auto_lens[21] , auto_lens[22] , auto_lens[23] , auto_lens[24] , auto_lens[25] , auto_lens[26] , auto_lens[27] , auto_lens[28] , auto_lens[29] , auto_lens[30] , auto_lens[31] , auto_lens[32] , auto_lens[33] , auto_lens[34] , auto_lens[35] , auto_lens[36] , auto_lens[37] , auto_lens[38] , auto_lens[39] , auto_lens[40] , auto_lens[41] , auto_lens[42] , auto_lens[43] , auto_lens[44] , auto_lens[45] , auto_lens[46] , auto_lens[47] , auto_lens[48] , auto_lens[49]]	--	--	49
[auto[1]]	[len_1023]	0	1	1

Covered bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto_lens[0]	65471	1			T1	16		T2	11		T3	1
auto[0]	len_2049	6	1			T101	1		T111	2		T112	3
auto[0]	len_2048	52	1			T4	1		T7	4		T74	2
auto[0]	len_1025	4	1			T113	2		T71	2		-	-
auto[0]	len_1024	83	1			T4	2		T7	4		T74	3
auto[0]	len_1023	1	1			T105	1		-	-		-	-
auto[0]	len_512	104	1			T4	3		T7	3		T23	1
auto[0]	len_511	4	1			T109	1		T110	3		-	-
auto[0]	len_1	179	1			T4	3		T6	2		T23	3
auto[0]	len_0	2491	1			T5	1		T4	533		T17	5
auto[1]	auto_lens[0]	49495	1			T1	10		T2	9		T5	16
auto[1]	len_2049	8	1			T24	1		T102	1		T112	1
auto[1]	len_2048	35	1			T4	1		T7	1		T23	1
auto[1]	len_2047	2	1			T103	2		-	-		-	-
auto[1]	len_1025	11	1			T4	1		T7	2		T104	2
auto[1]	len_1024	69	1			T4	2		T7	3		T23	2
auto[1]	len_513	21	1			T106	3		T107	13		T108	2
auto[1]	len_512	69	1			T4	1		T7	3		T23	1
auto[1]	len_511	2	1			T104	2		-	-		-	-
auto[1]	len_1	1181	1			T4	5		T7	32		T81	6
auto[1]	len_0	3282	1			T1	3		T2	1		T3	1

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	2	0	0.00	2

Automatically Generated Cross Bins for msg_len_upper_cross

Uncovered bins

hmac_en	msg_len_upper_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	2