Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv



Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 18 0 18 100.00
Crosses 96 0 96 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 16 0 16 100.00 100 1 1 0
fifo_full_cross 16 0 16 100.00 100 1 1 0
fifo_depth_cross 64 0 64 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7065476 1 T1 5342 T2 15 T3 463
auto[1] 2799064 1 T1 5412 T2 14 T3 490



Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2779675 1 T1 4933 T2 15 T3 490
auto[1] 7084865 1 T1 5821 T2 14 T3 463



Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5984064 1 T1 6793 T2 13 T3 672
auto[1] 3880476 1 T1 3961 T2 16 T3 281



Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 7979700 1 T1 6880 T2 12 T3 649
fifo_depth[1] 313499 1 T1 372 T3 29 T5 244
fifo_depth[2] 237434 1 T1 382 T3 39 T5 111
fifo_depth[3] 181672 1 T1 402 T3 31 T5 45
fifo_depth[4] 152393 1 T1 397 T3 30 T5 18
fifo_depth[5] 129061 1 T1 364 T3 31 T5 2
fifo_depth[6] 121584 1 T1 362 T3 30 T5 1
fifo_depth[7] 107568 1 T1 367 T3 28 T4 2929



Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1884840 1 T1 3874 T2 17 T3 304
auto[1] 7979700 1 T1 6880 T2 12 T3 649



Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9847305 1 T1 10754 T2 28 T3 953
auto[1] 17235 1 T2 1 T4 1554 T15 80



Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] 123499 1 T1 117 T2 3 T5 108
auto[0] auto[0] auto[0] auto[1] 117017 1 T1 879 T2 4 T3 134
auto[0] auto[0] auto[1] auto[0] 700652 1 T1 357 T2 2 T3 170
auto[0] auto[0] auto[1] auto[1] 109238 1 T1 1003 T2 1 T5 66
auto[0] auto[1] auto[0] auto[0] 214163 1 T1 512 T2 2 T5 46
auto[0] auto[1] auto[0] auto[1] 199403 1 T1 381 T2 1 T4 8063
auto[0] auto[1] auto[1] auto[0] 211343 1 T1 593 T2 2 T5 11
auto[0] auto[1] auto[1] auto[1] 209525 1 T1 32 T2 2 T5 82
auto[1] auto[0] auto[0] auto[0] 303213 1 T1 816 T5 1496 T4 2408
auto[1] auto[0] auto[0] auto[1] 283127 1 T1 1087 T2 1 T3 75
auto[1] auto[0] auto[1] auto[0] 4042094 1 T1 1099 T3 293 T5 1451
auto[1] auto[0] auto[1] auto[1] 305224 1 T1 1435 T2 2 T5 1325
auto[1] auto[1] auto[0] auto[0] 733837 1 T1 576 T2 2 T5 1827
auto[1] auto[1] auto[0] auto[1] 805416 1 T1 565 T2 2 T3 281
auto[1] auto[1] auto[1] auto[0] 736675 1 T1 1272 T2 4 T5 106
auto[1] auto[1] auto[1] auto[1] 770114 1 T1 30 T2 1 T5 868



Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] 423091 1 T1 933 T2 3 T5 1604
auto[0] auto[0] auto[0] auto[1] 398166 1 T1 1966 T2 5 T3 209
auto[0] auto[0] auto[1] auto[0] 4740866 1 T1 1456 T2 1 T3 463
auto[0] auto[0] auto[1] auto[1] 412304 1 T1 2438 T2 3 T5 1391
auto[0] auto[1] auto[0] auto[0] 947110 1 T1 1088 T2 4 T5 1873
auto[0] auto[1] auto[0] auto[1] 1002524 1 T1 946 T2 3 T3 281
auto[0] auto[1] auto[1] auto[0] 945409 1 T1 1865 T2 6 T5 117
auto[0] auto[1] auto[1] auto[1] 977835 1 T1 62 T2 3 T5 950
auto[1] auto[0] auto[0] auto[0] 3621 1 T4 285 T15 14 T19 1
auto[1] auto[0] auto[0] auto[1] 1978 1 T4 232 T15 18 T19 1
auto[1] auto[0] auto[1] auto[0] 1880 1 T2 1 T4 332 T7 52
auto[1] auto[0] auto[1] auto[1] 2158 1 T4 78 T15 2 T7 36
auto[1] auto[1] auto[0] auto[0] 890 1 T4 6 T7 28 T127 13
auto[1] auto[1] auto[0] auto[1] 2295 1 T4 69 T15 44 T7 47
auto[1] auto[1] auto[1] auto[0] 2609 1 T4 6 T15 2 T7 4
auto[1] auto[1] auto[1] auto[1] 1804 1 T4 546 T127 35 T44 1



Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] 303213 1 T1 816 T5 1496 T4 2408
fifo_depth[0] auto[0] auto[0] auto[1] 283127 1 T1 1087 T2 1 T3 75
fifo_depth[0] auto[0] auto[1] auto[0] 4042094 1 T1 1099 T3 293 T5 1451
fifo_depth[0] auto[0] auto[1] auto[1] 305224 1 T1 1435 T2 2 T5 1325
fifo_depth[0] auto[1] auto[0] auto[0] 733837 1 T1 576 T2 2 T5 1827
fifo_depth[0] auto[1] auto[0] auto[1] 805416 1 T1 565 T2 2 T3 281
fifo_depth[0] auto[1] auto[1] auto[0] 736675 1 T1 1272 T2 4 T5 106
fifo_depth[0] auto[1] auto[1] auto[1] 770114 1 T1 30 T2 1 T5 868
fifo_depth[1] auto[0] auto[0] auto[0] 10317 1 T1 12 T5 76 T4 144
fifo_depth[1] auto[0] auto[0] auto[1] 9978 1 T1 85 T3 13 T5 3
fifo_depth[1] auto[0] auto[1] auto[0] 195604 1 T1 31 T3 16 T5 56
fifo_depth[1] auto[0] auto[1] auto[1] 10050 1 T1 101 T5 30 T4 9
fifo_depth[1] auto[1] auto[0] auto[0] 21826 1 T1 58 T5 24 T4 153
fifo_depth[1] auto[1] auto[0] auto[1] 21373 1 T1 32 T4 255 T15 5
fifo_depth[1] auto[1] auto[1] auto[0] 22400 1 T1 50 T5 5 T4 278
fifo_depth[1] auto[1] auto[1] auto[1] 21951 1 T1 3 T5 50 T4 52
fifo_depth[2] auto[0] auto[0] auto[0] 9274 1 T1 15 T5 17 T4 161
fifo_depth[2] auto[0] auto[0] auto[1] 9045 1 T1 84 T3 18 T5 1
fifo_depth[2] auto[0] auto[1] auto[0] 128722 1 T1 31 T3 21 T5 32
fifo_depth[2] auto[0] auto[1] auto[1] 8699 1 T1 112 T5 22 T4 16
fifo_depth[2] auto[1] auto[0] auto[0] 20473 1 T1 51 T5 14 T4 207
fifo_depth[2] auto[1] auto[0] auto[1] 19855 1 T1 37 T4 256 T15 13
fifo_depth[2] auto[1] auto[1] auto[0] 20796 1 T1 48 T5 5 T4 309
fifo_depth[2] auto[1] auto[1] auto[1] 20570 1 T1 4 T5 20 T4 55
fifo_depth[3] auto[0] auto[0] auto[0] 7347 1 T1 5 T5 11 T4 96
fifo_depth[3] auto[0] auto[0] auto[1] 7354 1 T1 87 T3 13 T5 1
fifo_depth[3] auto[0] auto[1] auto[0] 88381 1 T1 36 T3 18 T5 8
fifo_depth[3] auto[0] auto[1] auto[1] 6982 1 T1 116 T5 10 T4 11
fifo_depth[3] auto[1] auto[0] auto[0] 17797 1 T1 66 T5 6 T4 216
fifo_depth[3] auto[1] auto[0] auto[1] 16983 1 T1 33 T4 274 T15 11
fifo_depth[3] auto[1] auto[1] auto[0] 18287 1 T1 56 T4 261 T16 47
fifo_depth[3] auto[1] auto[1] auto[1] 18541 1 T1 3 T5 9 T4 41
fifo_depth[4] auto[0] auto[0] auto[0] 7216 1 T1 12 T5 4 T4 71
fifo_depth[4] auto[0] auto[0] auto[1] 7260 1 T1 97 T3 14 T4 147
fifo_depth[4] auto[0] auto[1] auto[0] 62136 1 T1 43 T3 16 T5 5
fifo_depth[4] auto[0] auto[1] auto[1] 7062 1 T1 104 T5 4 T4 22
fifo_depth[4] auto[1] auto[0] auto[0] 17402 1 T1 47 T5 2 T4 354
fifo_depth[4] auto[1] auto[0] auto[1] 15972 1 T1 35 T4 277 T15 48
fifo_depth[4] auto[1] auto[1] auto[0] 17523 1 T1 56 T5 1 T4 323
fifo_depth[4] auto[1] auto[1] auto[1] 17822 1 T1 3 T5 2 T4 115
fifo_depth[5] auto[0] auto[0] auto[0] 5695 1 T1 9 T4 58 T15 9
fifo_depth[5] auto[0] auto[0] auto[1] 6199 1 T1 92 T3 20 T4 61
fifo_depth[5] auto[0] auto[1] auto[0] 49138 1 T1 28 T3 11 T5 2
fifo_depth[5] auto[0] auto[1] auto[1] 5853 1 T1 91 T4 13 T15 84
fifo_depth[5] auto[1] auto[0] auto[0] 15624 1 T1 53 T4 212 T16 35
fifo_depth[5] auto[1] auto[0] auto[1] 14295 1 T1 42 T4 279 T15 45
fifo_depth[5] auto[1] auto[1] auto[0] 16052 1 T1 47 T4 264 T16 49
fifo_depth[5] auto[1] auto[1] auto[1] 16205 1 T1 2 T4 30 T16 129
fifo_depth[6] auto[0] auto[0] auto[0] 5994 1 T1 9 T4 71 T15 9
fifo_depth[6] auto[0] auto[0] auto[1] 6168 1 T1 89 T3 17 T4 137
fifo_depth[6] auto[0] auto[1] auto[0] 41399 1 T1 25 T3 13 T4 2615
fifo_depth[6] auto[0] auto[1] auto[1] 5766 1 T1 93 T4 19 T15 61
fifo_depth[6] auto[1] auto[0] auto[0] 15593 1 T1 57 T4 205 T16 43
fifo_depth[6] auto[1] auto[0] auto[1] 14669 1 T1 35 T4 277 T15 10
fifo_depth[6] auto[1] auto[1] auto[0] 15832 1 T1 53 T4 320 T15 2
fifo_depth[6] auto[1] auto[1] auto[1] 16163 1 T1 1 T5 1 T4 92
fifo_depth[7] auto[0] auto[0] auto[0] 4980 1 T1 8 T4 42 T15 8
fifo_depth[7] auto[0] auto[0] auto[1] 5543 1 T1 88 T3 13 T4 84
fifo_depth[7] auto[0] auto[1] auto[0] 33167 1 T1 32 T3 15 T4 2035
fifo_depth[7] auto[0] auto[1] auto[1] 5501 1 T1 92 T4 13 T15 86
fifo_depth[7] auto[1] auto[0] auto[0] 14734 1 T1 50 T4 201 T16 32
fifo_depth[7] auto[1] auto[0] auto[1] 13361 1 T1 35 T4 287 T15 44
fifo_depth[7] auto[1] auto[1] auto[0] 15097 1 T1 58 T4 240 T16 45
fifo_depth[7] auto[1] auto[1] auto[1] 15185 1 T1 4 T4 27 T16 134

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