Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 0 7 100.00
Crosses 12 0 12 100.00


Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr_pin 3 0 3 100.00 100 1 1 0
cp_intr_pin_value 4 0 4 100.00 100 1 1 0


Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_intr_pins_all_values 12 0 12 100.00 100 1 1 0


Summary for Variable cp_intr_pin

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr_pin

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] 15398367 1 T1 11036 T2 316 T3 958
all_pins[1] 15398367 1 T1 11036 T2 316 T3 958
all_pins[2] 15398367 1 T1 11036 T2 316 T3 958



Summary for Variable cp_intr_pin_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr_pin_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 38476869 1 T1 30230 T2 899 T3 2589
values[0x1] 7718232 1 T1 2878 T2 49 T3 285
transitions[0x0=>0x1] 7718000 1 T1 2878 T2 49 T3 285
transitions[0x1=>0x0] 7718017 1 T1 2878 T2 49 T3 285



Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 12 0 12 100.00


Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins
cp_intr_pincp_intr_pin_valueCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] values[0x0] 15357771 1 T1 11009 T2 289 T3 955
all_pins[0] values[0x1] 40596 1 T1 27 T2 27 T3 3
all_pins[0] transitions[0x0=>0x1] 40491 1 T1 27 T2 27 T3 3
all_pins[0] transitions[0x1=>0x0] 7677152 1 T1 2851 T2 22 T3 282
all_pins[1] values[0x0] 15397971 1 T1 11036 T2 316 T3 958
all_pins[1] values[0x1] 396 1 T4 5 T15 1 T7 4
all_pins[1] transitions[0x0=>0x1] 327 1 T4 5 T15 1 T7 4
all_pins[1] transitions[0x1=>0x0] 40527 1 T1 27 T2 27 T3 3
all_pins[2] values[0x0] 7721127 1 T1 8185 T2 294 T3 676
all_pins[2] values[0x1] 7677240 1 T1 2851 T2 22 T3 282
all_pins[2] transitions[0x0=>0x1] 7677182 1 T1 2851 T2 22 T3 282
all_pins[2] transitions[0x1=>0x0] 338 1 T4 5 T15 1 T7 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%