Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1038 1 T4 4 T23 10 T50 20
all_values[1] 1038 1 T4 4 T23 10 T50 20
all_values[2] 1038 1 T4 4 T23 10 T50 20


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1545 1 T4 4 T23 7 T50 28
auto[1] 1569 1 T4 8 T23 23 T50 32


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1068 1 T4 6 T23 10 T50 10
auto[1] 2046 1 T4 6 T23 20 T50 50


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1724 1 T4 9 T23 18 T50 26
auto[1] 1390 1 T4 3 T23 12 T50 34


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 181 1 T23 2 T50 1 T114 4
all_values[0] auto[0] auto[0] auto[1] 101 1 T50 1 T100 1 T114 1
all_values[0] auto[0] auto[1] auto[0] 181 1 T4 2 T23 4 T50 3
all_values[0] auto[0] auto[1] auto[1] 97 1 T4 1 T23 1 T50 3
all_values[0] auto[1] auto[0] auto[1] 244 1 T23 1 T50 7 T100 3
all_values[0] auto[1] auto[1] auto[1] 234 1 T4 1 T23 2 T50 5
all_values[1] auto[0] auto[0] auto[0] 160 1 T50 2 T114 2 T8 2
all_values[1] auto[0] auto[0] auto[1] 116 1 T4 1 T50 2 T114 4
all_values[1] auto[0] auto[1] auto[0] 156 1 T23 1 T100 1 T114 2
all_values[1] auto[0] auto[1] auto[1] 149 1 T4 1 T23 4 T50 5
all_values[1] auto[1] auto[0] auto[1] 221 1 T23 2 T50 3 T100 2
all_values[1] auto[1] auto[1] auto[1] 236 1 T4 2 T23 3 T50 8
all_values[2] auto[0] auto[0] auto[0] 208 1 T4 3 T50 3 T100 2
all_values[2] auto[0] auto[0] auto[1] 101 1 T23 2 T50 4 T114 1
all_values[2] auto[0] auto[1] auto[0] 182 1 T4 1 T23 3 T50 1
all_values[2] auto[0] auto[1] auto[1] 92 1 T23 1 T50 1 T100 1
all_values[2] auto[1] auto[0] auto[1] 213 1 T50 5 T114 9 T8 1
all_values[2] auto[1] auto[1] auto[1] 242 1 T23 4 T50 6 T100 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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