Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
60.78	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	4	16	80.00
Crosses	82	36	46	56.10

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	2	3	60.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	1	6	85.71	100	1	1	0
sha_en	2	1	1	50.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	8	0	8	100.00	100	1	1	0
hmac_dis_x_sha_en	4	2	2	50.00	100	1	1	0
key_x_digest_mismatch	35	17	18	51.43	100	1	1	0
key_length_x_digest_size	35	17	18	51.43	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	2	3	60.00

User Defined Bins for digest_size

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
sha2_invalid	0	1	1
sha2_none	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_512	4642	1			T1	5		T2	8		T5	3
sha2_384	4811	1			T1	8		T2	7		T3	1
sha2_256	27713	1			T1	8		T2	2		T3	1

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30307

1

T1

9

T2

9

T3

1

auto[1]

6859

1

T1

12

T2

8

T3

1

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6868

1

T1

11

T2

10

T3

1

auto[1]

30298

1

T1

10

T2

7

T3

1

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

7457

1

T1

8

T2

7

T5

9

disabled

29709

1

T1

13

T2

10

T3

2

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for key_length

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
key_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	1203	1			T1	2		T5	3		T4	27
key_1024	2188	1			T1	5		T2	1		T3	1
key_512	2571	1			T1	4		T2	3		T5	5
key_384	2643	1			T1	6		T2	6		T5	3
key_256	25945	1			T1	4		T2	5		T5	2
key_128	2616	1			T2	2		T3	1		T5	2

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for sha_en

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
disabled	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

37166

1

T1

21

T2

17

T3

2

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
enabled	auto[0]	auto[0]	1719	1			T1	3		T2	2		T5	4
enabled	auto[0]	auto[1]	1746	1			T1	2		T2	1		T4	21
enabled	auto[1]	auto[0]	2263	1			T1	1		T2	2		T5	1
enabled	auto[1]	auto[1]	1729	1			T1	2		T2	2		T5	4
disabled	auto[0]	auto[0]	1717	1			T1	1		T2	3		T5	2
disabled	auto[0]	auto[1]	1686	1			T1	5		T2	4		T3	1
disabled	auto[1]	auto[0]	24608	1			T1	4		T2	2		T3	1
disabled	auto[1]	auto[1]	1698	1			T1	3		T2	1		T5	1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	2	2	50.00	2
Automatically Generated Cross Bins	3	2	1	33.33	2
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Element holes

hmac_en	sha_en	COUNT	AT LEAST	NUMBER	STATUS
*	[disabled]	--	--	2

Covered bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

7457

1

T1

8

T2

7

T5

9

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

29709

1

T1

13

T2

10

T3

2

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	17	18	51.43	17
Automatically Generated Cross Bins	34	17	17	50.00	17
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid , sha2_none]	--	--	12

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_512	407	1			T1	1		T4	11		T19	2
key_none	sha2_384	373	1			T1	1		T5	1		T4	7
key_none	sha2_256	423	1			T5	2		T4	9		T15	1
key_1024	sha2_512	863	1			T1	1		T2	1		T4	19
key_1024	sha2_384	951	1			T1	2		T3	1		T4	9
key_512	sha2_512	837	1			T2	2		T5	1		T4	6
key_512	sha2_384	849	1			T1	2		T2	1		T5	1
key_512	sha2_256	885	1			T1	2		T5	3		T4	19
key_384	sha2_512	902	1			T1	3		T2	2		T4	16
key_384	sha2_384	886	1			T1	1		T2	2		T5	2
key_384	sha2_256	855	1			T1	2		T2	2		T5	1
key_256	sha2_512	810	1			T2	2		T5	2		T4	12
key_256	sha2_384	878	1			T1	2		T2	3		T4	16
key_256	sha2_256	24257	1			T1	2		T4	416		T15	1
key_128	sha2_512	823	1			T2	1		T4	12		T16	4
key_128	sha2_384	874	1			T2	1		T4	14		T15	1
key_128	sha2_256	919	1			T3	1		T5	2		T4	15

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

374

1

T1

2

T4

9

T15

2

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	17	18	51.43	17

Automatically Generated Cross Bins for key_length_x_digest_size

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid , sha2_none]	--	--	12

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_512	407	1			T1	1		T4	11		T19	2
key_none	sha2_384	373	1			T1	1		T5	1		T4	7
key_none	sha2_256	423	1			T5	2		T4	9		T15	1
key_1024	sha2_512	863	1			T1	1		T2	1		T4	19
key_1024	sha2_384	951	1			T1	2		T3	1		T4	9
key_1024	sha2_256	374	1			T1	2		T4	9		T15	2
key_512	sha2_512	837	1			T2	2		T5	1		T4	6
key_512	sha2_384	849	1			T1	2		T2	1		T5	1
key_512	sha2_256	885	1			T1	2		T5	3		T4	19
key_384	sha2_512	902	1			T1	3		T2	2		T4	16
key_384	sha2_384	886	1			T1	1		T2	2		T5	2
key_384	sha2_256	855	1			T1	2		T2	2		T5	1
key_256	sha2_512	810	1			T2	2		T5	2		T4	12
key_256	sha2_384	878	1			T1	2		T2	3		T4	16
key_256	sha2_256	24257	1			T1	2		T4	416		T15	1
key_128	sha2_512	823	1			T2	1		T4	12		T16	4
key_128	sha2_384	874	1			T2	1		T4	14		T15	1
key_128	sha2_256	919	1			T3	1		T5	2		T4	15