Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.90 94.82 92.25 100.00 74.36 89.38 99.49 72.04


Total test records in report: 731
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T541 /workspace/coverage/default/38.hmac_long_msg.1367979762 Jun 06 01:07:39 PM PDT 24 Jun 06 01:09:48 PM PDT 24 24199224115 ps
T542 /workspace/coverage/default/24.hmac_smoke.1605374234 Jun 06 01:06:40 PM PDT 24 Jun 06 01:06:44 PM PDT 24 131066822 ps
T543 /workspace/coverage/default/48.hmac_test_sha_vectors.605125456 Jun 06 01:08:17 PM PDT 24 Jun 06 01:16:46 PM PDT 24 101178121812 ps
T544 /workspace/coverage/default/46.hmac_stress_all.2052499160 Jun 06 01:08:05 PM PDT 24 Jun 06 01:09:23 PM PDT 24 1465324909 ps
T545 /workspace/coverage/default/49.hmac_stress_all.3755425702 Jun 06 01:08:12 PM PDT 24 Jun 06 01:49:26 PM PDT 24 94398681650 ps
T546 /workspace/coverage/default/19.hmac_burst_wr.2585776679 Jun 06 01:06:38 PM PDT 24 Jun 06 01:07:29 PM PDT 24 3695293585 ps
T547 /workspace/coverage/default/37.hmac_test_hmac_vectors.3469833667 Jun 06 01:07:37 PM PDT 24 Jun 06 01:07:40 PM PDT 24 108630352 ps
T548 /workspace/coverage/default/7.hmac_burst_wr.2829321609 Jun 06 01:06:11 PM PDT 24 Jun 06 01:06:15 PM PDT 24 370221608 ps
T549 /workspace/coverage/default/8.hmac_long_msg.1369703597 Jun 06 01:06:22 PM PDT 24 Jun 06 01:07:02 PM PDT 24 36199970887 ps
T550 /workspace/coverage/default/26.hmac_test_hmac_vectors.2045752454 Jun 06 01:06:47 PM PDT 24 Jun 06 01:06:50 PM PDT 24 233862381 ps
T551 /workspace/coverage/default/8.hmac_smoke.1937851736 Jun 06 01:06:11 PM PDT 24 Jun 06 01:06:13 PM PDT 24 196034781 ps
T552 /workspace/coverage/default/4.hmac_error.3569547765 Jun 06 01:06:04 PM PDT 24 Jun 06 01:08:50 PM PDT 24 4073002675 ps
T553 /workspace/coverage/default/49.hmac_test_sha_vectors.2005852868 Jun 06 01:08:14 PM PDT 24 Jun 06 01:16:22 PM PDT 24 8868106254 ps
T554 /workspace/coverage/default/41.hmac_error.2244200935 Jun 06 01:07:44 PM PDT 24 Jun 06 01:10:54 PM PDT 24 3589698448 ps
T555 /workspace/coverage/default/14.hmac_smoke.27581151 Jun 06 01:06:27 PM PDT 24 Jun 06 01:06:31 PM PDT 24 120714979 ps
T556 /workspace/coverage/default/2.hmac_error.3009360264 Jun 06 01:06:02 PM PDT 24 Jun 06 01:07:08 PM PDT 24 1206679820 ps
T557 /workspace/coverage/default/27.hmac_error.2729409108 Jun 06 01:07:00 PM PDT 24 Jun 06 01:08:08 PM PDT 24 4690272197 ps
T558 /workspace/coverage/default/5.hmac_alert_test.3779396750 Jun 06 01:06:10 PM PDT 24 Jun 06 01:06:11 PM PDT 24 51507279 ps
T559 /workspace/coverage/default/16.hmac_long_msg.2558925967 Jun 06 01:06:27 PM PDT 24 Jun 06 01:07:18 PM PDT 24 1784051374 ps
T560 /workspace/coverage/default/42.hmac_wipe_secret.459865864 Jun 06 01:07:49 PM PDT 24 Jun 06 01:08:24 PM PDT 24 811472511 ps
T561 /workspace/coverage/default/16.hmac_stress_all.3762826240 Jun 06 01:06:30 PM PDT 24 Jun 06 01:09:50 PM PDT 24 28637046742 ps
T562 /workspace/coverage/default/24.hmac_datapath_stress.552522764 Jun 06 01:06:42 PM PDT 24 Jun 06 01:22:34 PM PDT 24 3450484718 ps
T563 /workspace/coverage/default/17.hmac_test_sha_vectors.1340652658 Jun 06 01:06:28 PM PDT 24 Jun 06 01:14:23 PM PDT 24 104475532251 ps
T564 /workspace/coverage/default/26.hmac_datapath_stress.370262923 Jun 06 01:06:50 PM PDT 24 Jun 06 01:15:47 PM PDT 24 2156589521 ps
T565 /workspace/coverage/default/38.hmac_error.440297652 Jun 06 01:07:40 PM PDT 24 Jun 06 01:09:43 PM PDT 24 6587151034 ps
T566 /workspace/coverage/default/34.hmac_error.3321715191 Jun 06 01:07:25 PM PDT 24 Jun 06 01:08:24 PM PDT 24 9003937748 ps
T567 /workspace/coverage/default/29.hmac_alert_test.3539125708 Jun 06 01:07:07 PM PDT 24 Jun 06 01:07:09 PM PDT 24 135357291 ps
T568 /workspace/coverage/default/11.hmac_error.1506725422 Jun 06 01:06:24 PM PDT 24 Jun 06 01:06:56 PM PDT 24 8115763547 ps
T569 /workspace/coverage/default/34.hmac_smoke.1253506576 Jun 06 01:07:15 PM PDT 24 Jun 06 01:07:19 PM PDT 24 239586919 ps
T570 /workspace/coverage/default/2.hmac_wipe_secret.2645517186 Jun 06 01:06:01 PM PDT 24 Jun 06 01:06:32 PM PDT 24 2328850937 ps
T571 /workspace/coverage/default/6.hmac_back_pressure.4108987700 Jun 06 01:06:16 PM PDT 24 Jun 06 01:06:55 PM PDT 24 2894427454 ps
T572 /workspace/coverage/default/15.hmac_stress_all_with_rand_reset.1526397989 Jun 06 01:06:29 PM PDT 24 Jun 06 02:06:52 PM PDT 24 153910524359 ps
T573 /workspace/coverage/default/27.hmac_wipe_secret.2753177518 Jun 06 01:07:04 PM PDT 24 Jun 06 01:07:47 PM PDT 24 1065310480 ps
T574 /workspace/coverage/default/32.hmac_test_sha_vectors.344523985 Jun 06 01:07:12 PM PDT 24 Jun 06 01:14:50 PM PDT 24 15432607349 ps
T575 /workspace/coverage/default/44.hmac_back_pressure.1429742594 Jun 06 01:07:55 PM PDT 24 Jun 06 01:08:36 PM PDT 24 1398686611 ps
T576 /workspace/coverage/default/49.hmac_datapath_stress.830023335 Jun 06 01:08:11 PM PDT 24 Jun 06 01:20:36 PM PDT 24 14178540307 ps
T577 /workspace/coverage/default/44.hmac_stress_all.2769333675 Jun 06 01:07:55 PM PDT 24 Jun 06 01:07:57 PM PDT 24 103729505 ps
T71 /workspace/coverage/default/19.hmac_stress_all.3621755245 Jun 06 01:06:36 PM PDT 24 Jun 06 01:27:31 PM PDT 24 217549074807 ps
T110 /workspace/coverage/default/40.hmac_stress_all.3544592334 Jun 06 01:07:47 PM PDT 24 Jun 06 01:37:08 PM PDT 24 18359015923 ps
T103 /workspace/coverage/default/40.hmac_back_pressure.1897465385 Jun 06 01:07:39 PM PDT 24 Jun 06 01:08:27 PM PDT 24 3138374908 ps
T578 /workspace/coverage/default/24.hmac_alert_test.3001548324 Jun 06 01:06:46 PM PDT 24 Jun 06 01:06:48 PM PDT 24 13044227 ps
T579 /workspace/coverage/default/1.hmac_burst_wr.1920424147 Jun 06 01:05:59 PM PDT 24 Jun 06 01:06:48 PM PDT 24 17667746699 ps
T580 /workspace/coverage/default/47.hmac_test_sha_vectors.1036391935 Jun 06 01:08:03 PM PDT 24 Jun 06 01:17:18 PM PDT 24 120737185934 ps
T581 /workspace/coverage/default/39.hmac_burst_wr.784925570 Jun 06 01:07:39 PM PDT 24 Jun 06 01:08:03 PM PDT 24 1607481598 ps
T582 /workspace/coverage/default/36.hmac_error.1735305499 Jun 06 01:07:27 PM PDT 24 Jun 06 01:07:33 PM PDT 24 213335333 ps
T583 /workspace/coverage/default/19.hmac_alert_test.2827712363 Jun 06 01:06:42 PM PDT 24 Jun 06 01:06:45 PM PDT 24 22105920 ps
T584 /workspace/coverage/default/8.hmac_wipe_secret.2324900396 Jun 06 01:06:21 PM PDT 24 Jun 06 01:07:08 PM PDT 24 4611326807 ps
T585 /workspace/coverage/default/4.hmac_back_pressure.3661538446 Jun 06 01:06:08 PM PDT 24 Jun 06 01:07:12 PM PDT 24 4538562881 ps
T586 /workspace/coverage/default/30.hmac_test_hmac_vectors.3863640310 Jun 06 01:07:05 PM PDT 24 Jun 06 01:07:07 PM PDT 24 333907210 ps
T587 /workspace/coverage/default/7.hmac_wipe_secret.2988728545 Jun 06 01:06:11 PM PDT 24 Jun 06 01:06:56 PM PDT 24 2208548046 ps
T588 /workspace/coverage/default/9.hmac_wipe_secret.1282713817 Jun 06 01:06:16 PM PDT 24 Jun 06 01:07:10 PM PDT 24 25496031438 ps
T589 /workspace/coverage/default/45.hmac_long_msg.2498677079 Jun 06 01:07:56 PM PDT 24 Jun 06 01:09:09 PM PDT 24 13703432929 ps
T590 /workspace/coverage/default/15.hmac_stress_all.3176695521 Jun 06 01:06:29 PM PDT 24 Jun 06 01:21:21 PM PDT 24 166623614682 ps
T591 /workspace/coverage/default/41.hmac_smoke.163909391 Jun 06 01:07:44 PM PDT 24 Jun 06 01:07:57 PM PDT 24 2223248439 ps
T592 /workspace/coverage/default/8.hmac_test_sha_vectors.507773332 Jun 06 01:06:12 PM PDT 24 Jun 06 01:13:46 PM PDT 24 10085664086 ps
T593 /workspace/coverage/default/41.hmac_alert_test.69511682 Jun 06 01:07:51 PM PDT 24 Jun 06 01:07:53 PM PDT 24 43093349 ps
T594 /workspace/coverage/default/16.hmac_test_sha_vectors.1307297353 Jun 06 01:06:27 PM PDT 24 Jun 06 01:14:38 PM PDT 24 56685986576 ps
T595 /workspace/coverage/default/18.hmac_back_pressure.3778652076 Jun 06 01:06:36 PM PDT 24 Jun 06 01:06:45 PM PDT 24 2807026980 ps
T596 /workspace/coverage/default/37.hmac_wipe_secret.464850903 Jun 06 01:07:37 PM PDT 24 Jun 06 01:08:32 PM PDT 24 7700815194 ps
T597 /workspace/coverage/default/45.hmac_burst_wr.2177567183 Jun 06 01:07:55 PM PDT 24 Jun 06 01:08:08 PM PDT 24 511654986 ps
T598 /workspace/coverage/default/32.hmac_error.229328579 Jun 06 01:07:13 PM PDT 24 Jun 06 01:08:31 PM PDT 24 1349355421 ps
T599 /workspace/coverage/default/45.hmac_smoke.3364790673 Jun 06 01:07:54 PM PDT 24 Jun 06 01:08:00 PM PDT 24 519596902 ps
T600 /workspace/coverage/default/3.hmac_long_msg.2251802899 Jun 06 01:06:04 PM PDT 24 Jun 06 01:07:19 PM PDT 24 7975754816 ps
T601 /workspace/coverage/default/0.hmac_alert_test.823891379 Jun 06 01:05:59 PM PDT 24 Jun 06 01:06:01 PM PDT 24 44128780 ps
T602 /workspace/coverage/default/27.hmac_test_hmac_vectors.2394676361 Jun 06 01:06:57 PM PDT 24 Jun 06 01:06:59 PM PDT 24 251878163 ps
T603 /workspace/coverage/default/37.hmac_stress_all.513462606 Jun 06 01:07:38 PM PDT 24 Jun 06 01:29:49 PM PDT 24 164808983795 ps
T604 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.319325392 Jun 06 01:04:58 PM PDT 24 Jun 06 01:05:03 PM PDT 24 874515628 ps
T72 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1853681102 Jun 06 01:05:35 PM PDT 24 Jun 06 01:05:37 PM PDT 24 188697147 ps
T51 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.520908053 Jun 06 01:05:06 PM PDT 24 Jun 06 01:05:10 PM PDT 24 44097170 ps
T52 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.251322680 Jun 06 01:05:18 PM PDT 24 Jun 06 01:14:47 PM PDT 24 125855682904 ps
T605 /workspace/coverage/cover_reg_top/8.hmac_intr_test.2266374072 Jun 06 01:05:03 PM PDT 24 Jun 06 01:05:05 PM PDT 24 20290421 ps
T606 /workspace/coverage/cover_reg_top/34.hmac_intr_test.2723458426 Jun 06 01:05:34 PM PDT 24 Jun 06 01:05:36 PM PDT 24 13581891 ps
T53 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2654944000 Jun 06 01:04:58 PM PDT 24 Jun 06 01:05:01 PM PDT 24 47641974 ps
T55 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2074362622 Jun 06 01:05:03 PM PDT 24 Jun 06 01:18:50 PM PDT 24 55617994997 ps
T607 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2984559705 Jun 06 01:05:19 PM PDT 24 Jun 06 01:05:22 PM PDT 24 203590685 ps
T608 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2074132514 Jun 06 01:05:05 PM PDT 24 Jun 06 01:05:09 PM PDT 24 158350819 ps
T609 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3263628895 Jun 06 01:04:58 PM PDT 24 Jun 06 01:05:05 PM PDT 24 110909772 ps
T610 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3854974603 Jun 06 01:05:33 PM PDT 24 Jun 06 01:05:36 PM PDT 24 10886439 ps
T611 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1367544600 Jun 06 01:04:52 PM PDT 24 Jun 06 01:04:54 PM PDT 24 203156656 ps
T612 /workspace/coverage/cover_reg_top/36.hmac_intr_test.4253240327 Jun 06 01:05:29 PM PDT 24 Jun 06 01:05:31 PM PDT 24 10858987 ps
T613 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.475209094 Jun 06 01:05:06 PM PDT 24 Jun 06 01:05:19 PM PDT 24 1463018413 ps
T614 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2421058780 Jun 06 01:05:04 PM PDT 24 Jun 06 01:05:09 PM PDT 24 250686565 ps
T615 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.4186742276 Jun 06 01:05:08 PM PDT 24 Jun 06 01:05:15 PM PDT 24 245558200 ps
T616 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1658657057 Jun 06 01:05:06 PM PDT 24 Jun 06 01:05:10 PM PDT 24 138614755 ps
T617 /workspace/coverage/cover_reg_top/27.hmac_intr_test.3098225053 Jun 06 01:05:17 PM PDT 24 Jun 06 01:05:19 PM PDT 24 23764976 ps
T47 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2988017086 Jun 06 01:05:17 PM PDT 24 Jun 06 01:05:21 PM PDT 24 86826590 ps
T618 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1027520579 Jun 06 01:05:08 PM PDT 24 Jun 06 01:05:11 PM PDT 24 14836119 ps
T619 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1395926447 Jun 06 01:05:07 PM PDT 24 Jun 06 01:05:12 PM PDT 24 440570494 ps
T84 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1470639044 Jun 06 01:05:07 PM PDT 24 Jun 06 01:05:10 PM PDT 24 19139913 ps
T620 /workspace/coverage/cover_reg_top/17.hmac_intr_test.4182695500 Jun 06 01:05:16 PM PDT 24 Jun 06 01:05:18 PM PDT 24 15190021 ps
T621 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1736107940 Jun 06 01:04:51 PM PDT 24 Jun 06 01:05:08 PM PDT 24 4434454303 ps
T85 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2951907848 Jun 06 01:04:58 PM PDT 24 Jun 06 01:05:01 PM PDT 24 28288748 ps
T622 /workspace/coverage/cover_reg_top/9.hmac_intr_test.308535012 Jun 06 01:05:05 PM PDT 24 Jun 06 01:05:08 PM PDT 24 89171816 ps
T623 /workspace/coverage/cover_reg_top/45.hmac_intr_test.866046464 Jun 06 01:05:30 PM PDT 24 Jun 06 01:05:32 PM PDT 24 34401543 ps
T48 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1617841568 Jun 06 01:05:20 PM PDT 24 Jun 06 01:05:22 PM PDT 24 153468690 ps
T49 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2652984145 Jun 06 01:05:07 PM PDT 24 Jun 06 01:05:13 PM PDT 24 1360809257 ps
T86 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2763721543 Jun 06 01:04:54 PM PDT 24 Jun 06 01:05:00 PM PDT 24 1155032962 ps
T624 /workspace/coverage/cover_reg_top/28.hmac_intr_test.1847779748 Jun 06 01:05:21 PM PDT 24 Jun 06 01:05:23 PM PDT 24 16823049 ps
T116 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3130622886 Jun 06 01:05:04 PM PDT 24 Jun 06 01:05:08 PM PDT 24 115579163 ps
T625 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1011443292 Jun 06 01:05:30 PM PDT 24 Jun 06 01:05:33 PM PDT 24 30380496 ps
T626 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3993259421 Jun 06 01:05:17 PM PDT 24 Jun 06 01:05:20 PM PDT 24 76023880 ps
T627 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2584988283 Jun 06 01:05:05 PM PDT 24 Jun 06 01:05:09 PM PDT 24 158779672 ps
T628 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1274442775 Jun 06 01:05:30 PM PDT 24 Jun 06 01:05:32 PM PDT 24 16967230 ps
T117 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2662422577 Jun 06 01:04:55 PM PDT 24 Jun 06 01:05:00 PM PDT 24 1014796019 ps
T629 /workspace/coverage/cover_reg_top/3.hmac_intr_test.1045836642 Jun 06 01:04:59 PM PDT 24 Jun 06 01:05:01 PM PDT 24 14586420 ps
T630 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1215163789 Jun 06 01:05:05 PM PDT 24 Jun 06 01:05:10 PM PDT 24 489216285 ps
T631 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3801812843 Jun 06 01:04:51 PM PDT 24 Jun 06 01:04:54 PM PDT 24 164759232 ps
T87 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3178961882 Jun 06 01:05:04 PM PDT 24 Jun 06 01:05:12 PM PDT 24 477685431 ps
T122 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2929699254 Jun 06 01:05:03 PM PDT 24 Jun 06 01:05:07 PM PDT 24 87070039 ps
T632 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1067256800 Jun 06 01:05:19 PM PDT 24 Jun 06 01:05:22 PM PDT 24 97158771 ps
T633 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1707506928 Jun 06 01:05:07 PM PDT 24 Jun 06 01:05:12 PM PDT 24 42597167 ps
T634 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2108863339 Jun 06 01:05:19 PM PDT 24 Jun 06 01:05:21 PM PDT 24 33532978 ps
T88 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.939509075 Jun 06 01:04:56 PM PDT 24 Jun 06 01:04:57 PM PDT 24 25176199 ps
T635 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3852288726 Jun 06 01:05:05 PM PDT 24 Jun 06 01:05:11 PM PDT 24 436645200 ps
T118 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.646441268 Jun 06 01:05:11 PM PDT 24 Jun 06 01:05:17 PM PDT 24 333014682 ps
T636 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3651278029 Jun 06 01:05:15 PM PDT 24 Jun 06 01:05:19 PM PDT 24 144637852 ps
T637 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3328117308 Jun 06 01:05:14 PM PDT 24 Jun 06 01:05:16 PM PDT 24 310695985 ps
T123 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.4234218539 Jun 06 01:05:13 PM PDT 24 Jun 06 01:05:16 PM PDT 24 173710217 ps
T638 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.651159018 Jun 06 01:04:52 PM PDT 24 Jun 06 01:17:03 PM PDT 24 102973793833 ps
T639 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2870281212 Jun 06 01:05:06 PM PDT 24 Jun 06 01:05:12 PM PDT 24 61622373 ps
T640 /workspace/coverage/cover_reg_top/5.hmac_intr_test.1923004692 Jun 06 01:04:57 PM PDT 24 Jun 06 01:04:59 PM PDT 24 17270336 ps
T641 /workspace/coverage/cover_reg_top/23.hmac_intr_test.1996964604 Jun 06 01:05:16 PM PDT 24 Jun 06 01:05:17 PM PDT 24 23191392 ps
T89 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.4144894331 Jun 06 01:04:58 PM PDT 24 Jun 06 01:05:02 PM PDT 24 48324875 ps
T642 /workspace/coverage/cover_reg_top/47.hmac_intr_test.2949641454 Jun 06 01:05:28 PM PDT 24 Jun 06 01:05:30 PM PDT 24 14089713 ps
T643 /workspace/coverage/cover_reg_top/35.hmac_intr_test.4180336334 Jun 06 01:05:30 PM PDT 24 Jun 06 01:05:32 PM PDT 24 12474395 ps
T644 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.668183159 Jun 06 01:05:08 PM PDT 24 Jun 06 01:05:11 PM PDT 24 34894425 ps
T90 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2739423805 Jun 06 01:05:05 PM PDT 24 Jun 06 01:05:08 PM PDT 24 81758652 ps
T91 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1247430421 Jun 06 01:05:10 PM PDT 24 Jun 06 01:05:12 PM PDT 24 42464636 ps
T645 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2108548243 Jun 06 01:05:14 PM PDT 24 Jun 06 01:05:19 PM PDT 24 55909125 ps
T646 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2870012245 Jun 06 01:05:07 PM PDT 24 Jun 06 01:05:11 PM PDT 24 13605827 ps
T647 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3726448862 Jun 06 01:05:17 PM PDT 24 Jun 06 01:05:19 PM PDT 24 14123358 ps
T648 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2932402611 Jun 06 01:05:04 PM PDT 24 Jun 06 01:05:10 PM PDT 24 2463488633 ps
T649 /workspace/coverage/cover_reg_top/1.hmac_intr_test.3192624629 Jun 06 01:04:52 PM PDT 24 Jun 06 01:04:53 PM PDT 24 56169148 ps
T92 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3443990138 Jun 06 01:04:58 PM PDT 24 Jun 06 01:05:08 PM PDT 24 1852704316 ps
T650 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1905625006 Jun 06 01:04:57 PM PDT 24 Jun 06 01:05:00 PM PDT 24 44323675 ps
T651 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1756003869 Jun 06 01:05:13 PM PDT 24 Jun 06 01:05:16 PM PDT 24 100341315 ps
T652 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2479884422 Jun 06 01:04:57 PM PDT 24 Jun 06 01:05:01 PM PDT 24 150119255 ps
T653 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1932907466 Jun 06 01:05:17 PM PDT 24 Jun 06 01:05:20 PM PDT 24 66505406 ps
T654 /workspace/coverage/cover_reg_top/10.hmac_intr_test.799674091 Jun 06 01:05:04 PM PDT 24 Jun 06 01:05:07 PM PDT 24 22769699 ps
T655 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2141143238 Jun 06 01:04:55 PM PDT 24 Jun 06 01:04:57 PM PDT 24 195868474 ps
T656 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.4171733853 Jun 06 01:05:08 PM PDT 24 Jun 06 01:05:12 PM PDT 24 187593681 ps
T120 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.4076574191 Jun 06 01:05:19 PM PDT 24 Jun 06 01:05:22 PM PDT 24 204427072 ps
T657 /workspace/coverage/cover_reg_top/7.hmac_intr_test.1388213414 Jun 06 01:05:00 PM PDT 24 Jun 06 01:05:03 PM PDT 24 11531448 ps
T658 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2975045970 Jun 06 01:05:03 PM PDT 24 Jun 06 01:05:06 PM PDT 24 24423552 ps
T659 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.856878956 Jun 06 01:04:56 PM PDT 24 Jun 06 01:04:59 PM PDT 24 215497989 ps
T660 /workspace/coverage/cover_reg_top/14.hmac_intr_test.2715442711 Jun 06 01:05:19 PM PDT 24 Jun 06 01:05:21 PM PDT 24 63447386 ps
T661 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.65508044 Jun 06 01:04:56 PM PDT 24 Jun 06 01:04:59 PM PDT 24 56886100 ps
T93 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1925920480 Jun 06 01:05:15 PM PDT 24 Jun 06 01:05:16 PM PDT 24 58233002 ps
T662 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2418865462 Jun 06 01:05:10 PM PDT 24 Jun 06 01:05:14 PM PDT 24 45823738 ps
T663 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1938693007 Jun 06 01:04:50 PM PDT 24 Jun 06 01:20:04 PM PDT 24 297708510481 ps
T119 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1265379504 Jun 06 01:05:05 PM PDT 24 Jun 06 01:05:12 PM PDT 24 276656485 ps
T664 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.236297914 Jun 06 01:05:05 PM PDT 24 Jun 06 01:05:08 PM PDT 24 22902816 ps
T665 /workspace/coverage/cover_reg_top/40.hmac_intr_test.1663766420 Jun 06 01:05:30 PM PDT 24 Jun 06 01:05:32 PM PDT 24 15040804 ps
T94 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3289905921 Jun 06 01:04:53 PM PDT 24 Jun 06 01:05:08 PM PDT 24 311764468 ps
T666 /workspace/coverage/cover_reg_top/31.hmac_intr_test.2442624598 Jun 06 01:05:30 PM PDT 24 Jun 06 01:05:32 PM PDT 24 37278655 ps
T667 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2901521939 Jun 06 01:05:14 PM PDT 24 Jun 06 01:05:16 PM PDT 24 123671682 ps
T668 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2967959380 Jun 06 01:04:51 PM PDT 24 Jun 06 01:04:52 PM PDT 24 15678121 ps
T669 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.423179378 Jun 06 01:04:59 PM PDT 24 Jun 06 01:05:02 PM PDT 24 21056424 ps
T670 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1496992048 Jun 06 01:05:00 PM PDT 24 Jun 06 01:05:04 PM PDT 24 156979369 ps
T671 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3927206890 Jun 06 01:05:15 PM PDT 24 Jun 06 01:05:19 PM PDT 24 193987146 ps
T672 /workspace/coverage/cover_reg_top/4.hmac_intr_test.1113573929 Jun 06 01:04:56 PM PDT 24 Jun 06 01:04:58 PM PDT 24 18478577 ps
T673 /workspace/coverage/cover_reg_top/41.hmac_intr_test.87260917 Jun 06 01:05:29 PM PDT 24 Jun 06 01:05:32 PM PDT 24 17936263 ps
T674 /workspace/coverage/cover_reg_top/13.hmac_intr_test.37103156 Jun 06 01:05:08 PM PDT 24 Jun 06 01:05:11 PM PDT 24 30125324 ps
T675 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.4219097371 Jun 06 01:05:16 PM PDT 24 Jun 06 01:05:20 PM PDT 24 404401096 ps
T676 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2609813303 Jun 06 01:05:05 PM PDT 24 Jun 06 01:05:10 PM PDT 24 121257411 ps
T97 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1917471706 Jun 06 01:05:03 PM PDT 24 Jun 06 01:05:05 PM PDT 24 82517138 ps
T121 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2195831802 Jun 06 01:04:52 PM PDT 24 Jun 06 01:04:56 PM PDT 24 1539065578 ps
T95 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.824933549 Jun 06 01:04:58 PM PDT 24 Jun 06 01:05:01 PM PDT 24 18289312 ps
T677 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2559566518 Jun 06 01:05:29 PM PDT 24 Jun 06 01:05:32 PM PDT 24 57710652 ps
T96 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.176533493 Jun 06 01:04:51 PM PDT 24 Jun 06 01:04:53 PM PDT 24 82853261 ps
T678 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.4161430437 Jun 06 01:05:00 PM PDT 24 Jun 06 01:05:04 PM PDT 24 1727430889 ps
T679 /workspace/coverage/cover_reg_top/11.hmac_intr_test.48693511 Jun 06 01:05:08 PM PDT 24 Jun 06 01:05:11 PM PDT 24 13570339 ps
T680 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.917385028 Jun 06 01:05:05 PM PDT 24 Jun 06 01:05:10 PM PDT 24 160428590 ps
T681 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2013098412 Jun 06 01:05:14 PM PDT 24 Jun 06 01:05:17 PM PDT 24 393529432 ps
T682 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.709737149 Jun 06 01:04:59 PM PDT 24 Jun 06 01:05:07 PM PDT 24 211143060 ps
T683 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1263481716 Jun 06 01:05:18 PM PDT 24 Jun 06 01:05:20 PM PDT 24 12907622 ps
T684 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2966130350 Jun 06 01:04:50 PM PDT 24 Jun 06 01:04:52 PM PDT 24 92391772 ps
T685 /workspace/coverage/cover_reg_top/49.hmac_intr_test.902739817 Jun 06 01:05:32 PM PDT 24 Jun 06 01:05:34 PM PDT 24 28389358 ps
T686 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2782531416 Jun 06 01:05:28 PM PDT 24 Jun 06 01:05:30 PM PDT 24 62681132 ps
T687 /workspace/coverage/cover_reg_top/25.hmac_intr_test.1758712077 Jun 06 01:05:19 PM PDT 24 Jun 06 01:05:21 PM PDT 24 99637971 ps
T688 /workspace/coverage/cover_reg_top/46.hmac_intr_test.359752502 Jun 06 01:05:30 PM PDT 24 Jun 06 01:05:32 PM PDT 24 18695789 ps
T689 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1450350581 Jun 06 01:05:08 PM PDT 24 Jun 06 01:05:11 PM PDT 24 47140214 ps
T690 /workspace/coverage/cover_reg_top/2.hmac_intr_test.297778333 Jun 06 01:05:00 PM PDT 24 Jun 06 01:05:02 PM PDT 24 14213571 ps
T691 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.734313506 Jun 06 01:05:13 PM PDT 24 Jun 06 01:05:15 PM PDT 24 113602142 ps
T692 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.230560889 Jun 06 01:05:16 PM PDT 24 Jun 06 01:05:18 PM PDT 24 69113408 ps
T693 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.739379583 Jun 06 01:04:51 PM PDT 24 Jun 06 01:04:53 PM PDT 24 79164309 ps
T125 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1261191631 Jun 06 01:05:19 PM PDT 24 Jun 06 01:05:22 PM PDT 24 326189603 ps
T694 /workspace/coverage/cover_reg_top/22.hmac_intr_test.712678489 Jun 06 01:05:18 PM PDT 24 Jun 06 01:05:20 PM PDT 24 27520954 ps
T695 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3670874207 Jun 06 01:05:30 PM PDT 24 Jun 06 01:05:32 PM PDT 24 54186628 ps
T696 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2229684517 Jun 06 01:05:17 PM PDT 24 Jun 06 01:05:19 PM PDT 24 14628752 ps
T697 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3787621124 Jun 06 01:04:51 PM PDT 24 Jun 06 01:04:56 PM PDT 24 2897958974 ps
T698 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3932183395 Jun 06 01:04:58 PM PDT 24 Jun 06 01:05:00 PM PDT 24 34116192 ps
T98 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2919221435 Jun 06 01:04:53 PM PDT 24 Jun 06 01:05:03 PM PDT 24 881819770 ps
T699 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1048327618 Jun 06 01:04:55 PM PDT 24 Jun 06 01:04:57 PM PDT 24 223343730 ps
T700 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2192706569 Jun 06 01:05:32 PM PDT 24 Jun 06 01:05:34 PM PDT 24 50123240 ps
T701 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.4152501370 Jun 06 01:04:54 PM PDT 24 Jun 06 01:04:56 PM PDT 24 24381841 ps
T702 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.381105530 Jun 06 01:05:21 PM PDT 24 Jun 06 01:05:24 PM PDT 24 107136203 ps
T703 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1929222370 Jun 06 01:04:52 PM PDT 24 Jun 06 01:04:56 PM PDT 24 462478523 ps
T704 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2006260399 Jun 06 01:04:52 PM PDT 24 Jun 06 01:05:07 PM PDT 24 735425445 ps
T54 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2086739525 Jun 06 01:05:18 PM PDT 24 Jun 06 01:05:24 PM PDT 24 1656256085 ps
T705 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.304951426 Jun 06 01:05:13 PM PDT 24 Jun 06 01:05:15 PM PDT 24 65384525 ps
T706 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2697688302 Jun 06 01:05:18 PM PDT 24 Jun 06 01:05:22 PM PDT 24 112462881 ps
T707 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.135931876 Jun 06 01:05:05 PM PDT 24 Jun 06 01:05:09 PM PDT 24 30528979 ps
T708 /workspace/coverage/cover_reg_top/48.hmac_intr_test.4245920788 Jun 06 01:05:31 PM PDT 24 Jun 06 01:05:34 PM PDT 24 34746639 ps
T709 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2232827743 Jun 06 01:05:06 PM PDT 24 Jun 06 01:05:10 PM PDT 24 119377104 ps
T710 /workspace/coverage/cover_reg_top/6.hmac_intr_test.252017243 Jun 06 01:04:59 PM PDT 24 Jun 06 01:05:01 PM PDT 24 11510991 ps
T711 /workspace/coverage/cover_reg_top/18.hmac_intr_test.290550655 Jun 06 01:05:16 PM PDT 24 Jun 06 01:05:17 PM PDT 24 24419735 ps
T115 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1366469011 Jun 06 01:05:03 PM PDT 24 Jun 06 01:05:07 PM PDT 24 171188954 ps
T712 /workspace/coverage/cover_reg_top/24.hmac_intr_test.2824662023 Jun 06 01:05:17 PM PDT 24 Jun 06 01:05:19 PM PDT 24 14441654 ps
T713 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.471724367 Jun 06 01:05:43 PM PDT 24 Jun 06 01:05:46 PM PDT 24 79993539 ps
T714 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.925165587 Jun 06 01:04:58 PM PDT 24 Jun 06 01:05:00 PM PDT 24 30192662 ps
T715 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1953605848 Jun 06 01:05:09 PM PDT 24 Jun 06 01:05:15 PM PDT 24 215404769 ps
T716 /workspace/coverage/cover_reg_top/16.hmac_intr_test.2121065581 Jun 06 01:05:16 PM PDT 24 Jun 06 01:05:17 PM PDT 24 28855649 ps
T124 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.4215773573 Jun 06 01:04:58 PM PDT 24 Jun 06 01:05:02 PM PDT 24 82968608 ps
T717 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.921962490 Jun 06 01:05:10 PM PDT 24 Jun 06 01:05:13 PM PDT 24 74920422 ps
T718 /workspace/coverage/cover_reg_top/26.hmac_intr_test.556624437 Jun 06 01:05:17 PM PDT 24 Jun 06 01:05:19 PM PDT 24 38708604 ps
T719 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.4129728507 Jun 06 01:05:16 PM PDT 24 Jun 06 01:05:18 PM PDT 24 29456997 ps
T720 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.600935452 Jun 06 01:05:05 PM PDT 24 Jun 06 01:05:08 PM PDT 24 99395068 ps
T721 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3426501726 Jun 06 01:05:19 PM PDT 24 Jun 06 01:05:22 PM PDT 24 155392145 ps
T722 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1413599920 Jun 06 01:05:21 PM PDT 24 Jun 06 01:05:23 PM PDT 24 24213428 ps
T723 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.40842901 Jun 06 01:04:58 PM PDT 24 Jun 06 01:05:05 PM PDT 24 246009861 ps
T126 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2243804870 Jun 06 01:04:57 PM PDT 24 Jun 06 01:05:03 PM PDT 24 253676648 ps
T724 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4277089929 Jun 06 01:05:04 PM PDT 24 Jun 06 01:05:08 PM PDT 24 392527730 ps
T725 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3157962173 Jun 06 01:05:14 PM PDT 24 Jun 06 01:05:16 PM PDT 24 66221498 ps
T726 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.385644156 Jun 06 01:04:52 PM PDT 24 Jun 06 01:04:54 PM PDT 24 54413054 ps
T727 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2468517432 Jun 06 01:05:29 PM PDT 24 Jun 06 01:05:31 PM PDT 24 36837254 ps
T728 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.736648131 Jun 06 01:05:05 PM PDT 24 Jun 06 01:05:12 PM PDT 24 350013996 ps
T99 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2394988923 Jun 06 01:05:19 PM PDT 24 Jun 06 01:05:21 PM PDT 24 167278796 ps
T729 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1879423861 Jun 06 01:04:59 PM PDT 24 Jun 06 01:05:03 PM PDT 24 128683726 ps
T730 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1452913761 Jun 06 01:05:10 PM PDT 24 Jun 06 01:05:15 PM PDT 24 102879976 ps
T731 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.764851992 Jun 06 01:04:51 PM PDT 24 Jun 06 01:04:55 PM PDT 24 245422204 ps

Test location /workspace/coverage/default/7.hmac_long_msg.4142150482
Short name T16
Test name
Test status
Simulation time 27374704302 ps
CPU time 80.19 seconds
Started Jun 06 01:06:16 PM PDT 24
Finished Jun 06 01:07:38 PM PDT 24
Peak memory 200500 kb
Host smart-00a1ba53-df54-428f-abc6-596c726daf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142150482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.4142150482
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/96.hmac_stress_all_with_rand_reset.2738121209
Short name T10
Test name
Test status
Simulation time 79844707648 ps
CPU time 4019.95 seconds
Started Jun 06 01:08:31 PM PDT 24
Finished Jun 06 02:15:33 PM PDT 24
Peak memory 812604 kb
Host smart-fa56362e-3c7f-4aff-8637-f1e9f59f14e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2738121209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.hmac_stress_all_with_rand_reset.2738121209
Directory /workspace/96.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.hmac_stress_all.369088529
Short name T4
Test name
Test status
Simulation time 26753580913 ps
CPU time 1934.37 seconds
Started Jun 06 01:08:15 PM PDT 24
Finished Jun 06 01:40:32 PM PDT 24
Peak memory 720476 kb
Host smart-52d31a49-a5af-42ed-9409-cbb627db3268
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369088529 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.369088529
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1205590731
Short name T25
Test name
Test status
Simulation time 448005907 ps
CPU time 1.04 seconds
Started Jun 06 01:05:59 PM PDT 24
Finished Jun 06 01:06:02 PM PDT 24
Peak memory 219836 kb
Host smart-66709f11-df57-456c-a46b-6b0490bd23ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205590731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1205590731
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2988017086
Short name T47
Test name
Test status
Simulation time 86826590 ps
CPU time 2.91 seconds
Started Jun 06 01:05:17 PM PDT 24
Finished Jun 06 01:05:21 PM PDT 24
Peak memory 199296 kb
Host smart-1fbb0017-5271-477c-910b-9d8b767c52be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988017086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2988017086
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/48.hmac_stress_all.4165234610
Short name T23
Test name
Test status
Simulation time 529264279449 ps
CPU time 1959.35 seconds
Started Jun 06 01:08:12 PM PDT 24
Finished Jun 06 01:40:53 PM PDT 24
Peak memory 241408 kb
Host smart-1ac65355-9402-4ec2-9e75-f35c5eb71eb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165234610 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.4165234610
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2739423805
Short name T90
Test name
Test status
Simulation time 81758652 ps
CPU time 0.99 seconds
Started Jun 06 01:05:05 PM PDT 24
Finished Jun 06 01:05:08 PM PDT 24
Peak memory 198956 kb
Host smart-d6658087-61df-4432-a844-5bfa2250af36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739423805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2739423805
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2086739525
Short name T54
Test name
Test status
Simulation time 1656256085 ps
CPU time 4.29 seconds
Started Jun 06 01:05:18 PM PDT 24
Finished Jun 06 01:05:24 PM PDT 24
Peak memory 199244 kb
Host smart-d833865b-b7bb-44ba-898d-4a09209acbd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086739525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2086739525
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1446116416
Short name T524
Test name
Test status
Simulation time 109932021520 ps
CPU time 3399.78 seconds
Started Jun 06 01:06:23 PM PDT 24
Finished Jun 06 02:03:05 PM PDT 24
Peak memory 771840 kb
Host smart-d77ffcc9-285f-4c02-bdf6-995f48f566bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446116416 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1446116416
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1376048696
Short name T171
Test name
Test status
Simulation time 20177806 ps
CPU time 0.55 seconds
Started Jun 06 01:06:22 PM PDT 24
Finished Jun 06 01:06:24 PM PDT 24
Peak memory 195144 kb
Host smart-58824cca-32ba-4ea2-af3f-9d4e4ebc0a30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376048696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1376048696
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1265379504
Short name T119
Test name
Test status
Simulation time 276656485 ps
CPU time 4.52 seconds
Started Jun 06 01:05:05 PM PDT 24
Finished Jun 06 01:05:12 PM PDT 24
Peak memory 199348 kb
Host smart-0cbfb897-99c8-484b-ae24-ed6ed9537ad1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265379504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1265379504
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1332431030
Short name T104
Test name
Test status
Simulation time 595026769415 ps
CPU time 2110.07 seconds
Started Jun 06 01:07:13 PM PDT 24
Finished Jun 06 01:42:25 PM PDT 24
Peak memory 796052 kb
Host smart-4e26137f-4ce5-4e36-b696-df2f7e24d4a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332431030 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1332431030
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3932174824
Short name T105
Test name
Test status
Simulation time 1127400130 ps
CPU time 56.56 seconds
Started Jun 06 01:07:38 PM PDT 24
Finished Jun 06 01:08:36 PM PDT 24
Peak memory 231912 kb
Host smart-40330f03-be49-4d3e-99ff-af9cdc855216
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3932174824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3932174824
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1897465385
Short name T103
Test name
Test status
Simulation time 3138374908 ps
CPU time 46.93 seconds
Started Jun 06 01:07:39 PM PDT 24
Finished Jun 06 01:08:27 PM PDT 24
Peak memory 231544 kb
Host smart-2a1f6a7d-7e5e-462d-b8bd-2824b659bacd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1897465385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1897465385
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.646441268
Short name T118
Test name
Test status
Simulation time 333014682 ps
CPU time 4.53 seconds
Started Jun 06 01:05:11 PM PDT 24
Finished Jun 06 01:05:17 PM PDT 24
Peak memory 199332 kb
Host smart-9e78584c-8c6d-4f46-9849-c46b348cc0a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646441268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.646441268
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2045278740
Short name T113
Test name
Test status
Simulation time 3709080793 ps
CPU time 106.94 seconds
Started Jun 06 01:06:17 PM PDT 24
Finished Jun 06 01:08:06 PM PDT 24
Peak memory 200476 kb
Host smart-12f15ed6-a860-4bbc-893f-f3e9c4c0687a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045278740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2045278740
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_stress_all.692625082
Short name T101
Test name
Test status
Simulation time 2352082677903 ps
CPU time 4242.3 seconds
Started Jun 06 01:06:38 PM PDT 24
Finished Jun 06 02:17:22 PM PDT 24
Peak memory 779612 kb
Host smart-c4e8efcc-24cc-4d4d-8b95-81b8385eaf58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692625082 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.692625082
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_stress_all.3544592334
Short name T110
Test name
Test status
Simulation time 18359015923 ps
CPU time 1759.23 seconds
Started Jun 06 01:07:47 PM PDT 24
Finished Jun 06 01:37:08 PM PDT 24
Peak memory 768200 kb
Host smart-79195142-6165-4830-972d-d0d0756e2fcf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544592334 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3544592334
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1367544600
Short name T611
Test name
Test status
Simulation time 203156656 ps
CPU time 1.09 seconds
Started Jun 06 01:04:52 PM PDT 24
Finished Jun 06 01:04:54 PM PDT 24
Peak memory 197608 kb
Host smart-00d48100-c182-4ea3-80a0-eff78ffb000a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367544600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.1367544600
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2652984145
Short name T49
Test name
Test status
Simulation time 1360809257 ps
CPU time 3.01 seconds
Started Jun 06 01:05:07 PM PDT 24
Finished Jun 06 01:05:13 PM PDT 24
Peak memory 199352 kb
Host smart-dbb0310b-ae37-46bd-b2d5-6466dc57dccd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652984145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2652984145
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2919221435
Short name T98
Test name
Test status
Simulation time 881819770 ps
CPU time 8.9 seconds
Started Jun 06 01:04:53 PM PDT 24
Finished Jun 06 01:05:03 PM PDT 24
Peak memory 199292 kb
Host smart-d30325d6-d8d0-4075-a0be-d67b7fc10679
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919221435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2919221435
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1736107940
Short name T621
Test name
Test status
Simulation time 4434454303 ps
CPU time 16.25 seconds
Started Jun 06 01:04:51 PM PDT 24
Finished Jun 06 01:05:08 PM PDT 24
Peak memory 198536 kb
Host smart-2fccd3bc-6263-4d48-b10d-bd70c7eda2a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736107940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1736107940
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.739379583
Short name T693
Test name
Test status
Simulation time 79164309 ps
CPU time 0.79 seconds
Started Jun 06 01:04:51 PM PDT 24
Finished Jun 06 01:04:53 PM PDT 24
Peak memory 197400 kb
Host smart-6fc71a86-67e1-4a1d-88c4-ca75cb459529
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739379583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.739379583
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1938693007
Short name T663
Test name
Test status
Simulation time 297708510481 ps
CPU time 913.29 seconds
Started Jun 06 01:04:50 PM PDT 24
Finished Jun 06 01:20:04 PM PDT 24
Peak memory 224044 kb
Host smart-77e4776d-6f6f-47d3-ad52-0c6dbb253c21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938693007 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1938693007
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2966130350
Short name T684
Test name
Test status
Simulation time 92391772 ps
CPU time 0.82 seconds
Started Jun 06 01:04:50 PM PDT 24
Finished Jun 06 01:04:52 PM PDT 24
Peak memory 198676 kb
Host smart-28d2051b-802a-4314-a662-a91dae34cb52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966130350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2966130350
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2967959380
Short name T668
Test name
Test status
Simulation time 15678121 ps
CPU time 0.64 seconds
Started Jun 06 01:04:51 PM PDT 24
Finished Jun 06 01:04:52 PM PDT 24
Peak memory 194272 kb
Host smart-b85e92b0-6a66-4947-87c5-eac696f471e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967959380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2967959380
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3801812843
Short name T631
Test name
Test status
Simulation time 164759232 ps
CPU time 1.79 seconds
Started Jun 06 01:04:51 PM PDT 24
Finished Jun 06 01:04:54 PM PDT 24
Peak memory 199380 kb
Host smart-16d10bed-7a22-430c-97b3-b20c43854374
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801812843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.3801812843
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.764851992
Short name T731
Test name
Test status
Simulation time 245422204 ps
CPU time 3.15 seconds
Started Jun 06 01:04:51 PM PDT 24
Finished Jun 06 01:04:55 PM PDT 24
Peak memory 199348 kb
Host smart-cdb7b544-6fee-4c0c-98d2-8d29c5e46e6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764851992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.764851992
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2763721543
Short name T86
Test name
Test status
Simulation time 1155032962 ps
CPU time 6.11 seconds
Started Jun 06 01:04:54 PM PDT 24
Finished Jun 06 01:05:00 PM PDT 24
Peak memory 199216 kb
Host smart-9d4d4b4f-8793-4ba5-9abd-c90345ea40f5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763721543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.2763721543
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2006260399
Short name T704
Test name
Test status
Simulation time 735425445 ps
CPU time 14.58 seconds
Started Jun 06 01:04:52 PM PDT 24
Finished Jun 06 01:05:07 PM PDT 24
Peak memory 199204 kb
Host smart-333cabae-1e46-451a-855d-261d61c6ed8c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006260399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2006260399
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.176533493
Short name T96
Test name
Test status
Simulation time 82853261 ps
CPU time 0.88 seconds
Started Jun 06 01:04:51 PM PDT 24
Finished Jun 06 01:04:53 PM PDT 24
Peak memory 198356 kb
Host smart-d38bc90d-ce9c-4b76-ba53-40bd6a30ef5e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176533493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.176533493
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.651159018
Short name T638
Test name
Test status
Simulation time 102973793833 ps
CPU time 729.82 seconds
Started Jun 06 01:04:52 PM PDT 24
Finished Jun 06 01:17:03 PM PDT 24
Peak memory 215836 kb
Host smart-2d8b3e68-08a9-4f0e-aaf1-34886b795ce3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651159018 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.651159018
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.4152501370
Short name T701
Test name
Test status
Simulation time 24381841 ps
CPU time 0.82 seconds
Started Jun 06 01:04:54 PM PDT 24
Finished Jun 06 01:04:56 PM PDT 24
Peak memory 198720 kb
Host smart-18d7f269-f9e9-4e9f-8490-86fc40e99d9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152501370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.4152501370
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.3192624629
Short name T649
Test name
Test status
Simulation time 56169148 ps
CPU time 0.59 seconds
Started Jun 06 01:04:52 PM PDT 24
Finished Jun 06 01:04:53 PM PDT 24
Peak memory 194184 kb
Host smart-d1ea8e15-3eaa-41df-aacd-6b38bdffdf75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192624629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.3192624629
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.385644156
Short name T726
Test name
Test status
Simulation time 54413054 ps
CPU time 1.16 seconds
Started Jun 06 01:04:52 PM PDT 24
Finished Jun 06 01:04:54 PM PDT 24
Peak memory 199092 kb
Host smart-22a2ff1c-f5f9-45a0-b0c9-9f436b90a577
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385644156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.385644156
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3787621124
Short name T697
Test name
Test status
Simulation time 2897958974 ps
CPU time 3.85 seconds
Started Jun 06 01:04:51 PM PDT 24
Finished Jun 06 01:04:56 PM PDT 24
Peak memory 199436 kb
Host smart-616d16f9-2b8d-4e71-9d52-b8d8119b1ddc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787621124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3787621124
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2195831802
Short name T121
Test name
Test status
Simulation time 1539065578 ps
CPU time 2.8 seconds
Started Jun 06 01:04:52 PM PDT 24
Finished Jun 06 01:04:56 PM PDT 24
Peak memory 199324 kb
Host smart-de591898-f550-4bd8-b845-10f21ea5557a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195831802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2195831802
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1658657057
Short name T616
Test name
Test status
Simulation time 138614755 ps
CPU time 1.78 seconds
Started Jun 06 01:05:06 PM PDT 24
Finished Jun 06 01:05:10 PM PDT 24
Peak memory 199428 kb
Host smart-0218c9b5-7669-461d-b0ef-ee3459024f18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658657057 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.1658657057
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.799674091
Short name T654
Test name
Test status
Simulation time 22769699 ps
CPU time 0.6 seconds
Started Jun 06 01:05:04 PM PDT 24
Finished Jun 06 01:05:07 PM PDT 24
Peak memory 194112 kb
Host smart-feecd7e8-d186-4db4-b8bf-e6387ac6f13e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799674091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.799674091
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1215163789
Short name T630
Test name
Test status
Simulation time 489216285 ps
CPU time 2.21 seconds
Started Jun 06 01:05:05 PM PDT 24
Finished Jun 06 01:05:10 PM PDT 24
Peak memory 199324 kb
Host smart-ce4226d0-8858-4455-8e4e-a315a6d43802
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215163789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1215163789
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2421058780
Short name T614
Test name
Test status
Simulation time 250686565 ps
CPU time 1.92 seconds
Started Jun 06 01:05:04 PM PDT 24
Finished Jun 06 01:05:09 PM PDT 24
Peak memory 199428 kb
Host smart-98661eba-96e1-4fec-8e61-1a838b744559
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421058780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2421058780
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2932402611
Short name T648
Test name
Test status
Simulation time 2463488633 ps
CPU time 3.03 seconds
Started Jun 06 01:05:04 PM PDT 24
Finished Jun 06 01:05:10 PM PDT 24
Peak memory 199404 kb
Host smart-1f217c87-879f-4edc-a55d-aec8a1717066
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932402611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2932402611
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1707506928
Short name T633
Test name
Test status
Simulation time 42597167 ps
CPU time 2.6 seconds
Started Jun 06 01:05:07 PM PDT 24
Finished Jun 06 01:05:12 PM PDT 24
Peak memory 199548 kb
Host smart-7c0fdb33-0f7c-4a60-9eeb-5d2e39cd7c88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707506928 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1707506928
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.921962490
Short name T717
Test name
Test status
Simulation time 74920422 ps
CPU time 0.95 seconds
Started Jun 06 01:05:10 PM PDT 24
Finished Jun 06 01:05:13 PM PDT 24
Peak memory 198720 kb
Host smart-c16a9b96-7705-44f9-a513-427f9abe2c1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921962490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.921962490
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.48693511
Short name T679
Test name
Test status
Simulation time 13570339 ps
CPU time 0.59 seconds
Started Jun 06 01:05:08 PM PDT 24
Finished Jun 06 01:05:11 PM PDT 24
Peak memory 194140 kb
Host smart-33b3bd0f-80fb-4cd0-bab1-276ca5cd2b53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48693511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.48693511
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2074132514
Short name T608
Test name
Test status
Simulation time 158350819 ps
CPU time 1.12 seconds
Started Jun 06 01:05:05 PM PDT 24
Finished Jun 06 01:05:09 PM PDT 24
Peak memory 198952 kb
Host smart-01e697f8-29f0-43a3-a547-a259e2907359
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074132514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2074132514
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2870281212
Short name T639
Test name
Test status
Simulation time 61622373 ps
CPU time 3.02 seconds
Started Jun 06 01:05:06 PM PDT 24
Finished Jun 06 01:05:12 PM PDT 24
Peak memory 199340 kb
Host smart-04a4193e-454e-4f40-82dd-96db7ad7b2e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870281212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2870281212
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1452913761
Short name T730
Test name
Test status
Simulation time 102879976 ps
CPU time 3.17 seconds
Started Jun 06 01:05:10 PM PDT 24
Finished Jun 06 01:05:15 PM PDT 24
Peak memory 207516 kb
Host smart-4e06e965-7895-48c2-8740-6dd05e45c7d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452913761 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1452913761
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1470639044
Short name T84
Test name
Test status
Simulation time 19139913 ps
CPU time 0.72 seconds
Started Jun 06 01:05:07 PM PDT 24
Finished Jun 06 01:05:10 PM PDT 24
Peak memory 197040 kb
Host smart-9abfe6c3-a7bf-4d06-9de6-84e4720554af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470639044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1470639044
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1450350581
Short name T689
Test name
Test status
Simulation time 47140214 ps
CPU time 0.57 seconds
Started Jun 06 01:05:08 PM PDT 24
Finished Jun 06 01:05:11 PM PDT 24
Peak memory 194136 kb
Host smart-12070dac-0495-4d48-872f-d7f18acd5e91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450350581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1450350581
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2418865462
Short name T662
Test name
Test status
Simulation time 45823738 ps
CPU time 2.12 seconds
Started Jun 06 01:05:10 PM PDT 24
Finished Jun 06 01:05:14 PM PDT 24
Peak memory 199368 kb
Host smart-301c06d0-82f6-4ebf-a24c-af9747263725
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418865462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2418865462
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1395926447
Short name T619
Test name
Test status
Simulation time 440570494 ps
CPU time 2.12 seconds
Started Jun 06 01:05:07 PM PDT 24
Finished Jun 06 01:05:12 PM PDT 24
Peak memory 199400 kb
Host smart-ca86da42-2815-4bea-85c7-77c67130e52b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395926447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1395926447
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.251322680
Short name T52
Test name
Test status
Simulation time 125855682904 ps
CPU time 566.9 seconds
Started Jun 06 01:05:18 PM PDT 24
Finished Jun 06 01:14:47 PM PDT 24
Peak memory 215800 kb
Host smart-d65d139d-c92a-4768-a7c2-9b42106f6510
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251322680 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.251322680
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1027520579
Short name T618
Test name
Test status
Simulation time 14836119 ps
CPU time 0.84 seconds
Started Jun 06 01:05:08 PM PDT 24
Finished Jun 06 01:05:11 PM PDT 24
Peak memory 198616 kb
Host smart-6ae1d8a4-38b7-4347-a3f9-39e98ffc306b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027520579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1027520579
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.37103156
Short name T674
Test name
Test status
Simulation time 30125324 ps
CPU time 0.58 seconds
Started Jun 06 01:05:08 PM PDT 24
Finished Jun 06 01:05:11 PM PDT 24
Peak memory 194068 kb
Host smart-b8be7c0a-a979-49e8-bee2-5636986007e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37103156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.37103156
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.4171733853
Short name T656
Test name
Test status
Simulation time 187593681 ps
CPU time 1.78 seconds
Started Jun 06 01:05:08 PM PDT 24
Finished Jun 06 01:05:12 PM PDT 24
Peak memory 199352 kb
Host smart-e2cda268-86ff-4b6f-95ee-d724195fd99e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171733853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.4171733853
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1953605848
Short name T715
Test name
Test status
Simulation time 215404769 ps
CPU time 4.43 seconds
Started Jun 06 01:05:09 PM PDT 24
Finished Jun 06 01:05:15 PM PDT 24
Peak memory 199372 kb
Host smart-444a48c6-fc27-4140-ab64-0f25a1d0874f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953605848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1953605848
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2984559705
Short name T607
Test name
Test status
Simulation time 203590685 ps
CPU time 1.13 seconds
Started Jun 06 01:05:19 PM PDT 24
Finished Jun 06 01:05:22 PM PDT 24
Peak memory 199056 kb
Host smart-aa0eaab1-b177-40f3-a1ef-309be5023fbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984559705 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2984559705
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.668183159
Short name T644
Test name
Test status
Simulation time 34894425 ps
CPU time 0.97 seconds
Started Jun 06 01:05:08 PM PDT 24
Finished Jun 06 01:05:11 PM PDT 24
Peak memory 199048 kb
Host smart-49e8fec9-38b8-4edc-92e7-e4ac1f115e3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668183159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.668183159
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.2715442711
Short name T660
Test name
Test status
Simulation time 63447386 ps
CPU time 0.6 seconds
Started Jun 06 01:05:19 PM PDT 24
Finished Jun 06 01:05:21 PM PDT 24
Peak memory 194036 kb
Host smart-eda11ac5-a005-48cb-bafc-0cc98423e282
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715442711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2715442711
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2697688302
Short name T706
Test name
Test status
Simulation time 112462881 ps
CPU time 2.3 seconds
Started Jun 06 01:05:18 PM PDT 24
Finished Jun 06 01:05:22 PM PDT 24
Peak memory 199016 kb
Host smart-7302652a-53e0-45e9-91ba-18582b3d5b32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697688302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2697688302
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3927206890
Short name T671
Test name
Test status
Simulation time 193987146 ps
CPU time 3.56 seconds
Started Jun 06 01:05:15 PM PDT 24
Finished Jun 06 01:05:19 PM PDT 24
Peak memory 199372 kb
Host smart-f3809b67-5bea-456c-9871-0e5beba539a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927206890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3927206890
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1617841568
Short name T48
Test name
Test status
Simulation time 153468690 ps
CPU time 1.64 seconds
Started Jun 06 01:05:20 PM PDT 24
Finished Jun 06 01:05:22 PM PDT 24
Peak memory 199248 kb
Host smart-fc67cf66-c450-43dd-bc63-b0e654cdcd80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617841568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1617841568
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2108548243
Short name T645
Test name
Test status
Simulation time 55909125 ps
CPU time 3.7 seconds
Started Jun 06 01:05:14 PM PDT 24
Finished Jun 06 01:05:19 PM PDT 24
Peak memory 199412 kb
Host smart-e8f2bc2b-ff6c-4aa7-917b-832736f32f96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108548243 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2108548243
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1247430421
Short name T91
Test name
Test status
Simulation time 42464636 ps
CPU time 0.67 seconds
Started Jun 06 01:05:10 PM PDT 24
Finished Jun 06 01:05:12 PM PDT 24
Peak memory 196928 kb
Host smart-fee44f29-78b4-4fcf-9c6e-18eaf07d5846
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247430421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1247430421
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2108863339
Short name T634
Test name
Test status
Simulation time 33532978 ps
CPU time 0.62 seconds
Started Jun 06 01:05:19 PM PDT 24
Finished Jun 06 01:05:21 PM PDT 24
Peak memory 193968 kb
Host smart-29e8aed5-1706-4678-ae0b-0b94a772af6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108863339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2108863339
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2013098412
Short name T681
Test name
Test status
Simulation time 393529432 ps
CPU time 2.03 seconds
Started Jun 06 01:05:14 PM PDT 24
Finished Jun 06 01:05:17 PM PDT 24
Peak memory 198812 kb
Host smart-e5308975-6fca-4107-910b-f18fa19e1111
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013098412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2013098412
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.4186742276
Short name T615
Test name
Test status
Simulation time 245558200 ps
CPU time 4.52 seconds
Started Jun 06 01:05:08 PM PDT 24
Finished Jun 06 01:05:15 PM PDT 24
Peak memory 199408 kb
Host smart-d7731fbc-2234-4cdd-8078-e4ca2f2888c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186742276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.4186742276
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3157962173
Short name T725
Test name
Test status
Simulation time 66221498 ps
CPU time 1.38 seconds
Started Jun 06 01:05:14 PM PDT 24
Finished Jun 06 01:05:16 PM PDT 24
Peak memory 199340 kb
Host smart-9994254e-44dd-465f-bed0-bab786b1f838
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157962173 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3157962173
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.734313506
Short name T691
Test name
Test status
Simulation time 113602142 ps
CPU time 0.82 seconds
Started Jun 06 01:05:13 PM PDT 24
Finished Jun 06 01:05:15 PM PDT 24
Peak memory 198244 kb
Host smart-0e1f57cb-3594-4ee6-a24a-a572beceea70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734313506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.734313506
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.2121065581
Short name T716
Test name
Test status
Simulation time 28855649 ps
CPU time 0.62 seconds
Started Jun 06 01:05:16 PM PDT 24
Finished Jun 06 01:05:17 PM PDT 24
Peak memory 194180 kb
Host smart-ed156411-5855-45da-ad0f-37f1decdf2f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121065581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2121065581
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1932907466
Short name T653
Test name
Test status
Simulation time 66505406 ps
CPU time 1.73 seconds
Started Jun 06 01:05:17 PM PDT 24
Finished Jun 06 01:05:20 PM PDT 24
Peak memory 199336 kb
Host smart-b36761ee-28a3-4a69-811f-bf3d175072ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932907466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1932907466
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.304951426
Short name T705
Test name
Test status
Simulation time 65384525 ps
CPU time 1.56 seconds
Started Jun 06 01:05:13 PM PDT 24
Finished Jun 06 01:05:15 PM PDT 24
Peak memory 199380 kb
Host smart-9f06de76-6d6c-41c5-91f6-c4e4f5586956
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304951426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.304951426
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.4076574191
Short name T120
Test name
Test status
Simulation time 204427072 ps
CPU time 1.74 seconds
Started Jun 06 01:05:19 PM PDT 24
Finished Jun 06 01:05:22 PM PDT 24
Peak memory 199372 kb
Host smart-400dd447-b9d0-46d7-89c3-85514f87a43f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076574191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.4076574191
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1756003869
Short name T651
Test name
Test status
Simulation time 100341315 ps
CPU time 2.13 seconds
Started Jun 06 01:05:13 PM PDT 24
Finished Jun 06 01:05:16 PM PDT 24
Peak memory 199368 kb
Host smart-8dc2e5d1-dfa7-4ebe-b856-113c38235792
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756003869 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1756003869
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.4129728507
Short name T719
Test name
Test status
Simulation time 29456997 ps
CPU time 0.9 seconds
Started Jun 06 01:05:16 PM PDT 24
Finished Jun 06 01:05:18 PM PDT 24
Peak memory 198788 kb
Host smart-e3bef3b4-1d85-429d-b8a1-69a6a5fcc5b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129728507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.4129728507
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.4182695500
Short name T620
Test name
Test status
Simulation time 15190021 ps
CPU time 0.61 seconds
Started Jun 06 01:05:16 PM PDT 24
Finished Jun 06 01:05:18 PM PDT 24
Peak memory 194144 kb
Host smart-6bd7a16f-82cf-427a-8f42-0d49364cbc0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182695500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.4182695500
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1067256800
Short name T632
Test name
Test status
Simulation time 97158771 ps
CPU time 1.75 seconds
Started Jun 06 01:05:19 PM PDT 24
Finished Jun 06 01:05:22 PM PDT 24
Peak memory 199368 kb
Host smart-b6c824e2-9bbc-4037-af5a-17e6ba31a80a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067256800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.1067256800
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3328117308
Short name T637
Test name
Test status
Simulation time 310695985 ps
CPU time 1.78 seconds
Started Jun 06 01:05:14 PM PDT 24
Finished Jun 06 01:05:16 PM PDT 24
Peak memory 199356 kb
Host smart-8880e6cc-93b1-45db-a84a-00a21b2ea21c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328117308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.3328117308
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.230560889
Short name T692
Test name
Test status
Simulation time 69113408 ps
CPU time 1.62 seconds
Started Jun 06 01:05:16 PM PDT 24
Finished Jun 06 01:05:18 PM PDT 24
Peak memory 199416 kb
Host smart-0d308f3f-ff16-4f3e-b711-c623d88e3c7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230560889 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.230560889
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1925920480
Short name T93
Test name
Test status
Simulation time 58233002 ps
CPU time 0.7 seconds
Started Jun 06 01:05:15 PM PDT 24
Finished Jun 06 01:05:16 PM PDT 24
Peak memory 196844 kb
Host smart-b1540ae0-db3c-4889-badb-e05db429192b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925920480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1925920480
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.290550655
Short name T711
Test name
Test status
Simulation time 24419735 ps
CPU time 0.57 seconds
Started Jun 06 01:05:16 PM PDT 24
Finished Jun 06 01:05:17 PM PDT 24
Peak memory 194140 kb
Host smart-20a785b2-be76-4ee9-adfa-861b1be74057
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290550655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.290550655
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3993259421
Short name T626
Test name
Test status
Simulation time 76023880 ps
CPU time 1.69 seconds
Started Jun 06 01:05:17 PM PDT 24
Finished Jun 06 01:05:20 PM PDT 24
Peak memory 199156 kb
Host smart-f2bb266b-cb89-4fdb-991f-77a18b499aa9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993259421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3993259421
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2901521939
Short name T667
Test name
Test status
Simulation time 123671682 ps
CPU time 1.42 seconds
Started Jun 06 01:05:14 PM PDT 24
Finished Jun 06 01:05:16 PM PDT 24
Peak memory 199336 kb
Host smart-c2bcdb74-f978-4846-aac3-9df0ca8dab2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901521939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2901521939
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1261191631
Short name T125
Test name
Test status
Simulation time 326189603 ps
CPU time 2.03 seconds
Started Jun 06 01:05:19 PM PDT 24
Finished Jun 06 01:05:22 PM PDT 24
Peak memory 199372 kb
Host smart-ad36d197-84b8-4eba-9afb-16be7d2de4d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261191631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.1261191631
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3651278029
Short name T636
Test name
Test status
Simulation time 144637852 ps
CPU time 2.4 seconds
Started Jun 06 01:05:15 PM PDT 24
Finished Jun 06 01:05:19 PM PDT 24
Peak memory 199400 kb
Host smart-75c629b2-c390-4420-b259-3068ee17c2cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651278029 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3651278029
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2394988923
Short name T99
Test name
Test status
Simulation time 167278796 ps
CPU time 0.84 seconds
Started Jun 06 01:05:19 PM PDT 24
Finished Jun 06 01:05:21 PM PDT 24
Peak memory 198592 kb
Host smart-bb086c54-07f5-4725-aa97-bc68ff4ab444
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394988923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2394988923
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1263481716
Short name T683
Test name
Test status
Simulation time 12907622 ps
CPU time 0.62 seconds
Started Jun 06 01:05:18 PM PDT 24
Finished Jun 06 01:05:20 PM PDT 24
Peak memory 194100 kb
Host smart-5a292dd2-37ed-4118-85e9-c2927a43df9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263481716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1263481716
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.381105530
Short name T702
Test name
Test status
Simulation time 107136203 ps
CPU time 2.19 seconds
Started Jun 06 01:05:21 PM PDT 24
Finished Jun 06 01:05:24 PM PDT 24
Peak memory 199028 kb
Host smart-17362d74-6249-431d-82ff-206a9f4b1331
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381105530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.381105530
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.4219097371
Short name T675
Test name
Test status
Simulation time 404401096 ps
CPU time 3.79 seconds
Started Jun 06 01:05:16 PM PDT 24
Finished Jun 06 01:05:20 PM PDT 24
Peak memory 199436 kb
Host smart-190f79de-be1d-4f6e-9b46-77ecfd35ec99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219097371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.4219097371
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3426501726
Short name T721
Test name
Test status
Simulation time 155392145 ps
CPU time 1.73 seconds
Started Jun 06 01:05:19 PM PDT 24
Finished Jun 06 01:05:22 PM PDT 24
Peak memory 199372 kb
Host smart-09c964b7-460f-4035-8fc2-e48723a227c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426501726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3426501726
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3443990138
Short name T92
Test name
Test status
Simulation time 1852704316 ps
CPU time 8.62 seconds
Started Jun 06 01:04:58 PM PDT 24
Finished Jun 06 01:05:08 PM PDT 24
Peak memory 199324 kb
Host smart-599ac960-6071-4783-96a3-fe613496e011
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443990138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3443990138
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3289905921
Short name T94
Test name
Test status
Simulation time 311764468 ps
CPU time 14.06 seconds
Started Jun 06 01:04:53 PM PDT 24
Finished Jun 06 01:05:08 PM PDT 24
Peak memory 199100 kb
Host smart-5f5eec33-846f-480a-b711-9a84c2ea6c7a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289905921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3289905921
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.4144894331
Short name T89
Test name
Test status
Simulation time 48324875 ps
CPU time 0.88 seconds
Started Jun 06 01:04:58 PM PDT 24
Finished Jun 06 01:05:02 PM PDT 24
Peak memory 198364 kb
Host smart-0ee38f2d-0c6a-484e-9cec-32a31222e1a3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144894331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.4144894331
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.471724367
Short name T713
Test name
Test status
Simulation time 79993539 ps
CPU time 1.82 seconds
Started Jun 06 01:05:43 PM PDT 24
Finished Jun 06 01:05:46 PM PDT 24
Peak memory 199348 kb
Host smart-b84efddb-34cc-49df-b8f0-6f7423ffa855
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471724367 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.471724367
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.939509075
Short name T88
Test name
Test status
Simulation time 25176199 ps
CPU time 0.92 seconds
Started Jun 06 01:04:56 PM PDT 24
Finished Jun 06 01:04:57 PM PDT 24
Peak memory 198208 kb
Host smart-9713fac0-b511-4727-978b-4077d3fb3247
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939509075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.939509075
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.297778333
Short name T690
Test name
Test status
Simulation time 14213571 ps
CPU time 0.68 seconds
Started Jun 06 01:05:00 PM PDT 24
Finished Jun 06 01:05:02 PM PDT 24
Peak memory 194140 kb
Host smart-501e03e9-0385-4bd4-8b93-cc2893c3f11e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297778333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.297778333
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2141143238
Short name T655
Test name
Test status
Simulation time 195868474 ps
CPU time 1.17 seconds
Started Jun 06 01:04:55 PM PDT 24
Finished Jun 06 01:04:57 PM PDT 24
Peak memory 198960 kb
Host smart-2b500e3a-9e4b-4f7b-9175-2a93572b57f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141143238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2141143238
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1929222370
Short name T703
Test name
Test status
Simulation time 462478523 ps
CPU time 3.04 seconds
Started Jun 06 01:04:52 PM PDT 24
Finished Jun 06 01:04:56 PM PDT 24
Peak memory 199388 kb
Host smart-8bdf098b-10bb-4d90-8c44-e35c86047f14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929222370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1929222370
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.4234218539
Short name T123
Test name
Test status
Simulation time 173710217 ps
CPU time 2.84 seconds
Started Jun 06 01:05:13 PM PDT 24
Finished Jun 06 01:05:16 PM PDT 24
Peak memory 199372 kb
Host smart-10b3660f-2756-472c-9042-be31a59810aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234218539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.4234218539
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1413599920
Short name T722
Test name
Test status
Simulation time 24213428 ps
CPU time 0.59 seconds
Started Jun 06 01:05:21 PM PDT 24
Finished Jun 06 01:05:23 PM PDT 24
Peak memory 194032 kb
Host smart-d7f2aefa-5540-4efa-ab97-18985168d5af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413599920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1413599920
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3726448862
Short name T647
Test name
Test status
Simulation time 14123358 ps
CPU time 0.59 seconds
Started Jun 06 01:05:17 PM PDT 24
Finished Jun 06 01:05:19 PM PDT 24
Peak memory 194096 kb
Host smart-a4fde049-8760-4ecc-aa10-b39231498158
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726448862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3726448862
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.712678489
Short name T694
Test name
Test status
Simulation time 27520954 ps
CPU time 0.59 seconds
Started Jun 06 01:05:18 PM PDT 24
Finished Jun 06 01:05:20 PM PDT 24
Peak memory 194188 kb
Host smart-8c3dd659-6305-4808-a933-dd7435dddfc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712678489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.712678489
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1996964604
Short name T641
Test name
Test status
Simulation time 23191392 ps
CPU time 0.62 seconds
Started Jun 06 01:05:16 PM PDT 24
Finished Jun 06 01:05:17 PM PDT 24
Peak memory 194204 kb
Host smart-ee2d840b-cf9e-4401-baf0-fafd88d5c08f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996964604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1996964604
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2824662023
Short name T712
Test name
Test status
Simulation time 14441654 ps
CPU time 0.58 seconds
Started Jun 06 01:05:17 PM PDT 24
Finished Jun 06 01:05:19 PM PDT 24
Peak memory 194132 kb
Host smart-5993aecd-3546-402c-aa2d-397f81dd24c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824662023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2824662023
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1758712077
Short name T687
Test name
Test status
Simulation time 99637971 ps
CPU time 0.57 seconds
Started Jun 06 01:05:19 PM PDT 24
Finished Jun 06 01:05:21 PM PDT 24
Peak memory 194196 kb
Host smart-56ed6e81-aa35-422d-ada2-fad72e6eecf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758712077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1758712077
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.556624437
Short name T718
Test name
Test status
Simulation time 38708604 ps
CPU time 0.61 seconds
Started Jun 06 01:05:17 PM PDT 24
Finished Jun 06 01:05:19 PM PDT 24
Peak memory 194180 kb
Host smart-06406cfe-57ff-4a13-8bb2-b8fa338c15d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556624437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.556624437
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3098225053
Short name T617
Test name
Test status
Simulation time 23764976 ps
CPU time 0.6 seconds
Started Jun 06 01:05:17 PM PDT 24
Finished Jun 06 01:05:19 PM PDT 24
Peak memory 194080 kb
Host smart-0b9398a3-ede7-4c99-a5e6-d357fa62efc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098225053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3098225053
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1847779748
Short name T624
Test name
Test status
Simulation time 16823049 ps
CPU time 0.64 seconds
Started Jun 06 01:05:21 PM PDT 24
Finished Jun 06 01:05:23 PM PDT 24
Peak memory 193976 kb
Host smart-9026f24a-788f-42f2-b42b-71bb21a159ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847779748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1847779748
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2229684517
Short name T696
Test name
Test status
Simulation time 14628752 ps
CPU time 0.57 seconds
Started Jun 06 01:05:17 PM PDT 24
Finished Jun 06 01:05:19 PM PDT 24
Peak memory 194072 kb
Host smart-459edd7f-ebac-4b92-926a-771d35875294
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229684517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2229684517
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.709737149
Short name T682
Test name
Test status
Simulation time 211143060 ps
CPU time 5.61 seconds
Started Jun 06 01:04:59 PM PDT 24
Finished Jun 06 01:05:07 PM PDT 24
Peak memory 199260 kb
Host smart-a25c4df9-3a68-4200-8a51-a6ba62eb717b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709737149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.709737149
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3178961882
Short name T87
Test name
Test status
Simulation time 477685431 ps
CPU time 5.76 seconds
Started Jun 06 01:05:04 PM PDT 24
Finished Jun 06 01:05:12 PM PDT 24
Peak memory 199212 kb
Host smart-9eb06d4d-41f4-4de7-aff5-468bd4068632
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178961882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3178961882
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1048327618
Short name T699
Test name
Test status
Simulation time 223343730 ps
CPU time 0.85 seconds
Started Jun 06 01:04:55 PM PDT 24
Finished Jun 06 01:04:57 PM PDT 24
Peak memory 197876 kb
Host smart-f324bc66-b73a-429c-93d6-7c77fd697b03
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048327618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1048327618
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1496992048
Short name T670
Test name
Test status
Simulation time 156979369 ps
CPU time 2.6 seconds
Started Jun 06 01:05:00 PM PDT 24
Finished Jun 06 01:05:04 PM PDT 24
Peak memory 199400 kb
Host smart-b1c7444f-90ea-46a2-8fe9-d208aac621e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496992048 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1496992048
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2951907848
Short name T85
Test name
Test status
Simulation time 28288748 ps
CPU time 0.88 seconds
Started Jun 06 01:04:58 PM PDT 24
Finished Jun 06 01:05:01 PM PDT 24
Peak memory 198820 kb
Host smart-46a7c64e-259e-4f5d-9c98-a1ab03157cdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951907848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2951907848
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.1045836642
Short name T629
Test name
Test status
Simulation time 14586420 ps
CPU time 0.6 seconds
Started Jun 06 01:04:59 PM PDT 24
Finished Jun 06 01:05:01 PM PDT 24
Peak memory 194200 kb
Host smart-a4c334ed-30ae-4593-9290-303908947aa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045836642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.1045836642
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.236297914
Short name T664
Test name
Test status
Simulation time 22902816 ps
CPU time 1.01 seconds
Started Jun 06 01:05:05 PM PDT 24
Finished Jun 06 01:05:08 PM PDT 24
Peak memory 199280 kb
Host smart-181ee8aa-8e35-4024-8a1a-a76dc820fd92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236297914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.236297914
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.856878956
Short name T659
Test name
Test status
Simulation time 215497989 ps
CPU time 2.19 seconds
Started Jun 06 01:04:56 PM PDT 24
Finished Jun 06 01:04:59 PM PDT 24
Peak memory 199360 kb
Host smart-bd9abfde-7d8a-4910-a035-fdd9d35a5011
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856878956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.856878956
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2662422577
Short name T117
Test name
Test status
Simulation time 1014796019 ps
CPU time 4.27 seconds
Started Jun 06 01:04:55 PM PDT 24
Finished Jun 06 01:05:00 PM PDT 24
Peak memory 199348 kb
Host smart-62e4ccdd-6abe-4be2-b68c-7cdf3edd23aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662422577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2662422577
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1853681102
Short name T72
Test name
Test status
Simulation time 188697147 ps
CPU time 0.58 seconds
Started Jun 06 01:05:35 PM PDT 24
Finished Jun 06 01:05:37 PM PDT 24
Peak memory 194016 kb
Host smart-87fd1a6b-d323-4636-808c-4276b5809c7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853681102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1853681102
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.2442624598
Short name T666
Test name
Test status
Simulation time 37278655 ps
CPU time 0.58 seconds
Started Jun 06 01:05:30 PM PDT 24
Finished Jun 06 01:05:32 PM PDT 24
Peak memory 194076 kb
Host smart-79811bb7-1031-4df3-ab2a-1e220a565075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442624598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2442624598
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3670874207
Short name T695
Test name
Test status
Simulation time 54186628 ps
CPU time 0.62 seconds
Started Jun 06 01:05:30 PM PDT 24
Finished Jun 06 01:05:32 PM PDT 24
Peak memory 194168 kb
Host smart-27006d87-dff6-41af-9b1f-6197382ee959
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670874207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3670874207
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2468517432
Short name T727
Test name
Test status
Simulation time 36837254 ps
CPU time 0.58 seconds
Started Jun 06 01:05:29 PM PDT 24
Finished Jun 06 01:05:31 PM PDT 24
Peak memory 194132 kb
Host smart-0465f16b-ac6f-4df4-b186-dc069e03f76a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468517432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2468517432
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.2723458426
Short name T606
Test name
Test status
Simulation time 13581891 ps
CPU time 0.66 seconds
Started Jun 06 01:05:34 PM PDT 24
Finished Jun 06 01:05:36 PM PDT 24
Peak memory 194172 kb
Host smart-f44e1053-31b5-4ac1-a089-535a3dbc34b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723458426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2723458426
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.4180336334
Short name T643
Test name
Test status
Simulation time 12474395 ps
CPU time 0.61 seconds
Started Jun 06 01:05:30 PM PDT 24
Finished Jun 06 01:05:32 PM PDT 24
Peak memory 194144 kb
Host smart-cfcbd92e-52b0-4aa0-a05c-f84d6916a771
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180336334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.4180336334
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.4253240327
Short name T612
Test name
Test status
Simulation time 10858987 ps
CPU time 0.58 seconds
Started Jun 06 01:05:29 PM PDT 24
Finished Jun 06 01:05:31 PM PDT 24
Peak memory 194108 kb
Host smart-f2f29d71-32c5-4a45-9d33-02c7ce0a7042
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253240327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.4253240327
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2782531416
Short name T686
Test name
Test status
Simulation time 62681132 ps
CPU time 0.57 seconds
Started Jun 06 01:05:28 PM PDT 24
Finished Jun 06 01:05:30 PM PDT 24
Peak memory 194024 kb
Host smart-aeb673e5-aa93-4253-ac3b-69d874749294
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782531416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2782531416
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2559566518
Short name T677
Test name
Test status
Simulation time 57710652 ps
CPU time 0.6 seconds
Started Jun 06 01:05:29 PM PDT 24
Finished Jun 06 01:05:32 PM PDT 24
Peak memory 194132 kb
Host smart-02823ed9-ef1f-4804-beae-c1653f59f5bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559566518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2559566518
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1011443292
Short name T625
Test name
Test status
Simulation time 30380496 ps
CPU time 0.58 seconds
Started Jun 06 01:05:30 PM PDT 24
Finished Jun 06 01:05:33 PM PDT 24
Peak memory 194068 kb
Host smart-2062c328-b978-48c6-afa7-b5ae41492cde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011443292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1011443292
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3263628895
Short name T609
Test name
Test status
Simulation time 110909772 ps
CPU time 5.64 seconds
Started Jun 06 01:04:58 PM PDT 24
Finished Jun 06 01:05:05 PM PDT 24
Peak memory 199252 kb
Host smart-ca9dbaf7-37ce-4624-8f27-ad378021ad62
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263628895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3263628895
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.475209094
Short name T613
Test name
Test status
Simulation time 1463018413 ps
CPU time 10.9 seconds
Started Jun 06 01:05:06 PM PDT 24
Finished Jun 06 01:05:19 PM PDT 24
Peak memory 199152 kb
Host smart-b351e921-a4c7-4e56-8e1b-cdae999950dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475209094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.475209094
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.925165587
Short name T714
Test name
Test status
Simulation time 30192662 ps
CPU time 0.91 seconds
Started Jun 06 01:04:58 PM PDT 24
Finished Jun 06 01:05:00 PM PDT 24
Peak memory 198580 kb
Host smart-e970b1e2-75d0-43d6-b4b9-12844fef0954
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925165587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.925165587
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2654944000
Short name T53
Test name
Test status
Simulation time 47641974 ps
CPU time 1.23 seconds
Started Jun 06 01:04:58 PM PDT 24
Finished Jun 06 01:05:01 PM PDT 24
Peak memory 199176 kb
Host smart-8e41c77d-0bac-4115-bf0e-9f016fd40428
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654944000 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.2654944000
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.824933549
Short name T95
Test name
Test status
Simulation time 18289312 ps
CPU time 0.88 seconds
Started Jun 06 01:04:58 PM PDT 24
Finished Jun 06 01:05:01 PM PDT 24
Peak memory 199012 kb
Host smart-815a78d3-5e69-4ab5-9613-c3cc0efc6b6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824933549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.824933549
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.1113573929
Short name T672
Test name
Test status
Simulation time 18478577 ps
CPU time 0.62 seconds
Started Jun 06 01:04:56 PM PDT 24
Finished Jun 06 01:04:58 PM PDT 24
Peak memory 194168 kb
Host smart-c2621811-61ed-4f42-8663-56040921244c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113573929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1113573929
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3852288726
Short name T635
Test name
Test status
Simulation time 436645200 ps
CPU time 2.2 seconds
Started Jun 06 01:05:05 PM PDT 24
Finished Jun 06 01:05:11 PM PDT 24
Peak memory 199228 kb
Host smart-6e82e165-d290-41bc-b802-39894b3e9700
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852288726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3852288726
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.65508044
Short name T661
Test name
Test status
Simulation time 56886100 ps
CPU time 2.76 seconds
Started Jun 06 01:04:56 PM PDT 24
Finished Jun 06 01:04:59 PM PDT 24
Peak memory 199356 kb
Host smart-7dc9d805-ca64-476d-aa11-64f6307ce5ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65508044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.65508044
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.40842901
Short name T723
Test name
Test status
Simulation time 246009861 ps
CPU time 4.25 seconds
Started Jun 06 01:04:58 PM PDT 24
Finished Jun 06 01:05:05 PM PDT 24
Peak memory 199328 kb
Host smart-0a6da3ee-74e6-451c-a1dd-5ac3f5066b12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40842901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.40842901
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1663766420
Short name T665
Test name
Test status
Simulation time 15040804 ps
CPU time 0.58 seconds
Started Jun 06 01:05:30 PM PDT 24
Finished Jun 06 01:05:32 PM PDT 24
Peak memory 194080 kb
Host smart-d7cbeb1c-78c5-4613-beb5-414c78c4a52e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663766420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1663766420
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.87260917
Short name T673
Test name
Test status
Simulation time 17936263 ps
CPU time 0.62 seconds
Started Jun 06 01:05:29 PM PDT 24
Finished Jun 06 01:05:32 PM PDT 24
Peak memory 194152 kb
Host smart-87552ce2-70d5-42ef-85a0-76c7be9a668a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87260917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.87260917
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1274442775
Short name T628
Test name
Test status
Simulation time 16967230 ps
CPU time 0.6 seconds
Started Jun 06 01:05:30 PM PDT 24
Finished Jun 06 01:05:32 PM PDT 24
Peak memory 194072 kb
Host smart-ed75fb8a-5552-4c09-b8f3-3b4c84644355
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274442775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1274442775
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3854974603
Short name T610
Test name
Test status
Simulation time 10886439 ps
CPU time 0.65 seconds
Started Jun 06 01:05:33 PM PDT 24
Finished Jun 06 01:05:36 PM PDT 24
Peak memory 194080 kb
Host smart-ac1bebf6-86fa-4a12-ad7f-84a29321230d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854974603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3854974603
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2192706569
Short name T700
Test name
Test status
Simulation time 50123240 ps
CPU time 0.61 seconds
Started Jun 06 01:05:32 PM PDT 24
Finished Jun 06 01:05:34 PM PDT 24
Peak memory 194176 kb
Host smart-cd4cef48-e9b0-4d52-bfec-e1c3dd075c0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192706569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2192706569
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.866046464
Short name T623
Test name
Test status
Simulation time 34401543 ps
CPU time 0.56 seconds
Started Jun 06 01:05:30 PM PDT 24
Finished Jun 06 01:05:32 PM PDT 24
Peak memory 194104 kb
Host smart-f93b10e3-b8b1-4ca7-89f0-d51e199b0fd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866046464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.866046464
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.359752502
Short name T688
Test name
Test status
Simulation time 18695789 ps
CPU time 0.6 seconds
Started Jun 06 01:05:30 PM PDT 24
Finished Jun 06 01:05:32 PM PDT 24
Peak memory 194216 kb
Host smart-88bdc5f1-f05f-43c7-8979-8c403ffef47c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359752502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.359752502
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.2949641454
Short name T642
Test name
Test status
Simulation time 14089713 ps
CPU time 0.59 seconds
Started Jun 06 01:05:28 PM PDT 24
Finished Jun 06 01:05:30 PM PDT 24
Peak memory 194056 kb
Host smart-96c32f1d-1c57-4dbc-b647-e322740fe228
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949641454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2949641454
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.4245920788
Short name T708
Test name
Test status
Simulation time 34746639 ps
CPU time 0.58 seconds
Started Jun 06 01:05:31 PM PDT 24
Finished Jun 06 01:05:34 PM PDT 24
Peak memory 194132 kb
Host smart-2badf275-e1f7-446b-a467-25a73729c156
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245920788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.4245920788
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.902739817
Short name T685
Test name
Test status
Simulation time 28389358 ps
CPU time 0.57 seconds
Started Jun 06 01:05:32 PM PDT 24
Finished Jun 06 01:05:34 PM PDT 24
Peak memory 194144 kb
Host smart-5cb6719f-5ebc-40ec-8eaa-dcd45716b3ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902739817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.902739817
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3932183395
Short name T698
Test name
Test status
Simulation time 34116192 ps
CPU time 1.04 seconds
Started Jun 06 01:04:58 PM PDT 24
Finished Jun 06 01:05:00 PM PDT 24
Peak memory 199188 kb
Host smart-f4c6d0f8-34e0-4d1a-a8f4-3209d2528332
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932183395 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3932183395
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.423179378
Short name T669
Test name
Test status
Simulation time 21056424 ps
CPU time 0.78 seconds
Started Jun 06 01:04:59 PM PDT 24
Finished Jun 06 01:05:02 PM PDT 24
Peak memory 197012 kb
Host smart-b38adf14-e7e6-4652-aa5d-b3e80d003ffb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423179378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.423179378
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1923004692
Short name T640
Test name
Test status
Simulation time 17270336 ps
CPU time 0.59 seconds
Started Jun 06 01:04:57 PM PDT 24
Finished Jun 06 01:04:59 PM PDT 24
Peak memory 194080 kb
Host smart-f0b42238-fa8f-4a95-8525-09ede6052e86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923004692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1923004692
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1905625006
Short name T650
Test name
Test status
Simulation time 44323675 ps
CPU time 2.08 seconds
Started Jun 06 01:04:57 PM PDT 24
Finished Jun 06 01:05:00 PM PDT 24
Peak memory 199376 kb
Host smart-a5886a50-66b5-4dcf-9a2b-467a3b6a0874
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905625006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1905625006
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2479884422
Short name T652
Test name
Test status
Simulation time 150119255 ps
CPU time 2.82 seconds
Started Jun 06 01:04:57 PM PDT 24
Finished Jun 06 01:05:01 PM PDT 24
Peak memory 199344 kb
Host smart-06ac198e-f821-4722-bfc3-0ae9ba029846
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479884422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.2479884422
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2243804870
Short name T126
Test name
Test status
Simulation time 253676648 ps
CPU time 4.16 seconds
Started Jun 06 01:04:57 PM PDT 24
Finished Jun 06 01:05:03 PM PDT 24
Peak memory 199412 kb
Host smart-570775f6-c99b-4148-811d-503c89e34838
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243804870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2243804870
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1879423861
Short name T729
Test name
Test status
Simulation time 128683726 ps
CPU time 1.89 seconds
Started Jun 06 01:04:59 PM PDT 24
Finished Jun 06 01:05:03 PM PDT 24
Peak memory 199428 kb
Host smart-08cde591-f9f0-4ba8-ba25-88f3d0d54d37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879423861 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1879423861
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.600935452
Short name T720
Test name
Test status
Simulation time 99395068 ps
CPU time 0.79 seconds
Started Jun 06 01:05:05 PM PDT 24
Finished Jun 06 01:05:08 PM PDT 24
Peak memory 198980 kb
Host smart-4256efa8-8796-4baa-8544-bd5ee7fb42c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600935452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.600935452
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.252017243
Short name T710
Test name
Test status
Simulation time 11510991 ps
CPU time 0.59 seconds
Started Jun 06 01:04:59 PM PDT 24
Finished Jun 06 01:05:01 PM PDT 24
Peak memory 194144 kb
Host smart-e1ead3a0-d0f2-48cd-952b-e7194ce23b53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252017243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.252017243
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.4161430437
Short name T678
Test name
Test status
Simulation time 1727430889 ps
CPU time 2.17 seconds
Started Jun 06 01:05:00 PM PDT 24
Finished Jun 06 01:05:04 PM PDT 24
Peak memory 199360 kb
Host smart-57b8120f-94a8-4af9-9c30-9a64302cc00e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161430437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.4161430437
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.319325392
Short name T604
Test name
Test status
Simulation time 874515628 ps
CPU time 3.73 seconds
Started Jun 06 01:04:58 PM PDT 24
Finished Jun 06 01:05:03 PM PDT 24
Peak memory 199340 kb
Host smart-3ae35f8d-0f56-4207-8cc8-f745598d2951
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319325392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.319325392
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3130622886
Short name T116
Test name
Test status
Simulation time 115579163 ps
CPU time 1.65 seconds
Started Jun 06 01:05:04 PM PDT 24
Finished Jun 06 01:05:08 PM PDT 24
Peak memory 199280 kb
Host smart-1e0b1800-c8b6-4649-b46e-33761c50375d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130622886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3130622886
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4277089929
Short name T724
Test name
Test status
Simulation time 392527730 ps
CPU time 2.3 seconds
Started Jun 06 01:05:04 PM PDT 24
Finished Jun 06 01:05:08 PM PDT 24
Peak memory 199412 kb
Host smart-0d4ff426-3d56-49f9-b601-abfcb69ea206
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277089929 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.4277089929
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2870012245
Short name T646
Test name
Test status
Simulation time 13605827 ps
CPU time 0.68 seconds
Started Jun 06 01:05:07 PM PDT 24
Finished Jun 06 01:05:11 PM PDT 24
Peak memory 196740 kb
Host smart-a8ec8dcb-ec7b-485d-98b8-fba9438f17ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870012245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2870012245
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1388213414
Short name T657
Test name
Test status
Simulation time 11531448 ps
CPU time 0.55 seconds
Started Jun 06 01:05:00 PM PDT 24
Finished Jun 06 01:05:03 PM PDT 24
Peak memory 194060 kb
Host smart-caaf09ea-9c28-469c-9069-be2825a807d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388213414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1388213414
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2584988283
Short name T627
Test name
Test status
Simulation time 158779672 ps
CPU time 1.8 seconds
Started Jun 06 01:05:05 PM PDT 24
Finished Jun 06 01:05:09 PM PDT 24
Peak memory 199272 kb
Host smart-ff013137-a58a-4f70-a1c9-fa2854bc3900
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584988283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2584988283
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.917385028
Short name T680
Test name
Test status
Simulation time 160428590 ps
CPU time 2.94 seconds
Started Jun 06 01:05:05 PM PDT 24
Finished Jun 06 01:05:10 PM PDT 24
Peak memory 199368 kb
Host smart-223434d3-ec13-44c3-8fca-5242c8556878
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917385028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.917385028
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.4215773573
Short name T124
Test name
Test status
Simulation time 82968608 ps
CPU time 1.9 seconds
Started Jun 06 01:04:58 PM PDT 24
Finished Jun 06 01:05:02 PM PDT 24
Peak memory 199280 kb
Host smart-b511e5ce-9509-4e29-81e9-288b57a58965
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215773573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.4215773573
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2074362622
Short name T55
Test name
Test status
Simulation time 55617994997 ps
CPU time 825.27 seconds
Started Jun 06 01:05:03 PM PDT 24
Finished Jun 06 01:18:50 PM PDT 24
Peak memory 215824 kb
Host smart-e4e76586-2845-40dd-a996-c950e9d85411
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074362622 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2074362622
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1917471706
Short name T97
Test name
Test status
Simulation time 82517138 ps
CPU time 0.83 seconds
Started Jun 06 01:05:03 PM PDT 24
Finished Jun 06 01:05:05 PM PDT 24
Peak memory 198412 kb
Host smart-c057eb51-6c95-4a47-9a52-a0c42149dd2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917471706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1917471706
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.2266374072
Short name T605
Test name
Test status
Simulation time 20290421 ps
CPU time 0.61 seconds
Started Jun 06 01:05:03 PM PDT 24
Finished Jun 06 01:05:05 PM PDT 24
Peak memory 194176 kb
Host smart-d63670c8-ca14-46e5-bdab-7658ae10b1df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266374072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2266374072
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2975045970
Short name T658
Test name
Test status
Simulation time 24423552 ps
CPU time 1.14 seconds
Started Jun 06 01:05:03 PM PDT 24
Finished Jun 06 01:05:06 PM PDT 24
Peak memory 199120 kb
Host smart-a387fbb6-111d-40a5-aa13-c192fbb7657d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975045970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.2975045970
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.736648131
Short name T728
Test name
Test status
Simulation time 350013996 ps
CPU time 3.79 seconds
Started Jun 06 01:05:05 PM PDT 24
Finished Jun 06 01:05:12 PM PDT 24
Peak memory 199368 kb
Host smart-7bdc0796-9a72-4232-b06e-1a4654ecc528
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736648131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.736648131
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1366469011
Short name T115
Test name
Test status
Simulation time 171188954 ps
CPU time 1.68 seconds
Started Jun 06 01:05:03 PM PDT 24
Finished Jun 06 01:05:07 PM PDT 24
Peak memory 199304 kb
Host smart-5a5597e0-864c-41aa-a5f3-81b6df0b1cd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366469011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1366469011
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2232827743
Short name T709
Test name
Test status
Simulation time 119377104 ps
CPU time 1.05 seconds
Started Jun 06 01:05:06 PM PDT 24
Finished Jun 06 01:05:10 PM PDT 24
Peak memory 199212 kb
Host smart-a0dcdf9a-44dc-4641-8fcb-063b3c2538cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232827743 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2232827743
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.135931876
Short name T707
Test name
Test status
Simulation time 30528979 ps
CPU time 0.88 seconds
Started Jun 06 01:05:05 PM PDT 24
Finished Jun 06 01:05:09 PM PDT 24
Peak memory 198748 kb
Host smart-f9dcc43f-b050-4db9-9f73-01141d2bb93e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135931876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.135931876
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.308535012
Short name T622
Test name
Test status
Simulation time 89171816 ps
CPU time 0.6 seconds
Started Jun 06 01:05:05 PM PDT 24
Finished Jun 06 01:05:08 PM PDT 24
Peak memory 194124 kb
Host smart-0048a8ad-e2fe-48ab-a9a2-5f126d578e9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308535012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.308535012
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.520908053
Short name T51
Test name
Test status
Simulation time 44097170 ps
CPU time 1.12 seconds
Started Jun 06 01:05:06 PM PDT 24
Finished Jun 06 01:05:10 PM PDT 24
Peak memory 199128 kb
Host smart-a41df6bf-c3e6-47bf-bcfe-8c2b49ada964
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520908053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.520908053
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2609813303
Short name T676
Test name
Test status
Simulation time 121257411 ps
CPU time 1.82 seconds
Started Jun 06 01:05:05 PM PDT 24
Finished Jun 06 01:05:10 PM PDT 24
Peak memory 199340 kb
Host smart-238277d4-a1f7-495b-8715-fae0b999de42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609813303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2609813303
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2929699254
Short name T122
Test name
Test status
Simulation time 87070039 ps
CPU time 1.64 seconds
Started Jun 06 01:05:03 PM PDT 24
Finished Jun 06 01:05:07 PM PDT 24
Peak memory 199192 kb
Host smart-80218664-1fa2-4389-acab-579cec83a9a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929699254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2929699254
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.823891379
Short name T601
Test name
Test status
Simulation time 44128780 ps
CPU time 0.59 seconds
Started Jun 06 01:05:59 PM PDT 24
Finished Jun 06 01:06:01 PM PDT 24
Peak memory 196236 kb
Host smart-9a5fab3d-a59c-40ca-ad71-c4360286729a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823891379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.823891379
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2872694938
Short name T19
Test name
Test status
Simulation time 935816678 ps
CPU time 43.17 seconds
Started Jun 06 01:05:46 PM PDT 24
Finished Jun 06 01:06:31 PM PDT 24
Peak memory 229988 kb
Host smart-3626459d-e9cd-47f2-be72-ec4ea19ee309
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2872694938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2872694938
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.2559411289
Short name T445
Test name
Test status
Simulation time 5787383624 ps
CPU time 55.45 seconds
Started Jun 06 01:05:45 PM PDT 24
Finished Jun 06 01:06:41 PM PDT 24
Peak memory 200420 kb
Host smart-13627687-8c2d-449d-8f85-155affcad604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559411289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2559411289
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.3110216538
Short name T200
Test name
Test status
Simulation time 5756528168 ps
CPU time 554.51 seconds
Started Jun 06 01:05:49 PM PDT 24
Finished Jun 06 01:15:05 PM PDT 24
Peak memory 726316 kb
Host smart-7678ad37-857c-4272-96b3-2cb8cd5473fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3110216538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3110216538
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1019094875
Short name T341
Test name
Test status
Simulation time 4654273344 ps
CPU time 11.76 seconds
Started Jun 06 01:05:50 PM PDT 24
Finished Jun 06 01:06:03 PM PDT 24
Peak memory 200424 kb
Host smart-16597235-0a08-4bd7-accb-13ad68d6821a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019094875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1019094875
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.4157189566
Short name T147
Test name
Test status
Simulation time 2376845008 ps
CPU time 51.51 seconds
Started Jun 06 01:05:59 PM PDT 24
Finished Jun 06 01:06:52 PM PDT 24
Peak memory 200496 kb
Host smart-6a973bfc-e4f4-434d-b4e0-d588d30a9060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157189566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.4157189566
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.4131978180
Short name T397
Test name
Test status
Simulation time 113193673 ps
CPU time 1.16 seconds
Started Jun 06 01:05:54 PM PDT 24
Finished Jun 06 01:05:56 PM PDT 24
Peak memory 199572 kb
Host smart-147368ec-0b0f-467c-88c7-fae3b321fcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131978180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.4131978180
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3177554676
Short name T532
Test name
Test status
Simulation time 14352401846 ps
CPU time 740.32 seconds
Started Jun 06 01:05:57 PM PDT 24
Finished Jun 06 01:18:19 PM PDT 24
Peak memory 241344 kb
Host smart-476af112-80b5-4074-93d4-4931abc61ae0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177554676 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3177554676
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.204451304
Short name T359
Test name
Test status
Simulation time 108189589 ps
CPU time 1.04 seconds
Started Jun 06 01:05:59 PM PDT 24
Finished Jun 06 01:06:01 PM PDT 24
Peak memory 200372 kb
Host smart-1242a602-7fde-4928-a727-cdad0cf95db3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204451304 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_hmac_vectors.204451304
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.1915113149
Short name T174
Test name
Test status
Simulation time 53318301108 ps
CPU time 484.04 seconds
Started Jun 06 01:05:46 PM PDT 24
Finished Jun 06 01:13:51 PM PDT 24
Peak memory 200364 kb
Host smart-8ec80b74-cd58-4383-b682-eb23fb2861ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915113149 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.1915113149
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.2505928235
Short name T511
Test name
Test status
Simulation time 8678447800 ps
CPU time 28.43 seconds
Started Jun 06 01:05:48 PM PDT 24
Finished Jun 06 01:06:17 PM PDT 24
Peak memory 200316 kb
Host smart-5fa66231-4894-4079-935e-7ec5053975ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505928235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.2505928235
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.337715623
Short name T351
Test name
Test status
Simulation time 47870366 ps
CPU time 0.58 seconds
Started Jun 06 01:05:58 PM PDT 24
Finished Jun 06 01:06:00 PM PDT 24
Peak memory 196200 kb
Host smart-99496e11-51fc-4b7f-94c5-4fab6186a354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337715623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.337715623
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.893359331
Short name T263
Test name
Test status
Simulation time 2082320980 ps
CPU time 22.39 seconds
Started Jun 06 01:06:04 PM PDT 24
Finished Jun 06 01:06:27 PM PDT 24
Peak memory 200400 kb
Host smart-202f395f-2b00-4816-9e3f-14e4fbf98e23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=893359331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.893359331
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.1920424147
Short name T579
Test name
Test status
Simulation time 17667746699 ps
CPU time 47.81 seconds
Started Jun 06 01:05:59 PM PDT 24
Finished Jun 06 01:06:48 PM PDT 24
Peak memory 200464 kb
Host smart-6ba6f36d-b1e7-4dc2-ae36-61a89c850dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920424147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1920424147
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1227710117
Short name T447
Test name
Test status
Simulation time 50501434 ps
CPU time 1.21 seconds
Started Jun 06 01:06:03 PM PDT 24
Finished Jun 06 01:06:05 PM PDT 24
Peak memory 211092 kb
Host smart-51c1e75f-af72-4350-86c9-19e4c6467dad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1227710117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1227710117
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3552419700
Short name T233
Test name
Test status
Simulation time 4486455269 ps
CPU time 80.17 seconds
Started Jun 06 01:05:59 PM PDT 24
Finished Jun 06 01:07:21 PM PDT 24
Peak memory 200436 kb
Host smart-c980f8a0-644c-4671-939b-3f42f678b03d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552419700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3552419700
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.403267047
Short name T146
Test name
Test status
Simulation time 3249267049 ps
CPU time 45.72 seconds
Started Jun 06 01:05:59 PM PDT 24
Finished Jun 06 01:06:46 PM PDT 24
Peak memory 200452 kb
Host smart-66ba07f9-9ddb-46ff-95ba-1117a9963eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403267047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.403267047
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.2032177891
Short name T30
Test name
Test status
Simulation time 32588425 ps
CPU time 0.86 seconds
Started Jun 06 01:06:00 PM PDT 24
Finished Jun 06 01:06:02 PM PDT 24
Peak memory 218700 kb
Host smart-857d9e62-c086-49f7-a5c1-2368f71ccc9c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032177891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2032177891
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3256823546
Short name T535
Test name
Test status
Simulation time 79751646 ps
CPU time 0.91 seconds
Started Jun 06 01:05:59 PM PDT 24
Finished Jun 06 01:06:01 PM PDT 24
Peak memory 199208 kb
Host smart-ec311f4a-6d90-4f2e-92d8-94ef73de3977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256823546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3256823546
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.2147362867
Short name T106
Test name
Test status
Simulation time 40090670085 ps
CPU time 1100.15 seconds
Started Jun 06 01:06:00 PM PDT 24
Finished Jun 06 01:24:22 PM PDT 24
Peak memory 734824 kb
Host smart-846c8ba3-f9ba-4e7b-967b-514826ce86f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147362867 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2147362867
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.619781383
Short name T499
Test name
Test status
Simulation time 45234231 ps
CPU time 1.16 seconds
Started Jun 06 01:06:00 PM PDT 24
Finished Jun 06 01:06:02 PM PDT 24
Peak memory 200412 kb
Host smart-a81400b3-47f4-4ed2-960a-371d7332b465
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619781383 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_hmac_vectors.619781383
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.3312324893
Short name T236
Test name
Test status
Simulation time 29645817725 ps
CPU time 512.5 seconds
Started Jun 06 01:06:02 PM PDT 24
Finished Jun 06 01:14:36 PM PDT 24
Peak memory 200396 kb
Host smart-8ffa9f76-834a-4570-aa86-c61fb46822fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312324893 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.3312324893
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1660648838
Short name T276
Test name
Test status
Simulation time 1312535290 ps
CPU time 50.69 seconds
Started Jun 06 01:05:58 PM PDT 24
Finished Jun 06 01:06:50 PM PDT 24
Peak memory 200356 kb
Host smart-38ff31e3-95bc-4323-bee5-a539e8cacbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660648838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1660648838
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2076537926
Short name T285
Test name
Test status
Simulation time 45011765 ps
CPU time 0.6 seconds
Started Jun 06 01:06:17 PM PDT 24
Finished Jun 06 01:06:20 PM PDT 24
Peak memory 195200 kb
Host smart-05616042-35d8-4083-99f9-9d014615b94e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076537926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2076537926
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.487507685
Short name T315
Test name
Test status
Simulation time 1496055037 ps
CPU time 19.34 seconds
Started Jun 06 01:06:16 PM PDT 24
Finished Jun 06 01:06:37 PM PDT 24
Peak memory 216800 kb
Host smart-f31ccc1a-3d70-48be-8b22-103ffba6f74c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=487507685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.487507685
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.140466569
Short name T464
Test name
Test status
Simulation time 4864308067 ps
CPU time 18.89 seconds
Started Jun 06 01:06:18 PM PDT 24
Finished Jun 06 01:06:40 PM PDT 24
Peak memory 200452 kb
Host smart-ca744fd4-0770-496c-95bd-4bed80dea29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140466569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.140466569
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.3621920075
Short name T194
Test name
Test status
Simulation time 1811776909 ps
CPU time 466.63 seconds
Started Jun 06 01:06:17 PM PDT 24
Finished Jun 06 01:14:05 PM PDT 24
Peak memory 692200 kb
Host smart-44fbb068-09f4-4a31-964f-0c99b31d3d79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3621920075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.3621920075
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.556769645
Short name T152
Test name
Test status
Simulation time 14570245622 ps
CPU time 121.27 seconds
Started Jun 06 01:06:22 PM PDT 24
Finished Jun 06 01:08:25 PM PDT 24
Peak memory 200384 kb
Host smart-2e1e87d1-cb0c-445c-a372-e2205ea4086b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556769645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.556769645
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.1515845164
Short name T403
Test name
Test status
Simulation time 15466341065 ps
CPU time 74.04 seconds
Started Jun 06 01:06:18 PM PDT 24
Finished Jun 06 01:07:35 PM PDT 24
Peak memory 200396 kb
Host smart-264400da-e745-4b6d-b726-1ef01980e384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515845164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1515845164
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.2951016026
Short name T163
Test name
Test status
Simulation time 64050743 ps
CPU time 2.46 seconds
Started Jun 06 01:06:21 PM PDT 24
Finished Jun 06 01:06:26 PM PDT 24
Peak memory 200408 kb
Host smart-ab84ef3f-7bb5-4d52-8b00-e9f7f5d295be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951016026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.2951016026
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3651882326
Short name T384
Test name
Test status
Simulation time 133619343246 ps
CPU time 1182.76 seconds
Started Jun 06 01:06:19 PM PDT 24
Finished Jun 06 01:26:04 PM PDT 24
Peak memory 216748 kb
Host smart-5fef6444-076c-405e-8bfc-9784dd814570
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651882326 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3651882326
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.2539857656
Short name T428
Test name
Test status
Simulation time 62953507 ps
CPU time 1.41 seconds
Started Jun 06 01:06:18 PM PDT 24
Finished Jun 06 01:06:21 PM PDT 24
Peak memory 200448 kb
Host smart-9180216f-9177-4c39-956e-b4548dbe3b4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539857656 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.2539857656
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.1203604237
Short name T419
Test name
Test status
Simulation time 27839502392 ps
CPU time 507.32 seconds
Started Jun 06 01:06:18 PM PDT 24
Finished Jun 06 01:14:48 PM PDT 24
Peak memory 200384 kb
Host smart-00dc50c1-3601-4d17-a8b6-21f48d1c8b92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203604237 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.1203604237
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2036889529
Short name T375
Test name
Test status
Simulation time 10811405829 ps
CPU time 53.57 seconds
Started Jun 06 01:06:22 PM PDT 24
Finished Jun 06 01:07:18 PM PDT 24
Peak memory 200468 kb
Host smart-da06b97e-2dd6-48e6-b183-ff8dbaf2f37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036889529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2036889529
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1080575254
Short name T257
Test name
Test status
Simulation time 44636041 ps
CPU time 0.56 seconds
Started Jun 06 01:06:13 PM PDT 24
Finished Jun 06 01:06:15 PM PDT 24
Peak memory 196964 kb
Host smart-8ce5232f-dd82-49e7-8740-955034def97c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080575254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1080575254
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2483043974
Short name T155
Test name
Test status
Simulation time 120564472 ps
CPU time 3.61 seconds
Started Jun 06 01:06:20 PM PDT 24
Finished Jun 06 01:06:26 PM PDT 24
Peak memory 200164 kb
Host smart-427bb371-02f8-469c-a4b7-2a41c8d67f12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2483043974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2483043974
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.1524386260
Short name T107
Test name
Test status
Simulation time 4136740835 ps
CPU time 51.97 seconds
Started Jun 06 01:06:17 PM PDT 24
Finished Jun 06 01:07:11 PM PDT 24
Peak memory 200436 kb
Host smart-9c3c5bd7-530c-4b60-b7e3-f57bc02ffcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524386260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1524386260
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.3096267170
Short name T462
Test name
Test status
Simulation time 1887510970 ps
CPU time 409.91 seconds
Started Jun 06 01:06:16 PM PDT 24
Finished Jun 06 01:13:08 PM PDT 24
Peak memory 649212 kb
Host smart-62764432-7ebe-4406-906a-a6d0215a0c0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3096267170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3096267170
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1506725422
Short name T568
Test name
Test status
Simulation time 8115763547 ps
CPU time 31.18 seconds
Started Jun 06 01:06:24 PM PDT 24
Finished Jun 06 01:06:56 PM PDT 24
Peak memory 200276 kb
Host smart-23f70368-4bb0-494e-b46c-8fd078ee723a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506725422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1506725422
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_smoke.497481864
Short name T449
Test name
Test status
Simulation time 2782405248 ps
CPU time 12.28 seconds
Started Jun 06 01:06:15 PM PDT 24
Finished Jun 06 01:06:29 PM PDT 24
Peak memory 200428 kb
Host smart-48b93ef8-27ac-4113-ac77-1c6fcab622fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497481864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.497481864
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.688959252
Short name T258
Test name
Test status
Simulation time 21615540015 ps
CPU time 433.41 seconds
Started Jun 06 01:06:19 PM PDT 24
Finished Jun 06 01:13:35 PM PDT 24
Peak memory 200436 kb
Host smart-4f7c9566-3a82-47cd-aba7-7e034eb6c682
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688959252 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.688959252
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.1105858766
Short name T241
Test name
Test status
Simulation time 237247201 ps
CPU time 1.07 seconds
Started Jun 06 01:06:19 PM PDT 24
Finished Jun 06 01:06:22 PM PDT 24
Peak memory 200244 kb
Host smart-ab3bd25e-f4cc-44a3-80c7-e023a629773e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105858766 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.1105858766
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.3069480663
Short name T405
Test name
Test status
Simulation time 148844581276 ps
CPU time 508.06 seconds
Started Jun 06 01:06:23 PM PDT 24
Finished Jun 06 01:14:53 PM PDT 24
Peak memory 200376 kb
Host smart-db599b69-3546-4bdd-870d-57bb142a482c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069480663 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.3069480663
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.3797293240
Short name T442
Test name
Test status
Simulation time 495282316 ps
CPU time 21.72 seconds
Started Jun 06 01:06:16 PM PDT 24
Finished Jun 06 01:06:39 PM PDT 24
Peak memory 200292 kb
Host smart-c0633da6-7216-45ba-a210-9e8d34da7fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797293240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3797293240
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/113.hmac_stress_all_with_rand_reset.2184047991
Short name T11
Test name
Test status
Simulation time 55951369427 ps
CPU time 2180.26 seconds
Started Jun 06 01:08:29 PM PDT 24
Finished Jun 06 01:44:51 PM PDT 24
Peak memory 754804 kb
Host smart-4636c231-4b8f-4413-befe-9ec83ea158ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2184047991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.hmac_stress_all_with_rand_reset.2184047991
Directory /workspace/113.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.4275401950
Short name T331
Test name
Test status
Simulation time 1140172048 ps
CPU time 62.62 seconds
Started Jun 06 01:06:20 PM PDT 24
Finished Jun 06 01:07:25 PM PDT 24
Peak memory 233088 kb
Host smart-0180754b-35e7-4065-a42a-3e438add10f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4275401950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.4275401950
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1842996312
Short name T36
Test name
Test status
Simulation time 6654915033 ps
CPU time 24.24 seconds
Started Jun 06 01:06:22 PM PDT 24
Finished Jun 06 01:06:48 PM PDT 24
Peak memory 200436 kb
Host smart-f9880893-ffe2-4dd7-a981-20cc6c22ebb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842996312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1842996312
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3128581933
Short name T81
Test name
Test status
Simulation time 1573016299 ps
CPU time 410.21 seconds
Started Jun 06 01:06:22 PM PDT 24
Finished Jun 06 01:13:15 PM PDT 24
Peak memory 639284 kb
Host smart-3fbb7f3f-b121-45be-ab5e-3957e7f9b4ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3128581933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3128581933
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1246747016
Short name T469
Test name
Test status
Simulation time 23404888944 ps
CPU time 104.11 seconds
Started Jun 06 01:06:22 PM PDT 24
Finished Jun 06 01:08:08 PM PDT 24
Peak memory 200392 kb
Host smart-c2308e83-a71c-4b3c-9e80-ae244d190ab8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246747016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1246747016
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.2547291374
Short name T498
Test name
Test status
Simulation time 2257577472 ps
CPU time 89.75 seconds
Started Jun 06 01:06:19 PM PDT 24
Finished Jun 06 01:07:51 PM PDT 24
Peak memory 200448 kb
Host smart-a74922ca-99c0-4aca-92af-7c08d8922f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547291374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2547291374
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3883433884
Short name T522
Test name
Test status
Simulation time 654255909 ps
CPU time 6.37 seconds
Started Jun 06 01:06:18 PM PDT 24
Finished Jun 06 01:06:26 PM PDT 24
Peak memory 200320 kb
Host smart-d5b729cf-8193-4aa4-beea-0373642eebd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883433884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3883433884
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.3450768664
Short name T179
Test name
Test status
Simulation time 30721729 ps
CPU time 1.18 seconds
Started Jun 06 01:06:23 PM PDT 24
Finished Jun 06 01:06:26 PM PDT 24
Peak memory 200356 kb
Host smart-81d54441-e906-41cd-9645-66a1e87af823
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450768664 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.3450768664
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.780826998
Short name T468
Test name
Test status
Simulation time 16029868837 ps
CPU time 447.41 seconds
Started Jun 06 01:06:17 PM PDT 24
Finished Jun 06 01:13:46 PM PDT 24
Peak memory 200432 kb
Host smart-76421bbc-6574-402c-8349-6c29b61c86af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780826998 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.780826998
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.1203473490
Short name T441
Test name
Test status
Simulation time 4859397327 ps
CPU time 44.63 seconds
Started Jun 06 01:06:22 PM PDT 24
Finished Jun 06 01:07:09 PM PDT 24
Peak memory 200396 kb
Host smart-3c5c4a34-93f1-4253-a36a-16a8f9867f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203473490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1203473490
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/120.hmac_stress_all_with_rand_reset.5236241
Short name T8
Test name
Test status
Simulation time 45785697725 ps
CPU time 1049.59 seconds
Started Jun 06 01:08:41 PM PDT 24
Finished Jun 06 01:26:13 PM PDT 24
Peak memory 241620 kb
Host smart-50d33e9b-78ea-48fb-a22b-b9f143971604
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=5236241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.hmac_stress_all_with_rand_reset.5236241
Directory /workspace/120.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3165817577
Short name T333
Test name
Test status
Simulation time 10937160 ps
CPU time 0.57 seconds
Started Jun 06 01:06:28 PM PDT 24
Finished Jun 06 01:06:31 PM PDT 24
Peak memory 195192 kb
Host smart-cffaacb1-c1b9-4487-84a9-2ecad4be8ec9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165817577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3165817577
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3735128655
Short name T518
Test name
Test status
Simulation time 986247414 ps
CPU time 44.51 seconds
Started Jun 06 01:06:27 PM PDT 24
Finished Jun 06 01:07:14 PM PDT 24
Peak memory 224424 kb
Host smart-24de71f3-2d64-4de7-905b-94ca7c7d61da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3735128655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3735128655
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.23464914
Short name T361
Test name
Test status
Simulation time 785390054 ps
CPU time 40 seconds
Started Jun 06 01:06:27 PM PDT 24
Finished Jun 06 01:07:09 PM PDT 24
Peak memory 200388 kb
Host smart-6f1e4bf8-4329-4b52-b463-a02e3be6995a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23464914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.23464914
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1201103636
Short name T108
Test name
Test status
Simulation time 7704310115 ps
CPU time 974.53 seconds
Started Jun 06 01:06:38 PM PDT 24
Finished Jun 06 01:22:54 PM PDT 24
Peak memory 727496 kb
Host smart-74d0e386-a729-435b-9b0c-f8d7a38dad58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1201103636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1201103636
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.3410110172
Short name T209
Test name
Test status
Simulation time 2016431946 ps
CPU time 25.23 seconds
Started Jun 06 01:06:30 PM PDT 24
Finished Jun 06 01:06:57 PM PDT 24
Peak memory 200332 kb
Host smart-7f3f1134-16b4-4a1a-9aa1-4c4fc02cd691
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410110172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3410110172
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1816983858
Short name T455
Test name
Test status
Simulation time 6250616080 ps
CPU time 65.31 seconds
Started Jun 06 01:06:26 PM PDT 24
Finished Jun 06 01:07:33 PM PDT 24
Peak memory 200440 kb
Host smart-2770516c-66cd-4e88-8299-a7d755c23e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816983858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1816983858
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.628418524
Short name T515
Test name
Test status
Simulation time 554311163 ps
CPU time 2.73 seconds
Started Jun 06 01:06:31 PM PDT 24
Finished Jun 06 01:06:35 PM PDT 24
Peak memory 200428 kb
Host smart-9b666ec0-70ac-4464-8843-605069993a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628418524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.628418524
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.1634137774
Short name T7
Test name
Test status
Simulation time 84136838527 ps
CPU time 3494.34 seconds
Started Jun 06 01:06:27 PM PDT 24
Finished Jun 06 02:04:44 PM PDT 24
Peak memory 858532 kb
Host smart-5ff3a92b-3805-4727-b055-ee9550567998
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634137774 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1634137774
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.3797581732
Short name T395
Test name
Test status
Simulation time 250235505 ps
CPU time 1.45 seconds
Started Jun 06 01:06:26 PM PDT 24
Finished Jun 06 01:06:29 PM PDT 24
Peak memory 200388 kb
Host smart-5bfc3f27-6e09-44e0-80d6-d5db85cb4620
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797581732 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.3797581732
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.498017493
Short name T39
Test name
Test status
Simulation time 27380555792 ps
CPU time 545.54 seconds
Started Jun 06 01:06:29 PM PDT 24
Finished Jun 06 01:15:36 PM PDT 24
Peak memory 200716 kb
Host smart-798605f1-d7f4-434a-855b-a4164813a11e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498017493 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.498017493
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.4128198571
Short name T210
Test name
Test status
Simulation time 2504050878 ps
CPU time 47.2 seconds
Started Jun 06 01:06:25 PM PDT 24
Finished Jun 06 01:07:14 PM PDT 24
Peak memory 200392 kb
Host smart-405a587b-0add-4194-8b26-d25d5ae6bfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128198571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.4128198571
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2684716126
Short name T484
Test name
Test status
Simulation time 31694923 ps
CPU time 0.57 seconds
Started Jun 06 01:06:26 PM PDT 24
Finished Jun 06 01:06:28 PM PDT 24
Peak memory 195992 kb
Host smart-43c7573b-ae73-44b4-befc-8e16304fdf73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684716126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2684716126
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2788040553
Short name T265
Test name
Test status
Simulation time 3949761826 ps
CPU time 35.29 seconds
Started Jun 06 01:06:28 PM PDT 24
Finished Jun 06 01:07:05 PM PDT 24
Peak memory 208688 kb
Host smart-dc859fba-bdb2-4815-8b50-e09fa3d2cf56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2788040553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2788040553
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3748861618
Short name T521
Test name
Test status
Simulation time 3741928632 ps
CPU time 10.81 seconds
Started Jun 06 01:06:26 PM PDT 24
Finished Jun 06 01:06:38 PM PDT 24
Peak memory 200420 kb
Host smart-0f6fd52d-87b2-4409-8e2c-5198fa6074ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748861618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3748861618
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.498523373
Short name T400
Test name
Test status
Simulation time 10206128066 ps
CPU time 718.86 seconds
Started Jun 06 01:06:32 PM PDT 24
Finished Jun 06 01:18:32 PM PDT 24
Peak memory 729528 kb
Host smart-1bcea974-8e28-4f60-a408-3cfd9552badb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=498523373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.498523373
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3436997306
Short name T17
Test name
Test status
Simulation time 9624485514 ps
CPU time 154.12 seconds
Started Jun 06 01:06:29 PM PDT 24
Finished Jun 06 01:09:05 PM PDT 24
Peak memory 200212 kb
Host smart-828c9913-5ce4-41d9-8d35-3b450fe01beb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436997306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3436997306
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.2047850726
Short name T443
Test name
Test status
Simulation time 997470385 ps
CPU time 20.48 seconds
Started Jun 06 01:06:27 PM PDT 24
Finished Jun 06 01:06:50 PM PDT 24
Peak memory 200404 kb
Host smart-3e3c0fa4-ddfb-4b3e-8866-2f280a1943cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047850726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2047850726
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.27581151
Short name T555
Test name
Test status
Simulation time 120714979 ps
CPU time 2.14 seconds
Started Jun 06 01:06:27 PM PDT 24
Finished Jun 06 01:06:31 PM PDT 24
Peak memory 200332 kb
Host smart-9d7c7a82-3fc6-40ad-b946-04bd8417521c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27581151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.27581151
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2235639480
Short name T264
Test name
Test status
Simulation time 159720484007 ps
CPU time 2003.7 seconds
Started Jun 06 01:06:30 PM PDT 24
Finished Jun 06 01:39:56 PM PDT 24
Peak memory 501564 kb
Host smart-b3577e24-c6fa-4041-86e4-96645f291116
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235639480 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2235639480
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.4272572761
Short name T142
Test name
Test status
Simulation time 53031645 ps
CPU time 1.19 seconds
Started Jun 06 01:06:28 PM PDT 24
Finished Jun 06 01:06:31 PM PDT 24
Peak memory 200344 kb
Host smart-ae2d6b1e-8c53-44db-b133-80485e6bc383
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272572761 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.4272572761
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.2732122225
Short name T280
Test name
Test status
Simulation time 92638066328 ps
CPU time 556.68 seconds
Started Jun 06 01:06:29 PM PDT 24
Finished Jun 06 01:15:48 PM PDT 24
Peak memory 200408 kb
Host smart-d7c0217e-ed0c-457c-b005-29af29935813
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732122225 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.2732122225
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.1987699280
Short name T149
Test name
Test status
Simulation time 4910103151 ps
CPU time 59.41 seconds
Started Jun 06 01:06:28 PM PDT 24
Finished Jun 06 01:07:30 PM PDT 24
Peak memory 200444 kb
Host smart-cae2c6bb-7fc8-4ac7-9417-f7c65a99fba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987699280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.1987699280
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.897513583
Short name T202
Test name
Test status
Simulation time 13815108 ps
CPU time 0.56 seconds
Started Jun 06 01:06:28 PM PDT 24
Finished Jun 06 01:06:31 PM PDT 24
Peak memory 195200 kb
Host smart-8bfb4801-6fa3-4a09-a674-9c5b508a3e3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897513583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.897513583
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.4039362306
Short name T268
Test name
Test status
Simulation time 2714570221 ps
CPU time 46.75 seconds
Started Jun 06 01:06:33 PM PDT 24
Finished Jun 06 01:07:20 PM PDT 24
Peak memory 219856 kb
Host smart-2ea55663-3c5a-4962-83d0-f35ffa258009
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4039362306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.4039362306
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1408445629
Short name T286
Test name
Test status
Simulation time 345042363 ps
CPU time 5.84 seconds
Started Jun 06 01:06:28 PM PDT 24
Finished Jun 06 01:06:36 PM PDT 24
Peak memory 200328 kb
Host smart-46de9168-a426-420f-8db7-d78b0134461e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408445629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1408445629
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3657453329
Short name T213
Test name
Test status
Simulation time 1660833673 ps
CPU time 324.83 seconds
Started Jun 06 01:06:28 PM PDT 24
Finished Jun 06 01:11:55 PM PDT 24
Peak memory 633592 kb
Host smart-407dfa7f-0d33-4877-8078-1867c02a7960
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3657453329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3657453329
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.4062192165
Short name T139
Test name
Test status
Simulation time 8450485728 ps
CPU time 32.67 seconds
Started Jun 06 01:06:26 PM PDT 24
Finished Jun 06 01:07:00 PM PDT 24
Peak memory 200404 kb
Host smart-d1a6c4be-ecc2-403e-aa6f-34dc5b8cd92a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062192165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.4062192165
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1883954502
Short name T295
Test name
Test status
Simulation time 79137293031 ps
CPU time 92.36 seconds
Started Jun 06 01:06:27 PM PDT 24
Finished Jun 06 01:08:01 PM PDT 24
Peak memory 200416 kb
Host smart-7ba03e71-a939-4354-aeda-52cf735c2166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883954502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1883954502
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.572997535
Short name T244
Test name
Test status
Simulation time 162319037 ps
CPU time 2.81 seconds
Started Jun 06 01:06:30 PM PDT 24
Finished Jun 06 01:06:35 PM PDT 24
Peak memory 200384 kb
Host smart-708172a5-597d-4b88-8f92-ee9b24f45781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572997535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.572997535
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.3176695521
Short name T590
Test name
Test status
Simulation time 166623614682 ps
CPU time 890.13 seconds
Started Jun 06 01:06:29 PM PDT 24
Finished Jun 06 01:21:21 PM PDT 24
Peak memory 427052 kb
Host smart-fa3262c5-96ac-4628-bc91-a137d9fefde4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176695521 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3176695521
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_stress_all_with_rand_reset.1526397989
Short name T572
Test name
Test status
Simulation time 153910524359 ps
CPU time 3620.82 seconds
Started Jun 06 01:06:29 PM PDT 24
Finished Jun 06 02:06:52 PM PDT 24
Peak memory 741668 kb
Host smart-f6979a60-daf2-477c-9ab1-7e041286e352
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1526397989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all_with_rand_reset.1526397989
Directory /workspace/15.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.3070948304
Short name T394
Test name
Test status
Simulation time 115415399 ps
CPU time 1.23 seconds
Started Jun 06 01:06:26 PM PDT 24
Finished Jun 06 01:06:29 PM PDT 24
Peak memory 200344 kb
Host smart-b9cb0ca2-ea37-416d-bc76-68045778ad9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070948304 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.3070948304
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.1764411948
Short name T273
Test name
Test status
Simulation time 25738028542 ps
CPU time 508.05 seconds
Started Jun 06 01:06:27 PM PDT 24
Finished Jun 06 01:14:56 PM PDT 24
Peak memory 200364 kb
Host smart-06104432-dc4e-4e9a-b559-0c31caf0007b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764411948 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.1764411948
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.704868492
Short name T33
Test name
Test status
Simulation time 892612701 ps
CPU time 36.98 seconds
Started Jun 06 01:06:31 PM PDT 24
Finished Jun 06 01:07:09 PM PDT 24
Peak memory 200376 kb
Host smart-3de40a98-0e73-4c09-ba99-c0c00ff462f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704868492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.704868492
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2538444158
Short name T259
Test name
Test status
Simulation time 27234658 ps
CPU time 0.59 seconds
Started Jun 06 01:06:56 PM PDT 24
Finished Jun 06 01:06:57 PM PDT 24
Peak memory 196020 kb
Host smart-6f233ef1-cf1f-44c2-a0ba-36e37537427f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538444158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2538444158
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.3881776441
Short name T45
Test name
Test status
Simulation time 971920577 ps
CPU time 53.42 seconds
Started Jun 06 01:06:28 PM PDT 24
Finished Jun 06 01:07:24 PM PDT 24
Peak memory 224184 kb
Host smart-63e87353-3ae8-4e20-ad8a-c39a7114f545
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3881776441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.3881776441
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1098138733
Short name T413
Test name
Test status
Simulation time 8343922537 ps
CPU time 44.02 seconds
Started Jun 06 01:06:30 PM PDT 24
Finished Jun 06 01:07:16 PM PDT 24
Peak memory 200508 kb
Host smart-ae4d98da-9f6a-459d-8f41-0165b6adaf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098138733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1098138733
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3828227515
Short name T214
Test name
Test status
Simulation time 6236646638 ps
CPU time 950.8 seconds
Started Jun 06 01:06:30 PM PDT 24
Finished Jun 06 01:22:23 PM PDT 24
Peak memory 777184 kb
Host smart-7f9ebad8-76aa-4429-9cfa-f5895cd8961a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3828227515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3828227515
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.844756493
Short name T272
Test name
Test status
Simulation time 2850527970 ps
CPU time 53.74 seconds
Started Jun 06 01:06:27 PM PDT 24
Finished Jun 06 01:07:23 PM PDT 24
Peak memory 200400 kb
Host smart-88207573-1dcb-446a-afc0-92706fe760af
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844756493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.844756493
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2558925967
Short name T559
Test name
Test status
Simulation time 1784051374 ps
CPU time 48.73 seconds
Started Jun 06 01:06:27 PM PDT 24
Finished Jun 06 01:07:18 PM PDT 24
Peak memory 200420 kb
Host smart-a9a2944d-8ebe-449c-b2ad-384d7e748b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558925967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2558925967
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.30947284
Short name T261
Test name
Test status
Simulation time 1692400286 ps
CPU time 10.29 seconds
Started Jun 06 01:06:27 PM PDT 24
Finished Jun 06 01:06:39 PM PDT 24
Peak memory 200368 kb
Host smart-063277bb-3673-4edd-ad0c-d60332cf881e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30947284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.30947284
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3762826240
Short name T561
Test name
Test status
Simulation time 28637046742 ps
CPU time 198.15 seconds
Started Jun 06 01:06:30 PM PDT 24
Finished Jun 06 01:09:50 PM PDT 24
Peak memory 216936 kb
Host smart-78c1d99a-834c-4bec-a8b7-71bccefbaa05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762826240 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3762826240
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.4140261607
Short name T227
Test name
Test status
Simulation time 86165361 ps
CPU time 1.07 seconds
Started Jun 06 01:06:30 PM PDT 24
Finished Jun 06 01:06:33 PM PDT 24
Peak memory 200324 kb
Host smart-9107ade0-af0d-4edc-a7db-a124a529b8c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140261607 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.4140261607
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.1307297353
Short name T594
Test name
Test status
Simulation time 56685986576 ps
CPU time 488.72 seconds
Started Jun 06 01:06:27 PM PDT 24
Finished Jun 06 01:14:38 PM PDT 24
Peak memory 200440 kb
Host smart-bbd57f0a-6fb2-4418-a13a-b52309b5e858
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307297353 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.1307297353
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1846229990
Short name T369
Test name
Test status
Simulation time 2388894623 ps
CPU time 83.11 seconds
Started Jun 06 01:06:26 PM PDT 24
Finished Jun 06 01:07:51 PM PDT 24
Peak memory 200456 kb
Host smart-82ffd3b1-aa79-4cf1-87b3-3eec33a2c12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846229990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1846229990
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/165.hmac_stress_all_with_rand_reset.3994818534
Short name T57
Test name
Test status
Simulation time 18196102206 ps
CPU time 452.8 seconds
Started Jun 06 01:08:51 PM PDT 24
Finished Jun 06 01:16:25 PM PDT 24
Peak memory 224536 kb
Host smart-af6f671d-5005-494b-a5dc-7ae39e964ed6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3994818534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.hmac_stress_all_with_rand_reset.3994818534
Directory /workspace/165.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/167.hmac_stress_all_with_rand_reset.301073621
Short name T13
Test name
Test status
Simulation time 39809498499 ps
CPU time 1891.84 seconds
Started Jun 06 01:08:51 PM PDT 24
Finished Jun 06 01:40:24 PM PDT 24
Peak memory 768944 kb
Host smart-1fdc634c-e1c2-4d5b-80b3-2a5c32ac0886
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=301073621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.hmac_stress_all_with_rand_reset.301073621
Directory /workspace/167.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3602364898
Short name T254
Test name
Test status
Simulation time 55957061 ps
CPU time 0.6 seconds
Started Jun 06 01:06:32 PM PDT 24
Finished Jun 06 01:06:34 PM PDT 24
Peak memory 196212 kb
Host smart-07e6965d-d0da-4f95-a236-1ebaeb166e13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602364898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3602364898
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.1655625049
Short name T292
Test name
Test status
Simulation time 647980077 ps
CPU time 29.61 seconds
Started Jun 06 01:06:30 PM PDT 24
Finished Jun 06 01:07:01 PM PDT 24
Peak memory 212180 kb
Host smart-53fe4b58-408b-468d-b074-8cae22ab1c50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1655625049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1655625049
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3145457309
Short name T437
Test name
Test status
Simulation time 2354804236 ps
CPU time 63.87 seconds
Started Jun 06 01:06:28 PM PDT 24
Finished Jun 06 01:07:34 PM PDT 24
Peak memory 200512 kb
Host smart-a856cdce-fc62-42f9-85cd-afe115198944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145457309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3145457309
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2521521646
Short name T451
Test name
Test status
Simulation time 4208597033 ps
CPU time 383.13 seconds
Started Jun 06 01:06:32 PM PDT 24
Finished Jun 06 01:12:56 PM PDT 24
Peak memory 616952 kb
Host smart-97a11a0b-3fa6-4018-a89c-c001b3f28d5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2521521646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2521521646
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.2492005710
Short name T349
Test name
Test status
Simulation time 8525057644 ps
CPU time 12.61 seconds
Started Jun 06 01:06:29 PM PDT 24
Finished Jun 06 01:06:44 PM PDT 24
Peak memory 200376 kb
Host smart-4cfaec6c-e856-4618-8add-ecd39aa104cb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492005710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2492005710
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.1395887954
Short name T461
Test name
Test status
Simulation time 3454300559 ps
CPU time 101.23 seconds
Started Jun 06 01:06:25 PM PDT 24
Finished Jun 06 01:08:08 PM PDT 24
Peak memory 200424 kb
Host smart-1043b1d4-8023-426e-be51-317270492805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395887954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1395887954
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.450571199
Short name T510
Test name
Test status
Simulation time 375592577 ps
CPU time 5.23 seconds
Started Jun 06 01:06:30 PM PDT 24
Finished Jun 06 01:06:37 PM PDT 24
Peak memory 200396 kb
Host smart-72efaff4-5b5e-4558-a360-c4979099ab4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450571199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.450571199
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.4117384922
Short name T473
Test name
Test status
Simulation time 43688154701 ps
CPU time 855.04 seconds
Started Jun 06 01:06:28 PM PDT 24
Finished Jun 06 01:20:45 PM PDT 24
Peak memory 248568 kb
Host smart-6d30ebb6-b327-4cb3-bb70-e1daab543506
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117384922 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.4117384922
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.2363279979
Short name T353
Test name
Test status
Simulation time 128668499 ps
CPU time 1.34 seconds
Started Jun 06 01:06:27 PM PDT 24
Finished Jun 06 01:06:30 PM PDT 24
Peak memory 200396 kb
Host smart-83211029-d89a-4a49-adc3-fc4088c5cd97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363279979 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.2363279979
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.1340652658
Short name T563
Test name
Test status
Simulation time 104475532251 ps
CPU time 471.84 seconds
Started Jun 06 01:06:28 PM PDT 24
Finished Jun 06 01:14:23 PM PDT 24
Peak memory 200336 kb
Host smart-4563fc46-3f2b-4c14-8e8a-97d447593918
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340652658 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.1340652658
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1106547223
Short name T496
Test name
Test status
Simulation time 286626927 ps
CPU time 13.87 seconds
Started Jun 06 01:06:27 PM PDT 24
Finished Jun 06 01:06:43 PM PDT 24
Peak memory 200324 kb
Host smart-3febae0b-4af1-43b6-b851-b5fe4c65c334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106547223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1106547223
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1497551165
Short name T181
Test name
Test status
Simulation time 13080133 ps
CPU time 0.58 seconds
Started Jun 06 01:06:36 PM PDT 24
Finished Jun 06 01:06:38 PM PDT 24
Peak memory 196204 kb
Host smart-44160ac5-7e34-4cf1-97d8-0fb4a6a41358
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497551165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1497551165
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.3778652076
Short name T595
Test name
Test status
Simulation time 2807026980 ps
CPU time 8.24 seconds
Started Jun 06 01:06:36 PM PDT 24
Finished Jun 06 01:06:45 PM PDT 24
Peak memory 200492 kb
Host smart-fdb8b29c-5ea0-4ce8-958e-f7de525edf0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3778652076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.3778652076
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3373427091
Short name T382
Test name
Test status
Simulation time 1975442846 ps
CPU time 17.39 seconds
Started Jun 06 01:06:36 PM PDT 24
Finished Jun 06 01:06:56 PM PDT 24
Peak memory 200392 kb
Host smart-5c32072a-5ef7-4a72-9250-85b522415c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373427091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3373427091
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.169212295
Short name T396
Test name
Test status
Simulation time 6621427894 ps
CPU time 867.12 seconds
Started Jun 06 01:06:37 PM PDT 24
Finished Jun 06 01:21:06 PM PDT 24
Peak memory 736832 kb
Host smart-e04c270f-5472-42b2-98f8-20d0f57d19f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=169212295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.169212295
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3531412458
Short name T316
Test name
Test status
Simulation time 26516964171 ps
CPU time 165.76 seconds
Started Jun 06 01:06:37 PM PDT 24
Finished Jun 06 01:09:24 PM PDT 24
Peak memory 200428 kb
Host smart-6b96a90e-5822-49bc-8c82-d21b38270d38
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531412458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3531412458
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.3709520830
Short name T321
Test name
Test status
Simulation time 679278161 ps
CPU time 21.06 seconds
Started Jun 06 01:06:35 PM PDT 24
Finished Jun 06 01:06:58 PM PDT 24
Peak memory 200356 kb
Host smart-f2eb93e0-4bff-475c-a1cf-199018f0d1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709520830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.3709520830
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.554030275
Short name T129
Test name
Test status
Simulation time 1023121523 ps
CPU time 5.57 seconds
Started Jun 06 01:06:38 PM PDT 24
Finished Jun 06 01:06:44 PM PDT 24
Peak memory 200440 kb
Host smart-265c3f9c-956b-4994-867a-f30c40ec7d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554030275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.554030275
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3726414564
Short name T159
Test name
Test status
Simulation time 12985546490 ps
CPU time 1503.41 seconds
Started Jun 06 01:06:37 PM PDT 24
Finished Jun 06 01:31:42 PM PDT 24
Peak memory 769252 kb
Host smart-1cecb83e-ddf6-4445-b524-60f533a21452
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726414564 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3726414564
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.2833024374
Short name T296
Test name
Test status
Simulation time 30950118 ps
CPU time 1.03 seconds
Started Jun 06 01:06:36 PM PDT 24
Finished Jun 06 01:06:38 PM PDT 24
Peak memory 200384 kb
Host smart-a3d5f027-394c-4174-b6f2-5726c2b2ee71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833024374 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.2833024374
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.2992344467
Short name T534
Test name
Test status
Simulation time 110317447422 ps
CPU time 482.17 seconds
Started Jun 06 01:06:38 PM PDT 24
Finished Jun 06 01:14:42 PM PDT 24
Peak memory 200440 kb
Host smart-df7d24dc-589d-422d-9118-ff0ff21d65da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992344467 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.2992344467
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2377154969
Short name T374
Test name
Test status
Simulation time 6595207962 ps
CPU time 96.95 seconds
Started Jun 06 01:06:42 PM PDT 24
Finished Jun 06 01:08:21 PM PDT 24
Peak memory 200412 kb
Host smart-514c21bf-e354-4e75-9b87-a0437b67e512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377154969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2377154969
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/186.hmac_stress_all_with_rand_reset.3480260471
Short name T9
Test name
Test status
Simulation time 24517313202 ps
CPU time 569.2 seconds
Started Jun 06 01:09:01 PM PDT 24
Finished Jun 06 01:18:31 PM PDT 24
Peak memory 231992 kb
Host smart-f72cd9dc-a3bf-42bc-a877-6bf450d4d0c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3480260471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.hmac_stress_all_with_rand_reset.3480260471
Directory /workspace/186.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2827712363
Short name T583
Test name
Test status
Simulation time 22105920 ps
CPU time 0.62 seconds
Started Jun 06 01:06:42 PM PDT 24
Finished Jun 06 01:06:45 PM PDT 24
Peak memory 195160 kb
Host smart-6d4f0708-cb14-4f00-8d4b-4e641d09d07e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827712363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2827712363
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2698617045
Short name T270
Test name
Test status
Simulation time 708539962 ps
CPU time 37.12 seconds
Started Jun 06 01:06:37 PM PDT 24
Finished Jun 06 01:07:16 PM PDT 24
Peak memory 225868 kb
Host smart-405207e9-e001-415a-9c30-8ef5d1a20cf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2698617045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2698617045
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2585776679
Short name T546
Test name
Test status
Simulation time 3695293585 ps
CPU time 49.8 seconds
Started Jun 06 01:06:38 PM PDT 24
Finished Jun 06 01:07:29 PM PDT 24
Peak memory 200440 kb
Host smart-355ca00f-dc3e-4d21-9994-c3b60c966f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585776679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2585776679
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.567274940
Short name T78
Test name
Test status
Simulation time 17229599264 ps
CPU time 1120.45 seconds
Started Jun 06 01:06:37 PM PDT 24
Finished Jun 06 01:25:19 PM PDT 24
Peak memory 772828 kb
Host smart-ce6c28a0-e3d0-4547-9d9d-0cdf0887296e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=567274940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.567274940
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3057701060
Short name T58
Test name
Test status
Simulation time 37149233452 ps
CPU time 105.75 seconds
Started Jun 06 01:06:36 PM PDT 24
Finished Jun 06 01:08:23 PM PDT 24
Peak memory 200364 kb
Host smart-bbc1d7c3-d95d-4b4f-ab62-75b7044ef698
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057701060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3057701060
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1770507113
Short name T310
Test name
Test status
Simulation time 1652081415 ps
CPU time 94.13 seconds
Started Jun 06 01:06:42 PM PDT 24
Finished Jun 06 01:08:18 PM PDT 24
Peak memory 200376 kb
Host smart-333504fe-5acc-433d-841f-8f35c4fe1af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770507113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1770507113
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.4043663424
Short name T132
Test name
Test status
Simulation time 185249313 ps
CPU time 2.09 seconds
Started Jun 06 01:06:37 PM PDT 24
Finished Jun 06 01:06:40 PM PDT 24
Peak memory 200292 kb
Host smart-e7e37598-c203-4e1d-be12-7ce2cc6f3cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043663424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.4043663424
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.3621755245
Short name T71
Test name
Test status
Simulation time 217549074807 ps
CPU time 1253.04 seconds
Started Jun 06 01:06:36 PM PDT 24
Finished Jun 06 01:27:31 PM PDT 24
Peak memory 703308 kb
Host smart-35123ec1-323e-484e-8aad-a265c9d6d8cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621755245 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3621755245
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.2854132762
Short name T377
Test name
Test status
Simulation time 46310682 ps
CPU time 1.04 seconds
Started Jun 06 01:06:37 PM PDT 24
Finished Jun 06 01:06:39 PM PDT 24
Peak memory 200136 kb
Host smart-4953896b-306b-4a63-b8f6-3fe52419c726
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854132762 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.2854132762
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.3856565360
Short name T497
Test name
Test status
Simulation time 76993869891 ps
CPU time 521.26 seconds
Started Jun 06 01:06:38 PM PDT 24
Finished Jun 06 01:15:21 PM PDT 24
Peak memory 200376 kb
Host smart-e5b06130-8d68-446f-99f1-cc351c2359c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856565360 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.3856565360
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.34010446
Short name T427
Test name
Test status
Simulation time 28055812038 ps
CPU time 103.52 seconds
Started Jun 06 01:06:35 PM PDT 24
Finished Jun 06 01:08:20 PM PDT 24
Peak memory 200404 kb
Host smart-48042c1f-a88a-4120-85e7-42db0bd77dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34010446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.34010446
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.4060801320
Short name T512
Test name
Test status
Simulation time 23947547 ps
CPU time 0.57 seconds
Started Jun 06 01:06:07 PM PDT 24
Finished Jun 06 01:06:08 PM PDT 24
Peak memory 195152 kb
Host smart-40d75b65-34b8-4b44-a2a6-ae0b60d25d1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060801320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.4060801320
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3773042171
Short name T262
Test name
Test status
Simulation time 283710772 ps
CPU time 10.92 seconds
Started Jun 06 01:06:00 PM PDT 24
Finished Jun 06 01:06:12 PM PDT 24
Peak memory 200376 kb
Host smart-7f0a436f-f37e-415c-acfe-d5635bb34881
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3773042171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3773042171
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1009336022
Short name T127
Test name
Test status
Simulation time 1087024974 ps
CPU time 26.65 seconds
Started Jun 06 01:06:02 PM PDT 24
Finished Jun 06 01:06:29 PM PDT 24
Peak memory 200352 kb
Host smart-da0fc50a-42a2-4883-919a-7264f86f2517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009336022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1009336022
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3814817226
Short name T372
Test name
Test status
Simulation time 5631347740 ps
CPU time 738.23 seconds
Started Jun 06 01:06:02 PM PDT 24
Finished Jun 06 01:18:21 PM PDT 24
Peak memory 730092 kb
Host smart-66d76bbd-4658-4031-9cdb-84134aa555b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3814817226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3814817226
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3009360264
Short name T556
Test name
Test status
Simulation time 1206679820 ps
CPU time 65.17 seconds
Started Jun 06 01:06:02 PM PDT 24
Finished Jun 06 01:07:08 PM PDT 24
Peak memory 200320 kb
Host smart-c66661ba-7435-4e08-9aee-4c81ac6f3498
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009360264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3009360264
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.1851431109
Short name T388
Test name
Test status
Simulation time 15338230167 ps
CPU time 84.42 seconds
Started Jun 06 01:06:03 PM PDT 24
Finished Jun 06 01:07:28 PM PDT 24
Peak memory 200456 kb
Host smart-b330a11c-6bd0-432b-8cc2-20290bf4714a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851431109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1851431109
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.4230036592
Short name T27
Test name
Test status
Simulation time 101114066 ps
CPU time 0.84 seconds
Started Jun 06 01:06:00 PM PDT 24
Finished Jun 06 01:06:02 PM PDT 24
Peak memory 218732 kb
Host smart-10485cab-5de3-4a34-a36d-2d6abedd5f4a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230036592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.4230036592
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2305052021
Short name T410
Test name
Test status
Simulation time 942413007 ps
CPU time 5.08 seconds
Started Jun 06 01:06:03 PM PDT 24
Finished Jun 06 01:06:09 PM PDT 24
Peak memory 200376 kb
Host smart-8e907152-a78a-4b22-9ca4-b8ae9b5a078c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305052021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2305052021
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.856816230
Short name T100
Test name
Test status
Simulation time 147835779375 ps
CPU time 1478.14 seconds
Started Jun 06 01:06:01 PM PDT 24
Finished Jun 06 01:30:41 PM PDT 24
Peak memory 734844 kb
Host smart-5049dc20-8264-4913-a385-76a4b0254348
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856816230 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.856816230
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.2805789256
Short name T271
Test name
Test status
Simulation time 103320580 ps
CPU time 1.07 seconds
Started Jun 06 01:06:02 PM PDT 24
Finished Jun 06 01:06:04 PM PDT 24
Peak memory 200012 kb
Host smart-c103e05f-01a7-4d25-b1ef-dd4e3412bd18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805789256 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.2805789256
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.153202165
Short name T379
Test name
Test status
Simulation time 93196654180 ps
CPU time 480.16 seconds
Started Jun 06 01:06:01 PM PDT 24
Finished Jun 06 01:14:03 PM PDT 24
Peak memory 200352 kb
Host smart-ffca7c7b-86d3-4ae0-ba2b-c3ae6e16df39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153202165 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.153202165
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2645517186
Short name T570
Test name
Test status
Simulation time 2328850937 ps
CPU time 29.22 seconds
Started Jun 06 01:06:01 PM PDT 24
Finished Jun 06 01:06:32 PM PDT 24
Peak memory 200396 kb
Host smart-55725775-8b92-4c5e-a2ae-0a3cb0e67994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645517186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2645517186
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1450023726
Short name T63
Test name
Test status
Simulation time 66053240 ps
CPU time 0.57 seconds
Started Jun 06 01:06:40 PM PDT 24
Finished Jun 06 01:06:42 PM PDT 24
Peak memory 196232 kb
Host smart-a93143a7-18e8-4831-92df-8e1f724918b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450023726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1450023726
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.3140093914
Short name T291
Test name
Test status
Simulation time 2591803417 ps
CPU time 12.54 seconds
Started Jun 06 01:06:36 PM PDT 24
Finished Jun 06 01:06:50 PM PDT 24
Peak memory 216788 kb
Host smart-dda920da-8383-4716-8e2e-816b2b776579
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3140093914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.3140093914
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.203149262
Short name T165
Test name
Test status
Simulation time 8227445655 ps
CPU time 34.92 seconds
Started Jun 06 01:06:39 PM PDT 24
Finished Jun 06 01:07:15 PM PDT 24
Peak memory 200516 kb
Host smart-d169c353-2f6f-4074-a6c8-6bee53f415ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203149262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.203149262
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1768145249
Short name T373
Test name
Test status
Simulation time 1559629775 ps
CPU time 39.6 seconds
Started Jun 06 01:06:34 PM PDT 24
Finished Jun 06 01:07:15 PM PDT 24
Peak memory 315716 kb
Host smart-b3bf8535-b769-4d9f-8ac6-8bf401d08d4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1768145249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1768145249
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1090446333
Short name T173
Test name
Test status
Simulation time 6715192063 ps
CPU time 90.25 seconds
Started Jun 06 01:06:35 PM PDT 24
Finished Jun 06 01:08:06 PM PDT 24
Peak memory 200348 kb
Host smart-16713d8b-166a-45a0-84b9-4c8d90e98dbf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090446333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1090446333
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1846137735
Short name T392
Test name
Test status
Simulation time 586009303 ps
CPU time 18.26 seconds
Started Jun 06 01:06:36 PM PDT 24
Finished Jun 06 01:06:55 PM PDT 24
Peak memory 200396 kb
Host smart-e2bfff6b-c44e-48f3-9725-6f315a3b9058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846137735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1846137735
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1268601836
Short name T144
Test name
Test status
Simulation time 343985171 ps
CPU time 2.89 seconds
Started Jun 06 01:06:36 PM PDT 24
Finished Jun 06 01:06:40 PM PDT 24
Peak memory 200328 kb
Host smart-320fbbf1-a8dd-4508-900b-e256cc8dac5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268601836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1268601836
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.537330004
Short name T326
Test name
Test status
Simulation time 54031707288 ps
CPU time 1137.09 seconds
Started Jun 06 01:06:39 PM PDT 24
Finished Jun 06 01:25:37 PM PDT 24
Peak memory 697352 kb
Host smart-65cd7cb6-76da-4eb9-a760-0e3258712a7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537330004 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.537330004
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_stress_all_with_rand_reset.2688164955
Short name T12
Test name
Test status
Simulation time 90241050196 ps
CPU time 1717.25 seconds
Started Jun 06 01:06:40 PM PDT 24
Finished Jun 06 01:35:19 PM PDT 24
Peak memory 667224 kb
Host smart-d3ab474b-4d0f-4324-852f-106287a0408f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2688164955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all_with_rand_reset.2688164955
Directory /workspace/20.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.3669622912
Short name T453
Test name
Test status
Simulation time 105706933 ps
CPU time 1.06 seconds
Started Jun 06 01:06:37 PM PDT 24
Finished Jun 06 01:06:39 PM PDT 24
Peak memory 200220 kb
Host smart-f847caef-2f1e-4d1c-9b37-616163b1d777
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669622912 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.3669622912
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.636684566
Short name T6
Test name
Test status
Simulation time 30366947729 ps
CPU time 452.93 seconds
Started Jun 06 01:06:36 PM PDT 24
Finished Jun 06 01:14:11 PM PDT 24
Peak memory 200404 kb
Host smart-9b1be87d-b8cf-4d78-8a79-81a9e217580d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636684566 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.636684566
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.251969836
Short name T76
Test name
Test status
Simulation time 3616144024 ps
CPU time 67.41 seconds
Started Jun 06 01:06:36 PM PDT 24
Finished Jun 06 01:07:45 PM PDT 24
Peak memory 200424 kb
Host smart-e6e8fa5e-582b-4c61-99cf-cf583ed8db23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251969836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.251969836
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.762086665
Short name T195
Test name
Test status
Simulation time 36441412 ps
CPU time 0.58 seconds
Started Jun 06 01:06:40 PM PDT 24
Finished Jun 06 01:06:42 PM PDT 24
Peak memory 195136 kb
Host smart-2f391cf9-2663-4229-ad52-a505759beb53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762086665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.762086665
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.2678602468
Short name T530
Test name
Test status
Simulation time 1286206594 ps
CPU time 13.89 seconds
Started Jun 06 01:06:39 PM PDT 24
Finished Jun 06 01:06:54 PM PDT 24
Peak memory 208544 kb
Host smart-89538cd6-0203-4df1-a0f8-b1cc5abb42bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2678602468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.2678602468
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.87252767
Short name T222
Test name
Test status
Simulation time 1539833365 ps
CPU time 8.38 seconds
Started Jun 06 01:06:41 PM PDT 24
Finished Jun 06 01:06:50 PM PDT 24
Peak memory 200472 kb
Host smart-3569e963-0716-4bc9-834d-656f32ce23ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87252767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.87252767
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.8564928
Short name T151
Test name
Test status
Simulation time 6807504584 ps
CPU time 326.05 seconds
Started Jun 06 01:06:42 PM PDT 24
Finished Jun 06 01:12:10 PM PDT 24
Peak memory 606724 kb
Host smart-f6577472-dba4-4f1e-8b34-0a26a85f42c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=8564928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.8564928
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3381569197
Short name T507
Test name
Test status
Simulation time 5273655358 ps
CPU time 15.87 seconds
Started Jun 06 01:06:41 PM PDT 24
Finished Jun 06 01:06:58 PM PDT 24
Peak memory 200196 kb
Host smart-00033b10-4cd6-43fe-af71-dbe1ccbe6270
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381569197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3381569197
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.3894015256
Short name T398
Test name
Test status
Simulation time 2882660102 ps
CPU time 42.39 seconds
Started Jun 06 01:06:42 PM PDT 24
Finished Jun 06 01:07:26 PM PDT 24
Peak memory 200708 kb
Host smart-cfb0a2a8-a842-44cf-9618-ce1fd3311236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894015256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.3894015256
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3614350506
Short name T368
Test name
Test status
Simulation time 4485203583 ps
CPU time 13.79 seconds
Started Jun 06 01:06:43 PM PDT 24
Finished Jun 06 01:06:59 PM PDT 24
Peak memory 200784 kb
Host smart-d98cf751-ffe6-4cd6-8742-ddfcf70327ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614350506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3614350506
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3498679467
Short name T414
Test name
Test status
Simulation time 534324542433 ps
CPU time 2647.21 seconds
Started Jun 06 01:06:41 PM PDT 24
Finished Jun 06 01:50:50 PM PDT 24
Peak memory 556184 kb
Host smart-b27bb9d5-849a-4336-90a7-6184c7d6a038
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498679467 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3498679467
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.1554560452
Short name T302
Test name
Test status
Simulation time 114678305 ps
CPU time 1.14 seconds
Started Jun 06 01:06:40 PM PDT 24
Finished Jun 06 01:06:43 PM PDT 24
Peak memory 200432 kb
Host smart-4920e341-6228-495b-8e52-42bf8f09c829
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554560452 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.1554560452
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.3692473241
Short name T267
Test name
Test status
Simulation time 8626304085 ps
CPU time 448.77 seconds
Started Jun 06 01:06:39 PM PDT 24
Finished Jun 06 01:14:09 PM PDT 24
Peak memory 200380 kb
Host smart-65155946-1cf7-411f-93c1-cbd1f1abf8eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692473241 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.3692473241
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2863151271
Short name T170
Test name
Test status
Simulation time 2200136369 ps
CPU time 47.69 seconds
Started Jun 06 01:06:39 PM PDT 24
Finished Jun 06 01:07:28 PM PDT 24
Peak memory 200472 kb
Host smart-cb77a6b6-70c9-4de3-bfba-7acf4229bd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863151271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2863151271
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3476356498
Short name T301
Test name
Test status
Simulation time 32713233 ps
CPU time 0.56 seconds
Started Jun 06 01:06:44 PM PDT 24
Finished Jun 06 01:06:47 PM PDT 24
Peak memory 195968 kb
Host smart-f9b9eed6-98f6-4c5c-9957-1371ec8a1ec7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476356498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3476356498
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3300439726
Short name T529
Test name
Test status
Simulation time 572816206 ps
CPU time 6.07 seconds
Started Jun 06 01:06:42 PM PDT 24
Finished Jun 06 01:06:51 PM PDT 24
Peak memory 200344 kb
Host smart-400c1f85-e84d-43c4-9e89-cfbf11b54e32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3300439726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3300439726
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2555050954
Short name T40
Test name
Test status
Simulation time 1504721038 ps
CPU time 2.43 seconds
Started Jun 06 01:06:45 PM PDT 24
Finished Jun 06 01:06:49 PM PDT 24
Peak memory 200352 kb
Host smart-be96ff79-374b-4122-a008-be985cf3625a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555050954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2555050954
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.2659165839
Short name T294
Test name
Test status
Simulation time 3959047454 ps
CPU time 1217.59 seconds
Started Jun 06 01:06:43 PM PDT 24
Finished Jun 06 01:27:03 PM PDT 24
Peak memory 772560 kb
Host smart-74ca8a51-f665-4605-89c8-8382802053dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2659165839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2659165839
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2235862137
Short name T365
Test name
Test status
Simulation time 18137295131 ps
CPU time 230.34 seconds
Started Jun 06 01:06:44 PM PDT 24
Finished Jun 06 01:10:36 PM PDT 24
Peak memory 200432 kb
Host smart-184e3130-d426-443c-ad8c-dbbdc84558de
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235862137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2235862137
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1951560359
Short name T411
Test name
Test status
Simulation time 5890569444 ps
CPU time 90.74 seconds
Started Jun 06 01:06:42 PM PDT 24
Finished Jun 06 01:08:14 PM PDT 24
Peak memory 200396 kb
Host smart-fed814ce-be7a-44de-80b9-965fcad17d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951560359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1951560359
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2540669516
Short name T509
Test name
Test status
Simulation time 416465449 ps
CPU time 7.52 seconds
Started Jun 06 01:06:40 PM PDT 24
Finished Jun 06 01:06:49 PM PDT 24
Peak memory 200352 kb
Host smart-49c37cca-13e3-4102-b6a2-5484bb0d4e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540669516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2540669516
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2485616971
Short name T303
Test name
Test status
Simulation time 153192270722 ps
CPU time 2855.78 seconds
Started Jun 06 01:06:42 PM PDT 24
Finished Jun 06 01:54:20 PM PDT 24
Peak memory 247760 kb
Host smart-893f2861-4050-4591-a616-7b5d5b4f3c4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485616971 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2485616971
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.1815335242
Short name T402
Test name
Test status
Simulation time 56916072 ps
CPU time 0.99 seconds
Started Jun 06 01:06:41 PM PDT 24
Finished Jun 06 01:06:44 PM PDT 24
Peak memory 200108 kb
Host smart-612412ae-bc28-4496-b0cf-f40afa1e59d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815335242 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.1815335242
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.1612181259
Short name T136
Test name
Test status
Simulation time 30417782015 ps
CPU time 488.49 seconds
Started Jun 06 01:06:45 PM PDT 24
Finished Jun 06 01:14:55 PM PDT 24
Peak memory 200324 kb
Host smart-f5b03f4e-a678-476e-963e-527cc533519f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612181259 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.1612181259
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.35467136
Short name T444
Test name
Test status
Simulation time 1722589529 ps
CPU time 59.87 seconds
Started Jun 06 01:06:42 PM PDT 24
Finished Jun 06 01:07:44 PM PDT 24
Peak memory 200340 kb
Host smart-abf8f598-73ef-43fe-8663-20c88f6c617e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35467136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.35467136
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.3572539648
Short name T481
Test name
Test status
Simulation time 37317398 ps
CPU time 0.55 seconds
Started Jun 06 01:06:39 PM PDT 24
Finished Jun 06 01:06:41 PM PDT 24
Peak memory 195840 kb
Host smart-474bfc9c-c961-4147-b7ec-5107d92da0ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572539648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3572539648
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.3113339546
Short name T282
Test name
Test status
Simulation time 264826832 ps
CPU time 13.29 seconds
Started Jun 06 01:06:41 PM PDT 24
Finished Jun 06 01:06:55 PM PDT 24
Peak memory 233132 kb
Host smart-da7d1db6-9214-4fe0-bfff-bc6bd9dab27f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3113339546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3113339546
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.913364904
Short name T342
Test name
Test status
Simulation time 374430222 ps
CPU time 20.34 seconds
Started Jun 06 01:06:44 PM PDT 24
Finished Jun 06 01:07:07 PM PDT 24
Peak memory 200404 kb
Host smart-2aed4c40-d8ad-4270-89a8-bfc12a2c8a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913364904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.913364904
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2740539130
Short name T133
Test name
Test status
Simulation time 2091987979 ps
CPU time 544 seconds
Started Jun 06 01:06:39 PM PDT 24
Finished Jun 06 01:15:44 PM PDT 24
Peak memory 724360 kb
Host smart-ab9f6086-6ef1-4d16-b0f3-49dd76055dc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2740539130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2740539130
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1808620720
Short name T196
Test name
Test status
Simulation time 5422495554 ps
CPU time 74.71 seconds
Started Jun 06 01:06:42 PM PDT 24
Finished Jun 06 01:07:59 PM PDT 24
Peak memory 200448 kb
Host smart-17f85c61-cca5-4ae0-9c7d-3ebc3094fbc3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808620720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1808620720
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.263910590
Short name T1
Test name
Test status
Simulation time 4896746054 ps
CPU time 74.18 seconds
Started Jun 06 01:06:42 PM PDT 24
Finished Jun 06 01:07:59 PM PDT 24
Peak memory 200248 kb
Host smart-0e4a0c8b-b700-4745-9d05-81e0bafb834a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263910590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.263910590
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.3237488014
Short name T434
Test name
Test status
Simulation time 1376215601 ps
CPU time 8.17 seconds
Started Jun 06 01:06:42 PM PDT 24
Finished Jun 06 01:06:52 PM PDT 24
Peak memory 200400 kb
Host smart-34eb026a-034f-4729-8733-6907a3746bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237488014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3237488014
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.1272368572
Short name T479
Test name
Test status
Simulation time 233558391 ps
CPU time 1.15 seconds
Started Jun 06 01:06:43 PM PDT 24
Finished Jun 06 01:06:46 PM PDT 24
Peak memory 200052 kb
Host smart-4c6ee338-9e93-4645-89e8-9b9c2781ce21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272368572 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.1272368572
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.1833006891
Short name T226
Test name
Test status
Simulation time 323769576965 ps
CPU time 504.9 seconds
Started Jun 06 01:06:43 PM PDT 24
Finished Jun 06 01:15:10 PM PDT 24
Peak memory 200412 kb
Host smart-4a4ed9cc-d670-4a64-98d8-d0fc61d38d97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833006891 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.1833006891
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.4144583703
Short name T247
Test name
Test status
Simulation time 7830388040 ps
CPU time 58.07 seconds
Started Jun 06 01:06:42 PM PDT 24
Finished Jun 06 01:07:43 PM PDT 24
Peak memory 200276 kb
Host smart-c6c1b0ce-b45e-4b76-b782-935a5964754e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144583703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.4144583703
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3001548324
Short name T578
Test name
Test status
Simulation time 13044227 ps
CPU time 0.58 seconds
Started Jun 06 01:06:46 PM PDT 24
Finished Jun 06 01:06:48 PM PDT 24
Peak memory 195192 kb
Host smart-abbd055e-6a61-46ee-bf32-af41362d80fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001548324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3001548324
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3506957908
Short name T41
Test name
Test status
Simulation time 668662997 ps
CPU time 6.79 seconds
Started Jun 06 01:06:45 PM PDT 24
Finished Jun 06 01:06:54 PM PDT 24
Peak memory 208404 kb
Host smart-ba1a13ef-7c33-4b6b-b912-420a2af8b534
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3506957908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3506957908
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.601314876
Short name T317
Test name
Test status
Simulation time 20631130328 ps
CPU time 58.43 seconds
Started Jun 06 01:06:42 PM PDT 24
Finished Jun 06 01:07:43 PM PDT 24
Peak memory 200432 kb
Host smart-b5d5e84f-6cf9-4c9d-baaa-406b461982b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601314876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.601314876
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.552522764
Short name T562
Test name
Test status
Simulation time 3450484718 ps
CPU time 949.27 seconds
Started Jun 06 01:06:42 PM PDT 24
Finished Jun 06 01:22:34 PM PDT 24
Peak memory 716620 kb
Host smart-395b6ab8-5fe7-4c7d-a53a-fa377f08b137
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=552522764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.552522764
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.883452689
Short name T130
Test name
Test status
Simulation time 3578501825 ps
CPU time 10.3 seconds
Started Jun 06 01:06:43 PM PDT 24
Finished Jun 06 01:06:55 PM PDT 24
Peak memory 200396 kb
Host smart-3fa41465-319f-4286-a77b-a2c6259b6931
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883452689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.883452689
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.301534437
Short name T5
Test name
Test status
Simulation time 19259440659 ps
CPU time 68.31 seconds
Started Jun 06 01:06:42 PM PDT 24
Finished Jun 06 01:07:53 PM PDT 24
Peak memory 200304 kb
Host smart-1ddbd125-395b-40e2-a637-228b03a3457b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301534437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.301534437
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1605374234
Short name T542
Test name
Test status
Simulation time 131066822 ps
CPU time 2.33 seconds
Started Jun 06 01:06:40 PM PDT 24
Finished Jun 06 01:06:44 PM PDT 24
Peak memory 200388 kb
Host smart-2948df67-8ef2-4072-bf92-a04489d9011c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605374234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1605374234
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3883234242
Short name T494
Test name
Test status
Simulation time 96169956866 ps
CPU time 1460.02 seconds
Started Jun 06 01:06:44 PM PDT 24
Finished Jun 06 01:31:06 PM PDT 24
Peak memory 690664 kb
Host smart-e59426f3-9897-4764-a4a0-08458b866e34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883234242 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3883234242
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.1495085270
Short name T513
Test name
Test status
Simulation time 62848230 ps
CPU time 1.23 seconds
Started Jun 06 01:06:47 PM PDT 24
Finished Jun 06 01:06:50 PM PDT 24
Peak memory 200368 kb
Host smart-f2a1fc5c-51c1-4b92-a3f1-53a1a7cc98ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495085270 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.1495085270
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.1969085981
Short name T488
Test name
Test status
Simulation time 99838103015 ps
CPU time 463.04 seconds
Started Jun 06 01:06:46 PM PDT 24
Finished Jun 06 01:14:31 PM PDT 24
Peak memory 200392 kb
Host smart-b0319835-7922-4a48-ad4c-0ef74383f5a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969085981 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.1969085981
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3680005173
Short name T523
Test name
Test status
Simulation time 7749315153 ps
CPU time 28.67 seconds
Started Jun 06 01:07:08 PM PDT 24
Finished Jun 06 01:07:38 PM PDT 24
Peak memory 200280 kb
Host smart-445f56d2-0636-4593-b700-a1411091a07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680005173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3680005173
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2875960477
Short name T177
Test name
Test status
Simulation time 11545614 ps
CPU time 0.55 seconds
Started Jun 06 01:06:44 PM PDT 24
Finished Jun 06 01:06:47 PM PDT 24
Peak memory 196204 kb
Host smart-16f60433-f309-4701-a8cb-93ec83cabac4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875960477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2875960477
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3537053231
Short name T354
Test name
Test status
Simulation time 2314831410 ps
CPU time 26.48 seconds
Started Jun 06 01:06:49 PM PDT 24
Finished Jun 06 01:07:17 PM PDT 24
Peak memory 212336 kb
Host smart-30046c6e-c19a-4ddb-9b1f-dcf96b5bc0d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3537053231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3537053231
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.4256498311
Short name T446
Test name
Test status
Simulation time 839456397 ps
CPU time 41.8 seconds
Started Jun 06 01:06:47 PM PDT 24
Finished Jun 06 01:07:31 PM PDT 24
Peak memory 200384 kb
Host smart-8b0cb449-e5f2-4327-a3dc-d4662e814bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256498311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.4256498311
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.2094113025
Short name T224
Test name
Test status
Simulation time 4194910970 ps
CPU time 1136.55 seconds
Started Jun 06 01:06:50 PM PDT 24
Finished Jun 06 01:25:49 PM PDT 24
Peak memory 751136 kb
Host smart-b625ea09-af90-461a-ac50-79a3cc47de72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2094113025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2094113025
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.1183821534
Short name T77
Test name
Test status
Simulation time 18464377909 ps
CPU time 213.1 seconds
Started Jun 06 01:06:45 PM PDT 24
Finished Jun 06 01:10:20 PM PDT 24
Peak memory 200508 kb
Host smart-b96cc1f9-bc66-4251-a037-bdf5bffb38b2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183821534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.1183821534
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2852215432
Short name T220
Test name
Test status
Simulation time 2961090284 ps
CPU time 41.12 seconds
Started Jun 06 01:06:45 PM PDT 24
Finished Jun 06 01:07:28 PM PDT 24
Peak memory 200520 kb
Host smart-02f85163-3711-4d28-a371-96dce79d3297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852215432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2852215432
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.816825847
Short name T307
Test name
Test status
Simulation time 428051206 ps
CPU time 1.26 seconds
Started Jun 06 01:06:47 PM PDT 24
Finished Jun 06 01:06:50 PM PDT 24
Peak memory 200288 kb
Host smart-17edeb19-34ec-4b43-a860-f46f807a3801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816825847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.816825847
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2508387018
Short name T514
Test name
Test status
Simulation time 98059751902 ps
CPU time 283.26 seconds
Started Jun 06 01:06:46 PM PDT 24
Finished Jun 06 01:11:31 PM PDT 24
Peak memory 211436 kb
Host smart-d4c3973b-f13c-4e2d-82f4-74cff901e695
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508387018 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2508387018
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.81719753
Short name T281
Test name
Test status
Simulation time 60649244 ps
CPU time 1.32 seconds
Started Jun 06 01:06:44 PM PDT 24
Finished Jun 06 01:06:47 PM PDT 24
Peak memory 200360 kb
Host smart-63d4ffcc-cdb5-4143-b1c4-db60540aa992
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81719753 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.hmac_test_hmac_vectors.81719753
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.131197779
Short name T246
Test name
Test status
Simulation time 7602063141 ps
CPU time 412.15 seconds
Started Jun 06 01:06:47 PM PDT 24
Finished Jun 06 01:13:41 PM PDT 24
Peak memory 200372 kb
Host smart-fdc7aee1-4a0b-4c89-aa39-6304a6dbde0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131197779 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.131197779
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1842459335
Short name T471
Test name
Test status
Simulation time 2652452656 ps
CPU time 27.19 seconds
Started Jun 06 01:06:44 PM PDT 24
Finished Jun 06 01:07:13 PM PDT 24
Peak memory 200416 kb
Host smart-d0065fa2-07f8-4153-b774-caac0ff7f3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842459335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1842459335
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.4129265232
Short name T250
Test name
Test status
Simulation time 22806698 ps
CPU time 0.56 seconds
Started Jun 06 01:06:50 PM PDT 24
Finished Jun 06 01:06:53 PM PDT 24
Peak memory 196128 kb
Host smart-1d484185-612f-4e44-94e4-f8a3c2b9dd4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129265232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.4129265232
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2602836638
Short name T219
Test name
Test status
Simulation time 2482059918 ps
CPU time 54.34 seconds
Started Jun 06 01:06:48 PM PDT 24
Finished Jun 06 01:07:45 PM PDT 24
Peak memory 228116 kb
Host smart-e2771b0f-432a-4722-9b13-0bc151abebd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2602836638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2602836638
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2087489385
Short name T416
Test name
Test status
Simulation time 3224794648 ps
CPU time 45.59 seconds
Started Jun 06 01:06:46 PM PDT 24
Finished Jun 06 01:07:33 PM PDT 24
Peak memory 200488 kb
Host smart-8ef4b696-c3eb-437f-b136-c42d363a0fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087489385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2087489385
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.370262923
Short name T564
Test name
Test status
Simulation time 2156589521 ps
CPU time 534.25 seconds
Started Jun 06 01:06:50 PM PDT 24
Finished Jun 06 01:15:47 PM PDT 24
Peak memory 637988 kb
Host smart-cb99029b-7f0d-419a-a805-15125d28df84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=370262923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.370262923
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3231764588
Short name T417
Test name
Test status
Simulation time 16860288790 ps
CPU time 149.66 seconds
Started Jun 06 01:06:47 PM PDT 24
Finished Jun 06 01:09:18 PM PDT 24
Peak memory 200408 kb
Host smart-2cc04d6c-e969-47ad-add9-da77b178f0e7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231764588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3231764588
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3779156593
Short name T350
Test name
Test status
Simulation time 2689583046 ps
CPU time 37.18 seconds
Started Jun 06 01:06:49 PM PDT 24
Finished Jun 06 01:07:29 PM PDT 24
Peak memory 200424 kb
Host smart-dac84a96-8f3d-4fdd-8fd1-bb62269a67ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779156593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3779156593
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.792455316
Short name T352
Test name
Test status
Simulation time 346954930 ps
CPU time 6.53 seconds
Started Jun 06 01:06:50 PM PDT 24
Finished Jun 06 01:06:58 PM PDT 24
Peak memory 200364 kb
Host smart-854a7b23-1d73-4cb7-acd3-f2b42df5fa90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792455316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.792455316
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.2106380645
Short name T65
Test name
Test status
Simulation time 367876038789 ps
CPU time 1740.87 seconds
Started Jun 06 01:06:49 PM PDT 24
Finished Jun 06 01:35:53 PM PDT 24
Peak memory 342348 kb
Host smart-93820bcd-4ff5-468c-a3cb-48987c6fd49c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106380645 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.2106380645
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.2045752454
Short name T550
Test name
Test status
Simulation time 233862381 ps
CPU time 1.42 seconds
Started Jun 06 01:06:47 PM PDT 24
Finished Jun 06 01:06:50 PM PDT 24
Peak memory 200396 kb
Host smart-6b1fd165-f015-401a-9c31-0bc7b010d525
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045752454 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.2045752454
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.3069472281
Short name T336
Test name
Test status
Simulation time 34749250416 ps
CPU time 524.73 seconds
Started Jun 06 01:06:45 PM PDT 24
Finished Jun 06 01:15:31 PM PDT 24
Peak memory 200412 kb
Host smart-474a3243-fc15-4c39-9b2f-990853311f3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069472281 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.3069472281
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2005899136
Short name T3
Test name
Test status
Simulation time 229913619 ps
CPU time 6.44 seconds
Started Jun 06 01:06:43 PM PDT 24
Finished Jun 06 01:06:52 PM PDT 24
Peak memory 200304 kb
Host smart-d1b1ef37-d17b-46a1-a8b4-b61ed96d9107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005899136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2005899136
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.2216692953
Short name T327
Test name
Test status
Simulation time 31860238 ps
CPU time 0.61 seconds
Started Jun 06 01:06:57 PM PDT 24
Finished Jun 06 01:06:59 PM PDT 24
Peak memory 196956 kb
Host smart-615308a6-dccb-456e-a55e-9cab489b91b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216692953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2216692953
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3990420749
Short name T169
Test name
Test status
Simulation time 541903374 ps
CPU time 28.87 seconds
Started Jun 06 01:06:47 PM PDT 24
Finished Jun 06 01:07:17 PM PDT 24
Peak memory 220872 kb
Host smart-5f47712c-23cc-4443-937f-d0b3abfa02aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3990420749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3990420749
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.825053202
Short name T371
Test name
Test status
Simulation time 221337271 ps
CPU time 8.99 seconds
Started Jun 06 01:06:57 PM PDT 24
Finished Jun 06 01:07:07 PM PDT 24
Peak memory 200376 kb
Host smart-76da97cd-c103-4745-ae57-e48bb7bd4704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825053202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.825053202
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3211444505
Short name T211
Test name
Test status
Simulation time 21179149381 ps
CPU time 1356.82 seconds
Started Jun 06 01:06:56 PM PDT 24
Finished Jun 06 01:29:34 PM PDT 24
Peak memory 794240 kb
Host smart-2b4b5055-e780-49f0-8c5d-42b2848f787c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3211444505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3211444505
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2729409108
Short name T557
Test name
Test status
Simulation time 4690272197 ps
CPU time 66.43 seconds
Started Jun 06 01:07:00 PM PDT 24
Finished Jun 06 01:08:08 PM PDT 24
Peak memory 200436 kb
Host smart-9bbf42a1-eb78-4505-9b81-65a071cecba9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729409108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2729409108
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2171324390
Short name T483
Test name
Test status
Simulation time 6281575246 ps
CPU time 60.38 seconds
Started Jun 06 01:06:47 PM PDT 24
Finished Jun 06 01:07:49 PM PDT 24
Peak memory 200460 kb
Host smart-dea30358-b8a2-4469-ab98-a5d12deae721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171324390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2171324390
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1525881095
Short name T145
Test name
Test status
Simulation time 485379142 ps
CPU time 7.2 seconds
Started Jun 06 01:06:47 PM PDT 24
Finished Jun 06 01:06:56 PM PDT 24
Peak memory 200356 kb
Host smart-0a8b6228-af2c-4af8-bc05-011ec492ad92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525881095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1525881095
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2769633591
Short name T225
Test name
Test status
Simulation time 485669588269 ps
CPU time 2241.6 seconds
Started Jun 06 01:06:57 PM PDT 24
Finished Jun 06 01:44:20 PM PDT 24
Peak memory 216252 kb
Host smart-fc962195-035a-4be6-b2b9-e67139c8c23c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769633591 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2769633591
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.2394676361
Short name T602
Test name
Test status
Simulation time 251878163 ps
CPU time 1.39 seconds
Started Jun 06 01:06:57 PM PDT 24
Finished Jun 06 01:06:59 PM PDT 24
Peak memory 200436 kb
Host smart-c3003da7-eb87-448d-8107-1dfbb2899304
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394676361 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.2394676361
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.797142014
Short name T340
Test name
Test status
Simulation time 20050041137 ps
CPU time 423.65 seconds
Started Jun 06 01:07:00 PM PDT 24
Finished Jun 06 01:14:05 PM PDT 24
Peak memory 200372 kb
Host smart-7837ba26-10db-49f4-8376-eb7375fbf1a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797142014 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.797142014
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.2753177518
Short name T573
Test name
Test status
Simulation time 1065310480 ps
CPU time 43.1 seconds
Started Jun 06 01:07:04 PM PDT 24
Finished Jun 06 01:07:47 PM PDT 24
Peak memory 200648 kb
Host smart-271616f5-5293-41ce-89cd-5b6d040cdfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753177518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2753177518
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.3295176619
Short name T158
Test name
Test status
Simulation time 40915534 ps
CPU time 0.62 seconds
Started Jun 06 01:07:00 PM PDT 24
Finished Jun 06 01:07:02 PM PDT 24
Peak memory 196100 kb
Host smart-36cea622-3762-424d-aa0d-0d5422a61209
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295176619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.3295176619
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3084736580
Short name T61
Test name
Test status
Simulation time 741601841 ps
CPU time 37.41 seconds
Started Jun 06 01:06:59 PM PDT 24
Finished Jun 06 01:07:37 PM PDT 24
Peak memory 216772 kb
Host smart-0daf759b-0865-4167-a7be-abd39822d04a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3084736580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3084736580
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.4235454513
Short name T167
Test name
Test status
Simulation time 1662368458 ps
CPU time 45.94 seconds
Started Jun 06 01:06:58 PM PDT 24
Finished Jun 06 01:07:45 PM PDT 24
Peak memory 200368 kb
Host smart-c8c32d36-8e25-4b85-a3eb-fd2285823a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235454513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.4235454513
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.1323990142
Short name T131
Test name
Test status
Simulation time 6957998391 ps
CPU time 414.07 seconds
Started Jun 06 01:06:59 PM PDT 24
Finished Jun 06 01:13:54 PM PDT 24
Peak memory 640960 kb
Host smart-22c37d9f-128b-4fc9-b965-9c687388404c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1323990142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1323990142
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.273383508
Short name T253
Test name
Test status
Simulation time 10821671401 ps
CPU time 154.16 seconds
Started Jun 06 01:06:59 PM PDT 24
Finished Jun 06 01:09:34 PM PDT 24
Peak memory 200420 kb
Host smart-f86fbeb9-456e-4f4d-8be1-d36216a3c7fd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273383508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.273383508
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.3276643354
Short name T79
Test name
Test status
Simulation time 1693222158 ps
CPU time 93.58 seconds
Started Jun 06 01:07:00 PM PDT 24
Finished Jun 06 01:08:34 PM PDT 24
Peak memory 200400 kb
Host smart-38e6ad2a-e305-4fe0-b051-97d1c958b069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276643354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3276643354
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.130293986
Short name T278
Test name
Test status
Simulation time 442434263 ps
CPU time 5.27 seconds
Started Jun 06 01:06:59 PM PDT 24
Finished Jun 06 01:07:06 PM PDT 24
Peak memory 200400 kb
Host smart-f347e812-7145-45f8-b78d-0444fdf6396e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130293986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.130293986
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3953243453
Short name T114
Test name
Test status
Simulation time 1555120091596 ps
CPU time 1586.89 seconds
Started Jun 06 01:07:00 PM PDT 24
Finished Jun 06 01:33:28 PM PDT 24
Peak memory 241424 kb
Host smart-e32ccfa9-2fd2-4942-bf92-99451d21955b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953243453 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3953243453
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.943412843
Short name T128
Test name
Test status
Simulation time 106534458 ps
CPU time 1.01 seconds
Started Jun 06 01:06:59 PM PDT 24
Finished Jun 06 01:07:01 PM PDT 24
Peak memory 200212 kb
Host smart-bc51bdf2-b119-44e3-9a19-572e5a4f3cf0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943412843 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_hmac_vectors.943412843
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.3239996300
Short name T493
Test name
Test status
Simulation time 8222945024 ps
CPU time 465.19 seconds
Started Jun 06 01:07:04 PM PDT 24
Finished Jun 06 01:14:50 PM PDT 24
Peak memory 200780 kb
Host smart-1440847c-b428-49a5-8a59-365b86829b57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239996300 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.3239996300
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.718954572
Short name T277
Test name
Test status
Simulation time 2298884939 ps
CPU time 50.88 seconds
Started Jun 06 01:07:01 PM PDT 24
Finished Jun 06 01:07:53 PM PDT 24
Peak memory 200400 kb
Host smart-579f9759-79ca-40e4-b2cc-05cf110f967c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718954572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.718954572
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.3539125708
Short name T567
Test name
Test status
Simulation time 135357291 ps
CPU time 0.6 seconds
Started Jun 06 01:07:07 PM PDT 24
Finished Jun 06 01:07:09 PM PDT 24
Peak memory 196232 kb
Host smart-baefc6ba-cc5b-42bd-aa80-ba79abeb0211
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539125708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3539125708
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3529445701
Short name T193
Test name
Test status
Simulation time 286584179 ps
CPU time 14.52 seconds
Started Jun 06 01:07:00 PM PDT 24
Finished Jun 06 01:07:16 PM PDT 24
Peak memory 215960 kb
Host smart-d4c1fbe2-591b-4b91-93dc-f30e2efb31df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3529445701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3529445701
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.1512737258
Short name T415
Test name
Test status
Simulation time 1924787297 ps
CPU time 52.6 seconds
Started Jun 06 01:07:00 PM PDT 24
Finished Jun 06 01:07:54 PM PDT 24
Peak memory 200320 kb
Host smart-dcc0436a-d8f8-4a70-a876-96fa9a6dd7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512737258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1512737258
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.419685474
Short name T380
Test name
Test status
Simulation time 2746049295 ps
CPU time 276.85 seconds
Started Jun 06 01:07:26 PM PDT 24
Finished Jun 06 01:12:05 PM PDT 24
Peak memory 625088 kb
Host smart-fa6628b3-ed18-44c3-a466-d488eb7e74a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=419685474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.419685474
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.1022505079
Short name T184
Test name
Test status
Simulation time 3477411316 ps
CPU time 31.86 seconds
Started Jun 06 01:07:00 PM PDT 24
Finished Jun 06 01:07:32 PM PDT 24
Peak memory 200392 kb
Host smart-c680a96c-2717-4d3f-b432-483984a9aa65
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022505079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1022505079
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.768071064
Short name T288
Test name
Test status
Simulation time 5518932478 ps
CPU time 84.85 seconds
Started Jun 06 01:07:00 PM PDT 24
Finished Jun 06 01:08:26 PM PDT 24
Peak memory 200452 kb
Host smart-97c0362c-002c-4188-bacb-71fc1a0d8927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768071064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.768071064
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.620610722
Short name T401
Test name
Test status
Simulation time 576252923 ps
CPU time 8.97 seconds
Started Jun 06 01:07:02 PM PDT 24
Finished Jun 06 01:07:11 PM PDT 24
Peak memory 200364 kb
Host smart-3947d8c5-aad9-4e04-9ef6-c39239de8b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620610722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.620610722
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.1063153343
Short name T240
Test name
Test status
Simulation time 10690023957 ps
CPU time 231.51 seconds
Started Jun 06 01:07:11 PM PDT 24
Finished Jun 06 01:11:03 PM PDT 24
Peak memory 380004 kb
Host smart-9b6765f8-2c06-4bd8-a363-3041895bc483
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063153343 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1063153343
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.3169400539
Short name T393
Test name
Test status
Simulation time 162980944 ps
CPU time 1.15 seconds
Started Jun 06 01:07:10 PM PDT 24
Finished Jun 06 01:07:11 PM PDT 24
Peak memory 200080 kb
Host smart-dfa147b3-f4c3-4b8f-88f7-a1b8bc5e5092
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169400539 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.3169400539
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.1729143342
Short name T389
Test name
Test status
Simulation time 155266930204 ps
CPU time 540.24 seconds
Started Jun 06 01:07:07 PM PDT 24
Finished Jun 06 01:16:08 PM PDT 24
Peak memory 200396 kb
Host smart-f9b21a20-27fe-4a1c-aa91-7f36f88dfc44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729143342 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.1729143342
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.471982423
Short name T339
Test name
Test status
Simulation time 1269549443 ps
CPU time 60.86 seconds
Started Jun 06 01:07:01 PM PDT 24
Finished Jun 06 01:08:03 PM PDT 24
Peak memory 200340 kb
Host smart-84fe8ebc-61aa-46a1-97cf-7005d151e7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471982423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.471982423
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.1731882823
Short name T474
Test name
Test status
Simulation time 72727863 ps
CPU time 0.57 seconds
Started Jun 06 01:06:03 PM PDT 24
Finished Jun 06 01:06:04 PM PDT 24
Peak memory 196216 kb
Host smart-97f38464-da2a-4576-940d-d1fb71af1bd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731882823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1731882823
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.803617940
Short name T42
Test name
Test status
Simulation time 531534371 ps
CPU time 27.59 seconds
Started Jun 06 01:06:05 PM PDT 24
Finished Jun 06 01:06:34 PM PDT 24
Peak memory 216352 kb
Host smart-3a55869b-c3ad-4394-9f61-e5aa37362f2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=803617940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.803617940
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3000576702
Short name T356
Test name
Test status
Simulation time 4402037564 ps
CPU time 62.52 seconds
Started Jun 06 01:06:07 PM PDT 24
Finished Jun 06 01:07:10 PM PDT 24
Peak memory 200428 kb
Host smart-aa41547e-c06d-4855-a7d9-66e1b1055df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000576702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3000576702
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.239231698
Short name T82
Test name
Test status
Simulation time 1981439487 ps
CPU time 73.75 seconds
Started Jun 06 01:06:06 PM PDT 24
Finished Jun 06 01:07:20 PM PDT 24
Peak memory 333628 kb
Host smart-c49cfa2b-86b0-4735-9d35-343e5008498a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=239231698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.239231698
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2608329636
Short name T287
Test name
Test status
Simulation time 7538335123 ps
CPU time 74.35 seconds
Started Jun 06 01:06:05 PM PDT 24
Finished Jun 06 01:07:20 PM PDT 24
Peak memory 200424 kb
Host smart-02a0a083-5716-41cd-905c-d950a5493adc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608329636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2608329636
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2251802899
Short name T600
Test name
Test status
Simulation time 7975754816 ps
CPU time 73.59 seconds
Started Jun 06 01:06:04 PM PDT 24
Finished Jun 06 01:07:19 PM PDT 24
Peak memory 200464 kb
Host smart-e9943ac8-61c6-45b2-b42b-236e99b69e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251802899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2251802899
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1657088962
Short name T28
Test name
Test status
Simulation time 110425691 ps
CPU time 0.81 seconds
Started Jun 06 01:06:05 PM PDT 24
Finished Jun 06 01:06:06 PM PDT 24
Peak memory 218900 kb
Host smart-0924b567-709d-42b4-806c-9e54ed55495a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657088962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1657088962
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3319266100
Short name T32
Test name
Test status
Simulation time 1186428902 ps
CPU time 9.76 seconds
Started Jun 06 01:06:04 PM PDT 24
Finished Jun 06 01:06:15 PM PDT 24
Peak memory 200400 kb
Host smart-479e89ff-b8a2-494b-b873-23dc9d62652c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319266100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3319266100
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1332557330
Short name T160
Test name
Test status
Simulation time 11265845494 ps
CPU time 155.31 seconds
Started Jun 06 01:06:08 PM PDT 24
Finished Jun 06 01:08:45 PM PDT 24
Peak memory 200452 kb
Host smart-6ea31966-0f1d-45f0-94a8-a86c47baf03e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332557330 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1332557330
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.1727390747
Short name T314
Test name
Test status
Simulation time 223258825 ps
CPU time 1.03 seconds
Started Jun 06 01:06:07 PM PDT 24
Finished Jun 06 01:06:09 PM PDT 24
Peak memory 200376 kb
Host smart-5cfb5aef-931a-4cd5-86e3-1d00bd6d5c33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727390747 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.1727390747
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.1312743114
Short name T412
Test name
Test status
Simulation time 7974161105 ps
CPU time 410.22 seconds
Started Jun 06 01:06:05 PM PDT 24
Finished Jun 06 01:12:56 PM PDT 24
Peak memory 200448 kb
Host smart-ec68338c-941e-48a8-97a3-bfe1a36f0799
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312743114 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.1312743114
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.2113034484
Short name T197
Test name
Test status
Simulation time 3832728049 ps
CPU time 26.81 seconds
Started Jun 06 01:06:15 PM PDT 24
Finished Jun 06 01:06:43 PM PDT 24
Peak memory 200444 kb
Host smart-c937055c-298f-4c65-b56d-cd94e5cbedb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113034484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2113034484
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1945418478
Short name T344
Test name
Test status
Simulation time 23757742 ps
CPU time 0.6 seconds
Started Jun 06 01:07:08 PM PDT 24
Finished Jun 06 01:07:10 PM PDT 24
Peak memory 196860 kb
Host smart-d882c77f-461d-455b-8f02-73ad5de196cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945418478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1945418478
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.4040689041
Short name T501
Test name
Test status
Simulation time 10416678027 ps
CPU time 49.37 seconds
Started Jun 06 01:07:05 PM PDT 24
Finished Jun 06 01:07:55 PM PDT 24
Peak memory 229104 kb
Host smart-b7ed2598-cb37-4d70-9bc5-787d0c292d64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4040689041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.4040689041
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1909103911
Short name T201
Test name
Test status
Simulation time 3178995365 ps
CPU time 69.12 seconds
Started Jun 06 01:07:04 PM PDT 24
Finished Jun 06 01:08:14 PM PDT 24
Peak memory 200452 kb
Host smart-52d4d097-8338-4a4e-aa9a-4b6b72ce3e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909103911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1909103911
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.3448015817
Short name T228
Test name
Test status
Simulation time 3676175424 ps
CPU time 1034.01 seconds
Started Jun 06 01:07:11 PM PDT 24
Finished Jun 06 01:24:26 PM PDT 24
Peak memory 720244 kb
Host smart-a6dbee35-59af-4a42-b3b2-375dc7233ea0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3448015817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3448015817
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3992225895
Short name T448
Test name
Test status
Simulation time 7276517237 ps
CPU time 121.97 seconds
Started Jun 06 01:07:10 PM PDT 24
Finished Jun 06 01:09:13 PM PDT 24
Peak memory 200432 kb
Host smart-09381ba1-9b05-4744-84cf-e7e7a52931bf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992225895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3992225895
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2190794532
Short name T311
Test name
Test status
Simulation time 127267139 ps
CPU time 7.37 seconds
Started Jun 06 01:07:03 PM PDT 24
Finished Jun 06 01:07:11 PM PDT 24
Peak memory 200364 kb
Host smart-47433445-55a1-4f11-892d-28b80f5dbff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190794532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2190794532
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3176164558
Short name T406
Test name
Test status
Simulation time 46454072 ps
CPU time 0.78 seconds
Started Jun 06 01:07:05 PM PDT 24
Finished Jun 06 01:07:07 PM PDT 24
Peak memory 198212 kb
Host smart-8ff7dafa-e8fb-40cd-b625-a7f87f15c81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176164558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3176164558
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1337085809
Short name T70
Test name
Test status
Simulation time 114323840979 ps
CPU time 1450.56 seconds
Started Jun 06 01:07:04 PM PDT 24
Finished Jun 06 01:31:15 PM PDT 24
Peak memory 233188 kb
Host smart-89bb7aa1-3266-4ac6-a218-b8fd7b1246de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337085809 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1337085809
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.3863640310
Short name T586
Test name
Test status
Simulation time 333907210 ps
CPU time 1.55 seconds
Started Jun 06 01:07:05 PM PDT 24
Finished Jun 06 01:07:07 PM PDT 24
Peak memory 200408 kb
Host smart-080b4914-9a9f-46a0-bb88-10a99d77ee63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863640310 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.3863640310
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.2749582454
Short name T176
Test name
Test status
Simulation time 37156034079 ps
CPU time 465.05 seconds
Started Jun 06 01:07:07 PM PDT 24
Finished Jun 06 01:14:53 PM PDT 24
Peak memory 200408 kb
Host smart-866ed2c9-4da1-4cb1-a030-065df8c9924a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749582454 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.2749582454
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3060814188
Short name T283
Test name
Test status
Simulation time 2764306074 ps
CPU time 27.76 seconds
Started Jun 06 01:07:06 PM PDT 24
Finished Jun 06 01:07:34 PM PDT 24
Peak memory 200472 kb
Host smart-5146b13a-bdb1-41e4-861a-b3d448be9f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060814188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3060814188
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.58310254
Short name T463
Test name
Test status
Simulation time 26472458 ps
CPU time 0.59 seconds
Started Jun 06 01:07:12 PM PDT 24
Finished Jun 06 01:07:14 PM PDT 24
Peak memory 196260 kb
Host smart-2ee40598-9e5a-4199-8fc2-996a8dc0d8cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58310254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.58310254
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.870030375
Short name T421
Test name
Test status
Simulation time 299663130 ps
CPU time 15.34 seconds
Started Jun 06 01:07:08 PM PDT 24
Finished Jun 06 01:07:24 PM PDT 24
Peak memory 208600 kb
Host smart-6c8d6773-d1aa-44de-91a2-42131973f081
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=870030375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.870030375
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.578387345
Short name T299
Test name
Test status
Simulation time 2143866051 ps
CPU time 27.82 seconds
Started Jun 06 01:07:10 PM PDT 24
Finished Jun 06 01:07:38 PM PDT 24
Peak memory 200292 kb
Host smart-6cbd7ffb-4edd-46b7-abfc-090d0aafbfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578387345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.578387345
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2746811566
Short name T318
Test name
Test status
Simulation time 1170149458 ps
CPU time 213.94 seconds
Started Jun 06 01:07:05 PM PDT 24
Finished Jun 06 01:10:40 PM PDT 24
Peak memory 599368 kb
Host smart-4fdc1d1e-eb77-4f4a-9439-d3c5eda53d00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2746811566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2746811566
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3483077666
Short name T459
Test name
Test status
Simulation time 20233788266 ps
CPU time 188.16 seconds
Started Jun 06 01:07:02 PM PDT 24
Finished Jun 06 01:10:11 PM PDT 24
Peak memory 200420 kb
Host smart-a2f5d24c-5f71-494b-8974-9447a480ba1c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483077666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3483077666
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3045726938
Short name T75
Test name
Test status
Simulation time 34272188738 ps
CPU time 89.21 seconds
Started Jun 06 01:07:10 PM PDT 24
Finished Jun 06 01:08:40 PM PDT 24
Peak memory 200460 kb
Host smart-0ab0cf85-e695-45eb-a9c2-765a846f89ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045726938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3045726938
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.647019170
Short name T343
Test name
Test status
Simulation time 457864239 ps
CPU time 3.73 seconds
Started Jun 06 01:07:11 PM PDT 24
Finished Jun 06 01:07:16 PM PDT 24
Peak memory 200400 kb
Host smart-39e59d3c-cf43-4972-95e3-0f15edbe5997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647019170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.647019170
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2464144633
Short name T467
Test name
Test status
Simulation time 5860428326 ps
CPU time 29.41 seconds
Started Jun 06 01:07:05 PM PDT 24
Finished Jun 06 01:07:36 PM PDT 24
Peak memory 200512 kb
Host smart-6596f88d-e698-477e-9230-3d318ffc0668
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464144633 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2464144633
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.3589464155
Short name T423
Test name
Test status
Simulation time 63053952 ps
CPU time 1.42 seconds
Started Jun 06 01:07:06 PM PDT 24
Finished Jun 06 01:07:09 PM PDT 24
Peak memory 200320 kb
Host smart-ac51757a-05d0-4a65-b605-5e7dc86eefce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589464155 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.3589464155
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.1732486719
Short name T157
Test name
Test status
Simulation time 50788816701 ps
CPU time 471.8 seconds
Started Jun 06 01:07:08 PM PDT 24
Finished Jun 06 01:15:01 PM PDT 24
Peak memory 200360 kb
Host smart-cbee7ec5-9363-41d6-a048-8b4048ffacea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732486719 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.1732486719
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.3348642961
Short name T367
Test name
Test status
Simulation time 15615148189 ps
CPU time 55.36 seconds
Started Jun 06 01:07:09 PM PDT 24
Finished Jun 06 01:08:05 PM PDT 24
Peak memory 200328 kb
Host smart-e76f88ea-ffcf-4bd9-84b7-55a1003c5cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348642961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.3348642961
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2166845142
Short name T330
Test name
Test status
Simulation time 30482907 ps
CPU time 0.55 seconds
Started Jun 06 01:07:17 PM PDT 24
Finished Jun 06 01:07:19 PM PDT 24
Peak memory 195200 kb
Host smart-c684a305-3fc1-4f2a-8171-6266ec8ead03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166845142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2166845142
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.4135813777
Short name T148
Test name
Test status
Simulation time 1876361700 ps
CPU time 21.51 seconds
Started Jun 06 01:07:14 PM PDT 24
Finished Jun 06 01:07:37 PM PDT 24
Peak memory 216588 kb
Host smart-8581d017-2660-4286-bbae-c03707e5023f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4135813777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.4135813777
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.460857361
Short name T332
Test name
Test status
Simulation time 1008454491 ps
CPU time 53.52 seconds
Started Jun 06 01:07:14 PM PDT 24
Finished Jun 06 01:08:09 PM PDT 24
Peak memory 200384 kb
Host smart-d0ed9191-dc35-4de8-9512-429588ba0963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460857361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.460857361
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.4252100733
Short name T274
Test name
Test status
Simulation time 2477968437 ps
CPU time 605.81 seconds
Started Jun 06 01:07:12 PM PDT 24
Finished Jun 06 01:17:19 PM PDT 24
Peak memory 641760 kb
Host smart-8b862ba0-5c65-4a5d-8382-0f8ab0fdb1f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4252100733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.4252100733
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.229328579
Short name T598
Test name
Test status
Simulation time 1349355421 ps
CPU time 75.87 seconds
Started Jun 06 01:07:13 PM PDT 24
Finished Jun 06 01:08:31 PM PDT 24
Peak memory 200380 kb
Host smart-16d82a1e-4d36-4328-bf44-f607b47cb6d3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229328579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.229328579
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.1787345986
Short name T348
Test name
Test status
Simulation time 203303719 ps
CPU time 3.09 seconds
Started Jun 06 01:07:14 PM PDT 24
Finished Jun 06 01:07:18 PM PDT 24
Peak memory 200288 kb
Host smart-499fbbd5-a05b-41ef-bbf5-f42d15ab4b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787345986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1787345986
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.4073936363
Short name T223
Test name
Test status
Simulation time 150768810 ps
CPU time 2.36 seconds
Started Jun 06 01:07:13 PM PDT 24
Finished Jun 06 01:07:16 PM PDT 24
Peak memory 200356 kb
Host smart-bcd25ebe-0ddc-4ef8-b6ce-1a55e1ee91e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073936363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.4073936363
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.745068400
Short name T370
Test name
Test status
Simulation time 234964797 ps
CPU time 1.35 seconds
Started Jun 06 01:07:13 PM PDT 24
Finished Jun 06 01:07:16 PM PDT 24
Peak memory 200356 kb
Host smart-e157fe18-040d-411c-bf55-f204b139383a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745068400 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_hmac_vectors.745068400
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.344523985
Short name T574
Test name
Test status
Simulation time 15432607349 ps
CPU time 457.35 seconds
Started Jun 06 01:07:12 PM PDT 24
Finished Jun 06 01:14:50 PM PDT 24
Peak memory 200628 kb
Host smart-00ecdb0c-df33-41bf-a556-a8c17960d523
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344523985 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.344523985
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.615805579
Short name T154
Test name
Test status
Simulation time 12856725214 ps
CPU time 45.45 seconds
Started Jun 06 01:07:14 PM PDT 24
Finished Jun 06 01:08:02 PM PDT 24
Peak memory 200420 kb
Host smart-d9991b4f-b232-49f7-ba08-6c815bcb5019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615805579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.615805579
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.3865545559
Short name T387
Test name
Test status
Simulation time 49271934 ps
CPU time 0.6 seconds
Started Jun 06 01:07:13 PM PDT 24
Finished Jun 06 01:07:15 PM PDT 24
Peak memory 196204 kb
Host smart-c079b142-59be-43ce-b5b1-8526961817d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865545559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3865545559
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3832900491
Short name T505
Test name
Test status
Simulation time 961353278 ps
CPU time 45.89 seconds
Started Jun 06 01:07:14 PM PDT 24
Finished Jun 06 01:08:01 PM PDT 24
Peak memory 241352 kb
Host smart-e65a8834-44e2-4639-922a-4c6152b42a81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3832900491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3832900491
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.2673299640
Short name T166
Test name
Test status
Simulation time 798469748 ps
CPU time 8.29 seconds
Started Jun 06 01:07:13 PM PDT 24
Finished Jun 06 01:07:23 PM PDT 24
Peak memory 200440 kb
Host smart-ced1fa07-163e-45b8-a6e8-bb3ab5e79125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673299640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2673299640
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.318182400
Short name T538
Test name
Test status
Simulation time 3741297867 ps
CPU time 853.33 seconds
Started Jun 06 01:07:15 PM PDT 24
Finished Jun 06 01:21:30 PM PDT 24
Peak memory 724404 kb
Host smart-16164ef4-192b-4e3e-8fc3-15f606388eaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=318182400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.318182400
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.773374009
Short name T364
Test name
Test status
Simulation time 6845545399 ps
CPU time 214.75 seconds
Started Jun 06 01:07:14 PM PDT 24
Finished Jun 06 01:10:51 PM PDT 24
Peak memory 200440 kb
Host smart-a480a0fa-e3e1-42c3-a250-7232cd03a419
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773374009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.773374009
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.2368229000
Short name T466
Test name
Test status
Simulation time 3185418436 ps
CPU time 51.52 seconds
Started Jun 06 01:07:14 PM PDT 24
Finished Jun 06 01:08:08 PM PDT 24
Peak memory 200508 kb
Host smart-cd43a21d-dab0-4170-8344-9183d0af3866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368229000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2368229000
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.4052975917
Short name T216
Test name
Test status
Simulation time 745210828 ps
CPU time 7.55 seconds
Started Jun 06 01:07:18 PM PDT 24
Finished Jun 06 01:07:27 PM PDT 24
Peak memory 200456 kb
Host smart-1e6b2041-a876-45e0-8c78-58470789758e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052975917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.4052975917
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3305909246
Short name T66
Test name
Test status
Simulation time 749991558582 ps
CPU time 1875.72 seconds
Started Jun 06 01:07:14 PM PDT 24
Finished Jun 06 01:38:31 PM PDT 24
Peak memory 200460 kb
Host smart-c48b2776-192c-4fce-b908-371d51fae604
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305909246 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3305909246
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.2358763269
Short name T390
Test name
Test status
Simulation time 32685582 ps
CPU time 1.1 seconds
Started Jun 06 01:07:14 PM PDT 24
Finished Jun 06 01:07:17 PM PDT 24
Peak memory 200124 kb
Host smart-765204db-d168-49ee-a371-4e0cf67f3be2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358763269 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.2358763269
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.4282759052
Short name T540
Test name
Test status
Simulation time 27609744930 ps
CPU time 464.46 seconds
Started Jun 06 01:07:12 PM PDT 24
Finished Jun 06 01:14:58 PM PDT 24
Peak memory 200388 kb
Host smart-ca344421-ea42-48a3-bc18-04b992739ccc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282759052 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.4282759052
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.834594210
Short name T439
Test name
Test status
Simulation time 2951344680 ps
CPU time 40.61 seconds
Started Jun 06 01:07:13 PM PDT 24
Finished Jun 06 01:07:55 PM PDT 24
Peak memory 200400 kb
Host smart-cb763c5f-6c8e-43a3-8f50-1cb7576a61ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834594210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.834594210
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3229855932
Short name T438
Test name
Test status
Simulation time 47997653 ps
CPU time 0.6 seconds
Started Jun 06 01:07:26 PM PDT 24
Finished Jun 06 01:07:28 PM PDT 24
Peak memory 195792 kb
Host smart-a44f872c-896b-4e0a-ae54-541134a15bf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229855932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3229855932
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3982841958
Short name T492
Test name
Test status
Simulation time 679554007 ps
CPU time 29.8 seconds
Started Jun 06 01:07:26 PM PDT 24
Finished Jun 06 01:07:58 PM PDT 24
Peak memory 224944 kb
Host smart-7584e2a3-b31b-453a-b1a0-f92e6af91f33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3982841958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3982841958
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.3992860152
Short name T190
Test name
Test status
Simulation time 2017287860 ps
CPU time 28.65 seconds
Started Jun 06 01:07:29 PM PDT 24
Finished Jun 06 01:07:59 PM PDT 24
Peak memory 200456 kb
Host smart-46565375-0106-42e1-bf6f-3feb97de84b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992860152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.3992860152
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.840730618
Short name T454
Test name
Test status
Simulation time 13191596861 ps
CPU time 1081.55 seconds
Started Jun 06 01:07:24 PM PDT 24
Finished Jun 06 01:25:28 PM PDT 24
Peak memory 772184 kb
Host smart-dac289fd-cc78-49ef-b8ec-c575c7688e96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=840730618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.840730618
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.3321715191
Short name T566
Test name
Test status
Simulation time 9003937748 ps
CPU time 56.79 seconds
Started Jun 06 01:07:25 PM PDT 24
Finished Jun 06 01:08:24 PM PDT 24
Peak memory 200480 kb
Host smart-13ff661a-95ee-4bbf-95b3-8785e736864f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321715191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3321715191
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.202696107
Short name T80
Test name
Test status
Simulation time 1032291951 ps
CPU time 21.92 seconds
Started Jun 06 01:07:25 PM PDT 24
Finished Jun 06 01:07:48 PM PDT 24
Peak memory 200332 kb
Host smart-7d057e60-90e7-4e22-93b2-800dd2382901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202696107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.202696107
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1253506576
Short name T569
Test name
Test status
Simulation time 239586919 ps
CPU time 2.45 seconds
Started Jun 06 01:07:15 PM PDT 24
Finished Jun 06 01:07:19 PM PDT 24
Peak memory 200324 kb
Host smart-244209a9-8e37-4c81-818f-ec6dd8559242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253506576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1253506576
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.2142880189
Short name T407
Test name
Test status
Simulation time 18356164790 ps
CPU time 1594.4 seconds
Started Jun 06 01:07:24 PM PDT 24
Finished Jun 06 01:34:00 PM PDT 24
Peak memory 782160 kb
Host smart-30c6daa8-d749-437a-8244-b8cee2ebd92b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142880189 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2142880189
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.2591517452
Short name T487
Test name
Test status
Simulation time 42767227 ps
CPU time 1.09 seconds
Started Jun 06 01:07:24 PM PDT 24
Finished Jun 06 01:07:27 PM PDT 24
Peak memory 200156 kb
Host smart-fc7188e7-4973-43c0-823c-967df11fce19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591517452 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.2591517452
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.1666533976
Short name T520
Test name
Test status
Simulation time 28528730662 ps
CPU time 421.2 seconds
Started Jun 06 01:07:26 PM PDT 24
Finished Jun 06 01:14:29 PM PDT 24
Peak memory 200392 kb
Host smart-0f517a49-b7ce-4a29-91ac-c25ef50d42bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666533976 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.1666533976
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2942577719
Short name T289
Test name
Test status
Simulation time 5544599563 ps
CPU time 70.12 seconds
Started Jun 06 01:07:26 PM PDT 24
Finished Jun 06 01:08:38 PM PDT 24
Peak memory 200432 kb
Host smart-df4dbc03-eae8-4681-9015-6e94e6d74dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942577719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2942577719
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.307682785
Short name T383
Test name
Test status
Simulation time 11568202 ps
CPU time 0.59 seconds
Started Jun 06 01:07:29 PM PDT 24
Finished Jun 06 01:07:31 PM PDT 24
Peak memory 196216 kb
Host smart-e076756b-82a1-4563-ae0a-4dc2250bc477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307682785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.307682785
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1049452297
Short name T504
Test name
Test status
Simulation time 1368773818 ps
CPU time 41.36 seconds
Started Jun 06 01:07:29 PM PDT 24
Finished Jun 06 01:08:11 PM PDT 24
Peak memory 233164 kb
Host smart-480fabb9-36c7-4d7b-97af-94d2d969ce32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1049452297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1049452297
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2687689906
Short name T62
Test name
Test status
Simulation time 586684572 ps
CPU time 11.62 seconds
Started Jun 06 01:07:25 PM PDT 24
Finished Jun 06 01:07:39 PM PDT 24
Peak memory 200344 kb
Host smart-0cc56ec7-9a97-41d3-9943-68d0d0ea2dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687689906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2687689906
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3197175196
Short name T362
Test name
Test status
Simulation time 1545504141 ps
CPU time 305.86 seconds
Started Jun 06 01:07:26 PM PDT 24
Finished Jun 06 01:12:34 PM PDT 24
Peak memory 619276 kb
Host smart-0487eb09-1eb3-425a-b641-604ad362daa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3197175196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3197175196
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.923964326
Short name T212
Test name
Test status
Simulation time 46224089483 ps
CPU time 154.9 seconds
Started Jun 06 01:07:25 PM PDT 24
Finished Jun 06 01:10:02 PM PDT 24
Peak memory 200420 kb
Host smart-bef94e4b-3010-44f6-bc6f-9b01c0f60d88
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923964326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.923964326
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.2208847202
Short name T284
Test name
Test status
Simulation time 26066191979 ps
CPU time 95.63 seconds
Started Jun 06 01:07:24 PM PDT 24
Finished Jun 06 01:09:01 PM PDT 24
Peak memory 200428 kb
Host smart-e4364fd6-5619-45b7-bbed-dfbdc898f971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208847202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.2208847202
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.3709658134
Short name T425
Test name
Test status
Simulation time 407913065 ps
CPU time 7.27 seconds
Started Jun 06 01:07:29 PM PDT 24
Finished Jun 06 01:07:37 PM PDT 24
Peak memory 200456 kb
Host smart-e1502853-a69d-44df-bdfd-72e01328ad41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709658134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3709658134
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.1045219093
Short name T386
Test name
Test status
Simulation time 341776163325 ps
CPU time 2243.27 seconds
Started Jun 06 01:07:24 PM PDT 24
Finished Jun 06 01:44:49 PM PDT 24
Peak memory 776388 kb
Host smart-732fd47b-4752-4f74-ae58-b3ecfc684369
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045219093 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1045219093
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.3817394075
Short name T526
Test name
Test status
Simulation time 595806919 ps
CPU time 1.17 seconds
Started Jun 06 01:07:26 PM PDT 24
Finished Jun 06 01:07:29 PM PDT 24
Peak memory 200388 kb
Host smart-757e709d-e527-4c41-a441-a2e4c8ba9fd8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817394075 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.3817394075
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.2228057743
Short name T357
Test name
Test status
Simulation time 7524365381 ps
CPU time 412.68 seconds
Started Jun 06 01:07:27 PM PDT 24
Finished Jun 06 01:14:21 PM PDT 24
Peak memory 200240 kb
Host smart-2ff7e38e-5e32-47aa-930a-127824d525f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228057743 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.2228057743
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.4228134342
Short name T480
Test name
Test status
Simulation time 6215934430 ps
CPU time 95.36 seconds
Started Jun 06 01:07:25 PM PDT 24
Finished Jun 06 01:09:02 PM PDT 24
Peak memory 200424 kb
Host smart-7fa0f9c2-b3a5-42b4-9a60-916f0e488dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228134342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.4228134342
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2981541228
Short name T22
Test name
Test status
Simulation time 25526138 ps
CPU time 0.56 seconds
Started Jun 06 01:07:26 PM PDT 24
Finished Jun 06 01:07:28 PM PDT 24
Peak memory 196204 kb
Host smart-c61a1e23-7d8a-4687-9625-50c8bc8e5c57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981541228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2981541228
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3993353799
Short name T46
Test name
Test status
Simulation time 577562071 ps
CPU time 22.92 seconds
Started Jun 06 01:07:28 PM PDT 24
Finished Jun 06 01:07:52 PM PDT 24
Peak memory 216244 kb
Host smart-be3495f1-de5d-4421-a2ca-cbeabda69a33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3993353799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3993353799
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1512959806
Short name T218
Test name
Test status
Simulation time 1018655158 ps
CPU time 52.52 seconds
Started Jun 06 01:07:25 PM PDT 24
Finished Jun 06 01:08:19 PM PDT 24
Peak memory 200336 kb
Host smart-0c9eb2f3-b01a-4d48-9510-1928e77c3a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512959806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1512959806
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2994692754
Short name T334
Test name
Test status
Simulation time 57512092 ps
CPU time 0.78 seconds
Started Jun 06 01:07:26 PM PDT 24
Finished Jun 06 01:07:29 PM PDT 24
Peak memory 197608 kb
Host smart-b4c45ef9-6c7a-4529-8329-c57f17ac75c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2994692754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2994692754
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1735305499
Short name T582
Test name
Test status
Simulation time 213335333 ps
CPU time 3.78 seconds
Started Jun 06 01:07:27 PM PDT 24
Finished Jun 06 01:07:33 PM PDT 24
Peak memory 200188 kb
Host smart-12d7458d-b9ec-4348-8518-55760f834905
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735305499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1735305499
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3045087890
Short name T335
Test name
Test status
Simulation time 25926929276 ps
CPU time 87.77 seconds
Started Jun 06 01:07:24 PM PDT 24
Finished Jun 06 01:08:53 PM PDT 24
Peak memory 200416 kb
Host smart-1d029d67-4536-44d8-868f-fc6990234c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045087890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3045087890
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.3449084362
Short name T242
Test name
Test status
Simulation time 1538424357 ps
CPU time 6.04 seconds
Started Jun 06 01:07:26 PM PDT 24
Finished Jun 06 01:07:33 PM PDT 24
Peak memory 200400 kb
Host smart-c778e186-3279-4803-8adb-f93b63745e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449084362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.3449084362
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.2323583509
Short name T112
Test name
Test status
Simulation time 5396951311 ps
CPU time 15.59 seconds
Started Jun 06 01:07:24 PM PDT 24
Finished Jun 06 01:07:42 PM PDT 24
Peak memory 200464 kb
Host smart-a3742b4d-f1e7-469f-a723-59ffa3c6c656
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323583509 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2323583509
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.3598532906
Short name T527
Test name
Test status
Simulation time 44364960 ps
CPU time 0.99 seconds
Started Jun 06 01:07:27 PM PDT 24
Finished Jun 06 01:07:30 PM PDT 24
Peak memory 200048 kb
Host smart-c70b4098-5074-4f12-8938-697662be28e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598532906 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.3598532906
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.366365923
Short name T156
Test name
Test status
Simulation time 28120172205 ps
CPU time 405.9 seconds
Started Jun 06 01:07:26 PM PDT 24
Finished Jun 06 01:14:13 PM PDT 24
Peak memory 199904 kb
Host smart-4d97a4b8-e243-4a13-9606-67f64aeacd7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366365923 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.366365923
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.799583368
Short name T191
Test name
Test status
Simulation time 13226672661 ps
CPU time 30.91 seconds
Started Jun 06 01:07:33 PM PDT 24
Finished Jun 06 01:08:04 PM PDT 24
Peak memory 200428 kb
Host smart-d7bdd609-d7d1-4342-bb44-a74198829ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799583368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.799583368
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.1742296630
Short name T178
Test name
Test status
Simulation time 78729624 ps
CPU time 0.6 seconds
Started Jun 06 01:07:37 PM PDT 24
Finished Jun 06 01:07:39 PM PDT 24
Peak memory 196200 kb
Host smart-8bfa48e0-325c-4a7c-8813-3203b146e559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742296630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.1742296630
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.345315408
Short name T431
Test name
Test status
Simulation time 367657438 ps
CPU time 16.91 seconds
Started Jun 06 01:07:26 PM PDT 24
Finished Jun 06 01:07:44 PM PDT 24
Peak memory 208608 kb
Host smart-1238364c-d739-4064-b02a-7dde20b616e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=345315408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.345315408
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.2686639667
Short name T251
Test name
Test status
Simulation time 20244602 ps
CPU time 0.68 seconds
Started Jun 06 01:07:38 PM PDT 24
Finished Jun 06 01:07:40 PM PDT 24
Peak memory 196792 kb
Host smart-aedad1d7-40ff-4bf3-a635-c3adfcb3e897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686639667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2686639667
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.948621839
Short name T64
Test name
Test status
Simulation time 6058911656 ps
CPU time 702.81 seconds
Started Jun 06 01:07:36 PM PDT 24
Finished Jun 06 01:19:20 PM PDT 24
Peak memory 743524 kb
Host smart-9edad6c3-6aa2-43ad-8b73-56f5ff8c4261
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=948621839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.948621839
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1214383613
Short name T293
Test name
Test status
Simulation time 79874024836 ps
CPU time 81.2 seconds
Started Jun 06 01:07:37 PM PDT 24
Finished Jun 06 01:08:59 PM PDT 24
Peak memory 200376 kb
Host smart-677df29f-d0da-42fb-a7ef-2c325caccb03
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214383613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1214383613
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.4164894287
Short name T269
Test name
Test status
Simulation time 2039348640 ps
CPU time 110.63 seconds
Started Jun 06 01:07:58 PM PDT 24
Finished Jun 06 01:09:49 PM PDT 24
Peak memory 200368 kb
Host smart-134d292f-43f2-427e-b0d8-537da955e551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164894287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.4164894287
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3593764045
Short name T404
Test name
Test status
Simulation time 25090673 ps
CPU time 1.21 seconds
Started Jun 06 01:07:23 PM PDT 24
Finished Jun 06 01:07:26 PM PDT 24
Peak memory 200348 kb
Host smart-b3ab00a1-4b35-4be9-8302-90f62f3d1904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593764045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3593764045
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.513462606
Short name T603
Test name
Test status
Simulation time 164808983795 ps
CPU time 1330.22 seconds
Started Jun 06 01:07:38 PM PDT 24
Finished Jun 06 01:29:49 PM PDT 24
Peak memory 719336 kb
Host smart-a29eedf0-c8a9-4881-822e-2dd49df850df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513462606 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.513462606
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.3469833667
Short name T547
Test name
Test status
Simulation time 108630352 ps
CPU time 1.17 seconds
Started Jun 06 01:07:37 PM PDT 24
Finished Jun 06 01:07:40 PM PDT 24
Peak memory 200412 kb
Host smart-7cc4e9d0-6755-4e53-8c14-b0ee195c6b19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469833667 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.3469833667
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.80877525
Short name T37
Test name
Test status
Simulation time 32326615961 ps
CPU time 462.07 seconds
Started Jun 06 01:07:37 PM PDT 24
Finished Jun 06 01:15:20 PM PDT 24
Peak memory 200432 kb
Host smart-caaaa9a5-d7a6-4ca1-96da-495db30f1d66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80877525 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.80877525
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.464850903
Short name T596
Test name
Test status
Simulation time 7700815194 ps
CPU time 53.75 seconds
Started Jun 06 01:07:37 PM PDT 24
Finished Jun 06 01:08:32 PM PDT 24
Peak memory 200416 kb
Host smart-b253dad4-c595-4c82-b3ee-c9fb15dcff2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464850903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.464850903
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.416268636
Short name T456
Test name
Test status
Simulation time 14542139 ps
CPU time 0.6 seconds
Started Jun 06 01:07:36 PM PDT 24
Finished Jun 06 01:07:38 PM PDT 24
Peak memory 196904 kb
Host smart-4b1d3be2-f38b-4cd5-95e7-6bede99e9f2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416268636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.416268636
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.1995896328
Short name T432
Test name
Test status
Simulation time 990880137 ps
CPU time 32.19 seconds
Started Jun 06 01:07:37 PM PDT 24
Finished Jun 06 01:08:10 PM PDT 24
Peak memory 232252 kb
Host smart-2bdf1cf9-b3c1-47d2-b8fe-e744375e8339
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1995896328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1995896328
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.2584256561
Short name T486
Test name
Test status
Simulation time 3363257817 ps
CPU time 10 seconds
Started Jun 06 01:07:38 PM PDT 24
Finished Jun 06 01:07:50 PM PDT 24
Peak memory 200444 kb
Host smart-e2ba71a9-29f5-478e-aa88-72915ce3a9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584256561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.2584256561
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3821041491
Short name T140
Test name
Test status
Simulation time 9832708266 ps
CPU time 576.49 seconds
Started Jun 06 01:07:37 PM PDT 24
Finished Jun 06 01:17:15 PM PDT 24
Peak memory 696012 kb
Host smart-b4e5d017-3916-42f1-baac-e5ebed6c539b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3821041491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3821041491
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.440297652
Short name T565
Test name
Test status
Simulation time 6587151034 ps
CPU time 122.28 seconds
Started Jun 06 01:07:40 PM PDT 24
Finished Jun 06 01:09:43 PM PDT 24
Peak memory 200464 kb
Host smart-e7cf2fce-b50f-4d10-a466-1d3b8ea3c9da
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440297652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.440297652
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1367979762
Short name T541
Test name
Test status
Simulation time 24199224115 ps
CPU time 127.74 seconds
Started Jun 06 01:07:39 PM PDT 24
Finished Jun 06 01:09:48 PM PDT 24
Peak memory 200416 kb
Host smart-c53987f7-22f1-4def-85b1-01c098651919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367979762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1367979762
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2757996677
Short name T279
Test name
Test status
Simulation time 219479505 ps
CPU time 3.67 seconds
Started Jun 06 01:07:39 PM PDT 24
Finished Jun 06 01:07:44 PM PDT 24
Peak memory 200332 kb
Host smart-359000b4-9da4-4138-87d0-eff56fda78d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757996677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2757996677
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3333116521
Short name T182
Test name
Test status
Simulation time 27526911656 ps
CPU time 1081.93 seconds
Started Jun 06 01:07:39 PM PDT 24
Finished Jun 06 01:25:42 PM PDT 24
Peak memory 688396 kb
Host smart-bb4bf5c0-815d-4317-8564-e512f0894963
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333116521 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3333116521
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.3950641721
Short name T175
Test name
Test status
Simulation time 99588148 ps
CPU time 1.1 seconds
Started Jun 06 01:07:38 PM PDT 24
Finished Jun 06 01:07:40 PM PDT 24
Peak memory 200244 kb
Host smart-1f0e15c4-cf3e-47cf-b4ac-fb4070336658
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950641721 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.3950641721
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.1727244157
Short name T478
Test name
Test status
Simulation time 99661679261 ps
CPU time 504.98 seconds
Started Jun 06 01:07:38 PM PDT 24
Finished Jun 06 01:16:04 PM PDT 24
Peak memory 200436 kb
Host smart-43b77272-6879-4079-bfa0-ac6970281e0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727244157 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.1727244157
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.901597336
Short name T360
Test name
Test status
Simulation time 905339729 ps
CPU time 4.74 seconds
Started Jun 06 01:07:38 PM PDT 24
Finished Jun 06 01:07:44 PM PDT 24
Peak memory 200368 kb
Host smart-8a107b1e-ce7b-4d95-bfc7-ccbb051e4fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901597336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.901597336
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1301931056
Short name T502
Test name
Test status
Simulation time 12236480 ps
CPU time 0.57 seconds
Started Jun 06 01:07:40 PM PDT 24
Finished Jun 06 01:07:42 PM PDT 24
Peak memory 196160 kb
Host smart-3ee9c258-51f1-4726-b0e8-f1d6a00ddaef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301931056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1301931056
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.784925570
Short name T581
Test name
Test status
Simulation time 1607481598 ps
CPU time 22.4 seconds
Started Jun 06 01:07:39 PM PDT 24
Finished Jun 06 01:08:03 PM PDT 24
Peak memory 200416 kb
Host smart-0a015aec-8881-480c-9aed-a47f70448974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784925570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.784925570
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.91908565
Short name T519
Test name
Test status
Simulation time 8599782640 ps
CPU time 511.48 seconds
Started Jun 06 01:07:39 PM PDT 24
Finished Jun 06 01:16:12 PM PDT 24
Peak memory 697332 kb
Host smart-4136be66-444a-44fb-9ac1-6cf8c7e4be0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=91908565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.91908565
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.2370819429
Short name T429
Test name
Test status
Simulation time 2462880254 ps
CPU time 135.38 seconds
Started Jun 06 01:07:39 PM PDT 24
Finished Jun 06 01:09:56 PM PDT 24
Peak memory 200360 kb
Host smart-fbe01c1f-ffde-4394-aa4c-9d5738a6ce7e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370819429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.2370819429
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.259432315
Short name T323
Test name
Test status
Simulation time 556380676 ps
CPU time 12.13 seconds
Started Jun 06 01:07:39 PM PDT 24
Finished Jun 06 01:07:53 PM PDT 24
Peak memory 200404 kb
Host smart-dc2972a3-5fdf-4dc2-8966-1427bc3dcf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259432315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.259432315
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.4162619543
Short name T35
Test name
Test status
Simulation time 1502279874 ps
CPU time 11.31 seconds
Started Jun 06 01:07:37 PM PDT 24
Finished Jun 06 01:07:49 PM PDT 24
Peak memory 200476 kb
Host smart-903fbfbb-a24c-4990-b919-db8da2af54b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162619543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.4162619543
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.2124548243
Short name T495
Test name
Test status
Simulation time 67498128439 ps
CPU time 1368.65 seconds
Started Jun 06 01:07:37 PM PDT 24
Finished Jun 06 01:30:26 PM PDT 24
Peak memory 697644 kb
Host smart-62bc0ca1-e343-4d6a-bdde-3181a66561e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124548243 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2124548243
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.1947068409
Short name T363
Test name
Test status
Simulation time 103724384 ps
CPU time 1.11 seconds
Started Jun 06 01:07:39 PM PDT 24
Finished Jun 06 01:07:41 PM PDT 24
Peak memory 200032 kb
Host smart-a6bcfc90-5e07-498f-a307-fc2a72abb780
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947068409 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.1947068409
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.1853178787
Short name T503
Test name
Test status
Simulation time 32488387031 ps
CPU time 384.22 seconds
Started Jun 06 01:07:37 PM PDT 24
Finished Jun 06 01:14:03 PM PDT 24
Peak memory 200352 kb
Host smart-19b5d462-dd96-4d8d-87c8-5fdbe85eb27b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853178787 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.1853178787
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3280566146
Short name T485
Test name
Test status
Simulation time 15453690017 ps
CPU time 89.55 seconds
Started Jun 06 01:07:37 PM PDT 24
Finished Jun 06 01:09:08 PM PDT 24
Peak memory 200440 kb
Host smart-96f911a0-61d9-4520-8e7d-03835cbbe3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280566146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3280566146
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.1667120491
Short name T528
Test name
Test status
Simulation time 34727053 ps
CPU time 0.59 seconds
Started Jun 06 01:05:59 PM PDT 24
Finished Jun 06 01:06:01 PM PDT 24
Peak memory 196972 kb
Host smart-e5e2f111-84f8-4477-a26c-7735b269eaf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667120491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1667120491
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3661538446
Short name T585
Test name
Test status
Simulation time 4538562881 ps
CPU time 62.99 seconds
Started Jun 06 01:06:08 PM PDT 24
Finished Jun 06 01:07:12 PM PDT 24
Peak memory 249260 kb
Host smart-be63091e-3151-43ff-a079-38b08e6ae223
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3661538446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3661538446
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.1314599291
Short name T385
Test name
Test status
Simulation time 10133227683 ps
CPU time 42.07 seconds
Started Jun 06 01:05:58 PM PDT 24
Finished Jun 06 01:06:41 PM PDT 24
Peak memory 200412 kb
Host smart-76ea6230-1e0d-4f8d-bf79-5b4fc04d363f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314599291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.1314599291
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2481868049
Short name T102
Test name
Test status
Simulation time 7286242628 ps
CPU time 394.86 seconds
Started Jun 06 01:06:06 PM PDT 24
Finished Jun 06 01:12:42 PM PDT 24
Peak memory 680492 kb
Host smart-7eaa5b7a-d4d0-4d6b-ba87-ce1ce570f162
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2481868049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2481868049
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.3569547765
Short name T552
Test name
Test status
Simulation time 4073002675 ps
CPU time 164.23 seconds
Started Jun 06 01:06:04 PM PDT 24
Finished Jun 06 01:08:50 PM PDT 24
Peak memory 200444 kb
Host smart-6bb8e069-b8a8-4f7d-8146-40e6462905f1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569547765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3569547765
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3920219393
Short name T215
Test name
Test status
Simulation time 31629831023 ps
CPU time 124.32 seconds
Started Jun 06 01:06:08 PM PDT 24
Finished Jun 06 01:08:13 PM PDT 24
Peak memory 200524 kb
Host smart-8a5396aa-5f3a-49d3-bb0b-b719178a84a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920219393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3920219393
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.4101168007
Short name T29
Test name
Test status
Simulation time 325901046 ps
CPU time 0.89 seconds
Started Jun 06 01:05:59 PM PDT 24
Finished Jun 06 01:06:01 PM PDT 24
Peak memory 218700 kb
Host smart-a6989a76-38c7-47a3-a6d2-62a10a584714
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101168007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.4101168007
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1085415195
Short name T199
Test name
Test status
Simulation time 306183430 ps
CPU time 4.49 seconds
Started Jun 06 01:06:06 PM PDT 24
Finished Jun 06 01:06:11 PM PDT 24
Peak memory 200364 kb
Host smart-d15748cf-f30d-4c24-87a0-723bfb637502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085415195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1085415195
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.4197115620
Short name T245
Test name
Test status
Simulation time 73170375503 ps
CPU time 3039.43 seconds
Started Jun 06 01:05:59 PM PDT 24
Finished Jun 06 01:56:39 PM PDT 24
Peak memory 770300 kb
Host smart-aa664cf3-9454-4e72-b394-edd4f7431a9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197115620 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.4197115620
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.208310739
Short name T460
Test name
Test status
Simulation time 32414372 ps
CPU time 1.3 seconds
Started Jun 06 01:05:58 PM PDT 24
Finished Jun 06 01:06:01 PM PDT 24
Peak memory 200340 kb
Host smart-15453ece-e2b6-4578-9ce0-dd20fe50efc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208310739 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_hmac_vectors.208310739
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.1983580684
Short name T435
Test name
Test status
Simulation time 24109290104 ps
CPU time 498.37 seconds
Started Jun 06 01:06:09 PM PDT 24
Finished Jun 06 01:14:28 PM PDT 24
Peak memory 200364 kb
Host smart-faff28e8-2f99-44ed-96b6-3cd7e6038dad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983580684 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.1983580684
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.3126044317
Short name T300
Test name
Test status
Simulation time 563411802 ps
CPU time 6.27 seconds
Started Jun 06 01:05:58 PM PDT 24
Finished Jun 06 01:06:05 PM PDT 24
Peak memory 200324 kb
Host smart-cf57ed78-421c-4447-97d5-2381d64d17cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126044317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3126044317
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.1608185786
Short name T255
Test name
Test status
Simulation time 18263451 ps
CPU time 0.63 seconds
Started Jun 06 01:07:49 PM PDT 24
Finished Jun 06 01:07:50 PM PDT 24
Peak memory 196144 kb
Host smart-2927bf16-0df9-4bec-bc8f-57d2ff4f1174
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608185786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1608185786
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.4286254664
Short name T420
Test name
Test status
Simulation time 4696406932 ps
CPU time 34.98 seconds
Started Jun 06 01:07:39 PM PDT 24
Finished Jun 06 01:08:15 PM PDT 24
Peak memory 200452 kb
Host smart-d7f48d15-3c8d-4a79-8088-a901cd44b81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286254664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.4286254664
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1700031617
Short name T243
Test name
Test status
Simulation time 1279575264 ps
CPU time 86.34 seconds
Started Jun 06 01:07:38 PM PDT 24
Finished Jun 06 01:09:05 PM PDT 24
Peak memory 446120 kb
Host smart-5d5fdbdd-5eed-43e9-9d36-87235af78fc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1700031617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1700031617
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.4111167430
Short name T153
Test name
Test status
Simulation time 4772632257 ps
CPU time 82.05 seconds
Started Jun 06 01:07:39 PM PDT 24
Finished Jun 06 01:09:02 PM PDT 24
Peak memory 200360 kb
Host smart-06d66c6d-be50-4188-b8ee-a3afc84bb246
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111167430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.4111167430
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.4238311955
Short name T203
Test name
Test status
Simulation time 177582853 ps
CPU time 2.99 seconds
Started Jun 06 01:07:38 PM PDT 24
Finished Jun 06 01:07:43 PM PDT 24
Peak memory 200376 kb
Host smart-6609ddb2-9c92-4578-9bb4-97a9f89e1377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238311955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.4238311955
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.572743125
Short name T290
Test name
Test status
Simulation time 158995341 ps
CPU time 5.22 seconds
Started Jun 06 01:07:35 PM PDT 24
Finished Jun 06 01:07:41 PM PDT 24
Peak memory 200392 kb
Host smart-546b031b-a0c0-422c-9a6b-e16f720ac94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572743125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.572743125
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.2835155020
Short name T205
Test name
Test status
Simulation time 60028121 ps
CPU time 1.21 seconds
Started Jun 06 01:07:47 PM PDT 24
Finished Jun 06 01:07:50 PM PDT 24
Peak memory 199232 kb
Host smart-85ce0963-b2ec-4c50-a457-fad7a8c65f54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835155020 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.2835155020
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.1764894071
Short name T188
Test name
Test status
Simulation time 40865858994 ps
CPU time 513.39 seconds
Started Jun 06 01:07:47 PM PDT 24
Finished Jun 06 01:16:22 PM PDT 24
Peak memory 200356 kb
Host smart-ae254764-67f8-443b-b33e-6aa4212d9025
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764894071 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.1764894071
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.4007799637
Short name T430
Test name
Test status
Simulation time 1416847710 ps
CPU time 65.44 seconds
Started Jun 06 01:07:45 PM PDT 24
Finished Jun 06 01:08:53 PM PDT 24
Peak memory 200420 kb
Host smart-edf77f1f-e106-4528-ad6e-79f4fe02da38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007799637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.4007799637
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.69511682
Short name T593
Test name
Test status
Simulation time 43093349 ps
CPU time 0.58 seconds
Started Jun 06 01:07:51 PM PDT 24
Finished Jun 06 01:07:53 PM PDT 24
Peak memory 195656 kb
Host smart-5b04c5e4-d035-4540-9fe8-d05f6c97fb01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69511682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.69511682
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1710523673
Short name T161
Test name
Test status
Simulation time 1395536166 ps
CPU time 13.53 seconds
Started Jun 06 01:07:45 PM PDT 24
Finished Jun 06 01:08:01 PM PDT 24
Peak memory 212056 kb
Host smart-9ea5c02c-dfb0-444a-948b-4a48371f584a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1710523673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1710523673
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3298173332
Short name T150
Test name
Test status
Simulation time 3642521622 ps
CPU time 47.48 seconds
Started Jun 06 01:07:50 PM PDT 24
Finished Jun 06 01:08:39 PM PDT 24
Peak memory 200512 kb
Host smart-73ead443-cdbd-4774-aaea-5245b05f3e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298173332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3298173332
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.3728983141
Short name T235
Test name
Test status
Simulation time 8346335215 ps
CPU time 349.05 seconds
Started Jun 06 01:07:49 PM PDT 24
Finished Jun 06 01:13:40 PM PDT 24
Peak memory 633576 kb
Host smart-893715af-30c7-4b9d-a0e9-c5f86470b7d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3728983141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.3728983141
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2244200935
Short name T554
Test name
Test status
Simulation time 3589698448 ps
CPU time 189.05 seconds
Started Jun 06 01:07:44 PM PDT 24
Finished Jun 06 01:10:54 PM PDT 24
Peak memory 200412 kb
Host smart-32059b7f-5896-4c97-ae96-a44255d064de
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244200935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2244200935
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.732377751
Short name T338
Test name
Test status
Simulation time 12508887549 ps
CPU time 106.8 seconds
Started Jun 06 01:07:46 PM PDT 24
Finished Jun 06 01:09:35 PM PDT 24
Peak memory 200432 kb
Host smart-9b072312-9e6e-4404-873a-ced823b3d1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732377751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.732377751
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.163909391
Short name T591
Test name
Test status
Simulation time 2223248439 ps
CPU time 10.51 seconds
Started Jun 06 01:07:44 PM PDT 24
Finished Jun 06 01:07:57 PM PDT 24
Peak memory 200472 kb
Host smart-9b59e067-efcd-4204-9193-84cd241e1030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163909391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.163909391
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.35258432
Short name T109
Test name
Test status
Simulation time 396071028175 ps
CPU time 3505.03 seconds
Started Jun 06 01:07:44 PM PDT 24
Finished Jun 06 02:06:11 PM PDT 24
Peak memory 813464 kb
Host smart-852f773c-7719-41a0-8227-d9832a68e959
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35258432 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.35258432
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.734657660
Short name T491
Test name
Test status
Simulation time 32830120 ps
CPU time 1.3 seconds
Started Jun 06 01:07:44 PM PDT 24
Finished Jun 06 01:07:47 PM PDT 24
Peak memory 200292 kb
Host smart-e7c0087f-ee14-4813-8b36-44c6079056ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734657660 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.hmac_test_hmac_vectors.734657660
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.2276312760
Short name T537
Test name
Test status
Simulation time 46198378007 ps
CPU time 589.63 seconds
Started Jun 06 01:07:45 PM PDT 24
Finished Jun 06 01:17:37 PM PDT 24
Peak memory 200384 kb
Host smart-eae515c3-4c2c-4ef0-9fda-7da90842cdd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276312760 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.2276312760
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3785267239
Short name T345
Test name
Test status
Simulation time 1039999754 ps
CPU time 10.93 seconds
Started Jun 06 01:07:45 PM PDT 24
Finished Jun 06 01:07:59 PM PDT 24
Peak memory 200448 kb
Host smart-c95df22a-88f1-4062-8e58-91310ac64b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785267239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3785267239
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.773242007
Short name T249
Test name
Test status
Simulation time 17556069 ps
CPU time 0.65 seconds
Started Jun 06 01:07:50 PM PDT 24
Finished Jun 06 01:07:52 PM PDT 24
Peak memory 196868 kb
Host smart-5c1569fc-96dd-410a-8477-c4fdea3c834f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773242007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.773242007
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1007761295
Short name T457
Test name
Test status
Simulation time 3707581820 ps
CPU time 59.45 seconds
Started Jun 06 01:07:46 PM PDT 24
Finished Jun 06 01:08:47 PM PDT 24
Peak memory 232948 kb
Host smart-1b5c9f03-b53c-414b-876b-c1f40b567ce7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1007761295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1007761295
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.561965748
Short name T74
Test name
Test status
Simulation time 41247320459 ps
CPU time 37.65 seconds
Started Jun 06 01:07:49 PM PDT 24
Finished Jun 06 01:08:27 PM PDT 24
Peak memory 200424 kb
Host smart-3ea36aa9-5b2f-4179-8430-2169c5255e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561965748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.561965748
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1571548951
Short name T308
Test name
Test status
Simulation time 12766628562 ps
CPU time 814 seconds
Started Jun 06 01:07:50 PM PDT 24
Finished Jun 06 01:21:25 PM PDT 24
Peak memory 763916 kb
Host smart-6cf9dc08-e0d5-4164-a948-5da41f0322e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1571548951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1571548951
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.976590712
Short name T458
Test name
Test status
Simulation time 9674508455 ps
CPU time 36 seconds
Started Jun 06 01:07:50 PM PDT 24
Finished Jun 06 01:08:28 PM PDT 24
Peak memory 200432 kb
Host smart-682f5b3a-995c-448b-9a09-3336ff0b13d0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976590712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.976590712
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.4181395312
Short name T477
Test name
Test status
Simulation time 14993464309 ps
CPU time 120.08 seconds
Started Jun 06 01:07:45 PM PDT 24
Finished Jun 06 01:09:47 PM PDT 24
Peak memory 200436 kb
Host smart-62b8ae60-af03-4d34-a4f5-a81a64f0ab7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181395312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.4181395312
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.2726790773
Short name T305
Test name
Test status
Simulation time 417104543 ps
CPU time 6.08 seconds
Started Jun 06 01:07:51 PM PDT 24
Finished Jun 06 01:07:59 PM PDT 24
Peak memory 200292 kb
Host smart-580c090a-d534-4e82-b97a-3b3f0155e87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726790773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2726790773
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2561027514
Short name T450
Test name
Test status
Simulation time 2763927614 ps
CPU time 28.47 seconds
Started Jun 06 01:07:47 PM PDT 24
Finished Jun 06 01:08:17 PM PDT 24
Peak memory 200508 kb
Host smart-6886bf7f-7438-431c-8054-326c983d8a3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561027514 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2561027514
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.1377041859
Short name T189
Test name
Test status
Simulation time 29936430 ps
CPU time 1.1 seconds
Started Jun 06 01:07:45 PM PDT 24
Finished Jun 06 01:07:48 PM PDT 24
Peak memory 200364 kb
Host smart-ea57dbd4-e495-4ea5-bb90-7e05df4bef2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377041859 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.1377041859
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.1745273864
Short name T440
Test name
Test status
Simulation time 40568826307 ps
CPU time 535.93 seconds
Started Jun 06 01:07:45 PM PDT 24
Finished Jun 06 01:16:43 PM PDT 24
Peak memory 200720 kb
Host smart-6cc8efab-8471-44a6-a513-8fa5766df109
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745273864 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.1745273864
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.459865864
Short name T560
Test name
Test status
Simulation time 811472511 ps
CPU time 33.25 seconds
Started Jun 06 01:07:49 PM PDT 24
Finished Jun 06 01:08:24 PM PDT 24
Peak memory 200364 kb
Host smart-1f4628ea-9bfe-4a7d-8912-9ab4b77d1de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459865864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.459865864
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.684095522
Short name T21
Test name
Test status
Simulation time 15748550 ps
CPU time 0.64 seconds
Started Jun 06 01:07:53 PM PDT 24
Finished Jun 06 01:07:55 PM PDT 24
Peak memory 196176 kb
Host smart-1f88ac3b-d82c-4b74-8cad-9f6e2152d2bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684095522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.684095522
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.586963108
Short name T60
Test name
Test status
Simulation time 3925994088 ps
CPU time 53.03 seconds
Started Jun 06 01:07:43 PM PDT 24
Finished Jun 06 01:08:37 PM PDT 24
Peak memory 235260 kb
Host smart-97a696bf-d236-47d4-92a0-e0bed113f878
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=586963108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.586963108
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2770489014
Short name T239
Test name
Test status
Simulation time 35086793328 ps
CPU time 54.65 seconds
Started Jun 06 01:07:55 PM PDT 24
Finished Jun 06 01:08:51 PM PDT 24
Peak memory 200388 kb
Host smart-97543c82-34ef-4184-921b-69893749f209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770489014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2770489014
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.182914820
Short name T399
Test name
Test status
Simulation time 18000158850 ps
CPU time 1038.53 seconds
Started Jun 06 01:07:54 PM PDT 24
Finished Jun 06 01:25:14 PM PDT 24
Peak memory 738396 kb
Host smart-1315c0ca-b767-4603-a01f-13ee41a27d81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=182914820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.182914820
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.2115112620
Short name T135
Test name
Test status
Simulation time 125863269 ps
CPU time 7.31 seconds
Started Jun 06 01:07:53 PM PDT 24
Finished Jun 06 01:08:01 PM PDT 24
Peak memory 200140 kb
Host smart-77387313-dfb6-4fce-8edb-c8e26fdf0217
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115112620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.2115112620
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3396171566
Short name T319
Test name
Test status
Simulation time 51607078 ps
CPU time 0.87 seconds
Started Jun 06 01:07:44 PM PDT 24
Finished Jun 06 01:07:47 PM PDT 24
Peak memory 199156 kb
Host smart-56c0d12f-c15b-4308-89cd-71295bbe63e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396171566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3396171566
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2827321310
Short name T358
Test name
Test status
Simulation time 148353016 ps
CPU time 2.65 seconds
Started Jun 06 01:07:51 PM PDT 24
Finished Jun 06 01:07:55 PM PDT 24
Peak memory 200336 kb
Host smart-60ffeb30-951b-4215-9adf-5db16c27ef07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827321310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2827321310
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.2031947379
Short name T68
Test name
Test status
Simulation time 161681234617 ps
CPU time 4073.59 seconds
Started Jun 06 01:07:55 PM PDT 24
Finished Jun 06 02:15:50 PM PDT 24
Peak memory 846992 kb
Host smart-baf574b3-5dc0-4bd1-825e-5fc5c9045b7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031947379 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2031947379
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_stress_all_with_rand_reset.525607920
Short name T24
Test name
Test status
Simulation time 80916544446 ps
CPU time 2870.84 seconds
Started Jun 06 01:07:54 PM PDT 24
Finished Jun 06 01:55:47 PM PDT 24
Peak memory 835428 kb
Host smart-939289ec-beef-4886-878c-d6f829232f56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=525607920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all_with_rand_reset.525607920
Directory /workspace/43.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.2471756019
Short name T376
Test name
Test status
Simulation time 63914156 ps
CPU time 1.42 seconds
Started Jun 06 01:08:06 PM PDT 24
Finished Jun 06 01:08:08 PM PDT 24
Peak memory 200448 kb
Host smart-5c1e17b9-2df1-4862-b459-a2fcf8a6a172
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471756019 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.2471756019
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.605732671
Short name T185
Test name
Test status
Simulation time 94821334294 ps
CPU time 470.02 seconds
Started Jun 06 01:07:54 PM PDT 24
Finished Jun 06 01:15:45 PM PDT 24
Peak memory 200340 kb
Host smart-d9dfdd94-ddc9-4649-8d49-9180993128eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605732671 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.605732671
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.121124327
Short name T34
Test name
Test status
Simulation time 21676607401 ps
CPU time 66.36 seconds
Started Jun 06 01:07:55 PM PDT 24
Finished Jun 06 01:09:03 PM PDT 24
Peak memory 200368 kb
Host smart-0dbce4d1-9096-4b0a-8db3-8a8cbc3935e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121124327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.121124327
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3108910984
Short name T347
Test name
Test status
Simulation time 13249460 ps
CPU time 0.6 seconds
Started Jun 06 01:07:55 PM PDT 24
Finished Jun 06 01:07:57 PM PDT 24
Peak memory 196908 kb
Host smart-a1e31c17-cd36-473f-80b8-85992dc78f9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108910984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3108910984
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.1429742594
Short name T575
Test name
Test status
Simulation time 1398686611 ps
CPU time 39.61 seconds
Started Jun 06 01:07:55 PM PDT 24
Finished Jun 06 01:08:36 PM PDT 24
Peak memory 233100 kb
Host smart-657bc9a2-0ed4-4d34-8b23-07f36a3a9b54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1429742594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.1429742594
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1325280477
Short name T426
Test name
Test status
Simulation time 2546702292 ps
CPU time 11.42 seconds
Started Jun 06 01:07:54 PM PDT 24
Finished Jun 06 01:08:07 PM PDT 24
Peak memory 200432 kb
Host smart-a3066b49-aa32-4602-9aee-b22c38d73f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325280477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1325280477
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.332723814
Short name T313
Test name
Test status
Simulation time 12285193530 ps
CPU time 741.76 seconds
Started Jun 06 01:07:55 PM PDT 24
Finished Jun 06 01:20:18 PM PDT 24
Peak memory 714636 kb
Host smart-84d4ac44-cc88-480b-8ef7-e61363ed8b8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=332723814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.332723814
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3794826404
Short name T304
Test name
Test status
Simulation time 591854353 ps
CPU time 6.34 seconds
Started Jun 06 01:07:55 PM PDT 24
Finished Jun 06 01:08:02 PM PDT 24
Peak memory 200264 kb
Host smart-6b360901-c003-47e7-818d-e345f7cc8f75
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794826404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3794826404
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.4069688405
Short name T83
Test name
Test status
Simulation time 7678456838 ps
CPU time 56.65 seconds
Started Jun 06 01:07:54 PM PDT 24
Finished Jun 06 01:08:52 PM PDT 24
Peak memory 200536 kb
Host smart-32190031-7c13-4df0-9a0f-cac0487d12f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069688405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.4069688405
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3718681927
Short name T476
Test name
Test status
Simulation time 383735345 ps
CPU time 2.23 seconds
Started Jun 06 01:07:56 PM PDT 24
Finished Jun 06 01:07:59 PM PDT 24
Peak memory 200372 kb
Host smart-3125aaff-ae6e-489b-8c5b-69f42a1fbfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718681927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3718681927
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2769333675
Short name T577
Test name
Test status
Simulation time 103729505 ps
CPU time 0.66 seconds
Started Jun 06 01:07:55 PM PDT 24
Finished Jun 06 01:07:57 PM PDT 24
Peak memory 195920 kb
Host smart-1067d73f-a381-41be-b128-e95fe2cf59b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769333675 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2769333675
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.3584573297
Short name T312
Test name
Test status
Simulation time 64187143 ps
CPU time 1.41 seconds
Started Jun 06 01:07:55 PM PDT 24
Finished Jun 06 01:07:58 PM PDT 24
Peak memory 200340 kb
Host smart-9485d663-a156-4f61-8873-c41ecb23169d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584573297 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.3584573297
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.2896121735
Short name T500
Test name
Test status
Simulation time 139546005212 ps
CPU time 489.89 seconds
Started Jun 06 01:07:54 PM PDT 24
Finished Jun 06 01:16:06 PM PDT 24
Peak memory 200336 kb
Host smart-981a1268-0a33-4c20-9721-fb9f8307042b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896121735 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.2896121735
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1935038195
Short name T217
Test name
Test status
Simulation time 3057364807 ps
CPU time 58.93 seconds
Started Jun 06 01:07:59 PM PDT 24
Finished Jun 06 01:09:00 PM PDT 24
Peak memory 200428 kb
Host smart-43ee7a43-799a-4a38-842a-8051e614e12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935038195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1935038195
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.3941764933
Short name T298
Test name
Test status
Simulation time 15686025 ps
CPU time 0.59 seconds
Started Jun 06 01:08:15 PM PDT 24
Finished Jun 06 01:08:17 PM PDT 24
Peak memory 196464 kb
Host smart-94e2d120-e850-4603-9b60-069ffffff495
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941764933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3941764933
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1291521347
Short name T2
Test name
Test status
Simulation time 831454529 ps
CPU time 56.97 seconds
Started Jun 06 01:07:57 PM PDT 24
Finished Jun 06 01:08:55 PM PDT 24
Peak memory 233072 kb
Host smart-591a7105-aeec-4005-a3c5-61b25d21c0e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1291521347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1291521347
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2177567183
Short name T597
Test name
Test status
Simulation time 511654986 ps
CPU time 11.19 seconds
Started Jun 06 01:07:55 PM PDT 24
Finished Jun 06 01:08:08 PM PDT 24
Peak memory 200452 kb
Host smart-e55cc847-c3ef-44fe-9bb6-72c1faca9d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177567183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2177567183
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1364909755
Short name T232
Test name
Test status
Simulation time 13678121613 ps
CPU time 897.88 seconds
Started Jun 06 01:07:54 PM PDT 24
Finished Jun 06 01:22:54 PM PDT 24
Peak memory 782416 kb
Host smart-b881218f-4a99-488a-8dc3-fcd1fe5d32ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1364909755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1364909755
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.2202529447
Short name T346
Test name
Test status
Simulation time 3063462783 ps
CPU time 40.42 seconds
Started Jun 06 01:07:55 PM PDT 24
Finished Jun 06 01:08:37 PM PDT 24
Peak memory 200384 kb
Host smart-686597a9-ac86-4788-ab46-83dc82728215
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202529447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2202529447
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.2498677079
Short name T589
Test name
Test status
Simulation time 13703432929 ps
CPU time 72.26 seconds
Started Jun 06 01:07:56 PM PDT 24
Finished Jun 06 01:09:09 PM PDT 24
Peak memory 200424 kb
Host smart-1c5f9c97-3497-4c0f-ad80-235d24408fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498677079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.2498677079
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3364790673
Short name T599
Test name
Test status
Simulation time 519596902 ps
CPU time 4.54 seconds
Started Jun 06 01:07:54 PM PDT 24
Finished Jun 06 01:08:00 PM PDT 24
Peak memory 200372 kb
Host smart-5312e442-f1b1-4b59-9c17-f4a155bfc95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364790673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3364790673
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2962332227
Short name T320
Test name
Test status
Simulation time 3157422899 ps
CPU time 599.23 seconds
Started Jun 06 01:08:06 PM PDT 24
Finished Jun 06 01:18:06 PM PDT 24
Peak memory 711184 kb
Host smart-7da08395-a5c9-48d7-b521-b1cbf0dfd3e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962332227 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2962332227
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.3677641503
Short name T472
Test name
Test status
Simulation time 159514096 ps
CPU time 1.43 seconds
Started Jun 06 01:08:03 PM PDT 24
Finished Jun 06 01:08:05 PM PDT 24
Peak memory 200388 kb
Host smart-8f2a5d16-ab91-42d2-bdda-09d5ce8db450
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677641503 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.3677641503
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.48927024
Short name T424
Test name
Test status
Simulation time 25656163385 ps
CPU time 483.32 seconds
Started Jun 06 01:08:15 PM PDT 24
Finished Jun 06 01:16:20 PM PDT 24
Peak memory 200604 kb
Host smart-bcea88ab-9b2e-498b-9bdd-47457ced53d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48927024 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.48927024
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3645938922
Short name T355
Test name
Test status
Simulation time 22644774570 ps
CPU time 77.84 seconds
Started Jun 06 01:07:55 PM PDT 24
Finished Jun 06 01:09:14 PM PDT 24
Peak memory 200492 kb
Host smart-c331fbdf-a76e-4a93-a3ea-0482705410eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645938922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3645938922
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3817417829
Short name T366
Test name
Test status
Simulation time 32311400 ps
CPU time 0.56 seconds
Started Jun 06 01:08:05 PM PDT 24
Finished Jun 06 01:08:07 PM PDT 24
Peak memory 195160 kb
Host smart-ad06596a-36fe-4287-8998-a9f4aab7fc96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817417829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3817417829
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3244281036
Short name T44
Test name
Test status
Simulation time 1028621248 ps
CPU time 47.07 seconds
Started Jun 06 01:08:04 PM PDT 24
Finished Jun 06 01:08:52 PM PDT 24
Peak memory 225688 kb
Host smart-60d04023-a0ac-47fa-a02b-fc2e2693210e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3244281036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3244281036
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.919552769
Short name T408
Test name
Test status
Simulation time 4313932864 ps
CPU time 58.88 seconds
Started Jun 06 01:08:04 PM PDT 24
Finished Jun 06 01:09:04 PM PDT 24
Peak memory 200536 kb
Host smart-45187134-fe4b-4a6e-a06d-470238cf9ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919552769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.919552769
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2311444927
Short name T134
Test name
Test status
Simulation time 26482091649 ps
CPU time 312.89 seconds
Started Jun 06 01:08:05 PM PDT 24
Finished Jun 06 01:13:19 PM PDT 24
Peak memory 500088 kb
Host smart-984a1a1a-86ec-4215-874c-630fa6d64c9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2311444927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2311444927
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.1715427679
Short name T38
Test name
Test status
Simulation time 10030780517 ps
CPU time 86.92 seconds
Started Jun 06 01:08:15 PM PDT 24
Finished Jun 06 01:09:44 PM PDT 24
Peak memory 200688 kb
Host smart-04847773-ee2a-47fa-b9b6-618a7c0c1500
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715427679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1715427679
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.2135302383
Short name T324
Test name
Test status
Simulation time 796806485 ps
CPU time 51.42 seconds
Started Jun 06 01:08:06 PM PDT 24
Finished Jun 06 01:08:58 PM PDT 24
Peak memory 200392 kb
Host smart-edae053e-ccb2-45ee-a8e6-d23004ee28b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135302383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2135302383
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3649558801
Short name T234
Test name
Test status
Simulation time 54628545 ps
CPU time 0.98 seconds
Started Jun 06 01:08:05 PM PDT 24
Finished Jun 06 01:08:07 PM PDT 24
Peak memory 199912 kb
Host smart-0056c782-f41d-4e74-bde1-7c8f8597430d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649558801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3649558801
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2052499160
Short name T544
Test name
Test status
Simulation time 1465324909 ps
CPU time 76.85 seconds
Started Jun 06 01:08:05 PM PDT 24
Finished Jun 06 01:09:23 PM PDT 24
Peak memory 233188 kb
Host smart-bae33058-d084-4cc6-8516-a830c60d375f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052499160 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2052499160
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.1066276220
Short name T198
Test name
Test status
Simulation time 35180581 ps
CPU time 1.28 seconds
Started Jun 06 01:08:02 PM PDT 24
Finished Jun 06 01:08:04 PM PDT 24
Peak memory 200396 kb
Host smart-1620116c-f385-4932-9a67-00e410214487
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066276220 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.1066276220
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.1622938855
Short name T533
Test name
Test status
Simulation time 28282347065 ps
CPU time 481.6 seconds
Started Jun 06 01:08:05 PM PDT 24
Finished Jun 06 01:16:08 PM PDT 24
Peak memory 200388 kb
Host smart-a0a85576-1a85-4dee-8e99-b8699349a2f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622938855 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.1622938855
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1272974022
Short name T489
Test name
Test status
Simulation time 1202269653 ps
CPU time 42.03 seconds
Started Jun 06 01:08:04 PM PDT 24
Finished Jun 06 01:08:47 PM PDT 24
Peak memory 200416 kb
Host smart-86ac837f-0277-46db-8610-899b33312654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272974022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1272974022
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3571551265
Short name T20
Test name
Test status
Simulation time 25579250 ps
CPU time 0.58 seconds
Started Jun 06 01:08:13 PM PDT 24
Finished Jun 06 01:08:15 PM PDT 24
Peak memory 195880 kb
Host smart-9d0f9be2-2234-4019-aaaa-f7a0374f7eba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571551265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3571551265
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.4070622285
Short name T180
Test name
Test status
Simulation time 1441429259 ps
CPU time 36.05 seconds
Started Jun 06 01:08:04 PM PDT 24
Finished Jun 06 01:08:41 PM PDT 24
Peak memory 212592 kb
Host smart-4702cbd9-6d5f-4ba4-9011-266fa93621ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4070622285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.4070622285
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2475130738
Short name T306
Test name
Test status
Simulation time 6192356384 ps
CPU time 32.75 seconds
Started Jun 06 01:08:04 PM PDT 24
Finished Jun 06 01:08:39 PM PDT 24
Peak memory 200436 kb
Host smart-c74c1ff2-d846-4d2a-a32b-0771a329eeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475130738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2475130738
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.739138247
Short name T422
Test name
Test status
Simulation time 2356349969 ps
CPU time 463.4 seconds
Started Jun 06 01:07:59 PM PDT 24
Finished Jun 06 01:15:44 PM PDT 24
Peak memory 672936 kb
Host smart-52b8748f-3a53-48e6-84b2-d865355bc6b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=739138247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.739138247
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1673506423
Short name T230
Test name
Test status
Simulation time 7151061331 ps
CPU time 106.99 seconds
Started Jun 06 01:08:04 PM PDT 24
Finished Jun 06 01:09:53 PM PDT 24
Peak memory 200456 kb
Host smart-b81bef7c-6f0d-4449-b351-98f1de85f3ea
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673506423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1673506423
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3867587589
Short name T141
Test name
Test status
Simulation time 28419421597 ps
CPU time 88.03 seconds
Started Jun 06 01:08:04 PM PDT 24
Finished Jun 06 01:09:33 PM PDT 24
Peak memory 200468 kb
Host smart-3442bc98-ef6b-4b88-95fa-a4d9a53ac27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867587589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3867587589
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3772092212
Short name T231
Test name
Test status
Simulation time 299479985 ps
CPU time 3.11 seconds
Started Jun 06 01:08:03 PM PDT 24
Finished Jun 06 01:08:07 PM PDT 24
Peak memory 200396 kb
Host smart-761b3604-8674-4d1a-838a-c570b14944e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772092212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3772092212
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.77411239
Short name T138
Test name
Test status
Simulation time 30994831 ps
CPU time 1.05 seconds
Started Jun 06 01:08:05 PM PDT 24
Finished Jun 06 01:08:07 PM PDT 24
Peak memory 200080 kb
Host smart-f3ef036c-4e89-4a45-8c81-9c2f2692b027
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77411239 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 47.hmac_test_hmac_vectors.77411239
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.1036391935
Short name T580
Test name
Test status
Simulation time 120737185934 ps
CPU time 553.48 seconds
Started Jun 06 01:08:03 PM PDT 24
Finished Jun 06 01:17:18 PM PDT 24
Peak memory 200364 kb
Host smart-db82ef04-d07b-4de2-a930-1ad9764fde16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036391935 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.1036391935
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.306406475
Short name T26
Test name
Test status
Simulation time 3169637030 ps
CPU time 35.05 seconds
Started Jun 06 01:08:03 PM PDT 24
Finished Jun 06 01:08:39 PM PDT 24
Peak memory 200436 kb
Host smart-39691d6c-6de4-41e5-93c0-60336caef6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306406475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.306406475
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3270030564
Short name T329
Test name
Test status
Simulation time 58566225 ps
CPU time 0.61 seconds
Started Jun 06 01:08:13 PM PDT 24
Finished Jun 06 01:08:15 PM PDT 24
Peak memory 196856 kb
Host smart-23900d5d-72b3-40e2-9054-64338d9237d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270030564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3270030564
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.3367974301
Short name T221
Test name
Test status
Simulation time 1462024705 ps
CPU time 21.32 seconds
Started Jun 06 01:08:12 PM PDT 24
Finished Jun 06 01:08:35 PM PDT 24
Peak memory 225104 kb
Host smart-7b729c67-6d9f-43a5-a37b-1df64c6d609d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3367974301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3367974301
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.107470233
Short name T168
Test name
Test status
Simulation time 799212989 ps
CPU time 40.88 seconds
Started Jun 06 01:08:16 PM PDT 24
Finished Jun 06 01:08:59 PM PDT 24
Peak memory 200332 kb
Host smart-d4a4d50d-5600-46f9-8d8c-9d4993904c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107470233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.107470233
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2497681111
Short name T206
Test name
Test status
Simulation time 891875558 ps
CPU time 265.06 seconds
Started Jun 06 01:08:13 PM PDT 24
Finished Jun 06 01:12:39 PM PDT 24
Peak memory 665460 kb
Host smart-a17c41cb-a6cd-4c1f-a1e5-b1380ea22c87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2497681111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2497681111
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1682597764
Short name T531
Test name
Test status
Simulation time 710920769 ps
CPU time 40.94 seconds
Started Jun 06 01:08:24 PM PDT 24
Finished Jun 06 01:09:07 PM PDT 24
Peak memory 200564 kb
Host smart-c04510a9-b68a-47c7-8bd6-4f6b4b9447dc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682597764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1682597764
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2808011124
Short name T238
Test name
Test status
Simulation time 2047567900 ps
CPU time 33.82 seconds
Started Jun 06 01:08:11 PM PDT 24
Finished Jun 06 01:08:46 PM PDT 24
Peak memory 200344 kb
Host smart-487b7795-53b6-4e6a-839d-8c332339c468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808011124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2808011124
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.452823518
Short name T164
Test name
Test status
Simulation time 1722672218 ps
CPU time 8.74 seconds
Started Jun 06 01:08:11 PM PDT 24
Finished Jun 06 01:08:21 PM PDT 24
Peak memory 200348 kb
Host smart-0c1c3ff8-faba-47d4-8ace-e96a7480d74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452823518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.452823518
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.1454020272
Short name T465
Test name
Test status
Simulation time 236016675 ps
CPU time 1.07 seconds
Started Jun 06 01:08:15 PM PDT 24
Finished Jun 06 01:08:18 PM PDT 24
Peak memory 200252 kb
Host smart-4b30602f-ad5a-4d76-b860-8902cf788d41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454020272 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.1454020272
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.605125456
Short name T543
Test name
Test status
Simulation time 101178121812 ps
CPU time 506.75 seconds
Started Jun 06 01:08:17 PM PDT 24
Finished Jun 06 01:16:46 PM PDT 24
Peak memory 200716 kb
Host smart-98b07deb-2ab2-4960-9b9e-b1d0d6d2a5e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605125456 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.605125456
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.4102783542
Short name T536
Test name
Test status
Simulation time 526886508 ps
CPU time 31.52 seconds
Started Jun 06 01:08:16 PM PDT 24
Finished Jun 06 01:08:49 PM PDT 24
Peak memory 200240 kb
Host smart-36a3a340-3463-461e-8887-ccc3e550b869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102783542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.4102783542
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1812183543
Short name T436
Test name
Test status
Simulation time 15391821 ps
CPU time 0.59 seconds
Started Jun 06 01:08:12 PM PDT 24
Finished Jun 06 01:08:14 PM PDT 24
Peak memory 196204 kb
Host smart-9db442a1-b86d-431b-9137-9ad5bb4b88de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812183543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1812183543
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1813482145
Short name T391
Test name
Test status
Simulation time 1944592290 ps
CPU time 39.97 seconds
Started Jun 06 01:08:12 PM PDT 24
Finished Jun 06 01:08:54 PM PDT 24
Peak memory 216452 kb
Host smart-f8d41015-bb70-4dd3-89a0-35ba14c6426a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1813482145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1813482145
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3277592912
Short name T192
Test name
Test status
Simulation time 2863489424 ps
CPU time 30.89 seconds
Started Jun 06 01:08:12 PM PDT 24
Finished Jun 06 01:08:45 PM PDT 24
Peak memory 200484 kb
Host smart-5b847e53-08d2-4529-bf72-81673db8bf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277592912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3277592912
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.830023335
Short name T576
Test name
Test status
Simulation time 14178540307 ps
CPU time 744.43 seconds
Started Jun 06 01:08:11 PM PDT 24
Finished Jun 06 01:20:36 PM PDT 24
Peak memory 757184 kb
Host smart-9e42be82-19d5-43d9-9021-0d45a0e57ef0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=830023335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.830023335
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2697393695
Short name T204
Test name
Test status
Simulation time 8857110756 ps
CPU time 60.41 seconds
Started Jun 06 01:08:24 PM PDT 24
Finished Jun 06 01:09:26 PM PDT 24
Peak memory 200688 kb
Host smart-9c8d04d6-0981-4129-b69d-c15d53ba6ed5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697393695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2697393695
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.1993078462
Short name T309
Test name
Test status
Simulation time 33685305363 ps
CPU time 112.14 seconds
Started Jun 06 01:08:15 PM PDT 24
Finished Jun 06 01:10:09 PM PDT 24
Peak memory 200472 kb
Host smart-b4fc9789-0894-41ed-83ff-81687a91e450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993078462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1993078462
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3238222461
Short name T297
Test name
Test status
Simulation time 176958823 ps
CPU time 3 seconds
Started Jun 06 01:08:11 PM PDT 24
Finished Jun 06 01:08:15 PM PDT 24
Peak memory 200328 kb
Host smart-80378465-e22e-4ecc-932e-bc6c26b99efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238222461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3238222461
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.3755425702
Short name T545
Test name
Test status
Simulation time 94398681650 ps
CPU time 2472.91 seconds
Started Jun 06 01:08:12 PM PDT 24
Finished Jun 06 01:49:26 PM PDT 24
Peak memory 737412 kb
Host smart-b29d321f-ec4f-4a8c-b443-a9302da25a39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755425702 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.3755425702
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.182084720
Short name T433
Test name
Test status
Simulation time 70906942 ps
CPU time 1.39 seconds
Started Jun 06 01:08:14 PM PDT 24
Finished Jun 06 01:08:17 PM PDT 24
Peak memory 200216 kb
Host smart-9473fcf7-3cef-419a-98a0-bda95a444902
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182084720 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_hmac_vectors.182084720
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.2005852868
Short name T553
Test name
Test status
Simulation time 8868106254 ps
CPU time 486.94 seconds
Started Jun 06 01:08:14 PM PDT 24
Finished Jun 06 01:16:22 PM PDT 24
Peak memory 200444 kb
Host smart-d05ca24e-fb66-45ef-ad8d-581be75e39e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005852868 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.2005852868
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.452018385
Short name T137
Test name
Test status
Simulation time 1423420407 ps
CPU time 56.04 seconds
Started Jun 06 01:08:12 PM PDT 24
Finished Jun 06 01:09:09 PM PDT 24
Peak memory 200352 kb
Host smart-da704f81-7018-4eeb-839d-d9038c91eb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452018385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.452018385
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.3779396750
Short name T558
Test name
Test status
Simulation time 51507279 ps
CPU time 0.58 seconds
Started Jun 06 01:06:10 PM PDT 24
Finished Jun 06 01:06:11 PM PDT 24
Peak memory 196176 kb
Host smart-d7565ea9-4f78-4106-8325-15a36469f621
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779396750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3779396750
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.98945410
Short name T418
Test name
Test status
Simulation time 997016695 ps
CPU time 48.49 seconds
Started Jun 06 01:06:07 PM PDT 24
Finished Jun 06 01:06:56 PM PDT 24
Peak memory 220876 kb
Host smart-27b334ae-d19f-4bcc-bbb6-3f747a9d2c4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=98945410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.98945410
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1506791120
Short name T15
Test name
Test status
Simulation time 2773584806 ps
CPU time 34.4 seconds
Started Jun 06 01:06:16 PM PDT 24
Finished Jun 06 01:06:52 PM PDT 24
Peak memory 200396 kb
Host smart-c3125ceb-4eca-4e12-8927-5cc2819eddfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506791120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1506791120
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.3930482362
Short name T378
Test name
Test status
Simulation time 3875955551 ps
CPU time 530.33 seconds
Started Jun 06 01:06:11 PM PDT 24
Finished Jun 06 01:15:02 PM PDT 24
Peak memory 660936 kb
Host smart-21703b50-f5ae-426c-9f71-85b813212931
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3930482362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3930482362
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.472368034
Short name T252
Test name
Test status
Simulation time 29047018752 ps
CPU time 78.12 seconds
Started Jun 06 01:06:11 PM PDT 24
Finished Jun 06 01:07:30 PM PDT 24
Peak memory 200396 kb
Host smart-75f2be07-ce9d-4ea4-8082-ec3464e98eba
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472368034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.472368034
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3078818528
Short name T183
Test name
Test status
Simulation time 231818297 ps
CPU time 6.41 seconds
Started Jun 06 01:06:03 PM PDT 24
Finished Jun 06 01:06:10 PM PDT 24
Peak memory 200396 kb
Host smart-2cf474a2-3995-4168-81b4-d9434f3159fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078818528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3078818528
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.4181989015
Short name T381
Test name
Test status
Simulation time 490078610 ps
CPU time 3.98 seconds
Started Jun 06 01:05:58 PM PDT 24
Finished Jun 06 01:06:03 PM PDT 24
Peak memory 200324 kb
Host smart-0d02a487-db83-49da-ab26-4db66a2628c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181989015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.4181989015
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1523052539
Short name T111
Test name
Test status
Simulation time 694962802955 ps
CPU time 1588.7 seconds
Started Jun 06 01:06:11 PM PDT 24
Finished Jun 06 01:32:41 PM PDT 24
Peak memory 722436 kb
Host smart-dce95b56-ac48-4aad-9642-be8c6a67e1ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523052539 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1523052539
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.3688238934
Short name T539
Test name
Test status
Simulation time 31211842 ps
CPU time 1.13 seconds
Started Jun 06 01:06:11 PM PDT 24
Finished Jun 06 01:06:13 PM PDT 24
Peak memory 199292 kb
Host smart-f0905f9d-4ad4-456e-9dd3-e64262818f2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688238934 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.3688238934
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.843390586
Short name T325
Test name
Test status
Simulation time 287813144490 ps
CPU time 478.01 seconds
Started Jun 06 01:06:17 PM PDT 24
Finished Jun 06 01:14:17 PM PDT 24
Peak memory 200388 kb
Host smart-3e885b53-29e4-4bdc-92ea-6d62f0360385
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843390586 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.843390586
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.632029365
Short name T248
Test name
Test status
Simulation time 28642703721 ps
CPU time 80.21 seconds
Started Jun 06 01:06:17 PM PDT 24
Finished Jun 06 01:07:38 PM PDT 24
Peak memory 200468 kb
Host smart-894534b3-a50b-4645-8fe4-a12da8b2163b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632029365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.632029365
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.4053741563
Short name T229
Test name
Test status
Simulation time 20247056 ps
CPU time 0.58 seconds
Started Jun 06 01:06:12 PM PDT 24
Finished Jun 06 01:06:13 PM PDT 24
Peak memory 195168 kb
Host smart-efb3f327-914a-4f7e-9ffd-ef40c35a9eab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053741563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.4053741563
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.4108987700
Short name T571
Test name
Test status
Simulation time 2894427454 ps
CPU time 37.73 seconds
Started Jun 06 01:06:16 PM PDT 24
Finished Jun 06 01:06:55 PM PDT 24
Peak memory 233416 kb
Host smart-ab00b24f-eac4-4db0-9fda-fd550fd0ad3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4108987700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.4108987700
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.2207145816
Short name T475
Test name
Test status
Simulation time 1401562905 ps
CPU time 18.4 seconds
Started Jun 06 01:06:14 PM PDT 24
Finished Jun 06 01:06:34 PM PDT 24
Peak memory 200404 kb
Host smart-2077e76d-27ca-45c7-a07e-1f2e5133f8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207145816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2207145816
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1557245379
Short name T162
Test name
Test status
Simulation time 14830714081 ps
CPU time 979.53 seconds
Started Jun 06 01:06:10 PM PDT 24
Finished Jun 06 01:22:30 PM PDT 24
Peak memory 764204 kb
Host smart-61df342d-a055-4771-a522-6bb89255028c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1557245379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1557245379
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3653280660
Short name T18
Test name
Test status
Simulation time 43141419658 ps
CPU time 138.15 seconds
Started Jun 06 01:06:15 PM PDT 24
Finished Jun 06 01:08:34 PM PDT 24
Peak memory 200412 kb
Host smart-8228574d-693d-48d2-b5b8-569113415e02
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653280660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3653280660
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3971831367
Short name T275
Test name
Test status
Simulation time 35858667339 ps
CPU time 152.03 seconds
Started Jun 06 01:06:10 PM PDT 24
Finished Jun 06 01:08:43 PM PDT 24
Peak memory 200524 kb
Host smart-26e50e8f-6b58-4676-b3bd-79a3a56c81f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971831367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3971831367
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3287553181
Short name T516
Test name
Test status
Simulation time 48626745 ps
CPU time 1.06 seconds
Started Jun 06 01:06:45 PM PDT 24
Finished Jun 06 01:06:48 PM PDT 24
Peak memory 200168 kb
Host smart-ee3bf618-d66f-4915-b7f7-7b3ac7aa47d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287553181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3287553181
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.3784582663
Short name T50
Test name
Test status
Simulation time 602417318527 ps
CPU time 2480.79 seconds
Started Jun 06 01:06:11 PM PDT 24
Finished Jun 06 01:47:33 PM PDT 24
Peak memory 311204 kb
Host smart-f11f95ec-0eb2-4123-8e0e-44c94c09a6d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784582663 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3784582663
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.4276717701
Short name T172
Test name
Test status
Simulation time 29481588 ps
CPU time 1.11 seconds
Started Jun 06 01:06:10 PM PDT 24
Finished Jun 06 01:06:12 PM PDT 24
Peak memory 200380 kb
Host smart-b883a089-fe00-4f8e-8054-522ceacc981d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276717701 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.4276717701
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.2029988656
Short name T508
Test name
Test status
Simulation time 88465842586 ps
CPU time 593.64 seconds
Started Jun 06 01:06:10 PM PDT 24
Finished Jun 06 01:16:04 PM PDT 24
Peak memory 200348 kb
Host smart-35e55ef7-16b7-4b35-87fd-0f03bcbf7651
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029988656 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.2029988656
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.4140117285
Short name T266
Test name
Test status
Simulation time 18061504684 ps
CPU time 69.25 seconds
Started Jun 06 01:06:11 PM PDT 24
Finished Jun 06 01:07:21 PM PDT 24
Peak memory 200440 kb
Host smart-cb54b9e4-3370-498f-9191-16fa8f7d68e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140117285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.4140117285
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/66.hmac_stress_all_with_rand_reset.4017325238
Short name T14
Test name
Test status
Simulation time 62515126221 ps
CPU time 1187.06 seconds
Started Jun 06 01:08:23 PM PDT 24
Finished Jun 06 01:28:12 PM PDT 24
Peak memory 669880 kb
Host smart-158e77a7-8fe4-47b5-a3ee-32e46304805f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4017325238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.hmac_stress_all_with_rand_reset.4017325238
Directory /workspace/66.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.1020541552
Short name T452
Test name
Test status
Simulation time 30677000 ps
CPU time 0.56 seconds
Started Jun 06 01:06:21 PM PDT 24
Finished Jun 06 01:06:23 PM PDT 24
Peak memory 195200 kb
Host smart-cd9c3967-db27-4db6-9485-87f2d98f07b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020541552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1020541552
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1761914703
Short name T43
Test name
Test status
Simulation time 595400309 ps
CPU time 24.88 seconds
Started Jun 06 01:06:11 PM PDT 24
Finished Jun 06 01:06:37 PM PDT 24
Peak memory 216384 kb
Host smart-354bfce3-b9fc-45b2-827c-d4c9a8c3d05b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1761914703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1761914703
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2829321609
Short name T548
Test name
Test status
Simulation time 370221608 ps
CPU time 3.38 seconds
Started Jun 06 01:06:11 PM PDT 24
Finished Jun 06 01:06:15 PM PDT 24
Peak memory 200340 kb
Host smart-80d2de4b-436b-4068-b25d-442afc6cd6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829321609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2829321609
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.1022533427
Short name T506
Test name
Test status
Simulation time 7997788041 ps
CPU time 1152.57 seconds
Started Jun 06 01:06:11 PM PDT 24
Finished Jun 06 01:25:25 PM PDT 24
Peak memory 738780 kb
Host smart-58c2a58a-0b07-4439-b52f-1a141d38c5dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1022533427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1022533427
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.859953369
Short name T187
Test name
Test status
Simulation time 6118919877 ps
CPU time 83.84 seconds
Started Jun 06 01:06:20 PM PDT 24
Finished Jun 06 01:07:46 PM PDT 24
Peak memory 200440 kb
Host smart-9195e180-3956-4074-8fc0-7d8b0ab06c27
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859953369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.859953369
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_smoke.2618766862
Short name T186
Test name
Test status
Simulation time 1116573155 ps
CPU time 6.09 seconds
Started Jun 06 01:06:17 PM PDT 24
Finished Jun 06 01:06:25 PM PDT 24
Peak memory 200388 kb
Host smart-0f56aa0d-1140-47ba-81f0-dbca13a5fe83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618766862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2618766862
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.3296868717
Short name T67
Test name
Test status
Simulation time 251188440502 ps
CPU time 1908.68 seconds
Started Jun 06 01:06:21 PM PDT 24
Finished Jun 06 01:38:12 PM PDT 24
Peak memory 463988 kb
Host smart-7dd22fa2-c602-4d64-8487-a4a554d3f0ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296868717 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.3296868717
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.1890205074
Short name T482
Test name
Test status
Simulation time 194654242 ps
CPU time 1.27 seconds
Started Jun 06 01:06:11 PM PDT 24
Finished Jun 06 01:06:13 PM PDT 24
Peak memory 200404 kb
Host smart-f70e5c85-92c3-4508-92ac-c10482016d5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890205074 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.1890205074
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.120954212
Short name T31
Test name
Test status
Simulation time 114831762913 ps
CPU time 538.87 seconds
Started Jun 06 01:06:11 PM PDT 24
Finished Jun 06 01:15:12 PM PDT 24
Peak memory 200332 kb
Host smart-d7343aa6-d736-4290-9c9f-15d81459e06d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120954212 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.120954212
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2988728545
Short name T587
Test name
Test status
Simulation time 2208548046 ps
CPU time 44.07 seconds
Started Jun 06 01:06:11 PM PDT 24
Finished Jun 06 01:06:56 PM PDT 24
Peak memory 200380 kb
Host smart-90e7b700-5e28-4c51-9af7-8c91e87d3a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988728545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2988728545
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/76.hmac_stress_all_with_rand_reset.4043949735
Short name T56
Test name
Test status
Simulation time 212909370046 ps
CPU time 1241.7 seconds
Started Jun 06 01:08:20 PM PDT 24
Finished Jun 06 01:29:04 PM PDT 24
Peak memory 216960 kb
Host smart-6d406a89-6af1-4ac0-93ab-440cb367970c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4043949735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.hmac_stress_all_with_rand_reset.4043949735
Directory /workspace/76.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.791978804
Short name T517
Test name
Test status
Simulation time 105961356 ps
CPU time 0.58 seconds
Started Jun 06 01:06:13 PM PDT 24
Finished Jun 06 01:06:15 PM PDT 24
Peak memory 195848 kb
Host smart-4b33cab5-1ade-4815-a00c-c95241f90311
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791978804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.791978804
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2859954158
Short name T337
Test name
Test status
Simulation time 36214431 ps
CPU time 1.64 seconds
Started Jun 06 01:06:22 PM PDT 24
Finished Jun 06 01:06:26 PM PDT 24
Peak memory 200440 kb
Host smart-869ea9e5-2e86-491a-a989-7e003dc3543c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2859954158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2859954158
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1227492559
Short name T328
Test name
Test status
Simulation time 852858781 ps
CPU time 3.36 seconds
Started Jun 06 01:06:21 PM PDT 24
Finished Jun 06 01:06:26 PM PDT 24
Peak memory 200396 kb
Host smart-89d67a30-9ad0-4bdf-ac75-4e145afed841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227492559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1227492559
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3817787631
Short name T207
Test name
Test status
Simulation time 1355198476 ps
CPU time 297.96 seconds
Started Jun 06 01:06:13 PM PDT 24
Finished Jun 06 01:11:12 PM PDT 24
Peak memory 648032 kb
Host smart-78b0e8c4-8a95-4c1c-b2f1-8d6b3bd69e17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3817787631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3817787631
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.380677735
Short name T256
Test name
Test status
Simulation time 11650277339 ps
CPU time 37.55 seconds
Started Jun 06 01:06:22 PM PDT 24
Finished Jun 06 01:07:02 PM PDT 24
Peak memory 200440 kb
Host smart-fdcb3d06-6ced-4941-9972-e934d9c839bf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380677735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.380677735
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1369703597
Short name T549
Test name
Test status
Simulation time 36199970887 ps
CPU time 38.79 seconds
Started Jun 06 01:06:22 PM PDT 24
Finished Jun 06 01:07:02 PM PDT 24
Peak memory 200524 kb
Host smart-955357bb-ef9c-4598-9e38-9730d9a90d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369703597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1369703597
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1937851736
Short name T551
Test name
Test status
Simulation time 196034781 ps
CPU time 0.8 seconds
Started Jun 06 01:06:11 PM PDT 24
Finished Jun 06 01:06:13 PM PDT 24
Peak memory 198100 kb
Host smart-0611a39e-8131-42d4-a12c-17de3f67d38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937851736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1937851736
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.4269615624
Short name T322
Test name
Test status
Simulation time 4893432141 ps
CPU time 788.22 seconds
Started Jun 06 01:06:23 PM PDT 24
Finished Jun 06 01:19:33 PM PDT 24
Peak memory 693724 kb
Host smart-535a54f6-0a8f-46b1-b2aa-5cd612fba022
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269615624 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.4269615624
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.2333755472
Short name T260
Test name
Test status
Simulation time 67948159 ps
CPU time 1.29 seconds
Started Jun 06 01:06:12 PM PDT 24
Finished Jun 06 01:06:15 PM PDT 24
Peak memory 200360 kb
Host smart-b5965fe7-ac87-4cb8-af07-994ac3fd08c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333755472 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.2333755472
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.507773332
Short name T592
Test name
Test status
Simulation time 10085664086 ps
CPU time 452.16 seconds
Started Jun 06 01:06:12 PM PDT 24
Finished Jun 06 01:13:46 PM PDT 24
Peak memory 200428 kb
Host smart-c06b70a4-4254-44eb-923e-5edfd38d38a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507773332 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.507773332
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2324900396
Short name T584
Test name
Test status
Simulation time 4611326807 ps
CPU time 44.63 seconds
Started Jun 06 01:06:21 PM PDT 24
Finished Jun 06 01:07:08 PM PDT 24
Peak memory 200496 kb
Host smart-92bf5027-1539-41a2-9071-40710579181d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324900396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2324900396
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3619457917
Short name T208
Test name
Test status
Simulation time 40595991 ps
CPU time 0.59 seconds
Started Jun 06 01:06:22 PM PDT 24
Finished Jun 06 01:06:24 PM PDT 24
Peak memory 196132 kb
Host smart-f3e66e7c-e2ca-4090-b6fd-9a1e11871b58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619457917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3619457917
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.542907782
Short name T470
Test name
Test status
Simulation time 29190499 ps
CPU time 1.62 seconds
Started Jun 06 01:06:13 PM PDT 24
Finished Jun 06 01:06:16 PM PDT 24
Peak memory 200324 kb
Host smart-daa14088-fd7f-4158-99c8-57bbc4ebf2da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=542907782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.542907782
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2920794324
Short name T73
Test name
Test status
Simulation time 948735867 ps
CPU time 11.87 seconds
Started Jun 06 01:06:15 PM PDT 24
Finished Jun 06 01:06:28 PM PDT 24
Peak memory 200380 kb
Host smart-2894ca40-e9c8-4aa7-9cb2-513c2a2491df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920794324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2920794324
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.2239510604
Short name T525
Test name
Test status
Simulation time 1161442056 ps
CPU time 46.5 seconds
Started Jun 06 01:06:17 PM PDT 24
Finished Jun 06 01:07:05 PM PDT 24
Peak memory 321836 kb
Host smart-1e5d2e4b-0400-41d0-b0d8-d278c2aecde1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2239510604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2239510604
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.1301719293
Short name T237
Test name
Test status
Simulation time 18956242 ps
CPU time 0.65 seconds
Started Jun 06 01:06:08 PM PDT 24
Finished Jun 06 01:06:09 PM PDT 24
Peak memory 196588 kb
Host smart-46e117f7-1d54-410f-824c-7c105c8bb3ac
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301719293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1301719293
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.1502091849
Short name T409
Test name
Test status
Simulation time 1506137568 ps
CPU time 45.12 seconds
Started Jun 06 01:06:21 PM PDT 24
Finished Jun 06 01:07:08 PM PDT 24
Peak memory 200404 kb
Host smart-4341cc60-724e-4a25-a1df-830a580bf125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502091849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1502091849
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3577864827
Short name T59
Test name
Test status
Simulation time 634095166 ps
CPU time 2.63 seconds
Started Jun 06 01:06:14 PM PDT 24
Finished Jun 06 01:06:18 PM PDT 24
Peak memory 200664 kb
Host smart-696bd9e2-558d-4a09-9368-b40a3ed9497b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577864827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3577864827
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.716112306
Short name T69
Test name
Test status
Simulation time 35009711981 ps
CPU time 122.31 seconds
Started Jun 06 01:06:16 PM PDT 24
Finished Jun 06 01:08:20 PM PDT 24
Peak memory 200452 kb
Host smart-aec463bf-c79a-4f81-9cb2-4d7537a3e6ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716112306 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.716112306
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.2235830704
Short name T490
Test name
Test status
Simulation time 63839220 ps
CPU time 1.37 seconds
Started Jun 06 01:06:14 PM PDT 24
Finished Jun 06 01:06:17 PM PDT 24
Peak memory 200388 kb
Host smart-fc92b681-3fee-442b-b134-c3bd18cf983f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235830704 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.2235830704
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.1569003768
Short name T143
Test name
Test status
Simulation time 38894727237 ps
CPU time 514.18 seconds
Started Jun 06 01:06:22 PM PDT 24
Finished Jun 06 01:14:58 PM PDT 24
Peak memory 200356 kb
Host smart-eab031fe-f026-4056-9227-3875f4bfe2e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569003768 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.1569003768
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.1282713817
Short name T588
Test name
Test status
Simulation time 25496031438 ps
CPU time 52.51 seconds
Started Jun 06 01:06:16 PM PDT 24
Finished Jun 06 01:07:10 PM PDT 24
Peak memory 200472 kb
Host smart-57661be1-9f00-40c5-84b0-28d8b79165cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282713817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1282713817
Directory /workspace/9.hmac_wipe_secret/latest
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