Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15277364	1			T1	88		T2	71234		T3	458
all_values[1]	15277364	1			T1	88		T2	71234		T3	458
all_values[2]	15277364	1			T1	88		T2	71234		T3	458

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102709

1

T3

53

T6

261

T31

2

auto[1]

45729383

1

T1

264

T2

213702

T3

1321

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38251163

1

T1

206

T2

179922

T3

1257

auto[1]

7580929

1

T1

58

T2

33780

T3

117

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	33560	1			T3	29		T6	259		T31	1
all_values[0]	auto[0]	auto[1]	317	1			T3	4		T6	2		T46	2
all_values[0]	auto[1]	auto[0]	15203923	1			T1	84		T2	71040		T3	386
all_values[0]	auto[1]	auto[1]	39564	1			T1	4		T2	194		T3	39
all_values[1]	auto[0]	auto[0]	32324	1			T3	10		T24	122		T61	130
all_values[1]	auto[0]	auto[1]	173	1			T24	7		T39	1		T54	2
all_values[1]	auto[1]	auto[0]	15244562	1			T1	88		T2	71234		T3	448
all_values[1]	auto[1]	auto[1]	305	1			T16	1		T29	1		T24	3
all_values[2]	auto[0]	auto[0]	15804	1			T3	10		T31	1		T8	2
all_values[2]	auto[0]	auto[1]	20531	1			T26	2		T17	2034		T24	6
all_values[2]	auto[1]	auto[0]	7720990	1			T1	34		T2	37648		T3	374
all_values[2]	auto[1]	auto[1]	7520039	1			T1	54		T2	33586		T3	74