Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7216447

1

T1

29

T2

37453

T3

123

auto[1]

2571750

1

T3

126

T6

1025

T4

6186

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2530452

1

T3

146

T6

988

T4

7143

auto[1]

7257745

1

T1

29

T2

37453

T3

103

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6122187

1

T2

37453

T3

128

T6

924

auto[1]

3666010

1

T1

29

T3

121

T6

703

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	7662365	1			T1	27		T2	34878		T3	221
fifo_depth[1]	343601	1			T1	2		T2	1472		T3	5
fifo_depth[2]	281034	1			T2	671		T3	8		T6	3
fifo_depth[3]	221631	1			T2	292		T3	7		T6	3
fifo_depth[4]	178595	1			T2	99		T3	4		T6	2
fifo_depth[5]	150343	1			T2	34		T3	2		T6	2
fifo_depth[6]	138220	1			T2	7		T3	2		T6	3
fifo_depth[7]	118532	1			T12	45		T7	267		T18	786

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2125832

1

T1

2

T2

2575

T3

28

auto[1]

7662365

1

T1

27

T2

34878

T3

221

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9769392

1

T1

29

T2

37453

T3

249

auto[1]

18805

1

T5

1

T12

2

T8

1

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

108124

1

T4

106

T5

3

T8

1

auto[0]

auto[0]

auto[0]

auto[1]

111371

1

T4

29

T5

2

T8

6

auto[0]

auto[0]

auto[1]

auto[0]

1028628

1

T2

2575

T6

23

T4

22

auto[0]

auto[0]

auto[1]

auto[1]

106823

1

T4

10

T5

5

T8

3

auto[0]

auto[1]

auto[0]

auto[0]

196349

1

T3

16

T4

66

T5

3

auto[0]

auto[1]

auto[0]

auto[1]

182953

1

T3

3

T6

7

T4

33

auto[0]

auto[1]

auto[1]

auto[0]

189755

1

T1

2

T3

7

T4

104

auto[0]

auto[1]

auto[1]

auto[1]

201829

1

T3

2

T4

53

T5

2

auto[1]

auto[0]

auto[0]

auto[0]

254822

1

T3

21

T4

1522

T8

1

auto[1]

auto[0]

auto[0]

auto[1]

254641

1

T3

46

T6

285

T4

952

auto[1]

auto[0]

auto[1]

auto[0]

4015477

1

T2

34878

T3

30

T6

579

auto[1]

auto[0]

auto[1]

auto[1]

242301

1

T3

31

T6

37

T4

705

auto[1]

auto[1]

auto[0]

auto[0]

690868

1

T3

30

T4

2738

T5

1

auto[1]

auto[1]

auto[0]

auto[1]

731324

1

T3

30

T6

696

T4

1697

auto[1]

auto[1]

auto[1]

auto[0]

732424

1

T1

27

T3

19

T4

3310

auto[1]

auto[1]

auto[1]

auto[1]

740508

1

T3

14

T4

2707

T12

2

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

359831

1

T3

21

T4

1628

T5

3

auto[0]

auto[0]

auto[0]

auto[1]

363142

1

T3

46

T6

285

T4

981

auto[0]

auto[0]

auto[1]

auto[0]

5039620

1

T2

37453

T3

30

T6

602

auto[0]

auto[0]

auto[1]

auto[1]

347724

1

T3

31

T6

37

T4

715

auto[0]

auto[1]

auto[0]

auto[0]

884521

1

T3

46

T4

2804

T5

4

auto[0]

auto[1]

auto[0]

auto[1]

913103

1

T3

33

T6

703

T4

1730

auto[0]

auto[1]

auto[1]

auto[0]

920604

1

T1

29

T3

26

T4

3414

auto[0]

auto[1]

auto[1]

auto[1]

940847

1

T3

16

T4

2760

T5

2

auto[1]

auto[0]

auto[0]

auto[0]

3115

1

T26

1

T47

1

T61

14

auto[1]

auto[0]

auto[0]

auto[1]

2870

1

T23

1

T16

29

T29

18

auto[1]

auto[0]

auto[1]

auto[0]

4485

1

T5

1

T16

11

T29

11

auto[1]

auto[0]

auto[1]

auto[1]

1400

1

T29

8

T61

17

T43

1

auto[1]

auto[1]

auto[0]

auto[0]

2696

1

T50

1

T61

15

T124

75

auto[1]

auto[1]

auto[0]

auto[1]

1174

1

T19

1

T16

171

T48

1

auto[1]

auto[1]

auto[1]

auto[0]

1575

1

T49

1

T24

13

T60

2

auto[1]

auto[1]

auto[1]

auto[1]

1490

1

T12

2

T8

1

T50

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	254822	1			T3	21		T4	1522		T8	1
fifo_depth[0]	auto[0]	auto[0]	auto[1]	254641	1			T3	46		T6	285		T4	952
fifo_depth[0]	auto[0]	auto[1]	auto[0]	4015477	1			T2	34878		T3	30		T6	579
fifo_depth[0]	auto[0]	auto[1]	auto[1]	242301	1			T3	31		T6	37		T4	705
fifo_depth[0]	auto[1]	auto[0]	auto[0]	690868	1			T3	30		T4	2738		T5	1
fifo_depth[0]	auto[1]	auto[0]	auto[1]	731324	1			T3	30		T6	696		T4	1697
fifo_depth[0]	auto[1]	auto[1]	auto[0]	732424	1			T1	27		T3	19		T4	3310
fifo_depth[0]	auto[1]	auto[1]	auto[1]	740508	1			T3	14		T4	2707		T12	2
fifo_depth[1]	auto[0]	auto[0]	auto[0]	8553	1			T4	59		T7	75		T13	24
fifo_depth[1]	auto[0]	auto[0]	auto[1]	9090	1			T4	15		T7	17		T13	9
fifo_depth[1]	auto[0]	auto[1]	auto[0]	237320	1			T2	1472		T6	10		T4	12
fifo_depth[1]	auto[0]	auto[1]	auto[1]	8092	1			T4	8		T7	13		T13	9
fifo_depth[1]	auto[1]	auto[0]	auto[0]	20617	1			T3	3		T4	36		T7	45
fifo_depth[1]	auto[1]	auto[0]	auto[1]	19357	1			T3	1		T6	7		T4	23
fifo_depth[1]	auto[1]	auto[1]	auto[0]	19870	1			T1	2		T3	1		T4	63
fifo_depth[1]	auto[1]	auto[1]	auto[1]	20702	1			T4	29		T12	6		T7	70
fifo_depth[2]	auto[0]	auto[0]	auto[0]	7749	1			T4	28		T7	45		T13	17
fifo_depth[2]	auto[0]	auto[0]	auto[1]	8173	1			T4	10		T7	28		T13	6
fifo_depth[2]	auto[0]	auto[1]	auto[0]	183569	1			T2	671		T6	3		T4	7
fifo_depth[2]	auto[0]	auto[1]	auto[1]	7617	1			T4	2		T7	24		T13	12
fifo_depth[2]	auto[1]	auto[0]	auto[0]	18910	1			T3	4		T4	16		T7	28
fifo_depth[2]	auto[1]	auto[0]	auto[1]	17881	1			T3	1		T4	6		T7	17
fifo_depth[2]	auto[1]	auto[1]	auto[0]	17929	1			T3	2		T4	25		T7	19
fifo_depth[2]	auto[1]	auto[1]	auto[1]	19206	1			T3	1		T4	18		T12	6
fifo_depth[3]	auto[0]	auto[0]	auto[0]	6202	1			T4	15		T7	51		T13	7
fifo_depth[3]	auto[0]	auto[0]	auto[1]	6348	1			T4	3		T7	27		T13	5
fifo_depth[3]	auto[0]	auto[1]	auto[0]	139891	1			T2	292		T6	3		T4	3
fifo_depth[3]	auto[0]	auto[1]	auto[1]	5996	1			T7	26		T13	4		T16	244
fifo_depth[3]	auto[1]	auto[0]	auto[0]	16076	1			T3	5		T4	12		T7	34
fifo_depth[3]	auto[1]	auto[0]	auto[1]	15316	1			T4	3		T7	13		T13	6
fifo_depth[3]	auto[1]	auto[1]	auto[0]	15453	1			T3	2		T4	13		T7	28
fifo_depth[3]	auto[1]	auto[1]	auto[1]	16349	1			T4	5		T12	6		T7	70
fifo_depth[4]	auto[0]	auto[0]	auto[0]	6410	1			T4	4		T7	56		T13	13
fifo_depth[4]	auto[0]	auto[0]	auto[1]	6442	1			T4	1		T7	27		T13	15
fifo_depth[4]	auto[0]	auto[1]	auto[0]	100872	1			T2	99		T6	2		T7	35
fifo_depth[4]	auto[0]	auto[1]	auto[1]	6341	1			T7	23		T13	7		T16	321
fifo_depth[4]	auto[1]	auto[0]	auto[0]	14837	1			T3	3		T4	2		T7	29
fifo_depth[4]	auto[1]	auto[0]	auto[1]	14065	1			T4	1		T7	8		T13	21
fifo_depth[4]	auto[1]	auto[1]	auto[0]	14650	1			T3	1		T4	2		T7	18
fifo_depth[4]	auto[1]	auto[1]	auto[1]	14978	1			T4	1		T12	7		T7	56
fifo_depth[5]	auto[0]	auto[0]	auto[0]	5034	1			T7	52		T13	5		T16	265
fifo_depth[5]	auto[0]	auto[0]	auto[1]	5180	1			T7	21		T13	1		T15	1
fifo_depth[5]	auto[0]	auto[1]	auto[0]	81445	1			T2	34		T6	2		T7	32
fifo_depth[5]	auto[0]	auto[1]	auto[1]	4851	1			T7	16		T13	4		T16	268
fifo_depth[5]	auto[1]	auto[0]	auto[0]	13576	1			T3	1		T12	7		T7	27
fifo_depth[5]	auto[1]	auto[0]	auto[1]	12854	1			T3	1		T7	14		T13	6
fifo_depth[5]	auto[1]	auto[1]	auto[0]	13180	1			T4	1		T7	22		T13	6
fifo_depth[5]	auto[1]	auto[1]	auto[1]	14223	1			T12	7		T7	73		T16	294
fifo_depth[6]	auto[0]	auto[0]	auto[0]	5250	1			T7	60		T13	6		T16	256
fifo_depth[6]	auto[0]	auto[0]	auto[1]	5517	1			T7	18		T13	4		T16	222
fifo_depth[6]	auto[0]	auto[1]	auto[0]	70002	1			T2	7		T6	3		T7	43
fifo_depth[6]	auto[0]	auto[1]	auto[1]	5134	1			T7	19		T13	9		T16	299
fifo_depth[6]	auto[1]	auto[0]	auto[0]	13150	1			T12	10		T7	33		T13	8
fifo_depth[6]	auto[1]	auto[0]	auto[1]	12463	1			T7	15		T13	20		T16	445
fifo_depth[6]	auto[1]	auto[1]	auto[0]	13050	1			T3	1		T7	20		T13	4
fifo_depth[6]	auto[1]	auto[1]	auto[1]	13654	1			T3	1		T12	43		T7	74
fifo_depth[7]	auto[0]	auto[0]	auto[0]	4772	1			T7	44		T13	1		T16	254
fifo_depth[7]	auto[0]	auto[0]	auto[1]	4768	1			T7	23		T13	2		T16	193
fifo_depth[7]	auto[0]	auto[1]	auto[0]	54636	1			T7	33		T18	786		T13	2
fifo_depth[7]	auto[0]	auto[1]	auto[1]	4604	1			T7	29		T13	1		T16	234
fifo_depth[7]	auto[1]	auto[0]	auto[0]	12422	1			T12	7		T7	23		T13	1
fifo_depth[7]	auto[1]	auto[0]	auto[1]	11641	1			T7	15		T13	3		T16	490
fifo_depth[7]	auto[1]	auto[1]	auto[0]	12477	1			T7	25		T13	5		T16	474
fifo_depth[7]	auto[1]	auto[1]	auto[1]	13212	1			T12	38		T7	75		T16	299