Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	15277364	1			T1	88		T2	71234		T3	458
all_pins[1]	15277364	1			T1	88		T2	71234		T3	458
all_pins[2]	15277364	1			T1	88		T2	71234		T3	458

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	38271606	1			T1	206		T2	179922		T3	1260
values[0x1]	7560486	1			T1	58		T2	33780		T3	114
transitions[0x0=>0x1]	7560300	1			T1	58		T2	33780		T3	114
transitions[0x1=>0x0]	7560310	1			T1	58		T2	33780		T3	114

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	15237242	1			T1	84		T2	71040		T3	418
all_pins[0]	values[0x1]	40122	1			T1	4		T2	194		T3	40
all_pins[0]	transitions[0x0=>0x1]	40031	1			T1	4		T2	194		T3	40
all_pins[0]	transitions[0x1=>0x0]	7519958	1			T1	54		T2	33586		T3	74
all_pins[1]	values[0x0]	15277039	1			T1	88		T2	71234		T3	458
all_pins[1]	values[0x1]	325	1			T16	1		T29	2		T24	3
all_pins[1]	transitions[0x0=>0x1]	281	1			T16	1		T29	2		T24	2
all_pins[1]	transitions[0x1=>0x0]	40078	1			T1	4		T2	194		T3	40
all_pins[2]	values[0x0]	7757325	1			T1	34		T2	37648		T3	384
all_pins[2]	values[0x1]	7520039	1			T1	54		T2	33586		T3	74
all_pins[2]	transitions[0x0=>0x1]	7519988	1			T1	54		T2	33586		T3	74
all_pins[2]	transitions[0x1=>0x0]	274	1			T16	1		T29	2		T24	3