Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 811 1 T24 28 T39 4 T54 7
all_values[1] 811 1 T24 28 T39 4 T54 7
all_values[2] 811 1 T24 28 T39 4 T54 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1207 1 T24 35 T39 10 T54 10
auto[1] 1226 1 T24 49 T39 2 T54 11


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 837 1 T24 34 T39 6 T54 4
auto[1] 1596 1 T24 50 T39 6 T54 17


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1362 1 T24 50 T39 9 T54 8
auto[1] 1071 1 T24 34 T39 3 T54 13


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 140 1 T24 4 T39 2 T54 3
all_values[0] auto[0] auto[0] auto[1] 75 1 T24 3 T39 1 T101 2
all_values[0] auto[0] auto[1] auto[0] 174 1 T24 6 T54 1 T101 1
all_values[0] auto[0] auto[1] auto[1] 80 1 T24 2 T54 1 T27 2
all_values[0] auto[1] auto[0] auto[1] 154 1 T24 5 T39 1 T54 1
all_values[0] auto[1] auto[1] auto[1] 188 1 T24 8 T54 1 T27 5
all_values[1] auto[0] auto[0] auto[0] 140 1 T24 4 T27 1 T69 1
all_values[1] auto[0] auto[0] auto[1] 97 1 T24 3 T39 1 T101 1
all_values[1] auto[0] auto[1] auto[0] 104 1 T24 8 T101 2 T27 3
all_values[1] auto[0] auto[1] auto[1] 110 1 T24 3 T39 1 T54 1
all_values[1] auto[1] auto[0] auto[1] 184 1 T24 6 T39 2 T54 3
all_values[1] auto[1] auto[1] auto[1] 176 1 T24 4 T54 3 T101 1
all_values[2] auto[0] auto[0] auto[0] 148 1 T24 3 T39 3 T101 1
all_values[2] auto[0] auto[0] auto[1] 81 1 T24 2 T54 1 T27 2
all_values[2] auto[0] auto[1] auto[0] 131 1 T24 9 T39 1 T101 2
all_values[2] auto[0] auto[1] auto[1] 82 1 T24 3 T54 1 T101 1
all_values[2] auto[1] auto[0] auto[1] 188 1 T24 5 T54 2 T101 2
all_values[2] auto[1] auto[1] auto[1] 181 1 T24 6 T54 3 T101 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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