Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.55 94.84 92.14 100.00 71.79 89.38 99.49 72.18


Total test records in report: 730
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T84 /workspace/coverage/default/12.hmac_error.3012598275 Jun 07 07:15:35 PM PDT 24 Jun 07 07:17:56 PM PDT 24 9078625757 ps
T85 /workspace/coverage/default/41.hmac_datapath_stress.161137211 Jun 07 07:16:55 PM PDT 24 Jun 07 07:29:17 PM PDT 24 2811200538 ps
T86 /workspace/coverage/default/23.hmac_long_msg.3078076944 Jun 07 07:16:00 PM PDT 24 Jun 07 07:17:35 PM PDT 24 1572007439 ps
T87 /workspace/coverage/default/3.hmac_burst_wr.2579221101 Jun 07 07:15:16 PM PDT 24 Jun 07 07:15:33 PM PDT 24 279768932 ps
T35 /workspace/coverage/default/2.hmac_sec_cm.3468737952 Jun 07 07:15:10 PM PDT 24 Jun 07 07:15:13 PM PDT 24 276329979 ps
T88 /workspace/coverage/default/14.hmac_long_msg.3351706727 Jun 07 07:15:38 PM PDT 24 Jun 07 07:16:32 PM PDT 24 1871483650 ps
T89 /workspace/coverage/default/5.hmac_smoke.1035160204 Jun 07 07:15:18 PM PDT 24 Jun 07 07:15:22 PM PDT 24 36625305 ps
T544 /workspace/coverage/default/38.hmac_smoke.2711983051 Jun 07 07:16:54 PM PDT 24 Jun 07 07:17:10 PM PDT 24 1659143878 ps
T545 /workspace/coverage/default/7.hmac_burst_wr.4185502938 Jun 07 07:15:23 PM PDT 24 Jun 07 07:15:38 PM PDT 24 1296493533 ps
T546 /workspace/coverage/default/10.hmac_alert_test.714087472 Jun 07 07:15:35 PM PDT 24 Jun 07 07:15:43 PM PDT 24 21546721 ps
T547 /workspace/coverage/default/28.hmac_long_msg.3928699270 Jun 07 07:16:14 PM PDT 24 Jun 07 07:17:33 PM PDT 24 2292036863 ps
T548 /workspace/coverage/default/37.hmac_long_msg.2150302335 Jun 07 07:16:41 PM PDT 24 Jun 07 07:19:23 PM PDT 24 39828645454 ps
T45 /workspace/coverage/default/177.hmac_stress_all_with_rand_reset.2559605590 Jun 07 07:18:08 PM PDT 24 Jun 07 07:37:55 PM PDT 24 84388428543 ps
T549 /workspace/coverage/default/35.hmac_error.3467321803 Jun 07 07:16:43 PM PDT 24 Jun 07 07:19:08 PM PDT 24 19834263867 ps
T550 /workspace/coverage/default/35.hmac_wipe_secret.2806029310 Jun 07 07:16:41 PM PDT 24 Jun 07 07:17:24 PM PDT 24 1017615543 ps
T551 /workspace/coverage/default/2.hmac_long_msg.3446971740 Jun 07 07:15:21 PM PDT 24 Jun 07 07:16:05 PM PDT 24 2024816680 ps
T552 /workspace/coverage/default/13.hmac_alert_test.202033718 Jun 07 07:15:36 PM PDT 24 Jun 07 07:15:43 PM PDT 24 22121184 ps
T553 /workspace/coverage/default/5.hmac_stress_all.861490135 Jun 07 07:15:24 PM PDT 24 Jun 07 07:27:49 PM PDT 24 27509752177 ps
T554 /workspace/coverage/default/19.hmac_stress_all.2021124313 Jun 07 07:15:49 PM PDT 24 Jun 07 07:45:01 PM PDT 24 145190088613 ps
T555 /workspace/coverage/default/17.hmac_wipe_secret.4287062521 Jun 07 07:15:41 PM PDT 24 Jun 07 07:16:28 PM PDT 24 2169352258 ps
T556 /workspace/coverage/default/46.hmac_back_pressure.2331148644 Jun 07 07:17:37 PM PDT 24 Jun 07 07:18:19 PM PDT 24 680647205 ps
T557 /workspace/coverage/default/14.hmac_back_pressure.3800082497 Jun 07 07:15:42 PM PDT 24 Jun 07 07:16:03 PM PDT 24 875285442 ps
T558 /workspace/coverage/default/45.hmac_error.158490673 Jun 07 07:17:05 PM PDT 24 Jun 07 07:17:45 PM PDT 24 8669250095 ps
T11 /workspace/coverage/default/126.hmac_stress_all_with_rand_reset.2946332977 Jun 07 07:17:56 PM PDT 24 Jun 07 07:38:19 PM PDT 24 38769334184 ps
T559 /workspace/coverage/default/27.hmac_datapath_stress.602185005 Jun 07 07:16:11 PM PDT 24 Jun 07 07:31:16 PM PDT 24 34021097707 ps
T560 /workspace/coverage/default/44.hmac_back_pressure.3850613187 Jun 07 07:17:00 PM PDT 24 Jun 07 07:17:35 PM PDT 24 507368227 ps
T561 /workspace/coverage/default/27.hmac_stress_all.615853251 Jun 07 07:16:10 PM PDT 24 Jun 07 07:26:36 PM PDT 24 11052022378 ps
T562 /workspace/coverage/default/33.hmac_stress_all.4253251739 Jun 07 07:16:30 PM PDT 24 Jun 07 07:26:32 PM PDT 24 80383100459 ps
T563 /workspace/coverage/default/17.hmac_long_msg.1857426771 Jun 07 07:15:44 PM PDT 24 Jun 07 07:18:02 PM PDT 24 9476765633 ps
T564 /workspace/coverage/default/25.hmac_wipe_secret.431141143 Jun 07 07:16:02 PM PDT 24 Jun 07 07:16:41 PM PDT 24 2010535952 ps
T565 /workspace/coverage/default/3.hmac_alert_test.335133980 Jun 07 07:15:11 PM PDT 24 Jun 07 07:15:14 PM PDT 24 170329888 ps
T566 /workspace/coverage/default/9.hmac_wipe_secret.1591901176 Jun 07 07:15:26 PM PDT 24 Jun 07 07:16:41 PM PDT 24 4037876809 ps
T567 /workspace/coverage/default/12.hmac_stress_all.1974074527 Jun 07 07:15:31 PM PDT 24 Jun 07 08:21:11 PM PDT 24 645195911893 ps
T568 /workspace/coverage/default/13.hmac_smoke.3764098136 Jun 07 07:15:38 PM PDT 24 Jun 07 07:15:49 PM PDT 24 148472333 ps
T569 /workspace/coverage/default/34.hmac_datapath_stress.3969289401 Jun 07 07:16:27 PM PDT 24 Jun 07 07:18:42 PM PDT 24 539945147 ps
T570 /workspace/coverage/default/36.hmac_error.2101075755 Jun 07 07:16:40 PM PDT 24 Jun 07 07:19:00 PM PDT 24 48021082558 ps
T59 /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.3432101517 Jun 07 07:15:02 PM PDT 24 Jun 07 07:30:13 PM PDT 24 51465459964 ps
T571 /workspace/coverage/default/10.hmac_burst_wr.944194586 Jun 07 07:15:32 PM PDT 24 Jun 07 07:15:49 PM PDT 24 1685603743 ps
T572 /workspace/coverage/default/9.hmac_burst_wr.908077586 Jun 07 07:15:23 PM PDT 24 Jun 07 07:16:23 PM PDT 24 1099141067 ps
T573 /workspace/coverage/default/22.hmac_back_pressure.3868785186 Jun 07 07:15:48 PM PDT 24 Jun 07 07:16:49 PM PDT 24 3819235984 ps
T574 /workspace/coverage/default/19.hmac_datapath_stress.2677887077 Jun 07 07:15:51 PM PDT 24 Jun 07 07:25:53 PM PDT 24 23841319593 ps
T575 /workspace/coverage/default/27.hmac_back_pressure.865497932 Jun 07 07:16:09 PM PDT 24 Jun 07 07:16:54 PM PDT 24 2619346441 ps
T576 /workspace/coverage/default/31.hmac_long_msg.2994489665 Jun 07 07:16:22 PM PDT 24 Jun 07 07:18:04 PM PDT 24 41153740826 ps
T577 /workspace/coverage/default/22.hmac_burst_wr.3134102100 Jun 07 07:15:51 PM PDT 24 Jun 07 07:17:06 PM PDT 24 3384215013 ps
T578 /workspace/coverage/default/13.hmac_test_hmac_vectors.3863295508 Jun 07 07:15:34 PM PDT 24 Jun 07 07:15:42 PM PDT 24 317443936 ps
T579 /workspace/coverage/default/24.hmac_wipe_secret.2397437692 Jun 07 07:16:03 PM PDT 24 Jun 07 07:16:19 PM PDT 24 392547324 ps
T580 /workspace/coverage/default/31.hmac_back_pressure.1407917994 Jun 07 07:16:20 PM PDT 24 Jun 07 07:17:15 PM PDT 24 1059259052 ps
T581 /workspace/coverage/default/39.hmac_error.1380201543 Jun 07 07:16:55 PM PDT 24 Jun 07 07:20:07 PM PDT 24 10285661627 ps
T582 /workspace/coverage/default/4.hmac_datapath_stress.119100695 Jun 07 07:15:13 PM PDT 24 Jun 07 07:27:10 PM PDT 24 3512565809 ps
T583 /workspace/coverage/default/16.hmac_datapath_stress.3558833679 Jun 07 07:15:39 PM PDT 24 Jun 07 07:25:44 PM PDT 24 2010705623 ps
T584 /workspace/coverage/default/10.hmac_datapath_stress.1629689185 Jun 07 07:15:32 PM PDT 24 Jun 07 07:31:39 PM PDT 24 14551365342 ps
T585 /workspace/coverage/default/31.hmac_test_hmac_vectors.3421954604 Jun 07 07:16:21 PM PDT 24 Jun 07 07:16:30 PM PDT 24 264498502 ps
T586 /workspace/coverage/default/35.hmac_test_hmac_vectors.3988393863 Jun 07 07:16:43 PM PDT 24 Jun 07 07:16:51 PM PDT 24 56148655 ps
T587 /workspace/coverage/default/5.hmac_test_sha_vectors.1995311697 Jun 07 07:15:27 PM PDT 24 Jun 07 07:24:01 PM PDT 24 27331837742 ps
T588 /workspace/coverage/default/1.hmac_alert_test.2330029750 Jun 07 07:15:03 PM PDT 24 Jun 07 07:15:06 PM PDT 24 13877518 ps
T589 /workspace/coverage/default/15.hmac_alert_test.2602666715 Jun 07 07:15:41 PM PDT 24 Jun 07 07:15:50 PM PDT 24 14723000 ps
T590 /workspace/coverage/default/6.hmac_long_msg.1031756167 Jun 07 07:15:28 PM PDT 24 Jun 07 07:15:48 PM PDT 24 636252717 ps
T591 /workspace/coverage/default/37.hmac_smoke.236287248 Jun 07 07:16:43 PM PDT 24 Jun 07 07:16:51 PM PDT 24 61614080 ps
T592 /workspace/coverage/default/34.hmac_wipe_secret.2154268435 Jun 07 07:16:29 PM PDT 24 Jun 07 07:17:07 PM PDT 24 2460331815 ps
T593 /workspace/coverage/default/2.hmac_burst_wr.1862269813 Jun 07 07:15:16 PM PDT 24 Jun 07 07:16:02 PM PDT 24 2799409530 ps
T72 /workspace/coverage/default/26.hmac_stress_all.456889602 Jun 07 07:16:11 PM PDT 24 Jun 07 08:35:08 PM PDT 24 343549000524 ps
T594 /workspace/coverage/default/28.hmac_datapath_stress.3201924159 Jun 07 07:16:09 PM PDT 24 Jun 07 07:19:08 PM PDT 24 1865309657 ps
T595 /workspace/coverage/default/49.hmac_smoke.3182534196 Jun 07 07:17:52 PM PDT 24 Jun 07 07:18:07 PM PDT 24 156926158 ps
T596 /workspace/coverage/default/23.hmac_back_pressure.3936900850 Jun 07 07:16:00 PM PDT 24 Jun 07 07:16:46 PM PDT 24 3264343355 ps
T597 /workspace/coverage/default/21.hmac_smoke.262032697 Jun 07 07:15:48 PM PDT 24 Jun 07 07:15:58 PM PDT 24 280482843 ps
T598 /workspace/coverage/cover_reg_top/24.hmac_intr_test.2208534286 Jun 07 07:12:11 PM PDT 24 Jun 07 07:12:28 PM PDT 24 35455684 ps
T55 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3362097032 Jun 07 07:11:59 PM PDT 24 Jun 07 07:12:18 PM PDT 24 41008201 ps
T56 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4038963 Jun 07 07:11:51 PM PDT 24 Jun 07 07:12:09 PM PDT 24 36016343 ps
T51 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2694213692 Jun 07 07:11:51 PM PDT 24 Jun 07 07:12:12 PM PDT 24 553433345 ps
T599 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2919081697 Jun 07 07:11:59 PM PDT 24 Jun 07 07:12:17 PM PDT 24 42481790 ps
T600 /workspace/coverage/cover_reg_top/25.hmac_intr_test.4201679635 Jun 07 07:12:12 PM PDT 24 Jun 07 07:12:28 PM PDT 24 17389747 ps
T73 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1586040731 Jun 07 07:12:01 PM PDT 24 Jun 07 07:12:22 PM PDT 24 105538240 ps
T601 /workspace/coverage/cover_reg_top/12.hmac_intr_test.3313837973 Jun 07 07:12:10 PM PDT 24 Jun 07 07:12:27 PM PDT 24 85486194 ps
T74 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3047216818 Jun 07 07:12:00 PM PDT 24 Jun 07 07:12:19 PM PDT 24 66354060 ps
T602 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3949249511 Jun 07 07:12:13 PM PDT 24 Jun 07 07:12:28 PM PDT 24 16795035 ps
T603 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1911948108 Jun 07 07:12:01 PM PDT 24 Jun 07 07:12:20 PM PDT 24 35973960 ps
T604 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2635022980 Jun 07 07:12:12 PM PDT 24 Jun 07 07:12:28 PM PDT 24 17549317 ps
T605 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2282278920 Jun 07 07:12:11 PM PDT 24 Jun 07 07:12:28 PM PDT 24 20096052 ps
T98 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2574555454 Jun 07 07:11:46 PM PDT 24 Jun 07 07:12:06 PM PDT 24 730861172 ps
T606 /workspace/coverage/cover_reg_top/48.hmac_intr_test.1678407171 Jun 07 07:12:14 PM PDT 24 Jun 07 07:12:29 PM PDT 24 11956158 ps
T52 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.647164983 Jun 07 07:11:46 PM PDT 24 Jun 07 07:12:03 PM PDT 24 207813614 ps
T607 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3456079537 Jun 07 07:11:54 PM PDT 24 Jun 07 07:12:13 PM PDT 24 254122104 ps
T608 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3324509066 Jun 07 07:11:52 PM PDT 24 Jun 07 07:12:10 PM PDT 24 18702857 ps
T53 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.189565779 Jun 07 07:11:52 PM PDT 24 Jun 07 07:12:10 PM PDT 24 174820079 ps
T75 /workspace/coverage/cover_reg_top/31.hmac_intr_test.1967214858 Jun 07 07:12:13 PM PDT 24 Jun 07 07:12:28 PM PDT 24 251942866 ps
T609 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3005324031 Jun 07 07:11:45 PM PDT 24 Jun 07 07:12:09 PM PDT 24 213306501 ps
T610 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.747179038 Jun 07 07:12:00 PM PDT 24 Jun 07 07:12:21 PM PDT 24 162623142 ps
T611 /workspace/coverage/cover_reg_top/7.hmac_intr_test.1411346345 Jun 07 07:11:48 PM PDT 24 Jun 07 07:12:03 PM PDT 24 34930456 ps
T612 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2747411401 Jun 07 07:12:01 PM PDT 24 Jun 07 07:12:20 PM PDT 24 83107108 ps
T613 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1166908072 Jun 07 07:11:55 PM PDT 24 Jun 07 07:12:13 PM PDT 24 23915864 ps
T614 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4292235859 Jun 07 07:11:52 PM PDT 24 Jun 07 07:12:11 PM PDT 24 64580650 ps
T615 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3062472417 Jun 07 07:12:01 PM PDT 24 Jun 07 07:12:21 PM PDT 24 38539952 ps
T616 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3788311376 Jun 07 07:12:13 PM PDT 24 Jun 07 07:12:28 PM PDT 24 17705736 ps
T617 /workspace/coverage/cover_reg_top/35.hmac_intr_test.1077435697 Jun 07 07:12:14 PM PDT 24 Jun 07 07:12:29 PM PDT 24 20167161 ps
T618 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1568815424 Jun 07 07:12:13 PM PDT 24 Jun 07 07:12:29 PM PDT 24 55090943 ps
T619 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3480753423 Jun 07 07:11:56 PM PDT 24 Jun 07 07:12:16 PM PDT 24 140035371 ps
T620 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1520603911 Jun 07 07:12:10 PM PDT 24 Jun 07 07:12:29 PM PDT 24 386212871 ps
T621 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2526856978 Jun 07 07:12:14 PM PDT 24 Jun 07 07:12:30 PM PDT 24 28933180 ps
T622 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2982581395 Jun 07 07:11:52 PM PDT 24 Jun 07 07:12:10 PM PDT 24 461480379 ps
T111 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1132025446 Jun 07 07:12:01 PM PDT 24 Jun 07 07:12:24 PM PDT 24 531577566 ps
T623 /workspace/coverage/cover_reg_top/6.hmac_intr_test.995519821 Jun 07 07:11:57 PM PDT 24 Jun 07 07:12:14 PM PDT 24 21387629 ps
T624 /workspace/coverage/cover_reg_top/26.hmac_intr_test.400370690 Jun 07 07:12:17 PM PDT 24 Jun 07 07:12:31 PM PDT 24 35255172 ps
T625 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1631804361 Jun 07 07:12:01 PM PDT 24 Jun 07 07:12:20 PM PDT 24 123291955 ps
T626 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.449297390 Jun 07 07:11:50 PM PDT 24 Jun 07 07:12:15 PM PDT 24 213980628 ps
T90 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3683779443 Jun 07 07:11:54 PM PDT 24 Jun 07 07:12:13 PM PDT 24 17923780 ps
T627 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1261948655 Jun 07 07:11:53 PM PDT 24 Jun 07 07:13:51 PM PDT 24 61833743178 ps
T115 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3599781975 Jun 07 07:11:59 PM PDT 24 Jun 07 07:12:20 PM PDT 24 152711667 ps
T113 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3206241591 Jun 07 07:12:01 PM PDT 24 Jun 07 07:12:21 PM PDT 24 718186562 ps
T628 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3817260034 Jun 07 07:11:54 PM PDT 24 Jun 07 07:12:11 PM PDT 24 51227752 ps
T114 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2638383574 Jun 07 07:12:01 PM PDT 24 Jun 07 07:12:22 PM PDT 24 140287425 ps
T629 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2849870594 Jun 07 07:11:59 PM PDT 24 Jun 07 07:12:18 PM PDT 24 223418766 ps
T630 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.969308246 Jun 07 07:11:50 PM PDT 24 Jun 07 07:12:08 PM PDT 24 35262822 ps
T91 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1700591229 Jun 07 07:12:01 PM PDT 24 Jun 07 07:12:20 PM PDT 24 74038734 ps
T631 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.4041410003 Jun 07 07:11:45 PM PDT 24 Jun 07 07:12:01 PM PDT 24 34199762 ps
T632 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.303943810 Jun 07 07:12:01 PM PDT 24 Jun 07 07:12:20 PM PDT 24 327271416 ps
T633 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1245343782 Jun 07 07:11:52 PM PDT 24 Jun 07 07:12:10 PM PDT 24 75197887 ps
T634 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2386391333 Jun 07 07:11:52 PM PDT 24 Jun 07 07:12:11 PM PDT 24 576440543 ps
T635 /workspace/coverage/cover_reg_top/17.hmac_intr_test.3893642463 Jun 07 07:12:01 PM PDT 24 Jun 07 07:12:19 PM PDT 24 45142289 ps
T636 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.206408284 Jun 07 07:11:59 PM PDT 24 Jun 07 07:12:19 PM PDT 24 230372199 ps
T120 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2489292621 Jun 07 07:11:50 PM PDT 24 Jun 07 07:12:10 PM PDT 24 751380927 ps
T637 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3246078025 Jun 07 07:12:00 PM PDT 24 Jun 07 07:12:18 PM PDT 24 10158975 ps
T638 /workspace/coverage/cover_reg_top/9.hmac_intr_test.3622414197 Jun 07 07:11:57 PM PDT 24 Jun 07 07:12:14 PM PDT 24 48134862 ps
T639 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.622784168 Jun 07 07:11:43 PM PDT 24 Jun 07 07:24:55 PM PDT 24 54857159985 ps
T640 /workspace/coverage/cover_reg_top/27.hmac_intr_test.891747909 Jun 07 07:12:14 PM PDT 24 Jun 07 07:12:30 PM PDT 24 11808799 ps
T641 /workspace/coverage/cover_reg_top/23.hmac_intr_test.3019611555 Jun 07 07:12:11 PM PDT 24 Jun 07 07:12:27 PM PDT 24 16683168 ps
T642 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1700913092 Jun 07 07:11:59 PM PDT 24 Jun 07 07:12:19 PM PDT 24 2020060326 ps
T643 /workspace/coverage/cover_reg_top/4.hmac_intr_test.1776499849 Jun 07 07:11:55 PM PDT 24 Jun 07 07:12:12 PM PDT 24 41995038 ps
T644 /workspace/coverage/cover_reg_top/40.hmac_intr_test.792127929 Jun 07 07:12:13 PM PDT 24 Jun 07 07:12:29 PM PDT 24 42630758 ps
T645 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2846313480 Jun 07 07:12:01 PM PDT 24 Jun 07 07:12:20 PM PDT 24 259807112 ps
T646 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.572754075 Jun 07 07:11:52 PM PDT 24 Jun 07 07:12:11 PM PDT 24 219944557 ps
T647 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1640080806 Jun 07 07:12:13 PM PDT 24 Jun 07 07:12:29 PM PDT 24 12738695 ps
T648 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3509689557 Jun 07 07:12:10 PM PDT 24 Jun 07 07:12:27 PM PDT 24 170736838 ps
T649 /workspace/coverage/cover_reg_top/29.hmac_intr_test.3506811339 Jun 07 07:12:14 PM PDT 24 Jun 07 07:12:30 PM PDT 24 53241922 ps
T116 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1409610056 Jun 07 07:12:00 PM PDT 24 Jun 07 07:12:21 PM PDT 24 1196325619 ps
T650 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.4102921310 Jun 07 07:12:01 PM PDT 24 Jun 07 07:12:23 PM PDT 24 280199184 ps
T651 /workspace/coverage/cover_reg_top/38.hmac_intr_test.1435865138 Jun 07 07:12:15 PM PDT 24 Jun 07 07:12:30 PM PDT 24 13592465 ps
T92 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2500931676 Jun 07 07:11:44 PM PDT 24 Jun 07 07:11:58 PM PDT 24 23477414 ps
T117 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.164770268 Jun 07 07:11:51 PM PDT 24 Jun 07 07:12:09 PM PDT 24 61731285 ps
T93 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.45047264 Jun 07 07:11:45 PM PDT 24 Jun 07 07:12:00 PM PDT 24 11778486 ps
T652 /workspace/coverage/cover_reg_top/18.hmac_intr_test.632067914 Jun 07 07:11:59 PM PDT 24 Jun 07 07:12:17 PM PDT 24 49491478 ps
T653 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.694716617 Jun 07 07:11:45 PM PDT 24 Jun 07 07:12:01 PM PDT 24 74336303 ps
T94 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.436526339 Jun 07 07:11:47 PM PDT 24 Jun 07 07:12:11 PM PDT 24 301332521 ps
T654 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3562292228 Jun 07 07:11:59 PM PDT 24 Jun 07 07:12:16 PM PDT 24 29649541 ps
T95 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4173597488 Jun 07 07:11:53 PM PDT 24 Jun 07 07:12:14 PM PDT 24 158462856 ps
T655 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2069716553 Jun 07 07:11:59 PM PDT 24 Jun 07 07:12:22 PM PDT 24 105272112 ps
T656 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.4255805573 Jun 07 07:11:53 PM PDT 24 Jun 07 07:12:12 PM PDT 24 58959003 ps
T657 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.4209655165 Jun 07 07:12:01 PM PDT 24 Jun 07 07:12:21 PM PDT 24 192575443 ps
T658 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.358878962 Jun 07 07:12:00 PM PDT 24 Jun 07 07:12:19 PM PDT 24 116433628 ps
T659 /workspace/coverage/cover_reg_top/47.hmac_intr_test.338847643 Jun 07 07:12:14 PM PDT 24 Jun 07 07:12:29 PM PDT 24 15943663 ps
T96 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2299626983 Jun 07 07:11:54 PM PDT 24 Jun 07 07:12:12 PM PDT 24 29746535 ps
T660 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.62517785 Jun 07 07:11:58 PM PDT 24 Jun 07 07:12:18 PM PDT 24 213533580 ps
T121 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.4119189879 Jun 07 07:11:59 PM PDT 24 Jun 07 07:12:18 PM PDT 24 157557012 ps
T661 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1846232531 Jun 07 07:11:51 PM PDT 24 Jun 07 07:12:09 PM PDT 24 21794679 ps
T662 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.4057534075 Jun 07 07:11:50 PM PDT 24 Jun 07 07:12:08 PM PDT 24 31297974 ps
T663 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3355701032 Jun 07 07:11:48 PM PDT 24 Jun 07 07:12:06 PM PDT 24 172497531 ps
T664 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.294529839 Jun 07 07:11:50 PM PDT 24 Jun 07 07:12:07 PM PDT 24 275604370 ps
T665 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2361657190 Jun 07 07:11:56 PM PDT 24 Jun 07 07:12:15 PM PDT 24 271664981 ps
T666 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1744801536 Jun 07 07:11:52 PM PDT 24 Jun 07 07:12:12 PM PDT 24 77242687 ps
T97 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1806226776 Jun 07 07:11:42 PM PDT 24 Jun 07 07:11:56 PM PDT 24 63884728 ps
T667 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2962232636 Jun 07 07:12:17 PM PDT 24 Jun 07 07:12:31 PM PDT 24 55189866 ps
T668 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.416174970 Jun 07 07:11:52 PM PDT 24 Jun 07 07:12:10 PM PDT 24 69598925 ps
T99 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.256391584 Jun 07 07:11:44 PM PDT 24 Jun 07 07:12:08 PM PDT 24 538541887 ps
T669 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1073319108 Jun 07 07:12:13 PM PDT 24 Jun 07 07:12:29 PM PDT 24 32515510 ps
T670 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2025385898 Jun 07 07:11:59 PM PDT 24 Jun 07 07:12:17 PM PDT 24 110394593 ps
T671 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3493966121 Jun 07 07:11:54 PM PDT 24 Jun 07 07:12:13 PM PDT 24 170076818 ps
T672 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2421726657 Jun 07 07:12:15 PM PDT 24 Jun 07 07:12:30 PM PDT 24 16866182 ps
T673 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3782819292 Jun 07 07:11:51 PM PDT 24 Jun 07 07:12:07 PM PDT 24 292758915 ps
T674 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1466174794 Jun 07 07:11:58 PM PDT 24 Jun 07 07:12:15 PM PDT 24 32661662 ps
T675 /workspace/coverage/cover_reg_top/2.hmac_intr_test.1856578181 Jun 07 07:11:46 PM PDT 24 Jun 07 07:12:02 PM PDT 24 11937546 ps
T118 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.19105225 Jun 07 07:11:53 PM PDT 24 Jun 07 07:12:13 PM PDT 24 598962627 ps
T676 /workspace/coverage/cover_reg_top/10.hmac_intr_test.3428840603 Jun 07 07:11:56 PM PDT 24 Jun 07 07:12:14 PM PDT 24 180734343 ps
T677 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1503859049 Jun 07 07:12:03 PM PDT 24 Jun 07 07:12:21 PM PDT 24 14297511 ps
T678 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1158025916 Jun 07 07:12:10 PM PDT 24 Jun 07 07:12:29 PM PDT 24 198886709 ps
T679 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2782564176 Jun 07 07:12:00 PM PDT 24 Jun 07 07:12:19 PM PDT 24 112631884 ps
T680 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2363358800 Jun 07 07:11:52 PM PDT 24 Jun 07 07:12:15 PM PDT 24 547467760 ps
T100 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1026840976 Jun 07 07:11:45 PM PDT 24 Jun 07 07:12:00 PM PDT 24 61294047 ps
T681 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3858511985 Jun 07 07:11:57 PM PDT 24 Jun 07 07:12:14 PM PDT 24 20742340 ps
T682 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2207176892 Jun 07 07:11:50 PM PDT 24 Jun 07 07:12:07 PM PDT 24 51877658 ps
T683 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3333509500 Jun 07 07:11:58 PM PDT 24 Jun 07 07:12:18 PM PDT 24 244546902 ps
T684 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2830587294 Jun 07 07:11:55 PM PDT 24 Jun 07 07:12:14 PM PDT 24 12573963 ps
T685 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2606805550 Jun 07 07:11:50 PM PDT 24 Jun 07 07:12:07 PM PDT 24 71592904 ps
T686 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1095385258 Jun 07 07:11:50 PM PDT 24 Jun 07 07:12:07 PM PDT 24 76945237 ps
T687 /workspace/coverage/cover_reg_top/43.hmac_intr_test.1450808715 Jun 07 07:12:10 PM PDT 24 Jun 07 07:12:27 PM PDT 24 14397354 ps
T688 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3749449485 Jun 07 07:12:00 PM PDT 24 Jun 07 07:12:17 PM PDT 24 94455018 ps
T689 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.353879133 Jun 07 07:11:55 PM PDT 24 Jun 07 07:12:14 PM PDT 24 376643716 ps
T690 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2827491689 Jun 07 07:11:49 PM PDT 24 Jun 07 07:12:08 PM PDT 24 624059705 ps
T691 /workspace/coverage/cover_reg_top/3.hmac_intr_test.2541737809 Jun 07 07:11:51 PM PDT 24 Jun 07 07:12:08 PM PDT 24 10979724 ps
T122 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.4285128174 Jun 07 07:11:50 PM PDT 24 Jun 07 07:12:10 PM PDT 24 1328190646 ps
T692 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1540436109 Jun 07 07:11:59 PM PDT 24 Jun 07 07:12:17 PM PDT 24 142538449 ps
T693 /workspace/coverage/cover_reg_top/37.hmac_intr_test.880417109 Jun 07 07:12:13 PM PDT 24 Jun 07 07:12:28 PM PDT 24 14027952 ps
T694 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1230747829 Jun 07 07:11:48 PM PDT 24 Jun 07 07:17:56 PM PDT 24 143476957944 ps
T695 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2390216828 Jun 07 07:12:14 PM PDT 24 Jun 07 07:12:29 PM PDT 24 13560097 ps
T696 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3771114920 Jun 07 07:11:52 PM PDT 24 Jun 07 07:12:09 PM PDT 24 14942728 ps
T697 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3671703700 Jun 07 07:11:51 PM PDT 24 Jun 07 07:12:07 PM PDT 24 17510161 ps
T698 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2907790284 Jun 07 07:11:45 PM PDT 24 Jun 07 07:12:11 PM PDT 24 1444855612 ps
T699 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3686340227 Jun 07 07:12:13 PM PDT 24 Jun 07 07:12:28 PM PDT 24 45244632 ps
T700 /workspace/coverage/cover_reg_top/33.hmac_intr_test.1011957143 Jun 07 07:12:15 PM PDT 24 Jun 07 07:12:30 PM PDT 24 74050661 ps
T701 /workspace/coverage/cover_reg_top/49.hmac_intr_test.211726426 Jun 07 07:12:14 PM PDT 24 Jun 07 07:12:29 PM PDT 24 83096658 ps
T119 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3761532322 Jun 07 07:12:00 PM PDT 24 Jun 07 07:12:20 PM PDT 24 154052320 ps
T702 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2450744982 Jun 07 07:11:58 PM PDT 24 Jun 07 07:12:17 PM PDT 24 55028233 ps
T703 /workspace/coverage/cover_reg_top/22.hmac_intr_test.4272647730 Jun 07 07:12:14 PM PDT 24 Jun 07 07:12:29 PM PDT 24 31860776 ps
T704 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2030473985 Jun 07 07:11:54 PM PDT 24 Jun 07 07:12:11 PM PDT 24 32164418 ps
T705 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3622026180 Jun 07 07:11:54 PM PDT 24 Jun 07 07:12:12 PM PDT 24 363193707 ps
T706 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.180881608 Jun 07 07:11:55 PM PDT 24 Jun 07 07:12:14 PM PDT 24 49039771 ps
T707 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3330516076 Jun 07 07:12:10 PM PDT 24 Jun 07 07:12:27 PM PDT 24 30906830 ps
T708 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2483593335 Jun 07 07:11:49 PM PDT 24 Jun 07 07:12:05 PM PDT 24 90441880 ps
T709 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1046248703 Jun 07 07:11:43 PM PDT 24 Jun 07 07:11:57 PM PDT 24 33157262 ps
T710 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3440033120 Jun 07 07:12:14 PM PDT 24 Jun 07 07:12:30 PM PDT 24 17310512 ps
T711 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1647713251 Jun 07 07:12:00 PM PDT 24 Jun 07 07:12:20 PM PDT 24 731093168 ps
T712 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1850004043 Jun 07 07:11:59 PM PDT 24 Jun 07 07:12:18 PM PDT 24 119390887 ps
T713 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1379040389 Jun 07 07:11:59 PM PDT 24 Jun 07 07:12:17 PM PDT 24 71236876 ps
T714 /workspace/coverage/cover_reg_top/11.hmac_intr_test.2354951369 Jun 07 07:12:04 PM PDT 24 Jun 07 07:12:23 PM PDT 24 13209430 ps
T715 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3871054990 Jun 07 07:12:12 PM PDT 24 Jun 07 07:12:29 PM PDT 24 146890957 ps
T716 /workspace/coverage/cover_reg_top/30.hmac_intr_test.2371662885 Jun 07 07:12:13 PM PDT 24 Jun 07 07:12:28 PM PDT 24 70118457 ps
T717 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.4286788151 Jun 07 07:11:46 PM PDT 24 Jun 07 07:12:01 PM PDT 24 26324382 ps
T718 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2544131930 Jun 07 07:12:03 PM PDT 24 Jun 07 07:12:23 PM PDT 24 356492860 ps
T719 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2338856263 Jun 07 07:11:59 PM PDT 24 Jun 07 07:18:03 PM PDT 24 30299496364 ps
T720 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3060616672 Jun 07 07:12:10 PM PDT 24 Jun 07 07:12:27 PM PDT 24 13162667 ps
T721 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.204245549 Jun 07 07:11:59 PM PDT 24 Jun 07 07:12:19 PM PDT 24 76515069 ps
T722 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.44778007 Jun 07 07:11:46 PM PDT 24 Jun 07 07:12:05 PM PDT 24 75154168 ps
T723 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1938986887 Jun 07 07:11:49 PM PDT 24 Jun 07 07:12:05 PM PDT 24 66735194 ps
T123 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.4017336357 Jun 07 07:11:45 PM PDT 24 Jun 07 07:12:02 PM PDT 24 391554543 ps
T724 /workspace/coverage/cover_reg_top/28.hmac_intr_test.3297678608 Jun 07 07:12:17 PM PDT 24 Jun 07 07:12:31 PM PDT 24 99239956 ps
T725 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3504977087 Jun 07 07:11:59 PM PDT 24 Jun 07 07:12:21 PM PDT 24 136512786 ps
T726 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.742142583 Jun 07 07:12:00 PM PDT 24 Jun 07 07:12:21 PM PDT 24 194090728 ps
T727 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.803163183 Jun 07 07:12:01 PM PDT 24 Jun 07 07:12:23 PM PDT 24 61708911 ps
T112 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1702559021 Jun 07 07:11:46 PM PDT 24 Jun 07 07:12:04 PM PDT 24 4014802307 ps
T728 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.907216047 Jun 07 07:11:54 PM PDT 24 Jun 07 07:12:11 PM PDT 24 27855050 ps
T729 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1405250192 Jun 07 07:11:57 PM PDT 24 Jun 07 07:12:14 PM PDT 24 55203742 ps
T730 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3384085165 Jun 07 07:11:58 PM PDT 24 Jun 07 07:12:18 PM PDT 24 277155342 ps

Test location /workspace/coverage/default/11.hmac_wipe_secret.3686032573
Short name T7
Test name
Test status
Simulation time 5420734333 ps
CPU time 63.59 seconds
Started Jun 07 07:15:34 PM PDT 24
Finished Jun 07 07:16:44 PM PDT 24
Peak memory 200472 kb
Host smart-79010b3b-0a18-481b-80b3-02ca7e43855d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686032573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3686032573
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_stress_all_with_rand_reset.1515116199
Short name T24
Test name
Test status
Simulation time 40037298479 ps
CPU time 861.26 seconds
Started Jun 07 07:17:54 PM PDT 24
Finished Jun 07 07:32:26 PM PDT 24
Peak memory 216824 kb
Host smart-f47732a1-5162-46e1-8406-5c78afef0c4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1515116199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all_with_rand_reset.1515116199
Directory /workspace/49.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.667292722
Short name T19
Test name
Test status
Simulation time 6682339904 ps
CPU time 31.97 seconds
Started Jun 07 07:15:41 PM PDT 24
Finished Jun 07 07:16:21 PM PDT 24
Peak memory 210436 kb
Host smart-5ad025b9-92cd-41b8-9149-14ae7ffab222
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=667292722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.667292722
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3050753388
Short name T25
Test name
Test status
Simulation time 126787407 ps
CPU time 0.92 seconds
Started Jun 07 07:15:03 PM PDT 24
Finished Jun 07 07:15:06 PM PDT 24
Peak memory 218884 kb
Host smart-50dd8a28-8325-4579-8a9b-922b8d381536
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050753388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3050753388
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/61.hmac_stress_all_with_rand_reset.3400830938
Short name T10
Test name
Test status
Simulation time 133593017363 ps
CPU time 2320.66 seconds
Started Jun 07 07:17:53 PM PDT 24
Finished Jun 07 07:56:44 PM PDT 24
Peak memory 726524 kb
Host smart-3907cea1-6ad3-4eb5-b14c-59585d7c5bab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3400830938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.hmac_stress_all_with_rand_reset.3400830938
Directory /workspace/61.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.647164983
Short name T52
Test name
Test status
Simulation time 207813614 ps
CPU time 3.16 seconds
Started Jun 07 07:11:46 PM PDT 24
Finished Jun 07 07:12:03 PM PDT 24
Peak memory 199424 kb
Host smart-69d12a78-85cc-4612-a622-0668f3bd91d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647164983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.647164983
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/32.hmac_stress_all.605261564
Short name T16
Test name
Test status
Simulation time 12749011717 ps
CPU time 1545.7 seconds
Started Jun 07 07:16:28 PM PDT 24
Finished Jun 07 07:42:22 PM PDT 24
Peak memory 757532 kb
Host smart-f4c19092-3ffb-434e-a69f-d760231df09c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605261564 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.605261564
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_stress_all.521899212
Short name T54
Test name
Test status
Simulation time 231974599555 ps
CPU time 2244.08 seconds
Started Jun 07 07:16:52 PM PDT 24
Finished Jun 07 07:54:22 PM PDT 24
Peak memory 751892 kb
Host smart-ffae6a7e-69b2-4505-918d-6d8642e94929
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521899212 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.521899212
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_alert_test.580395570
Short name T20
Test name
Test status
Simulation time 41531331 ps
CPU time 0.57 seconds
Started Jun 07 07:15:08 PM PDT 24
Finished Jun 07 07:15:10 PM PDT 24
Peak memory 197140 kb
Host smart-e219dcec-a84e-492a-8f12-ae8cca9aa9b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580395570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.580395570
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3869292126
Short name T102
Test name
Test status
Simulation time 180788700280 ps
CPU time 2280.61 seconds
Started Jun 07 07:15:01 PM PDT 24
Finished Jun 07 07:53:04 PM PDT 24
Peak memory 700284 kb
Host smart-2106fb4d-5f0b-4211-a3ea-bc959d389027
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869292126 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3869292126
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.4106691331
Short name T26
Test name
Test status
Simulation time 439662464 ps
CPU time 27.41 seconds
Started Jun 07 07:17:01 PM PDT 24
Finished Jun 07 07:17:38 PM PDT 24
Peak memory 249580 kb
Host smart-a6978a5f-7e92-4351-a546-338d97c1e063
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4106691331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.4106691331
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2638383574
Short name T114
Test name
Test status
Simulation time 140287425 ps
CPU time 3.91 seconds
Started Jun 07 07:12:01 PM PDT 24
Finished Jun 07 07:12:22 PM PDT 24
Peak memory 199440 kb
Host smart-1a6d5e49-5680-4454-b758-206552f29341
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638383574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2638383574
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.742142583
Short name T726
Test name
Test status
Simulation time 194090728 ps
CPU time 3.13 seconds
Started Jun 07 07:12:00 PM PDT 24
Finished Jun 07 07:12:21 PM PDT 24
Peak memory 199464 kb
Host smart-643d4e80-f755-48a9-ab82-7097eca1b9f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742142583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.742142583
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2164779878
Short name T106
Test name
Test status
Simulation time 1975663480 ps
CPU time 470.32 seconds
Started Jun 07 07:15:41 PM PDT 24
Finished Jun 07 07:23:40 PM PDT 24
Peak memory 613800 kb
Host smart-4a8ce871-2964-42f0-b3ad-ca3979b264de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2164779878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2164779878
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_stress_all_with_rand_reset.4010617305
Short name T27
Test name
Test status
Simulation time 22591624159 ps
CPU time 667.17 seconds
Started Jun 07 07:15:40 PM PDT 24
Finished Jun 07 07:26:56 PM PDT 24
Peak memory 485944 kb
Host smart-2421822b-a1c1-48b6-bf48-be07e650d4d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4010617305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all_with_rand_reset.4010617305
Directory /workspace/17.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.256391584
Short name T99
Test name
Test status
Simulation time 538541887 ps
CPU time 8.99 seconds
Started Jun 07 07:11:44 PM PDT 24
Finished Jun 07 07:12:08 PM PDT 24
Peak memory 199368 kb
Host smart-85bc3f81-ee9e-4c6f-9993-46e5ac4a7047
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256391584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.256391584
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.577186358
Short name T61
Test name
Test status
Simulation time 733370419 ps
CPU time 20.73 seconds
Started Jun 07 07:15:03 PM PDT 24
Finished Jun 07 07:15:26 PM PDT 24
Peak memory 200408 kb
Host smart-7a8f4390-7979-4606-bd92-365d68c2e159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577186358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.577186358
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/126.hmac_stress_all_with_rand_reset.2946332977
Short name T11
Test name
Test status
Simulation time 38769334184 ps
CPU time 1211.24 seconds
Started Jun 07 07:17:56 PM PDT 24
Finished Jun 07 07:38:19 PM PDT 24
Peak memory 228968 kb
Host smart-419b210e-913b-4f2d-a5d2-6482e42403cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2946332977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.hmac_stress_all_with_rand_reset.2946332977
Directory /workspace/126.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/158.hmac_stress_all_with_rand_reset.3041141138
Short name T9
Test name
Test status
Simulation time 83295125541 ps
CPU time 5614.5 seconds
Started Jun 07 07:18:05 PM PDT 24
Finished Jun 07 08:51:53 PM PDT 24
Peak memory 806168 kb
Host smart-a0ad2e91-f22a-46f2-b2de-c14655986f61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3041141138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.hmac_stress_all_with_rand_reset.3041141138
Directory /workspace/158.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1556713879
Short name T47
Test name
Test status
Simulation time 623243961 ps
CPU time 7.71 seconds
Started Jun 07 07:15:41 PM PDT 24
Finished Jun 07 07:15:57 PM PDT 24
Peak memory 216536 kb
Host smart-5733ec2b-d748-4d04-9549-d3084b2877f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1556713879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1556713879
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3110080525
Short name T107
Test name
Test status
Simulation time 666136863146 ps
CPU time 5098.9 seconds
Started Jun 07 07:15:55 PM PDT 24
Finished Jun 07 08:41:04 PM PDT 24
Peak memory 833372 kb
Host smart-64c07d5e-5c41-45ca-8162-c3804c6c0d2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110080525 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3110080525
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2574555454
Short name T98
Test name
Test status
Simulation time 730861172 ps
CPU time 5.89 seconds
Started Jun 07 07:11:46 PM PDT 24
Finished Jun 07 07:12:06 PM PDT 24
Peak memory 199232 kb
Host smart-61d9b33c-4a08-4cef-a5aa-87ba25a5c7cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574555454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2574555454
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.4286788151
Short name T717
Test name
Test status
Simulation time 26324382 ps
CPU time 0.83 seconds
Started Jun 07 07:11:46 PM PDT 24
Finished Jun 07 07:12:01 PM PDT 24
Peak memory 198324 kb
Host smart-85a72663-df77-42c2-a15e-947ecec359ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286788151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.4286788151
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1230747829
Short name T694
Test name
Test status
Simulation time 143476957944 ps
CPU time 351.95 seconds
Started Jun 07 07:11:48 PM PDT 24
Finished Jun 07 07:17:56 PM PDT 24
Peak memory 215092 kb
Host smart-ec33c397-f431-4249-830e-e28f02acad98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230747829 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1230747829
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3324509066
Short name T608
Test name
Test status
Simulation time 18702857 ps
CPU time 0.7 seconds
Started Jun 07 07:11:52 PM PDT 24
Finished Jun 07 07:12:10 PM PDT 24
Peak memory 197304 kb
Host smart-4f52093c-b06c-49bd-8a1d-b22c029778ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324509066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3324509066
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2483593335
Short name T708
Test name
Test status
Simulation time 90441880 ps
CPU time 0.56 seconds
Started Jun 07 07:11:49 PM PDT 24
Finished Jun 07 07:12:05 PM PDT 24
Peak memory 194260 kb
Host smart-67b6a95e-d8bc-4ccf-85e5-1cd9be18bd08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483593335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2483593335
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1245343782
Short name T633
Test name
Test status
Simulation time 75197887 ps
CPU time 1.06 seconds
Started Jun 07 07:11:52 PM PDT 24
Finished Jun 07 07:12:10 PM PDT 24
Peak memory 198016 kb
Host smart-49cd3d9f-b5ce-4c5a-b6d6-c5b152a28418
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245343782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.1245343782
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.694716617
Short name T653
Test name
Test status
Simulation time 74336303 ps
CPU time 1.39 seconds
Started Jun 07 07:11:45 PM PDT 24
Finished Jun 07 07:12:01 PM PDT 24
Peak memory 199508 kb
Host smart-cd5a0001-15a6-4cb5-ac3f-477a8bb43bce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694716617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.694716617
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.436526339
Short name T94
Test name
Test status
Simulation time 301332521 ps
CPU time 8.41 seconds
Started Jun 07 07:11:47 PM PDT 24
Finished Jun 07 07:12:11 PM PDT 24
Peak memory 199124 kb
Host smart-b4785e20-3bb0-4b34-8be0-52455390ae5e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436526339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.436526339
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3005324031
Short name T609
Test name
Test status
Simulation time 213306501 ps
CPU time 10.08 seconds
Started Jun 07 07:11:45 PM PDT 24
Finished Jun 07 07:12:09 PM PDT 24
Peak memory 199312 kb
Host smart-98af2ab5-36c2-4a7a-8c8d-f23328367ded
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005324031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3005324031
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2500931676
Short name T92
Test name
Test status
Simulation time 23477414 ps
CPU time 0.72 seconds
Started Jun 07 07:11:44 PM PDT 24
Finished Jun 07 07:11:58 PM PDT 24
Peak memory 196996 kb
Host smart-81c23a63-1199-445f-97f6-b838f11ced9a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500931676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2500931676
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.622784168
Short name T639
Test name
Test status
Simulation time 54857159985 ps
CPU time 777.94 seconds
Started Jun 07 07:11:43 PM PDT 24
Finished Jun 07 07:24:55 PM PDT 24
Peak memory 215924 kb
Host smart-870428d7-1596-49f9-8169-ac993407a550
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622784168 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.622784168
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1806226776
Short name T97
Test name
Test status
Simulation time 63884728 ps
CPU time 0.91 seconds
Started Jun 07 07:11:42 PM PDT 24
Finished Jun 07 07:11:56 PM PDT 24
Peak memory 198708 kb
Host smart-b1a97952-c870-4892-9b6f-2fe9a98dc589
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806226776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1806226776
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1046248703
Short name T709
Test name
Test status
Simulation time 33157262 ps
CPU time 0.6 seconds
Started Jun 07 07:11:43 PM PDT 24
Finished Jun 07 07:11:57 PM PDT 24
Peak memory 194272 kb
Host smart-042cba1f-7eae-4932-80a3-38742115dcaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046248703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1046248703
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.4041410003
Short name T631
Test name
Test status
Simulation time 34199762 ps
CPU time 1.64 seconds
Started Jun 07 07:11:45 PM PDT 24
Finished Jun 07 07:12:01 PM PDT 24
Peak memory 199364 kb
Host smart-02fa6176-53a4-454d-9fc8-b0bae0b0237a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041410003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.4041410003
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3355701032
Short name T663
Test name
Test status
Simulation time 172497531 ps
CPU time 2.23 seconds
Started Jun 07 07:11:48 PM PDT 24
Finished Jun 07 07:12:06 PM PDT 24
Peak memory 199472 kb
Host smart-2ebac871-3e53-4389-a27b-8da4b8d0790a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355701032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3355701032
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1702559021
Short name T112
Test name
Test status
Simulation time 4014802307 ps
CPU time 4.38 seconds
Started Jun 07 07:11:46 PM PDT 24
Finished Jun 07 07:12:04 PM PDT 24
Peak memory 199428 kb
Host smart-17e882a2-7d36-4cba-83e4-1952501e22d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702559021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1702559021
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1911948108
Short name T603
Test name
Test status
Simulation time 35973960 ps
CPU time 1.18 seconds
Started Jun 07 07:12:01 PM PDT 24
Finished Jun 07 07:12:20 PM PDT 24
Peak memory 199140 kb
Host smart-f67d37cc-3345-46f4-8c50-2dfaac114a0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911948108 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.1911948108
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3771114920
Short name T696
Test name
Test status
Simulation time 14942728 ps
CPU time 0.8 seconds
Started Jun 07 07:11:52 PM PDT 24
Finished Jun 07 07:12:09 PM PDT 24
Peak memory 198488 kb
Host smart-cf90bcac-6adc-4290-b49a-bbf94ba1601d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771114920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3771114920
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3428840603
Short name T676
Test name
Test status
Simulation time 180734343 ps
CPU time 0.59 seconds
Started Jun 07 07:11:56 PM PDT 24
Finished Jun 07 07:12:14 PM PDT 24
Peak memory 194252 kb
Host smart-be7f1296-b2e7-4b89-b04e-4b2946b8e555
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428840603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3428840603
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.180881608
Short name T706
Test name
Test status
Simulation time 49039771 ps
CPU time 2.32 seconds
Started Jun 07 07:11:55 PM PDT 24
Finished Jun 07 07:12:14 PM PDT 24
Peak memory 199460 kb
Host smart-94e6a867-54a1-407b-9e8e-194ca8e6564d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180881608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr
_outstanding.180881608
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.4255805573
Short name T656
Test name
Test status
Simulation time 58959003 ps
CPU time 1.33 seconds
Started Jun 07 07:11:53 PM PDT 24
Finished Jun 07 07:12:12 PM PDT 24
Peak memory 199432 kb
Host smart-6085c1d0-60f2-4b9d-86b8-3cfd72da955b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255805573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.4255805573
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3761532322
Short name T119
Test name
Test status
Simulation time 154052320 ps
CPU time 3.05 seconds
Started Jun 07 07:12:00 PM PDT 24
Finished Jun 07 07:12:20 PM PDT 24
Peak memory 199364 kb
Host smart-a359d6de-0bea-4128-b6d7-7538eff94eca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761532322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3761532322
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.62517785
Short name T660
Test name
Test status
Simulation time 213533580 ps
CPU time 3.51 seconds
Started Jun 07 07:11:58 PM PDT 24
Finished Jun 07 07:12:18 PM PDT 24
Peak memory 215092 kb
Host smart-1570547d-6b50-43de-8b3b-5af3f0e99ab6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62517785 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.62517785
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3858511985
Short name T681
Test name
Test status
Simulation time 20742340 ps
CPU time 0.72 seconds
Started Jun 07 07:11:57 PM PDT 24
Finished Jun 07 07:12:14 PM PDT 24
Peak memory 197076 kb
Host smart-44f4bc46-e706-4e7e-92e1-2364550c23e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858511985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3858511985
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2354951369
Short name T714
Test name
Test status
Simulation time 13209430 ps
CPU time 0.61 seconds
Started Jun 07 07:12:04 PM PDT 24
Finished Jun 07 07:12:23 PM PDT 24
Peak memory 194204 kb
Host smart-78da5ce2-a2a7-4ed1-b968-0436e3d10a13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354951369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2354951369
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2782564176
Short name T679
Test name
Test status
Simulation time 112631884 ps
CPU time 1.16 seconds
Started Jun 07 07:12:00 PM PDT 24
Finished Jun 07 07:12:19 PM PDT 24
Peak memory 197860 kb
Host smart-bb7f348e-612c-47cf-b821-b8778c95b87b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782564176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2782564176
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.803163183
Short name T727
Test name
Test status
Simulation time 61708911 ps
CPU time 3.12 seconds
Started Jun 07 07:12:01 PM PDT 24
Finished Jun 07 07:12:23 PM PDT 24
Peak memory 199452 kb
Host smart-db40f759-1006-4960-9017-46081260c23b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803163183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.803163183
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2069716553
Short name T655
Test name
Test status
Simulation time 105272112 ps
CPU time 3.58 seconds
Started Jun 07 07:11:59 PM PDT 24
Finished Jun 07 07:12:22 PM PDT 24
Peak memory 199468 kb
Host smart-ea2bb6d9-41a7-4235-b673-e8933168a362
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069716553 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.2069716553
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1379040389
Short name T713
Test name
Test status
Simulation time 71236876 ps
CPU time 0.95 seconds
Started Jun 07 07:11:59 PM PDT 24
Finished Jun 07 07:12:17 PM PDT 24
Peak memory 198920 kb
Host smart-3424f2d2-a106-42d5-91c5-c9c22bf9181f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379040389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1379040389
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.3313837973
Short name T601
Test name
Test status
Simulation time 85486194 ps
CPU time 0.57 seconds
Started Jun 07 07:12:10 PM PDT 24
Finished Jun 07 07:12:27 PM PDT 24
Peak memory 194228 kb
Host smart-9c697fd9-d121-4163-aa16-e248c9acc3a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313837973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3313837973
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3362097032
Short name T55
Test name
Test status
Simulation time 41008201 ps
CPU time 1.5 seconds
Started Jun 07 07:11:59 PM PDT 24
Finished Jun 07 07:12:18 PM PDT 24
Peak memory 199372 kb
Host smart-dec92266-4a2f-4787-a2a5-1d2abe3cad6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362097032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.3362097032
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2025385898
Short name T670
Test name
Test status
Simulation time 110394593 ps
CPU time 2.25 seconds
Started Jun 07 07:11:59 PM PDT 24
Finished Jun 07 07:12:17 PM PDT 24
Peak memory 199568 kb
Host smart-41c130a7-636f-401b-89de-a0c0e8b2458c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025385898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2025385898
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1409610056
Short name T116
Test name
Test status
Simulation time 1196325619 ps
CPU time 4.39 seconds
Started Jun 07 07:12:00 PM PDT 24
Finished Jun 07 07:12:21 PM PDT 24
Peak memory 199472 kb
Host smart-723e61d8-90f8-49d5-8ef0-878dff0d54ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409610056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1409610056
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1520603911
Short name T620
Test name
Test status
Simulation time 386212871 ps
CPU time 2.62 seconds
Started Jun 07 07:12:10 PM PDT 24
Finished Jun 07 07:12:29 PM PDT 24
Peak memory 207704 kb
Host smart-41ef55f2-fd1d-4770-b03d-5cad7a3189e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520603911 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1520603911
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1405250192
Short name T729
Test name
Test status
Simulation time 55203742 ps
CPU time 1.01 seconds
Started Jun 07 07:11:57 PM PDT 24
Finished Jun 07 07:12:14 PM PDT 24
Peak memory 199084 kb
Host smart-8b41313c-fa33-4f1a-92f3-29f1f2f12fd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405250192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1405250192
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3060616672
Short name T720
Test name
Test status
Simulation time 13162667 ps
CPU time 0.6 seconds
Started Jun 07 07:12:10 PM PDT 24
Finished Jun 07 07:12:27 PM PDT 24
Peak memory 194388 kb
Host smart-387615dc-56b8-4138-8c53-559b76949b6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060616672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3060616672
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2747411401
Short name T612
Test name
Test status
Simulation time 83107108 ps
CPU time 2.09 seconds
Started Jun 07 07:12:01 PM PDT 24
Finished Jun 07 07:12:20 PM PDT 24
Peak memory 199372 kb
Host smart-866617e8-f99f-4e96-b19f-f1eb0e23e546
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747411401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2747411401
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2450744982
Short name T702
Test name
Test status
Simulation time 55028233 ps
CPU time 2.68 seconds
Started Jun 07 07:11:58 PM PDT 24
Finished Jun 07 07:12:17 PM PDT 24
Peak memory 199440 kb
Host smart-80e90e98-c9fb-49d2-ba28-dfe6b4800bbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450744982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2450744982
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3599781975
Short name T115
Test name
Test status
Simulation time 152711667 ps
CPU time 3.17 seconds
Started Jun 07 07:11:59 PM PDT 24
Finished Jun 07 07:12:20 PM PDT 24
Peak memory 199460 kb
Host smart-f1e4912f-d43c-46c2-8445-c9bbc40e4f22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599781975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3599781975
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2338856263
Short name T719
Test name
Test status
Simulation time 30299496364 ps
CPU time 346.16 seconds
Started Jun 07 07:11:59 PM PDT 24
Finished Jun 07 07:18:03 PM PDT 24
Peak memory 215916 kb
Host smart-f4579372-9b4d-4489-835e-32a8f46c9ada
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338856263 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2338856263
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1700591229
Short name T91
Test name
Test status
Simulation time 74038734 ps
CPU time 0.8 seconds
Started Jun 07 07:12:01 PM PDT 24
Finished Jun 07 07:12:20 PM PDT 24
Peak memory 198916 kb
Host smart-f74551c3-d0cb-476c-b747-6b6809d909d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700591229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.1700591229
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1503859049
Short name T677
Test name
Test status
Simulation time 14297511 ps
CPU time 0.59 seconds
Started Jun 07 07:12:03 PM PDT 24
Finished Jun 07 07:12:21 PM PDT 24
Peak memory 194196 kb
Host smart-bff81812-1649-47fe-b862-b0241ce2bd0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503859049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1503859049
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3062472417
Short name T615
Test name
Test status
Simulation time 38539952 ps
CPU time 1.7 seconds
Started Jun 07 07:12:01 PM PDT 24
Finished Jun 07 07:12:21 PM PDT 24
Peak memory 199280 kb
Host smart-2ac334a3-0c21-43a2-9d48-77f887a4ce9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062472417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3062472417
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.4102921310
Short name T650
Test name
Test status
Simulation time 280199184 ps
CPU time 3.95 seconds
Started Jun 07 07:12:01 PM PDT 24
Finished Jun 07 07:12:23 PM PDT 24
Peak memory 199452 kb
Host smart-90133acf-7be8-4b17-8673-d0fc32a90d8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102921310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.4102921310
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3504977087
Short name T725
Test name
Test status
Simulation time 136512786 ps
CPU time 4.17 seconds
Started Jun 07 07:11:59 PM PDT 24
Finished Jun 07 07:12:21 PM PDT 24
Peak memory 199532 kb
Host smart-0588b6f9-53a3-4263-a7ab-a619c034ee18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504977087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3504977087
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1586040731
Short name T73
Test name
Test status
Simulation time 105538240 ps
CPU time 2.41 seconds
Started Jun 07 07:12:01 PM PDT 24
Finished Jun 07 07:12:22 PM PDT 24
Peak memory 199400 kb
Host smart-33a7f2b3-1e28-4204-9f23-df80101a6f10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586040731 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1586040731
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3047216818
Short name T74
Test name
Test status
Simulation time 66354060 ps
CPU time 0.94 seconds
Started Jun 07 07:12:00 PM PDT 24
Finished Jun 07 07:12:19 PM PDT 24
Peak memory 199156 kb
Host smart-de674f30-9627-4a7a-8b55-01c0db166615
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047216818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3047216818
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1466174794
Short name T674
Test name
Test status
Simulation time 32661662 ps
CPU time 0.58 seconds
Started Jun 07 07:11:58 PM PDT 24
Finished Jun 07 07:12:15 PM PDT 24
Peak memory 194260 kb
Host smart-2343aa2b-e39d-4f05-a5ee-0465dc6b2845
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466174794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1466174794
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.4209655165
Short name T657
Test name
Test status
Simulation time 192575443 ps
CPU time 2.27 seconds
Started Jun 07 07:12:01 PM PDT 24
Finished Jun 07 07:12:21 PM PDT 24
Peak memory 199432 kb
Host smart-5945ad6d-0eb9-4ae9-a013-70c6c0dc2407
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209655165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.4209655165
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.747179038
Short name T610
Test name
Test status
Simulation time 162623142 ps
CPU time 2.96 seconds
Started Jun 07 07:12:00 PM PDT 24
Finished Jun 07 07:12:21 PM PDT 24
Peak memory 199452 kb
Host smart-de7cbd18-d8e6-49f7-aca9-81028e7b7864
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747179038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.747179038
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.4119189879
Short name T121
Test name
Test status
Simulation time 157557012 ps
CPU time 2.98 seconds
Started Jun 07 07:11:59 PM PDT 24
Finished Jun 07 07:12:18 PM PDT 24
Peak memory 199412 kb
Host smart-9bc4dced-24be-4c67-83e5-2165364a3f6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119189879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.4119189879
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2849870594
Short name T629
Test name
Test status
Simulation time 223418766 ps
CPU time 1.71 seconds
Started Jun 07 07:11:59 PM PDT 24
Finished Jun 07 07:12:18 PM PDT 24
Peak memory 199420 kb
Host smart-aaa4900e-33d5-4ae4-8d0a-b79102270b30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849870594 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2849870594
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3749449485
Short name T688
Test name
Test status
Simulation time 94455018 ps
CPU time 0.84 seconds
Started Jun 07 07:12:00 PM PDT 24
Finished Jun 07 07:12:17 PM PDT 24
Peak memory 198712 kb
Host smart-b705a735-c417-40cd-a175-4a97d65e6a71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749449485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3749449485
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3246078025
Short name T637
Test name
Test status
Simulation time 10158975 ps
CPU time 0.57 seconds
Started Jun 07 07:12:00 PM PDT 24
Finished Jun 07 07:12:18 PM PDT 24
Peak memory 194316 kb
Host smart-a4350057-fdbc-40d1-b019-77164cb8cd7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246078025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3246078025
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.358878962
Short name T658
Test name
Test status
Simulation time 116433628 ps
CPU time 1.22 seconds
Started Jun 07 07:12:00 PM PDT 24
Finished Jun 07 07:12:19 PM PDT 24
Peak memory 198028 kb
Host smart-c9da9716-c1c5-4ab4-b038-7a02a2e88c52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358878962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr
_outstanding.358878962
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3509689557
Short name T648
Test name
Test status
Simulation time 170736838 ps
CPU time 1.17 seconds
Started Jun 07 07:12:10 PM PDT 24
Finished Jun 07 07:12:27 PM PDT 24
Peak memory 199424 kb
Host smart-3d9f127e-c9cc-40ea-9e88-579b1511050c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509689557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3509689557
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.204245549
Short name T721
Test name
Test status
Simulation time 76515069 ps
CPU time 2.42 seconds
Started Jun 07 07:11:59 PM PDT 24
Finished Jun 07 07:12:19 PM PDT 24
Peak memory 207672 kb
Host smart-0cc25810-51f9-4fc1-84b6-dcea6297c229
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204245549 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.204245549
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2846313480
Short name T645
Test name
Test status
Simulation time 259807112 ps
CPU time 0.84 seconds
Started Jun 07 07:12:01 PM PDT 24
Finished Jun 07 07:12:20 PM PDT 24
Peak memory 199148 kb
Host smart-5b8d0b22-ab52-4070-b6a6-87770b1de1f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846313480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2846313480
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.3893642463
Short name T635
Test name
Test status
Simulation time 45142289 ps
CPU time 0.58 seconds
Started Jun 07 07:12:01 PM PDT 24
Finished Jun 07 07:12:19 PM PDT 24
Peak memory 194252 kb
Host smart-3f584176-2bc5-4f28-b26f-618d137aeb15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893642463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3893642463
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1850004043
Short name T712
Test name
Test status
Simulation time 119390887 ps
CPU time 2.27 seconds
Started Jun 07 07:11:59 PM PDT 24
Finished Jun 07 07:12:18 PM PDT 24
Peak memory 199432 kb
Host smart-9b2dbcc0-582a-42a2-93be-0eda2cbfe033
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850004043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.1850004043
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1700913092
Short name T642
Test name
Test status
Simulation time 2020060326 ps
CPU time 2.57 seconds
Started Jun 07 07:11:59 PM PDT 24
Finished Jun 07 07:12:19 PM PDT 24
Peak memory 199464 kb
Host smart-6491990d-6b60-4291-a08d-a6e7fc77a8be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700913092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1700913092
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1132025446
Short name T111
Test name
Test status
Simulation time 531577566 ps
CPU time 4.51 seconds
Started Jun 07 07:12:01 PM PDT 24
Finished Jun 07 07:12:24 PM PDT 24
Peak memory 199420 kb
Host smart-8d46250c-fdb6-4564-8dce-36fd5d9d12ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132025446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1132025446
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.303943810
Short name T632
Test name
Test status
Simulation time 327271416 ps
CPU time 2.18 seconds
Started Jun 07 07:12:01 PM PDT 24
Finished Jun 07 07:12:20 PM PDT 24
Peak memory 199340 kb
Host smart-fe0b554f-cc1c-4020-9152-af296e392ae0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303943810 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.303943810
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3330516076
Short name T707
Test name
Test status
Simulation time 30906830 ps
CPU time 0.71 seconds
Started Jun 07 07:12:10 PM PDT 24
Finished Jun 07 07:12:27 PM PDT 24
Peak memory 197332 kb
Host smart-0b1efdc1-4a62-4dc5-b062-73329dbf59a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330516076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3330516076
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.632067914
Short name T652
Test name
Test status
Simulation time 49491478 ps
CPU time 0.6 seconds
Started Jun 07 07:11:59 PM PDT 24
Finished Jun 07 07:12:17 PM PDT 24
Peak memory 194296 kb
Host smart-e58c7767-4455-4bed-ba7d-52a23f14e998
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632067914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.632067914
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1631804361
Short name T625
Test name
Test status
Simulation time 123291955 ps
CPU time 2.16 seconds
Started Jun 07 07:12:01 PM PDT 24
Finished Jun 07 07:12:20 PM PDT 24
Peak memory 199452 kb
Host smart-32cb1598-57f0-44c0-963b-9055371be43e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631804361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.1631804361
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2544131930
Short name T718
Test name
Test status
Simulation time 356492860 ps
CPU time 1.95 seconds
Started Jun 07 07:12:03 PM PDT 24
Finished Jun 07 07:12:23 PM PDT 24
Peak memory 199388 kb
Host smart-21d6d2eb-ba16-4d0e-b1a4-a17fea7f73b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544131930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2544131930
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3206241591
Short name T113
Test name
Test status
Simulation time 718186562 ps
CPU time 3.19 seconds
Started Jun 07 07:12:01 PM PDT 24
Finished Jun 07 07:12:21 PM PDT 24
Peak memory 199380 kb
Host smart-d6f958ff-dab6-41d9-b821-e08b23e2a1aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206241591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3206241591
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2526856978
Short name T621
Test name
Test status
Simulation time 28933180 ps
CPU time 1.18 seconds
Started Jun 07 07:12:14 PM PDT 24
Finished Jun 07 07:12:30 PM PDT 24
Peak memory 199256 kb
Host smart-611a25c6-82c2-4c2e-9034-99289b8e2928
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526856978 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.2526856978
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2635022980
Short name T604
Test name
Test status
Simulation time 17549317 ps
CPU time 0.8 seconds
Started Jun 07 07:12:12 PM PDT 24
Finished Jun 07 07:12:28 PM PDT 24
Peak memory 198944 kb
Host smart-24df7ca9-f16e-40a4-bb6e-07a0791f8337
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635022980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2635022980
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2919081697
Short name T599
Test name
Test status
Simulation time 42481790 ps
CPU time 0.57 seconds
Started Jun 07 07:11:59 PM PDT 24
Finished Jun 07 07:12:17 PM PDT 24
Peak memory 194276 kb
Host smart-b5d46a4b-e198-4c16-8c5a-ab56ec7f48b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919081697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2919081697
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3871054990
Short name T715
Test name
Test status
Simulation time 146890957 ps
CPU time 1.67 seconds
Started Jun 07 07:12:12 PM PDT 24
Finished Jun 07 07:12:29 PM PDT 24
Peak memory 199424 kb
Host smart-7ac5b553-9750-4651-ac75-23bef11eca79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871054990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3871054990
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1647713251
Short name T711
Test name
Test status
Simulation time 731093168 ps
CPU time 2.54 seconds
Started Jun 07 07:12:00 PM PDT 24
Finished Jun 07 07:12:20 PM PDT 24
Peak memory 199472 kb
Host smart-7d2f69a9-bb1e-4e1a-9c33-64209454e6b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647713251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1647713251
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1158025916
Short name T678
Test name
Test status
Simulation time 198886709 ps
CPU time 3.19 seconds
Started Jun 07 07:12:10 PM PDT 24
Finished Jun 07 07:12:29 PM PDT 24
Peak memory 199384 kb
Host smart-597fddab-5032-42ef-af57-720e984cace9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158025916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1158025916
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3333509500
Short name T683
Test name
Test status
Simulation time 244546902 ps
CPU time 3.12 seconds
Started Jun 07 07:11:58 PM PDT 24
Finished Jun 07 07:12:18 PM PDT 24
Peak memory 199056 kb
Host smart-5c92c7ce-714d-4d7d-9195-9229bd907f4d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333509500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3333509500
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2907790284
Short name T698
Test name
Test status
Simulation time 1444855612 ps
CPU time 10.66 seconds
Started Jun 07 07:11:45 PM PDT 24
Finished Jun 07 07:12:11 PM PDT 24
Peak memory 199336 kb
Host smart-ea4adfc3-f9c0-483e-9c2d-14525c3e2cae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907790284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2907790284
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1026840976
Short name T100
Test name
Test status
Simulation time 61294047 ps
CPU time 0.85 seconds
Started Jun 07 07:11:45 PM PDT 24
Finished Jun 07 07:12:00 PM PDT 24
Peak memory 198532 kb
Host smart-02256f32-2273-47d0-957b-e6ad46100383
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026840976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1026840976
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1540436109
Short name T692
Test name
Test status
Simulation time 142538449 ps
CPU time 2.46 seconds
Started Jun 07 07:11:59 PM PDT 24
Finished Jun 07 07:12:17 PM PDT 24
Peak memory 199396 kb
Host smart-07ea1314-bc7c-49f2-a592-2b5acb126fc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540436109 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1540436109
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.45047264
Short name T93
Test name
Test status
Simulation time 11778486 ps
CPU time 0.69 seconds
Started Jun 07 07:11:45 PM PDT 24
Finished Jun 07 07:12:00 PM PDT 24
Peak memory 197132 kb
Host smart-08a79ce7-6a6e-4bd6-b387-6ab6695cd3ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45047264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.45047264
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.1856578181
Short name T675
Test name
Test status
Simulation time 11937546 ps
CPU time 0.59 seconds
Started Jun 07 07:11:46 PM PDT 24
Finished Jun 07 07:12:02 PM PDT 24
Peak memory 194176 kb
Host smart-dec779b6-045e-49d9-a1c8-82f9c249df12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856578181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1856578181
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.969308246
Short name T630
Test name
Test status
Simulation time 35262822 ps
CPU time 1.65 seconds
Started Jun 07 07:11:50 PM PDT 24
Finished Jun 07 07:12:08 PM PDT 24
Peak memory 199392 kb
Host smart-4e84c4d0-30b5-4bf0-889b-52e88d0dc8fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969308246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_
outstanding.969308246
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.44778007
Short name T722
Test name
Test status
Simulation time 75154168 ps
CPU time 3.74 seconds
Started Jun 07 07:11:46 PM PDT 24
Finished Jun 07 07:12:05 PM PDT 24
Peak memory 199500 kb
Host smart-d9205f85-33bd-4f3e-bbf7-316c11869e6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44778007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.44778007
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.4017336357
Short name T123
Test name
Test status
Simulation time 391554543 ps
CPU time 1.79 seconds
Started Jun 07 07:11:45 PM PDT 24
Finished Jun 07 07:12:02 PM PDT 24
Peak memory 199348 kb
Host smart-46514a51-f89f-4977-b549-89a2311c4745
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017336357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.4017336357
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1640080806
Short name T647
Test name
Test status
Simulation time 12738695 ps
CPU time 0.61 seconds
Started Jun 07 07:12:13 PM PDT 24
Finished Jun 07 07:12:29 PM PDT 24
Peak memory 194252 kb
Host smart-4004e945-a1e7-47b5-ab4c-002364fc5c5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640080806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1640080806
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3440033120
Short name T710
Test name
Test status
Simulation time 17310512 ps
CPU time 0.63 seconds
Started Jun 07 07:12:14 PM PDT 24
Finished Jun 07 07:12:30 PM PDT 24
Peak memory 194200 kb
Host smart-7d01c4b6-5502-4dbd-8063-44b446ad8a06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440033120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3440033120
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.4272647730
Short name T703
Test name
Test status
Simulation time 31860776 ps
CPU time 0.57 seconds
Started Jun 07 07:12:14 PM PDT 24
Finished Jun 07 07:12:29 PM PDT 24
Peak memory 194312 kb
Host smart-3c039f30-c0f6-42e3-b33d-5aeec5d44d68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272647730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.4272647730
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.3019611555
Short name T641
Test name
Test status
Simulation time 16683168 ps
CPU time 0.63 seconds
Started Jun 07 07:12:11 PM PDT 24
Finished Jun 07 07:12:27 PM PDT 24
Peak memory 194204 kb
Host smart-abb87cc0-e34a-450a-8143-0ea78cb0b209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019611555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.3019611555
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2208534286
Short name T598
Test name
Test status
Simulation time 35455684 ps
CPU time 0.66 seconds
Started Jun 07 07:12:11 PM PDT 24
Finished Jun 07 07:12:28 PM PDT 24
Peak memory 194340 kb
Host smart-e01823dc-d6fe-4b30-8897-fc22d9e15e8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208534286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2208534286
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.4201679635
Short name T600
Test name
Test status
Simulation time 17389747 ps
CPU time 0.67 seconds
Started Jun 07 07:12:12 PM PDT 24
Finished Jun 07 07:12:28 PM PDT 24
Peak memory 194296 kb
Host smart-c4eb8cd9-ed26-43ab-bf83-ad875d8e585c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201679635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.4201679635
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.400370690
Short name T624
Test name
Test status
Simulation time 35255172 ps
CPU time 0.66 seconds
Started Jun 07 07:12:17 PM PDT 24
Finished Jun 07 07:12:31 PM PDT 24
Peak memory 194280 kb
Host smart-60722553-6c5b-4cdf-aea9-c4ed8a0962b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400370690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.400370690
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.891747909
Short name T640
Test name
Test status
Simulation time 11808799 ps
CPU time 0.62 seconds
Started Jun 07 07:12:14 PM PDT 24
Finished Jun 07 07:12:30 PM PDT 24
Peak memory 194260 kb
Host smart-ff85caac-75af-4d4f-a573-2bac3f10c711
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891747909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.891747909
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.3297678608
Short name T724
Test name
Test status
Simulation time 99239956 ps
CPU time 0.61 seconds
Started Jun 07 07:12:17 PM PDT 24
Finished Jun 07 07:12:31 PM PDT 24
Peak memory 194336 kb
Host smart-025dd62c-fc78-4bff-af1c-5c4aa0b810f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297678608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3297678608
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3506811339
Short name T649
Test name
Test status
Simulation time 53241922 ps
CPU time 0.6 seconds
Started Jun 07 07:12:14 PM PDT 24
Finished Jun 07 07:12:30 PM PDT 24
Peak memory 194280 kb
Host smart-b268e13c-24b6-4d87-bffe-6c47499adc8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506811339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3506811339
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4173597488
Short name T95
Test name
Test status
Simulation time 158462856 ps
CPU time 3.36 seconds
Started Jun 07 07:11:53 PM PDT 24
Finished Jun 07 07:12:14 PM PDT 24
Peak memory 199372 kb
Host smart-b5ffc199-a135-430d-9b4f-2eeb73519d23
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173597488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.4173597488
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.449297390
Short name T626
Test name
Test status
Simulation time 213980628 ps
CPU time 9.4 seconds
Started Jun 07 07:11:50 PM PDT 24
Finished Jun 07 07:12:15 PM PDT 24
Peak memory 198492 kb
Host smart-e74ad202-7cff-4cf7-bf78-04972b65c9f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449297390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.449297390
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3782819292
Short name T673
Test name
Test status
Simulation time 292758915 ps
CPU time 0.87 seconds
Started Jun 07 07:11:51 PM PDT 24
Finished Jun 07 07:12:07 PM PDT 24
Peak memory 198584 kb
Host smart-24067498-16b9-4598-9179-96e8345ee27a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782819292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3782819292
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.416174970
Short name T668
Test name
Test status
Simulation time 69598925 ps
CPU time 1.75 seconds
Started Jun 07 07:11:52 PM PDT 24
Finished Jun 07 07:12:10 PM PDT 24
Peak memory 199492 kb
Host smart-4f1e6994-546f-46f7-8cfd-66c1b9554817
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416174970 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.416174970
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3683779443
Short name T90
Test name
Test status
Simulation time 17923780 ps
CPU time 0.98 seconds
Started Jun 07 07:11:54 PM PDT 24
Finished Jun 07 07:12:13 PM PDT 24
Peak memory 198940 kb
Host smart-447fd167-65d4-475f-994d-2a493ba5a4f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683779443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3683779443
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2541737809
Short name T691
Test name
Test status
Simulation time 10979724 ps
CPU time 0.56 seconds
Started Jun 07 07:11:51 PM PDT 24
Finished Jun 07 07:12:08 PM PDT 24
Peak memory 194264 kb
Host smart-d9a98c84-bf02-45f0-a157-8efa63dee587
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541737809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2541737809
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4038963
Short name T56
Test name
Test status
Simulation time 36016343 ps
CPU time 1.48 seconds
Started Jun 07 07:11:51 PM PDT 24
Finished Jun 07 07:12:09 PM PDT 24
Peak memory 199376 kb
Host smart-d155bb9d-0545-4037-94e3-75509d332d16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_ou
tstanding.4038963
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2386391333
Short name T634
Test name
Test status
Simulation time 576440543 ps
CPU time 2.94 seconds
Started Jun 07 07:11:52 PM PDT 24
Finished Jun 07 07:12:11 PM PDT 24
Peak memory 199444 kb
Host smart-5035dc19-49f8-43de-9ff7-cee28848661c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386391333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2386391333
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2489292621
Short name T120
Test name
Test status
Simulation time 751380927 ps
CPU time 4.33 seconds
Started Jun 07 07:11:50 PM PDT 24
Finished Jun 07 07:12:10 PM PDT 24
Peak memory 199420 kb
Host smart-92f0cbc8-cefb-41a9-a0a4-6e9b514af3f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489292621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2489292621
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.2371662885
Short name T716
Test name
Test status
Simulation time 70118457 ps
CPU time 0.58 seconds
Started Jun 07 07:12:13 PM PDT 24
Finished Jun 07 07:12:28 PM PDT 24
Peak memory 194244 kb
Host smart-def63380-3d76-444c-8a43-2062a55e70cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371662885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2371662885
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1967214858
Short name T75
Test name
Test status
Simulation time 251942866 ps
CPU time 0.66 seconds
Started Jun 07 07:12:13 PM PDT 24
Finished Jun 07 07:12:28 PM PDT 24
Peak memory 194260 kb
Host smart-1b8582a8-a61f-4de7-bd17-e327b459b72e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967214858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1967214858
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3788311376
Short name T616
Test name
Test status
Simulation time 17705736 ps
CPU time 0.59 seconds
Started Jun 07 07:12:13 PM PDT 24
Finished Jun 07 07:12:28 PM PDT 24
Peak memory 194312 kb
Host smart-57b6c3b8-73db-43f2-9ed4-df663b820af8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788311376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3788311376
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.1011957143
Short name T700
Test name
Test status
Simulation time 74050661 ps
CPU time 0.61 seconds
Started Jun 07 07:12:15 PM PDT 24
Finished Jun 07 07:12:30 PM PDT 24
Peak memory 194252 kb
Host smart-146ab21c-6b62-430a-9851-124ea76cb77f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011957143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1011957143
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1073319108
Short name T669
Test name
Test status
Simulation time 32515510 ps
CPU time 0.6 seconds
Started Jun 07 07:12:13 PM PDT 24
Finished Jun 07 07:12:29 PM PDT 24
Peak memory 194184 kb
Host smart-0aee7171-48ae-41d9-82e5-8f4fec7c2cf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073319108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1073319108
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1077435697
Short name T617
Test name
Test status
Simulation time 20167161 ps
CPU time 0.66 seconds
Started Jun 07 07:12:14 PM PDT 24
Finished Jun 07 07:12:29 PM PDT 24
Peak memory 194260 kb
Host smart-d4c85342-3126-48ee-bc50-64f1016cc7bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077435697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1077435697
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2962232636
Short name T667
Test name
Test status
Simulation time 55189866 ps
CPU time 0.62 seconds
Started Jun 07 07:12:17 PM PDT 24
Finished Jun 07 07:12:31 PM PDT 24
Peak memory 194320 kb
Host smart-30606e03-698e-4843-b979-35e1e808857b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962232636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2962232636
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.880417109
Short name T693
Test name
Test status
Simulation time 14027952 ps
CPU time 0.63 seconds
Started Jun 07 07:12:13 PM PDT 24
Finished Jun 07 07:12:28 PM PDT 24
Peak memory 194356 kb
Host smart-de9bb7eb-6cab-4d0f-aa38-4d11429c2c8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880417109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.880417109
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.1435865138
Short name T651
Test name
Test status
Simulation time 13592465 ps
CPU time 0.56 seconds
Started Jun 07 07:12:15 PM PDT 24
Finished Jun 07 07:12:30 PM PDT 24
Peak memory 194236 kb
Host smart-f98e21e7-bc01-4dfa-9793-a76fffa66174
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435865138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1435865138
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1568815424
Short name T618
Test name
Test status
Simulation time 55090943 ps
CPU time 0.65 seconds
Started Jun 07 07:12:13 PM PDT 24
Finished Jun 07 07:12:29 PM PDT 24
Peak memory 194348 kb
Host smart-8f1c2a67-1b67-49a1-8f20-82f507548a79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568815424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1568815424
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2827491689
Short name T690
Test name
Test status
Simulation time 624059705 ps
CPU time 3.41 seconds
Started Jun 07 07:11:49 PM PDT 24
Finished Jun 07 07:12:08 PM PDT 24
Peak memory 198420 kb
Host smart-4d8fba03-76d4-4299-9995-56cf53c0f6df
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827491689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2827491689
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2363358800
Short name T680
Test name
Test status
Simulation time 547467760 ps
CPU time 6.16 seconds
Started Jun 07 07:11:52 PM PDT 24
Finished Jun 07 07:12:15 PM PDT 24
Peak memory 199164 kb
Host smart-ed7f19d2-b56b-4879-b7b9-e1777d86233e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363358800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2363358800
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1938986887
Short name T723
Test name
Test status
Simulation time 66735194 ps
CPU time 0.96 seconds
Started Jun 07 07:11:49 PM PDT 24
Finished Jun 07 07:12:05 PM PDT 24
Peak memory 199116 kb
Host smart-14e3a94d-9510-4a4b-be27-9f54db6084c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938986887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1938986887
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3493966121
Short name T671
Test name
Test status
Simulation time 170076818 ps
CPU time 1.96 seconds
Started Jun 07 07:11:54 PM PDT 24
Finished Jun 07 07:12:13 PM PDT 24
Peak memory 199260 kb
Host smart-a95b8d27-4c05-47f9-8baa-6e528911b075
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493966121 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3493966121
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2030473985
Short name T704
Test name
Test status
Simulation time 32164418 ps
CPU time 0.73 seconds
Started Jun 07 07:11:54 PM PDT 24
Finished Jun 07 07:12:11 PM PDT 24
Peak memory 197440 kb
Host smart-313711b4-3b31-41e1-b4b5-5c92d9db1552
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030473985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2030473985
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.1776499849
Short name T643
Test name
Test status
Simulation time 41995038 ps
CPU time 0.59 seconds
Started Jun 07 07:11:55 PM PDT 24
Finished Jun 07 07:12:12 PM PDT 24
Peak memory 194080 kb
Host smart-57b746c3-9292-4e0e-a01f-9718577dce6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776499849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1776499849
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2207176892
Short name T682
Test name
Test status
Simulation time 51877658 ps
CPU time 1.09 seconds
Started Jun 07 07:11:50 PM PDT 24
Finished Jun 07 07:12:07 PM PDT 24
Peak memory 197956 kb
Host smart-7bc8ebb5-5a94-4c52-9d5a-e5791d208a74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207176892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.2207176892
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3384085165
Short name T730
Test name
Test status
Simulation time 277155342 ps
CPU time 2.79 seconds
Started Jun 07 07:11:58 PM PDT 24
Finished Jun 07 07:12:18 PM PDT 24
Peak memory 199448 kb
Host smart-8a964436-1703-4ae2-9fa1-b1f0b01d269e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384085165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3384085165
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.4285128174
Short name T122
Test name
Test status
Simulation time 1328190646 ps
CPU time 4.45 seconds
Started Jun 07 07:11:50 PM PDT 24
Finished Jun 07 07:12:10 PM PDT 24
Peak memory 199408 kb
Host smart-55d6b94d-6290-4e9c-8985-7e9677000306
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285128174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.4285128174
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.792127929
Short name T644
Test name
Test status
Simulation time 42630758 ps
CPU time 0.57 seconds
Started Jun 07 07:12:13 PM PDT 24
Finished Jun 07 07:12:29 PM PDT 24
Peak memory 194284 kb
Host smart-86b21ff6-c78c-47cd-9bf1-47cf22017b32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792127929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.792127929
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2421726657
Short name T672
Test name
Test status
Simulation time 16866182 ps
CPU time 0.62 seconds
Started Jun 07 07:12:15 PM PDT 24
Finished Jun 07 07:12:30 PM PDT 24
Peak memory 194360 kb
Host smart-c362d55d-5d49-4ddd-a079-1f68b61ae2bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421726657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2421726657
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3949249511
Short name T602
Test name
Test status
Simulation time 16795035 ps
CPU time 0.64 seconds
Started Jun 07 07:12:13 PM PDT 24
Finished Jun 07 07:12:28 PM PDT 24
Peak memory 194344 kb
Host smart-245e9dc1-9d4b-46d3-9f74-61a574d3e19b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949249511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3949249511
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.1450808715
Short name T687
Test name
Test status
Simulation time 14397354 ps
CPU time 0.61 seconds
Started Jun 07 07:12:10 PM PDT 24
Finished Jun 07 07:12:27 PM PDT 24
Peak memory 194292 kb
Host smart-091e4fad-d60b-41c1-86d3-a1e7154947fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450808715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1450808715
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2390216828
Short name T695
Test name
Test status
Simulation time 13560097 ps
CPU time 0.66 seconds
Started Jun 07 07:12:14 PM PDT 24
Finished Jun 07 07:12:29 PM PDT 24
Peak memory 194316 kb
Host smart-71bbd8e8-f538-4ac0-96d9-ccd36cfaea94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390216828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2390216828
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2282278920
Short name T605
Test name
Test status
Simulation time 20096052 ps
CPU time 0.66 seconds
Started Jun 07 07:12:11 PM PDT 24
Finished Jun 07 07:12:28 PM PDT 24
Peak memory 194324 kb
Host smart-a960cb39-cef1-4a34-b7ba-83051119f439
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282278920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2282278920
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3686340227
Short name T699
Test name
Test status
Simulation time 45244632 ps
CPU time 0.63 seconds
Started Jun 07 07:12:13 PM PDT 24
Finished Jun 07 07:12:28 PM PDT 24
Peak memory 194272 kb
Host smart-f5a1d8b2-d9dd-4568-b8df-406cca2109e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686340227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3686340227
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.338847643
Short name T659
Test name
Test status
Simulation time 15943663 ps
CPU time 0.62 seconds
Started Jun 07 07:12:14 PM PDT 24
Finished Jun 07 07:12:29 PM PDT 24
Peak memory 194428 kb
Host smart-65baa170-0e0a-4c46-b7c2-3ab822ec8ffc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338847643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.338847643
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1678407171
Short name T606
Test name
Test status
Simulation time 11956158 ps
CPU time 0.61 seconds
Started Jun 07 07:12:14 PM PDT 24
Finished Jun 07 07:12:29 PM PDT 24
Peak memory 194308 kb
Host smart-30a20b63-f8a7-438e-a5bc-a365eddddf93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678407171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1678407171
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.211726426
Short name T701
Test name
Test status
Simulation time 83096658 ps
CPU time 0.6 seconds
Started Jun 07 07:12:14 PM PDT 24
Finished Jun 07 07:12:29 PM PDT 24
Peak memory 194232 kb
Host smart-a2a60554-1d6e-4abb-845f-52a0836ad83b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211726426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.211726426
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3480753423
Short name T619
Test name
Test status
Simulation time 140035371 ps
CPU time 2.37 seconds
Started Jun 07 07:11:56 PM PDT 24
Finished Jun 07 07:12:16 PM PDT 24
Peak memory 199488 kb
Host smart-6299fba4-1a6d-4096-9b71-c5f55e42dc24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480753423 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3480753423
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2830587294
Short name T684
Test name
Test status
Simulation time 12573963 ps
CPU time 0.83 seconds
Started Jun 07 07:11:55 PM PDT 24
Finished Jun 07 07:12:14 PM PDT 24
Peak memory 197460 kb
Host smart-55e85380-e235-42d1-a9da-0ec1015bf8fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830587294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2830587294
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3817260034
Short name T628
Test name
Test status
Simulation time 51227752 ps
CPU time 0.6 seconds
Started Jun 07 07:11:54 PM PDT 24
Finished Jun 07 07:12:11 PM PDT 24
Peak memory 194220 kb
Host smart-cb9f0edc-1fb5-4a09-84dd-5b1692fea1ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817260034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3817260034
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.294529839
Short name T664
Test name
Test status
Simulation time 275604370 ps
CPU time 1.26 seconds
Started Jun 07 07:11:50 PM PDT 24
Finished Jun 07 07:12:07 PM PDT 24
Peak memory 199176 kb
Host smart-c262250e-5f29-43ff-89ac-7db52a405df4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294529839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_
outstanding.294529839
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.572754075
Short name T646
Test name
Test status
Simulation time 219944557 ps
CPU time 2.96 seconds
Started Jun 07 07:11:52 PM PDT 24
Finished Jun 07 07:12:11 PM PDT 24
Peak memory 199364 kb
Host smart-eeeae3b3-d71e-4e9f-8327-543f70fb7256
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572754075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.572754075
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3622026180
Short name T705
Test name
Test status
Simulation time 363193707 ps
CPU time 1.86 seconds
Started Jun 07 07:11:54 PM PDT 24
Finished Jun 07 07:12:12 PM PDT 24
Peak memory 199428 kb
Host smart-22a37f2b-58d6-4eb4-aa63-d3b58b6672bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622026180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3622026180
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1261948655
Short name T627
Test name
Test status
Simulation time 61833743178 ps
CPU time 102.02 seconds
Started Jun 07 07:11:53 PM PDT 24
Finished Jun 07 07:13:51 PM PDT 24
Peak memory 215216 kb
Host smart-4043f9d9-1dab-4738-855a-e667d0f8dfd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261948655 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1261948655
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1095385258
Short name T686
Test name
Test status
Simulation time 76945237 ps
CPU time 0.81 seconds
Started Jun 07 07:11:50 PM PDT 24
Finished Jun 07 07:12:07 PM PDT 24
Peak memory 198572 kb
Host smart-bdb27653-1a6d-4a6d-8bd3-b7f32eac0a4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095385258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1095385258
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.995519821
Short name T623
Test name
Test status
Simulation time 21387629 ps
CPU time 0.58 seconds
Started Jun 07 07:11:57 PM PDT 24
Finished Jun 07 07:12:14 PM PDT 24
Peak memory 194252 kb
Host smart-c4a75129-160c-4b38-93d7-7199557e32e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995519821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.995519821
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2982581395
Short name T622
Test name
Test status
Simulation time 461480379 ps
CPU time 1.82 seconds
Started Jun 07 07:11:52 PM PDT 24
Finished Jun 07 07:12:10 PM PDT 24
Peak memory 199408 kb
Host smart-cf9f9882-b4e6-449a-b2c9-73abd27e6ed3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982581395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2982581395
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1744801536
Short name T666
Test name
Test status
Simulation time 77242687 ps
CPU time 3.99 seconds
Started Jun 07 07:11:52 PM PDT 24
Finished Jun 07 07:12:12 PM PDT 24
Peak memory 199452 kb
Host smart-49da1297-b177-467a-bac9-ccc97f6ce185
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744801536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1744801536
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2694213692
Short name T51
Test name
Test status
Simulation time 553433345 ps
CPU time 4.04 seconds
Started Jun 07 07:11:51 PM PDT 24
Finished Jun 07 07:12:12 PM PDT 24
Peak memory 199424 kb
Host smart-8a7c77fb-e519-437e-a900-0c68d3dc7d81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694213692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2694213692
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4292235859
Short name T614
Test name
Test status
Simulation time 64580650 ps
CPU time 1.8 seconds
Started Jun 07 07:11:52 PM PDT 24
Finished Jun 07 07:12:11 PM PDT 24
Peak memory 199460 kb
Host smart-fdbbb8ce-0c22-4c5a-b26d-f057b0930f93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292235859 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.4292235859
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3562292228
Short name T654
Test name
Test status
Simulation time 29649541 ps
CPU time 0.92 seconds
Started Jun 07 07:11:59 PM PDT 24
Finished Jun 07 07:12:16 PM PDT 24
Peak memory 199056 kb
Host smart-0d46b593-e534-4f85-8546-287ba7ba6ac6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562292228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3562292228
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1411346345
Short name T611
Test name
Test status
Simulation time 34930456 ps
CPU time 0.56 seconds
Started Jun 07 07:11:48 PM PDT 24
Finished Jun 07 07:12:03 PM PDT 24
Peak memory 194332 kb
Host smart-34b1b391-abb3-4569-ab65-1a0649d6f4fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411346345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1411346345
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1166908072
Short name T613
Test name
Test status
Simulation time 23915864 ps
CPU time 1.07 seconds
Started Jun 07 07:11:55 PM PDT 24
Finished Jun 07 07:12:13 PM PDT 24
Peak memory 197828 kb
Host smart-6569e36c-441d-49e3-b272-2b9791606d3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166908072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.1166908072
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.206408284
Short name T636
Test name
Test status
Simulation time 230372199 ps
CPU time 2.3 seconds
Started Jun 07 07:11:59 PM PDT 24
Finished Jun 07 07:12:19 PM PDT 24
Peak memory 199492 kb
Host smart-94ea082a-7b8b-427b-8354-2731be54497f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206408284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.206408284
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.19105225
Short name T118
Test name
Test status
Simulation time 598962627 ps
CPU time 3.96 seconds
Started Jun 07 07:11:53 PM PDT 24
Finished Jun 07 07:12:13 PM PDT 24
Peak memory 199404 kb
Host smart-280d0911-4241-4b1f-ad36-9b46dca0ae36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19105225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.19105225
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3456079537
Short name T607
Test name
Test status
Simulation time 254122104 ps
CPU time 1.99 seconds
Started Jun 07 07:11:54 PM PDT 24
Finished Jun 07 07:12:13 PM PDT 24
Peak memory 199464 kb
Host smart-fe19e9a2-0a67-40d9-b313-e4bc1b11c182
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456079537 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3456079537
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2299626983
Short name T96
Test name
Test status
Simulation time 29746535 ps
CPU time 0.97 seconds
Started Jun 07 07:11:54 PM PDT 24
Finished Jun 07 07:12:12 PM PDT 24
Peak memory 199140 kb
Host smart-d149528c-454e-4029-8b83-02a2081d519b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299626983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2299626983
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3671703700
Short name T697
Test name
Test status
Simulation time 17510161 ps
CPU time 0.62 seconds
Started Jun 07 07:11:51 PM PDT 24
Finished Jun 07 07:12:07 PM PDT 24
Peak memory 194364 kb
Host smart-1a94a301-e7cf-45f2-b9f9-ff3b87b710e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671703700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3671703700
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.353879133
Short name T689
Test name
Test status
Simulation time 376643716 ps
CPU time 1.88 seconds
Started Jun 07 07:11:55 PM PDT 24
Finished Jun 07 07:12:14 PM PDT 24
Peak memory 199108 kb
Host smart-8ca424a2-9cd2-4cd6-9613-7fff01b8c5a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353879133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_
outstanding.353879133
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2361657190
Short name T665
Test name
Test status
Simulation time 271664981 ps
CPU time 1.67 seconds
Started Jun 07 07:11:56 PM PDT 24
Finished Jun 07 07:12:15 PM PDT 24
Peak memory 199456 kb
Host smart-608798f3-3214-496b-9689-f0359e687a9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361657190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2361657190
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.164770268
Short name T117
Test name
Test status
Simulation time 61731285 ps
CPU time 1.72 seconds
Started Jun 07 07:11:51 PM PDT 24
Finished Jun 07 07:12:09 PM PDT 24
Peak memory 199464 kb
Host smart-b9f6a998-e3ba-4474-8d43-a57d95e3ec51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164770268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.164770268
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2606805550
Short name T685
Test name
Test status
Simulation time 71592904 ps
CPU time 1.21 seconds
Started Jun 07 07:11:50 PM PDT 24
Finished Jun 07 07:12:07 PM PDT 24
Peak memory 199268 kb
Host smart-26eadb13-f164-44f1-b69f-356b3ca4eebd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606805550 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2606805550
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.907216047
Short name T728
Test name
Test status
Simulation time 27855050 ps
CPU time 0.85 seconds
Started Jun 07 07:11:54 PM PDT 24
Finished Jun 07 07:12:11 PM PDT 24
Peak memory 198328 kb
Host smart-fd61bb2e-8d77-4154-ad51-5ebda4484c0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907216047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.907216047
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.3622414197
Short name T638
Test name
Test status
Simulation time 48134862 ps
CPU time 0.59 seconds
Started Jun 07 07:11:57 PM PDT 24
Finished Jun 07 07:12:14 PM PDT 24
Peak memory 194252 kb
Host smart-3db1b739-f88a-41ae-b59f-c6879a9911ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622414197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3622414197
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1846232531
Short name T661
Test name
Test status
Simulation time 21794679 ps
CPU time 1.11 seconds
Started Jun 07 07:11:51 PM PDT 24
Finished Jun 07 07:12:09 PM PDT 24
Peak memory 199188 kb
Host smart-7d378529-0d76-4a15-904d-02898f4761bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846232531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.1846232531
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.4057534075
Short name T662
Test name
Test status
Simulation time 31297974 ps
CPU time 1.72 seconds
Started Jun 07 07:11:50 PM PDT 24
Finished Jun 07 07:12:08 PM PDT 24
Peak memory 199432 kb
Host smart-9c31db27-af43-4dc3-abc4-f1a8883b4e18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057534075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.4057534075
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.189565779
Short name T53
Test name
Test status
Simulation time 174820079 ps
CPU time 1.65 seconds
Started Jun 07 07:11:52 PM PDT 24
Finished Jun 07 07:12:10 PM PDT 24
Peak memory 199420 kb
Host smart-00458e00-f864-4a74-979c-385dbe626fc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189565779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.189565779
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1999495937
Short name T143
Test name
Test status
Simulation time 31834221 ps
CPU time 0.58 seconds
Started Jun 07 07:15:08 PM PDT 24
Finished Jun 07 07:15:10 PM PDT 24
Peak memory 195964 kb
Host smart-ce233537-516e-410e-8e32-75c7bdbf10c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999495937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1999495937
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3224522298
Short name T49
Test name
Test status
Simulation time 817897806 ps
CPU time 17.57 seconds
Started Jun 07 07:15:02 PM PDT 24
Finished Jun 07 07:15:22 PM PDT 24
Peak memory 208620 kb
Host smart-53760f78-a8fa-4cf8-8937-1fb78a9ed2ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3224522298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3224522298
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.3622565667
Short name T168
Test name
Test status
Simulation time 2230973480 ps
CPU time 160.84 seconds
Started Jun 07 07:14:58 PM PDT 24
Finished Jun 07 07:17:41 PM PDT 24
Peak memory 600680 kb
Host smart-a0ca312f-5c19-4526-b0b0-b979f248e06c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3622565667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3622565667
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.3588402221
Short name T145
Test name
Test status
Simulation time 161896779 ps
CPU time 3.3 seconds
Started Jun 07 07:15:02 PM PDT 24
Finished Jun 07 07:15:08 PM PDT 24
Peak memory 200416 kb
Host smart-39ebe0d0-4d21-4409-88d7-731f7ffbb485
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588402221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.3588402221
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.4291510886
Short name T302
Test name
Test status
Simulation time 4578613887 ps
CPU time 64.73 seconds
Started Jun 07 07:15:03 PM PDT 24
Finished Jun 07 07:16:10 PM PDT 24
Peak memory 200432 kb
Host smart-79fd8855-c86d-46f0-82b2-ed477b16aaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291510886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.4291510886
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.22300650
Short name T459
Test name
Test status
Simulation time 765035291 ps
CPU time 7.99 seconds
Started Jun 07 07:15:02 PM PDT 24
Finished Jun 07 07:15:13 PM PDT 24
Peak memory 200384 kb
Host smart-9926bed6-9b5d-426b-a257-0f79821c19fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22300650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.22300650
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.1356872708
Short name T371
Test name
Test status
Simulation time 102188171 ps
CPU time 1.42 seconds
Started Jun 07 07:15:08 PM PDT 24
Finished Jun 07 07:15:11 PM PDT 24
Peak memory 200280 kb
Host smart-b243ea42-50cd-46c8-9848-5ecf004555c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356872708 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.1356872708
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.2799111628
Short name T62
Test name
Test status
Simulation time 114873867048 ps
CPU time 568.91 seconds
Started Jun 07 07:15:00 PM PDT 24
Finished Jun 07 07:24:31 PM PDT 24
Peak memory 200436 kb
Host smart-fca280ca-5770-45bc-905b-39460af10d98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799111628 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.2799111628
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.408883201
Short name T377
Test name
Test status
Simulation time 4345699435 ps
CPU time 53.98 seconds
Started Jun 07 07:15:01 PM PDT 24
Finished Jun 07 07:15:57 PM PDT 24
Peak memory 200456 kb
Host smart-8a7c99e9-b5a8-471d-8b13-9ae7b8353636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408883201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.408883201
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2330029750
Short name T588
Test name
Test status
Simulation time 13877518 ps
CPU time 0.61 seconds
Started Jun 07 07:15:03 PM PDT 24
Finished Jun 07 07:15:06 PM PDT 24
Peak memory 195348 kb
Host smart-80b27817-96cc-476c-b30b-15052f5581c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330029750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2330029750
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3653243811
Short name T321
Test name
Test status
Simulation time 531036029 ps
CPU time 17.15 seconds
Started Jun 07 07:15:05 PM PDT 24
Finished Jun 07 07:15:24 PM PDT 24
Peak memory 216832 kb
Host smart-d8cb3b9b-9af0-49fc-9a27-e3aa146bbf9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3653243811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3653243811
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.9289200
Short name T420
Test name
Test status
Simulation time 4531285943 ps
CPU time 21.34 seconds
Started Jun 07 07:15:00 PM PDT 24
Finished Jun 07 07:15:23 PM PDT 24
Peak memory 200536 kb
Host smart-7bee52e3-be5d-4d47-abbb-9571f8420ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9289200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.9289200
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2701537927
Short name T458
Test name
Test status
Simulation time 10189803210 ps
CPU time 602.03 seconds
Started Jun 07 07:15:02 PM PDT 24
Finished Jun 07 07:25:07 PM PDT 24
Peak memory 634560 kb
Host smart-591a19d9-10b9-47d9-9715-074de1b5a035
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2701537927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2701537927
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3911685518
Short name T37
Test name
Test status
Simulation time 3578329934 ps
CPU time 12.68 seconds
Started Jun 07 07:15:02 PM PDT 24
Finished Jun 07 07:15:17 PM PDT 24
Peak memory 200468 kb
Host smart-8880fb07-533a-432c-9ad3-0f648c5bef34
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911685518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3911685518
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.1105357745
Short name T179
Test name
Test status
Simulation time 18433393215 ps
CPU time 102.49 seconds
Started Jun 07 07:15:06 PM PDT 24
Finished Jun 07 07:16:50 PM PDT 24
Peak memory 200456 kb
Host smart-759e04d8-c0df-4970-b3f4-afdc47e13c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105357745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.1105357745
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3831392445
Short name T32
Test name
Test status
Simulation time 109364553 ps
CPU time 0.89 seconds
Started Jun 07 07:14:59 PM PDT 24
Finished Jun 07 07:15:02 PM PDT 24
Peak memory 218940 kb
Host smart-ea977903-ae1b-45d6-bbbe-d9ffe8885f16
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831392445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3831392445
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.2926462806
Short name T437
Test name
Test status
Simulation time 849049086 ps
CPU time 5.07 seconds
Started Jun 07 07:15:03 PM PDT 24
Finished Jun 07 07:15:10 PM PDT 24
Peak memory 200472 kb
Host smart-836d82ec-3761-47c6-bb2f-4c90a02187aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926462806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2926462806
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1910628622
Short name T170
Test name
Test status
Simulation time 133715475209 ps
CPU time 469.37 seconds
Started Jun 07 07:15:00 PM PDT 24
Finished Jun 07 07:22:51 PM PDT 24
Peak memory 225116 kb
Host smart-6bbff8ff-846e-42f2-ad8b-ea41402f2027
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910628622 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1910628622
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.3432101517
Short name T59
Test name
Test status
Simulation time 51465459964 ps
CPU time 909.79 seconds
Started Jun 07 07:15:02 PM PDT 24
Finished Jun 07 07:30:13 PM PDT 24
Peak memory 215420 kb
Host smart-bc4b8396-7698-4c26-9b81-c7855b5e83b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3432101517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.3432101517
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.3472551290
Short name T513
Test name
Test status
Simulation time 292586465 ps
CPU time 1.41 seconds
Started Jun 07 07:15:02 PM PDT 24
Finished Jun 07 07:15:06 PM PDT 24
Peak memory 200364 kb
Host smart-5f7aa13c-26bd-4b21-9523-0477d5aa25b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472551290 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.3472551290
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.2742152070
Short name T465
Test name
Test status
Simulation time 97016062105 ps
CPU time 445.27 seconds
Started Jun 07 07:14:59 PM PDT 24
Finished Jun 07 07:22:26 PM PDT 24
Peak memory 200356 kb
Host smart-ad0e5d9c-8a81-49c5-9c7d-eebdd68adcd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742152070 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.2742152070
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.2848410460
Short name T307
Test name
Test status
Simulation time 2195652315 ps
CPU time 55.79 seconds
Started Jun 07 07:14:58 PM PDT 24
Finished Jun 07 07:15:56 PM PDT 24
Peak memory 200496 kb
Host smart-d469eb5f-9803-448f-934e-efbcdc225ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848410460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2848410460
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.714087472
Short name T546
Test name
Test status
Simulation time 21546721 ps
CPU time 0.58 seconds
Started Jun 07 07:15:35 PM PDT 24
Finished Jun 07 07:15:43 PM PDT 24
Peak memory 197096 kb
Host smart-d616300a-7dbd-40fb-b2cb-7cb3a18f285e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714087472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.714087472
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.328125662
Short name T353
Test name
Test status
Simulation time 1235639288 ps
CPU time 35.22 seconds
Started Jun 07 07:15:30 PM PDT 24
Finished Jun 07 07:16:11 PM PDT 24
Peak memory 215796 kb
Host smart-6047aabc-a3b0-431b-ad4a-6d66d8b405c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=328125662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.328125662
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.944194586
Short name T571
Test name
Test status
Simulation time 1685603743 ps
CPU time 11.03 seconds
Started Jun 07 07:15:32 PM PDT 24
Finished Jun 07 07:15:49 PM PDT 24
Peak memory 200416 kb
Host smart-c311c28b-40d0-4c82-a882-e880c5abbe5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944194586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.944194586
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1629689185
Short name T584
Test name
Test status
Simulation time 14551365342 ps
CPU time 960.23 seconds
Started Jun 07 07:15:32 PM PDT 24
Finished Jun 07 07:31:39 PM PDT 24
Peak memory 732116 kb
Host smart-b9269299-519c-480a-8d70-988fe15eb0f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1629689185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1629689185
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3791640964
Short name T290
Test name
Test status
Simulation time 6266665536 ps
CPU time 83.64 seconds
Started Jun 07 07:15:38 PM PDT 24
Finished Jun 07 07:17:10 PM PDT 24
Peak memory 200532 kb
Host smart-6cd54e98-760d-4aee-925e-68c1dc704a23
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791640964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3791640964
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.2525214179
Short name T300
Test name
Test status
Simulation time 3176389782 ps
CPU time 89.66 seconds
Started Jun 07 07:15:35 PM PDT 24
Finished Jun 07 07:17:12 PM PDT 24
Peak memory 200484 kb
Host smart-662b5b76-7992-433d-ba8d-c9923c5e04df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525214179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2525214179
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.2780292427
Short name T241
Test name
Test status
Simulation time 68717268 ps
CPU time 2.34 seconds
Started Jun 07 07:15:33 PM PDT 24
Finished Jun 07 07:15:41 PM PDT 24
Peak memory 200412 kb
Host smart-c7a8bd3a-486f-4a95-894a-5cbf97c70373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780292427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.2780292427
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3215592139
Short name T412
Test name
Test status
Simulation time 25964199285 ps
CPU time 335.82 seconds
Started Jun 07 07:15:32 PM PDT 24
Finished Jun 07 07:21:14 PM PDT 24
Peak memory 216032 kb
Host smart-989e7dd8-077c-4a94-85fe-99545fbe3e65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215592139 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3215592139
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.390530151
Short name T503
Test name
Test status
Simulation time 49396078 ps
CPU time 1.19 seconds
Started Jun 07 07:15:31 PM PDT 24
Finished Jun 07 07:15:38 PM PDT 24
Peak memory 200380 kb
Host smart-41f625b2-702e-4371-badf-15a994954898
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390530151 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.hmac_test_hmac_vectors.390530151
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.414839241
Short name T373
Test name
Test status
Simulation time 7993316422 ps
CPU time 443.08 seconds
Started Jun 07 07:15:29 PM PDT 24
Finished Jun 07 07:22:58 PM PDT 24
Peak memory 200460 kb
Host smart-6b6f1b8d-4429-43ae-b615-d18dd4381c89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414839241 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.414839241
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2449645960
Short name T139
Test name
Test status
Simulation time 9722350299 ps
CPU time 81.16 seconds
Started Jun 07 07:15:30 PM PDT 24
Finished Jun 07 07:16:56 PM PDT 24
Peak memory 200516 kb
Host smart-6c3b5e94-422f-439a-b5d3-f74c12429f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449645960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2449645960
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1852116518
Short name T430
Test name
Test status
Simulation time 12117135 ps
CPU time 0.59 seconds
Started Jun 07 07:15:38 PM PDT 24
Finished Jun 07 07:15:47 PM PDT 24
Peak memory 197112 kb
Host smart-fd706725-9dca-4e66-a327-3247c5e3ff94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852116518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1852116518
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1611229979
Short name T446
Test name
Test status
Simulation time 8631916241 ps
CPU time 34.29 seconds
Started Jun 07 07:15:32 PM PDT 24
Finished Jun 07 07:16:13 PM PDT 24
Peak memory 228992 kb
Host smart-8ef08869-ee99-418e-9d50-f8740a77a511
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1611229979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1611229979
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.2297899176
Short name T282
Test name
Test status
Simulation time 1770817039 ps
CPU time 28.8 seconds
Started Jun 07 07:15:31 PM PDT 24
Finished Jun 07 07:16:05 PM PDT 24
Peak memory 200408 kb
Host smart-09d2693a-69cf-48a4-8155-91d79bd594fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297899176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.2297899176
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.2175661969
Short name T529
Test name
Test status
Simulation time 7811504960 ps
CPU time 453.94 seconds
Started Jun 07 07:15:39 PM PDT 24
Finished Jun 07 07:23:20 PM PDT 24
Peak memory 650528 kb
Host smart-d7959f6b-c3bb-4513-8a57-896ffc29c4e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2175661969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2175661969
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.663540191
Short name T248
Test name
Test status
Simulation time 3535118462 ps
CPU time 33.45 seconds
Started Jun 07 07:15:35 PM PDT 24
Finished Jun 07 07:16:15 PM PDT 24
Peak memory 200472 kb
Host smart-b1dfd1b2-6c05-426b-ad80-36d376d6a7a7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663540191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.663540191
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1748719279
Short name T478
Test name
Test status
Simulation time 4865699274 ps
CPU time 42.66 seconds
Started Jun 07 07:15:28 PM PDT 24
Finished Jun 07 07:16:17 PM PDT 24
Peak memory 200552 kb
Host smart-8561e74f-4060-4288-ac18-04e455ad3b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748719279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1748719279
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.708611515
Short name T128
Test name
Test status
Simulation time 220863460 ps
CPU time 4.04 seconds
Started Jun 07 07:15:36 PM PDT 24
Finished Jun 07 07:15:47 PM PDT 24
Peak memory 200384 kb
Host smart-c7ebb47a-1b56-4176-8451-c8c3b48d3f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708611515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.708611515
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.444125353
Short name T330
Test name
Test status
Simulation time 126691408751 ps
CPU time 3864.93 seconds
Started Jun 07 07:15:30 PM PDT 24
Finished Jun 07 08:20:01 PM PDT 24
Peak memory 771120 kb
Host smart-bb8424ef-f1a4-4aa3-8f64-346e0ccd58c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444125353 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.444125353
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_stress_all_with_rand_reset.3391579107
Short name T57
Test name
Test status
Simulation time 230987792444 ps
CPU time 1198.48 seconds
Started Jun 07 07:15:38 PM PDT 24
Finished Jun 07 07:35:44 PM PDT 24
Peak memory 646688 kb
Host smart-a993fc39-1ab1-404f-8355-9341e01fa30b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3391579107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all_with_rand_reset.3391579107
Directory /workspace/11.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.356013739
Short name T126
Test name
Test status
Simulation time 30717475 ps
CPU time 1.19 seconds
Started Jun 07 07:15:32 PM PDT 24
Finished Jun 07 07:15:39 PM PDT 24
Peak memory 200432 kb
Host smart-fd1f4c97-e17b-4517-80bd-97e0560dc5c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356013739 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_test_hmac_vectors.356013739
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.541437434
Short name T475
Test name
Test status
Simulation time 8747413497 ps
CPU time 499.17 seconds
Started Jun 07 07:15:30 PM PDT 24
Finished Jun 07 07:23:55 PM PDT 24
Peak memory 200456 kb
Host smart-1f2c62ee-59c5-4049-84f6-73175a9ea4b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541437434 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.541437434
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/117.hmac_stress_all_with_rand_reset.2044483187
Short name T58
Test name
Test status
Simulation time 5384555075 ps
CPU time 108.78 seconds
Started Jun 07 07:17:54 PM PDT 24
Finished Jun 07 07:19:53 PM PDT 24
Peak memory 250036 kb
Host smart-d5ce9e5f-1bd7-4041-97bd-b9f0cbab4c1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2044483187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.hmac_stress_all_with_rand_reset.2044483187
Directory /workspace/117.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.3111465401
Short name T277
Test name
Test status
Simulation time 11721092 ps
CPU time 0.6 seconds
Started Jun 07 07:15:31 PM PDT 24
Finished Jun 07 07:15:38 PM PDT 24
Peak memory 195208 kb
Host smart-218064ad-4eb2-43f7-859e-5307ae2acccc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111465401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3111465401
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.2865877082
Short name T162
Test name
Test status
Simulation time 4471406053 ps
CPU time 26.68 seconds
Started Jun 07 07:15:31 PM PDT 24
Finished Jun 07 07:16:04 PM PDT 24
Peak memory 208660 kb
Host smart-775137bb-16b3-498b-988e-11f1a4617830
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2865877082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.2865877082
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1458712519
Short name T541
Test name
Test status
Simulation time 477843731 ps
CPU time 12.53 seconds
Started Jun 07 07:15:32 PM PDT 24
Finished Jun 07 07:15:51 PM PDT 24
Peak memory 200456 kb
Host smart-64cf234f-d9e7-4de8-b60c-5a30b6bf3e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458712519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1458712519
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.1570426362
Short name T356
Test name
Test status
Simulation time 4638198987 ps
CPU time 244.38 seconds
Started Jun 07 07:15:30 PM PDT 24
Finished Jun 07 07:19:40 PM PDT 24
Peak memory 637160 kb
Host smart-3358b652-024a-41a2-b220-9f79eaa7c6ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1570426362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1570426362
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.3012598275
Short name T84
Test name
Test status
Simulation time 9078625757 ps
CPU time 134.09 seconds
Started Jun 07 07:15:35 PM PDT 24
Finished Jun 07 07:17:56 PM PDT 24
Peak memory 200400 kb
Host smart-d9020805-d64c-4259-becf-76cfbbe14026
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012598275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3012598275
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.2759577864
Short name T82
Test name
Test status
Simulation time 750260322 ps
CPU time 44.99 seconds
Started Jun 07 07:15:31 PM PDT 24
Finished Jun 07 07:16:22 PM PDT 24
Peak memory 200532 kb
Host smart-30662023-276e-4ff0-a16a-4a17143c8a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759577864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2759577864
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.819982398
Short name T456
Test name
Test status
Simulation time 2277150354 ps
CPU time 10.19 seconds
Started Jun 07 07:15:34 PM PDT 24
Finished Jun 07 07:15:50 PM PDT 24
Peak memory 200380 kb
Host smart-4fbe5b83-1101-41c8-880f-2f2eb27bcd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819982398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.819982398
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1974074527
Short name T567
Test name
Test status
Simulation time 645195911893 ps
CPU time 3934.08 seconds
Started Jun 07 07:15:31 PM PDT 24
Finished Jun 07 08:21:11 PM PDT 24
Peak memory 741840 kb
Host smart-2120ac47-6a75-4da9-a17c-34919c111e76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974074527 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1974074527
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.2069524728
Short name T265
Test name
Test status
Simulation time 106986625 ps
CPU time 1.05 seconds
Started Jun 07 07:15:29 PM PDT 24
Finished Jun 07 07:15:36 PM PDT 24
Peak memory 200204 kb
Host smart-d0759e6e-a207-452d-b705-e5ab244bb9b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069524728 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.2069524728
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.3660788760
Short name T76
Test name
Test status
Simulation time 27033804875 ps
CPU time 436.45 seconds
Started Jun 07 07:15:29 PM PDT 24
Finished Jun 07 07:22:52 PM PDT 24
Peak memory 200476 kb
Host smart-5d4bf7c5-d907-493c-9453-a136ca1c8b98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660788760 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.3660788760
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3337956983
Short name T514
Test name
Test status
Simulation time 4127663146 ps
CPU time 52.42 seconds
Started Jun 07 07:15:34 PM PDT 24
Finished Jun 07 07:16:33 PM PDT 24
Peak memory 200428 kb
Host smart-bc7a525d-da9c-4e16-9ccd-f259db80e567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337956983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3337956983
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.202033718
Short name T552
Test name
Test status
Simulation time 22121184 ps
CPU time 0.6 seconds
Started Jun 07 07:15:36 PM PDT 24
Finished Jun 07 07:15:43 PM PDT 24
Peak memory 197072 kb
Host smart-c75c4406-9afa-4564-97fe-fe0324be513d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202033718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.202033718
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3666743638
Short name T236
Test name
Test status
Simulation time 889185737 ps
CPU time 37.14 seconds
Started Jun 07 07:15:39 PM PDT 24
Finished Jun 07 07:16:24 PM PDT 24
Peak memory 218888 kb
Host smart-9b6afabb-4f27-4e43-b1db-7ddcd2de0462
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3666743638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3666743638
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2595231336
Short name T134
Test name
Test status
Simulation time 5771532139 ps
CPU time 6.91 seconds
Started Jun 07 07:15:38 PM PDT 24
Finished Jun 07 07:15:52 PM PDT 24
Peak memory 200572 kb
Host smart-6fad2978-6e19-4110-a0f3-a942d4387e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595231336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2595231336
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.4172309972
Short name T432
Test name
Test status
Simulation time 50914581 ps
CPU time 0.92 seconds
Started Jun 07 07:15:31 PM PDT 24
Finished Jun 07 07:15:38 PM PDT 24
Peak memory 211100 kb
Host smart-605ecce6-1c4b-4762-96cf-730c2ba7ab35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4172309972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.4172309972
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.1426323612
Short name T226
Test name
Test status
Simulation time 5730216407 ps
CPU time 108.46 seconds
Started Jun 07 07:15:34 PM PDT 24
Finished Jun 07 07:17:29 PM PDT 24
Peak memory 200192 kb
Host smart-be3c2bf0-d2f0-44e1-9379-5cb44cca4010
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426323612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1426323612
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.4123852376
Short name T331
Test name
Test status
Simulation time 18039271385 ps
CPU time 123.03 seconds
Started Jun 07 07:15:28 PM PDT 24
Finished Jun 07 07:17:38 PM PDT 24
Peak memory 200516 kb
Host smart-4ff37de2-a961-4521-98b0-9c4a064cbfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123852376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.4123852376
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3764098136
Short name T568
Test name
Test status
Simulation time 148472333 ps
CPU time 3.25 seconds
Started Jun 07 07:15:38 PM PDT 24
Finished Jun 07 07:15:49 PM PDT 24
Peak memory 200396 kb
Host smart-ee6492c8-391c-4266-bb5c-371d48b769b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764098136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3764098136
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2062228946
Short name T78
Test name
Test status
Simulation time 53163340884 ps
CPU time 1087.98 seconds
Started Jun 07 07:15:36 PM PDT 24
Finished Jun 07 07:33:51 PM PDT 24
Peak memory 676576 kb
Host smart-5363f0cb-5aa1-446c-a700-bfd46fcb474d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062228946 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2062228946
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.3863295508
Short name T578
Test name
Test status
Simulation time 317443936 ps
CPU time 1.42 seconds
Started Jun 07 07:15:34 PM PDT 24
Finished Jun 07 07:15:42 PM PDT 24
Peak memory 200108 kb
Host smart-d0e27498-5334-4e56-af04-0e1fe5b92296
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863295508 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.3863295508
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.276761170
Short name T315
Test name
Test status
Simulation time 33146863134 ps
CPU time 444.96 seconds
Started Jun 07 07:15:38 PM PDT 24
Finished Jun 07 07:23:11 PM PDT 24
Peak memory 200424 kb
Host smart-cbb7cbaf-7411-4480-9d72-bc80a17b31db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276761170 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.276761170
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.853779843
Short name T296
Test name
Test status
Simulation time 3579923494 ps
CPU time 84.09 seconds
Started Jun 07 07:15:30 PM PDT 24
Finished Jun 07 07:16:59 PM PDT 24
Peak memory 200592 kb
Host smart-290f2911-b255-4277-8796-180be8c9ca79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853779843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.853779843
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2070211101
Short name T453
Test name
Test status
Simulation time 41524569 ps
CPU time 0.58 seconds
Started Jun 07 07:15:39 PM PDT 24
Finished Jun 07 07:15:47 PM PDT 24
Peak memory 196392 kb
Host smart-45b291df-ca8a-4171-b67e-afd9452f68e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070211101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2070211101
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.3800082497
Short name T557
Test name
Test status
Simulation time 875285442 ps
CPU time 12.47 seconds
Started Jun 07 07:15:42 PM PDT 24
Finished Jun 07 07:16:03 PM PDT 24
Peak memory 208576 kb
Host smart-dae6427f-4ab4-480a-bc2d-330e15ca132a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3800082497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.3800082497
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3344703004
Short name T264
Test name
Test status
Simulation time 468514591 ps
CPU time 25.37 seconds
Started Jun 07 07:15:41 PM PDT 24
Finished Jun 07 07:16:15 PM PDT 24
Peak memory 200416 kb
Host smart-17bed0ef-8345-43e4-bad0-e3a006774d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344703004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3344703004
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3457375785
Short name T387
Test name
Test status
Simulation time 4449870089 ps
CPU time 1191.78 seconds
Started Jun 07 07:15:39 PM PDT 24
Finished Jun 07 07:35:38 PM PDT 24
Peak memory 761352 kb
Host smart-ea5072fc-aa58-4250-94a0-b9c3c67f82ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3457375785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3457375785
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3151451535
Short name T202
Test name
Test status
Simulation time 3594474504 ps
CPU time 49.32 seconds
Started Jun 07 07:15:43 PM PDT 24
Finished Jun 07 07:16:41 PM PDT 24
Peak memory 200408 kb
Host smart-61f287e6-f614-4513-8c3c-2404e8c154ee
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151451535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3151451535
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.3351706727
Short name T88
Test name
Test status
Simulation time 1871483650 ps
CPU time 46.49 seconds
Started Jun 07 07:15:38 PM PDT 24
Finished Jun 07 07:16:32 PM PDT 24
Peak memory 200520 kb
Host smart-64bf0c60-07f6-4b27-8b43-22ee003ab31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351706727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3351706727
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1404309000
Short name T164
Test name
Test status
Simulation time 630387173 ps
CPU time 6.3 seconds
Started Jun 07 07:15:29 PM PDT 24
Finished Jun 07 07:15:41 PM PDT 24
Peak memory 200420 kb
Host smart-961f8c21-d02e-487d-8e20-da2f2f5631f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404309000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1404309000
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2228392312
Short name T451
Test name
Test status
Simulation time 289389195608 ps
CPU time 1933.01 seconds
Started Jun 07 07:15:42 PM PDT 24
Finished Jun 07 07:48:04 PM PDT 24
Peak memory 718844 kb
Host smart-15285b85-8262-439f-a0c4-918ae8c7916f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228392312 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2228392312
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.2404273298
Short name T491
Test name
Test status
Simulation time 246238527 ps
CPU time 1.36 seconds
Started Jun 07 07:15:40 PM PDT 24
Finished Jun 07 07:15:50 PM PDT 24
Peak memory 200384 kb
Host smart-55860024-e1d1-461d-b8da-bb8bdccf58ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404273298 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.2404273298
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.736863323
Short name T279
Test name
Test status
Simulation time 25791782122 ps
CPU time 438.72 seconds
Started Jun 07 07:15:42 PM PDT 24
Finished Jun 07 07:23:09 PM PDT 24
Peak memory 200348 kb
Host smart-43192b4d-8a85-4b8d-8285-cee1020ad77b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736863323 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.736863323
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.1979621425
Short name T228
Test name
Test status
Simulation time 6478886046 ps
CPU time 71.68 seconds
Started Jun 07 07:15:41 PM PDT 24
Finished Jun 07 07:17:01 PM PDT 24
Peak memory 200524 kb
Host smart-924c126a-c383-4559-ac2b-d521995f88c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979621425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.1979621425
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.2602666715
Short name T589
Test name
Test status
Simulation time 14723000 ps
CPU time 0.61 seconds
Started Jun 07 07:15:41 PM PDT 24
Finished Jun 07 07:15:50 PM PDT 24
Peak memory 197152 kb
Host smart-7fd68904-90f3-4082-9223-d41a7e641eea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602666715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2602666715
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.2688254787
Short name T23
Test name
Test status
Simulation time 911720206 ps
CPU time 48.65 seconds
Started Jun 07 07:15:40 PM PDT 24
Finished Jun 07 07:16:37 PM PDT 24
Peak memory 240932 kb
Host smart-8f742f89-e81a-4511-847e-aadaef8534b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2688254787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2688254787
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2678084342
Short name T383
Test name
Test status
Simulation time 2397388011 ps
CPU time 6.94 seconds
Started Jun 07 07:15:40 PM PDT 24
Finished Jun 07 07:15:55 PM PDT 24
Peak memory 200384 kb
Host smart-c285b529-5f0d-46de-b1b2-217129ea4435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678084342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2678084342
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.287179464
Short name T68
Test name
Test status
Simulation time 257647627 ps
CPU time 21.04 seconds
Started Jun 07 07:15:42 PM PDT 24
Finished Jun 07 07:16:11 PM PDT 24
Peak memory 246392 kb
Host smart-dd5d3c7f-eb27-4f60-bca7-494504110277
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=287179464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.287179464
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.4090318588
Short name T463
Test name
Test status
Simulation time 37124435617 ps
CPU time 152.4 seconds
Started Jun 07 07:15:42 PM PDT 24
Finished Jun 07 07:18:23 PM PDT 24
Peak memory 200420 kb
Host smart-726c9f6f-516a-4a1b-aed2-7022d8d581d8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090318588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.4090318588
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1131789761
Short name T221
Test name
Test status
Simulation time 34536603053 ps
CPU time 114.34 seconds
Started Jun 07 07:15:41 PM PDT 24
Finished Jun 07 07:17:44 PM PDT 24
Peak memory 200492 kb
Host smart-68f7f694-13e3-48f3-aa21-2bca5e876db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131789761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1131789761
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1594947047
Short name T308
Test name
Test status
Simulation time 205448417 ps
CPU time 1.28 seconds
Started Jun 07 07:15:39 PM PDT 24
Finished Jun 07 07:15:48 PM PDT 24
Peak memory 200508 kb
Host smart-c3769557-bb91-46fb-9f41-e858aeb732c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594947047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1594947047
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.2189211069
Short name T494
Test name
Test status
Simulation time 62837198769 ps
CPU time 2022.22 seconds
Started Jun 07 07:15:42 PM PDT 24
Finished Jun 07 07:49:33 PM PDT 24
Peak memory 520064 kb
Host smart-c87c07bd-5467-49ff-9f95-afae649f124a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189211069 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2189211069
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.413611496
Short name T130
Test name
Test status
Simulation time 227776911 ps
CPU time 1.25 seconds
Started Jun 07 07:15:43 PM PDT 24
Finished Jun 07 07:15:53 PM PDT 24
Peak memory 200316 kb
Host smart-9d3c5954-9fbc-4d65-8578-a6141f62e17f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413611496 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_test_hmac_vectors.413611496
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.4240752823
Short name T280
Test name
Test status
Simulation time 28779352683 ps
CPU time 498.63 seconds
Started Jun 07 07:15:42 PM PDT 24
Finished Jun 07 07:24:10 PM PDT 24
Peak memory 200472 kb
Host smart-3aa50c13-ecd4-45de-bce5-abbb3e80be17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240752823 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.4240752823
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3159834215
Short name T467
Test name
Test status
Simulation time 6014227923 ps
CPU time 28.92 seconds
Started Jun 07 07:15:41 PM PDT 24
Finished Jun 07 07:16:18 PM PDT 24
Peak memory 200528 kb
Host smart-cd1a5519-003a-4706-a300-8a80b1cc2f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159834215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3159834215
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3541112576
Short name T181
Test name
Test status
Simulation time 13478715 ps
CPU time 0.58 seconds
Started Jun 07 07:15:42 PM PDT 24
Finished Jun 07 07:15:51 PM PDT 24
Peak memory 196356 kb
Host smart-3f02feb0-781f-489c-8cef-47ac701d4199
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541112576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3541112576
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1714583482
Short name T12
Test name
Test status
Simulation time 159682455 ps
CPU time 9.02 seconds
Started Jun 07 07:15:42 PM PDT 24
Finished Jun 07 07:15:59 PM PDT 24
Peak memory 200420 kb
Host smart-40bf2018-523c-45e8-a6b3-b4e7cc1dd45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714583482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1714583482
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3558833679
Short name T583
Test name
Test status
Simulation time 2010705623 ps
CPU time 596.9 seconds
Started Jun 07 07:15:39 PM PDT 24
Finished Jun 07 07:25:44 PM PDT 24
Peak memory 713784 kb
Host smart-6e555887-0c7f-431f-8f96-b65887441592
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3558833679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3558833679
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.3936480292
Short name T339
Test name
Test status
Simulation time 6871069270 ps
CPU time 125.77 seconds
Started Jun 07 07:15:43 PM PDT 24
Finished Jun 07 07:17:57 PM PDT 24
Peak memory 200420 kb
Host smart-6fea4567-5e4b-431e-9c9e-28e42a3efb51
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936480292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3936480292
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.406721060
Short name T410
Test name
Test status
Simulation time 8292923095 ps
CPU time 76.94 seconds
Started Jun 07 07:15:41 PM PDT 24
Finished Jun 07 07:17:06 PM PDT 24
Peak memory 200512 kb
Host smart-d474c971-4825-4096-a2aa-53fc0c56e318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406721060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.406721060
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.1994068982
Short name T534
Test name
Test status
Simulation time 368412790 ps
CPU time 6.04 seconds
Started Jun 07 07:15:42 PM PDT 24
Finished Jun 07 07:15:57 PM PDT 24
Peak memory 200432 kb
Host smart-88ab02b2-e51c-4ffc-80e0-f701dd865be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994068982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1994068982
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.2021983336
Short name T273
Test name
Test status
Simulation time 212684625483 ps
CPU time 3862.73 seconds
Started Jun 07 07:15:40 PM PDT 24
Finished Jun 07 08:20:12 PM PDT 24
Peak memory 797644 kb
Host smart-d8d1e955-bb89-4fd1-9443-9440a90f0ea2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021983336 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2021983336
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.3867622666
Short name T379
Test name
Test status
Simulation time 33224912 ps
CPU time 1.3 seconds
Started Jun 07 07:15:41 PM PDT 24
Finished Jun 07 07:15:50 PM PDT 24
Peak memory 200388 kb
Host smart-a7082214-30a4-4131-b356-4925c1b4a590
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867622666 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.3867622666
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.1512347014
Short name T200
Test name
Test status
Simulation time 141002935556 ps
CPU time 547.14 seconds
Started Jun 07 07:15:44 PM PDT 24
Finished Jun 07 07:25:00 PM PDT 24
Peak memory 200356 kb
Host smart-5d1f31a1-266a-411b-873f-4053980e607c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512347014 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.1512347014
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1536602249
Short name T488
Test name
Test status
Simulation time 1734473589 ps
CPU time 35.38 seconds
Started Jun 07 07:15:40 PM PDT 24
Finished Jun 07 07:16:24 PM PDT 24
Peak memory 200388 kb
Host smart-0d69b54b-59b3-4536-81a2-cd8c363c0bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536602249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1536602249
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.4041955967
Short name T242
Test name
Test status
Simulation time 13742032 ps
CPU time 0.6 seconds
Started Jun 07 07:15:41 PM PDT 24
Finished Jun 07 07:15:49 PM PDT 24
Peak memory 196044 kb
Host smart-7354d13f-dadf-4973-8889-7f5bb6f9a32f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041955967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.4041955967
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2841920229
Short name T482
Test name
Test status
Simulation time 942499710 ps
CPU time 25.98 seconds
Started Jun 07 07:15:42 PM PDT 24
Finished Jun 07 07:16:16 PM PDT 24
Peak memory 200460 kb
Host smart-489eb450-97f3-418e-bf44-74afe4722d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841920229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2841920229
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_error.2964858636
Short name T442
Test name
Test status
Simulation time 3933647552 ps
CPU time 28.02 seconds
Started Jun 07 07:15:39 PM PDT 24
Finished Jun 07 07:16:15 PM PDT 24
Peak memory 200484 kb
Host smart-cb96648f-eba8-4838-8672-6e67d45a7e00
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964858636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2964858636
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.1857426771
Short name T563
Test name
Test status
Simulation time 9476765633 ps
CPU time 128.76 seconds
Started Jun 07 07:15:44 PM PDT 24
Finished Jun 07 07:18:02 PM PDT 24
Peak memory 200488 kb
Host smart-1f94eba2-a0d8-452a-a8f9-291d6f660eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857426771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1857426771
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.1622046667
Short name T527
Test name
Test status
Simulation time 131490399 ps
CPU time 2.87 seconds
Started Jun 07 07:15:42 PM PDT 24
Finished Jun 07 07:15:54 PM PDT 24
Peak memory 200412 kb
Host smart-b1300aba-a3e1-489b-a1fb-0e5b45446302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622046667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.1622046667
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2452541188
Short name T71
Test name
Test status
Simulation time 58714704824 ps
CPU time 1723.47 seconds
Started Jun 07 07:15:42 PM PDT 24
Finished Jun 07 07:44:34 PM PDT 24
Peak memory 667204 kb
Host smart-02edbf91-b44b-4284-84b2-1c541ccefcb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452541188 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2452541188
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.3709753315
Short name T240
Test name
Test status
Simulation time 30274334 ps
CPU time 1.01 seconds
Started Jun 07 07:15:42 PM PDT 24
Finished Jun 07 07:15:52 PM PDT 24
Peak memory 200292 kb
Host smart-81c4c737-a39a-4089-abce-9491ffdc27dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709753315 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.3709753315
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.3075632018
Short name T341
Test name
Test status
Simulation time 448807397368 ps
CPU time 543.84 seconds
Started Jun 07 07:15:42 PM PDT 24
Finished Jun 07 07:24:55 PM PDT 24
Peak memory 200428 kb
Host smart-be525762-d53e-4de4-b509-bfaa5fd92c2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075632018 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.3075632018
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.4287062521
Short name T555
Test name
Test status
Simulation time 2169352258 ps
CPU time 38.67 seconds
Started Jun 07 07:15:41 PM PDT 24
Finished Jun 07 07:16:28 PM PDT 24
Peak memory 200504 kb
Host smart-1d0db74a-a2a6-49f3-a8ee-c011c362c00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287062521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.4287062521
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/177.hmac_stress_all_with_rand_reset.2559605590
Short name T45
Test name
Test status
Simulation time 84388428543 ps
CPU time 1175.02 seconds
Started Jun 07 07:18:08 PM PDT 24
Finished Jun 07 07:37:55 PM PDT 24
Peak memory 231236 kb
Host smart-d6571070-ae7e-4995-9d37-6ebad9f89501
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2559605590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.hmac_stress_all_with_rand_reset.2559605590
Directory /workspace/177.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.4171771093
Short name T406
Test name
Test status
Simulation time 12216178 ps
CPU time 0.58 seconds
Started Jun 07 07:15:43 PM PDT 24
Finished Jun 07 07:15:52 PM PDT 24
Peak memory 196352 kb
Host smart-395a5fe2-73d9-4106-acee-7df5443e7ebd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171771093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.4171771093
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.261799870
Short name T40
Test name
Test status
Simulation time 211576405 ps
CPU time 5.99 seconds
Started Jun 07 07:15:42 PM PDT 24
Finished Jun 07 07:15:56 PM PDT 24
Peak memory 200384 kb
Host smart-7a1cddb4-fa39-4087-94ab-0845df4eab80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=261799870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.261799870
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3598966271
Short name T208
Test name
Test status
Simulation time 1411716063 ps
CPU time 18.39 seconds
Started Jun 07 07:15:42 PM PDT 24
Finished Jun 07 07:16:09 PM PDT 24
Peak memory 200428 kb
Host smart-5b486efc-ce8d-45a8-bb6d-47e319361075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598966271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3598966271
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3286888929
Short name T110
Test name
Test status
Simulation time 2090147565 ps
CPU time 507.97 seconds
Started Jun 07 07:15:40 PM PDT 24
Finished Jun 07 07:24:16 PM PDT 24
Peak memory 694552 kb
Host smart-941263e3-37f5-4df9-89c6-5053cd962c65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3286888929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3286888929
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.2477135834
Short name T520
Test name
Test status
Simulation time 25791180452 ps
CPU time 160.59 seconds
Started Jun 07 07:15:42 PM PDT 24
Finished Jun 07 07:18:32 PM PDT 24
Peak memory 200480 kb
Host smart-5ee5d0a9-f999-4357-b0a9-36cf4c373230
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477135834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2477135834
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.821978895
Short name T152
Test name
Test status
Simulation time 3158951327 ps
CPU time 66.48 seconds
Started Jun 07 07:15:41 PM PDT 24
Finished Jun 07 07:16:55 PM PDT 24
Peak memory 200520 kb
Host smart-6d13ff0c-41ff-4cd1-b191-25d3409ee54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821978895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.821978895
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.1464242888
Short name T363
Test name
Test status
Simulation time 2100283349 ps
CPU time 3.29 seconds
Started Jun 07 07:15:41 PM PDT 24
Finished Jun 07 07:15:53 PM PDT 24
Peak memory 200316 kb
Host smart-4480e139-3f18-4aac-9f5c-4b3f763b396c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464242888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1464242888
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.2221594616
Short name T487
Test name
Test status
Simulation time 180570638294 ps
CPU time 2499.02 seconds
Started Jun 07 07:15:43 PM PDT 24
Finished Jun 07 07:57:31 PM PDT 24
Peak memory 763324 kb
Host smart-19867ad4-4019-43f1-a596-1212010a3c83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221594616 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2221594616
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.4256450915
Short name T207
Test name
Test status
Simulation time 39044369 ps
CPU time 1.07 seconds
Started Jun 07 07:15:41 PM PDT 24
Finished Jun 07 07:15:51 PM PDT 24
Peak memory 200244 kb
Host smart-b0c32ae2-4650-4700-8b37-407b6111f91c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256450915 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.4256450915
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.3863438135
Short name T210
Test name
Test status
Simulation time 80579182484 ps
CPU time 541.22 seconds
Started Jun 07 07:15:40 PM PDT 24
Finished Jun 07 07:24:49 PM PDT 24
Peak memory 200472 kb
Host smart-700f810a-534a-4e19-b223-548b5ce3740b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863438135 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.3863438135
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2544088621
Short name T516
Test name
Test status
Simulation time 12433164611 ps
CPU time 62.99 seconds
Started Jun 07 07:15:43 PM PDT 24
Finished Jun 07 07:16:54 PM PDT 24
Peak memory 200532 kb
Host smart-d7a9ce12-68a2-44ed-a83e-ddf4f5bbd432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544088621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2544088621
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1551942492
Short name T203
Test name
Test status
Simulation time 22436221 ps
CPU time 0.59 seconds
Started Jun 07 07:15:51 PM PDT 24
Finished Jun 07 07:16:01 PM PDT 24
Peak memory 196376 kb
Host smart-c0df51cc-5840-4e31-b531-00690f9838fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551942492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1551942492
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3360409425
Short name T433
Test name
Test status
Simulation time 969480173 ps
CPU time 48.48 seconds
Started Jun 07 07:15:53 PM PDT 24
Finished Jun 07 07:16:50 PM PDT 24
Peak memory 226484 kb
Host smart-f8012e4d-b603-42e1-b9eb-989e15dc184d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3360409425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3360409425
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2085486230
Short name T407
Test name
Test status
Simulation time 218535811 ps
CPU time 4.64 seconds
Started Jun 07 07:15:54 PM PDT 24
Finished Jun 07 07:16:07 PM PDT 24
Peak memory 200348 kb
Host smart-7bbdeea1-0588-481f-9b71-1cf7eb44319a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085486230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2085486230
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2677887077
Short name T574
Test name
Test status
Simulation time 23841319593 ps
CPU time 592.7 seconds
Started Jun 07 07:15:51 PM PDT 24
Finished Jun 07 07:25:53 PM PDT 24
Peak memory 735332 kb
Host smart-e1ea6092-db33-4e0c-8e07-1c68ce6ef76d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2677887077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2677887077
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3763873168
Short name T255
Test name
Test status
Simulation time 9575128744 ps
CPU time 154.64 seconds
Started Jun 07 07:15:54 PM PDT 24
Finished Jun 07 07:18:38 PM PDT 24
Peak memory 200524 kb
Host smart-0bab7c69-8411-448f-af1d-01095f3a9f03
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763873168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3763873168
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.935172524
Short name T343
Test name
Test status
Simulation time 2355473388 ps
CPU time 34.98 seconds
Started Jun 07 07:15:55 PM PDT 24
Finished Jun 07 07:16:39 PM PDT 24
Peak memory 200452 kb
Host smart-95edd1f9-8feb-4150-abd4-b9bc7e748f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935172524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.935172524
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1620310138
Short name T147
Test name
Test status
Simulation time 282933907 ps
CPU time 4.17 seconds
Started Jun 07 07:15:44 PM PDT 24
Finished Jun 07 07:15:57 PM PDT 24
Peak memory 200392 kb
Host smart-38f6ef83-cac9-4bc8-8475-fd5661d811c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620310138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1620310138
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.2021124313
Short name T554
Test name
Test status
Simulation time 145190088613 ps
CPU time 1742.17 seconds
Started Jun 07 07:15:49 PM PDT 24
Finished Jun 07 07:45:01 PM PDT 24
Peak memory 713924 kb
Host smart-120d2c56-4080-4aee-a926-d524f624a423
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021124313 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2021124313
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.490329799
Short name T404
Test name
Test status
Simulation time 32351992 ps
CPU time 1.11 seconds
Started Jun 07 07:15:51 PM PDT 24
Finished Jun 07 07:16:01 PM PDT 24
Peak memory 200360 kb
Host smart-02e94349-54a5-433a-bc19-987aeb271a1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490329799 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_hmac_vectors.490329799
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.1653975568
Short name T322
Test name
Test status
Simulation time 39262586436 ps
CPU time 445.84 seconds
Started Jun 07 07:15:53 PM PDT 24
Finished Jun 07 07:23:28 PM PDT 24
Peak memory 200476 kb
Host smart-86b1de19-7b9b-4888-96dd-364f1596ac34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653975568 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.1653975568
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.636665264
Short name T350
Test name
Test status
Simulation time 6535098692 ps
CPU time 70.84 seconds
Started Jun 07 07:15:55 PM PDT 24
Finished Jun 07 07:17:16 PM PDT 24
Peak memory 200488 kb
Host smart-d7b83751-98df-44af-a0af-79f7d0be7007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636665264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.636665264
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3189229160
Short name T48
Test name
Test status
Simulation time 2433102430 ps
CPU time 59.85 seconds
Started Jun 07 07:15:10 PM PDT 24
Finished Jun 07 07:16:12 PM PDT 24
Peak memory 231640 kb
Host smart-752c94c3-efa1-4da5-9370-26a83813f397
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3189229160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3189229160
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1862269813
Short name T593
Test name
Test status
Simulation time 2799409530 ps
CPU time 43.23 seconds
Started Jun 07 07:15:16 PM PDT 24
Finished Jun 07 07:16:02 PM PDT 24
Peak memory 200532 kb
Host smart-181ae373-9874-499e-aa9d-bed7de1df8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862269813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1862269813
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.4211936156
Short name T161
Test name
Test status
Simulation time 2117471990 ps
CPU time 555.9 seconds
Started Jun 07 07:15:12 PM PDT 24
Finished Jun 07 07:24:30 PM PDT 24
Peak memory 713476 kb
Host smart-2c8b2312-0370-4f51-afcf-c1e2be852714
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4211936156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.4211936156
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.1292492764
Short name T396
Test name
Test status
Simulation time 3407966322 ps
CPU time 41.49 seconds
Started Jun 07 07:15:11 PM PDT 24
Finished Jun 07 07:15:55 PM PDT 24
Peak memory 200292 kb
Host smart-7b6f8ea5-b513-4ee4-9a80-fc3d0ba6a88b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292492764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.1292492764
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3446971740
Short name T551
Test name
Test status
Simulation time 2024816680 ps
CPU time 40.38 seconds
Started Jun 07 07:15:21 PM PDT 24
Finished Jun 07 07:16:05 PM PDT 24
Peak memory 200452 kb
Host smart-5c712945-f2c8-4652-a3ee-1945a51cf1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446971740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3446971740
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3468737952
Short name T35
Test name
Test status
Simulation time 276329979 ps
CPU time 1.01 seconds
Started Jun 07 07:15:10 PM PDT 24
Finished Jun 07 07:15:13 PM PDT 24
Peak memory 219924 kb
Host smart-98f4597c-6fe4-4703-a31b-2845a2d8d5b7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468737952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3468737952
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2745476686
Short name T506
Test name
Test status
Simulation time 2657601894 ps
CPU time 10.74 seconds
Started Jun 07 07:15:11 PM PDT 24
Finished Jun 07 07:15:24 PM PDT 24
Peak memory 200444 kb
Host smart-7387c3a0-15a2-4843-a89e-6837d348f418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745476686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2745476686
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2738659253
Short name T411
Test name
Test status
Simulation time 79540201943 ps
CPU time 553.19 seconds
Started Jun 07 07:15:10 PM PDT 24
Finished Jun 07 07:24:25 PM PDT 24
Peak memory 208812 kb
Host smart-a359bd81-98a3-4900-b459-fae3875fe16b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738659253 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2738659253
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.1728422920
Short name T395
Test name
Test status
Simulation time 33654103 ps
CPU time 1.31 seconds
Started Jun 07 07:15:10 PM PDT 24
Finished Jun 07 07:15:13 PM PDT 24
Peak memory 200412 kb
Host smart-b7f264e3-264b-4c76-8d9f-9e7d449b7400
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728422920 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.1728422920
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.2462888386
Short name T166
Test name
Test status
Simulation time 30520662548 ps
CPU time 573.89 seconds
Started Jun 07 07:15:10 PM PDT 24
Finished Jun 07 07:24:47 PM PDT 24
Peak memory 200464 kb
Host smart-23a6ab6c-8f68-4ce9-8858-0e06134fb175
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462888386 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.2462888386
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.3319277244
Short name T196
Test name
Test status
Simulation time 2501019938 ps
CPU time 35.14 seconds
Started Jun 07 07:15:09 PM PDT 24
Finished Jun 07 07:15:46 PM PDT 24
Peak memory 200540 kb
Host smart-6041ee08-31c6-4aa6-88c8-40c987dbb97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319277244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3319277244
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.418919128
Short name T21
Test name
Test status
Simulation time 26987433 ps
CPU time 0.58 seconds
Started Jun 07 07:15:52 PM PDT 24
Finished Jun 07 07:16:01 PM PDT 24
Peak memory 196384 kb
Host smart-c21e9470-325f-4a06-b8ee-6b345bb89d51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418919128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.418919128
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2724010917
Short name T46
Test name
Test status
Simulation time 2507226248 ps
CPU time 42.22 seconds
Started Jun 07 07:15:47 PM PDT 24
Finished Jun 07 07:16:38 PM PDT 24
Peak memory 235580 kb
Host smart-c0802613-0913-4324-9fd5-efa2ad77f29c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2724010917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2724010917
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3670537192
Short name T191
Test name
Test status
Simulation time 2035311047 ps
CPU time 11.64 seconds
Started Jun 07 07:15:52 PM PDT 24
Finished Jun 07 07:16:13 PM PDT 24
Peak memory 200380 kb
Host smart-3f7fb899-d76f-455d-9e28-eb593facadcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670537192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3670537192
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1402701241
Short name T204
Test name
Test status
Simulation time 4536428039 ps
CPU time 1028.59 seconds
Started Jun 07 07:15:51 PM PDT 24
Finished Jun 07 07:33:10 PM PDT 24
Peak memory 761964 kb
Host smart-c702f889-be3e-41e0-9624-340ec35775cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1402701241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1402701241
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3033849240
Short name T521
Test name
Test status
Simulation time 5366669639 ps
CPU time 46.56 seconds
Started Jun 07 07:15:54 PM PDT 24
Finished Jun 07 07:16:51 PM PDT 24
Peak memory 200508 kb
Host smart-04307245-87a0-4714-8a5b-7a84054be7d1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033849240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3033849240
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1966087301
Short name T231
Test name
Test status
Simulation time 5911904276 ps
CPU time 111.23 seconds
Started Jun 07 07:15:49 PM PDT 24
Finished Jun 07 07:17:50 PM PDT 24
Peak memory 200492 kb
Host smart-3021c5aa-581b-4708-a02a-520d45bf7d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966087301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1966087301
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.3119320377
Short name T297
Test name
Test status
Simulation time 780185389 ps
CPU time 9.01 seconds
Started Jun 07 07:15:51 PM PDT 24
Finished Jun 07 07:16:09 PM PDT 24
Peak memory 200488 kb
Host smart-8d9b1951-430d-4794-92b6-36fb18123d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119320377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3119320377
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2562631381
Short name T104
Test name
Test status
Simulation time 107547677877 ps
CPU time 1525.75 seconds
Started Jun 07 07:15:55 PM PDT 24
Finished Jun 07 07:41:30 PM PDT 24
Peak memory 411564 kb
Host smart-14ba4900-6b70-461d-981d-f9d1b9810a19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562631381 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2562631381
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.3664573293
Short name T189
Test name
Test status
Simulation time 63532105 ps
CPU time 1.38 seconds
Started Jun 07 07:15:52 PM PDT 24
Finished Jun 07 07:16:03 PM PDT 24
Peak memory 200536 kb
Host smart-264bfc7d-ec9a-489b-9f69-75b9b3c2d837
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664573293 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.3664573293
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.1783073832
Short name T146
Test name
Test status
Simulation time 6638262000 ps
CPU time 401.66 seconds
Started Jun 07 07:15:51 PM PDT 24
Finished Jun 07 07:22:42 PM PDT 24
Peak memory 200428 kb
Host smart-5e1c9d28-2808-4fcf-ad98-a7e038957323
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783073832 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.1783073832
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.937166245
Short name T327
Test name
Test status
Simulation time 8585438631 ps
CPU time 23.47 seconds
Started Jun 07 07:15:51 PM PDT 24
Finished Jun 07 07:16:24 PM PDT 24
Peak memory 200488 kb
Host smart-6ff0f81e-adfa-4a02-a29a-ef8ffc5d5774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937166245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.937166245
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.245789596
Short name T259
Test name
Test status
Simulation time 19042611 ps
CPU time 0.57 seconds
Started Jun 07 07:16:00 PM PDT 24
Finished Jun 07 07:16:10 PM PDT 24
Peak memory 196380 kb
Host smart-5813ebba-d9ea-4979-94c5-b15a18dd9d5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245789596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.245789596
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3347046722
Short name T500
Test name
Test status
Simulation time 859141849 ps
CPU time 42.16 seconds
Started Jun 07 07:15:53 PM PDT 24
Finished Jun 07 07:16:45 PM PDT 24
Peak memory 228984 kb
Host smart-b13a012b-7d85-4169-8e4c-b846670e9855
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3347046722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3347046722
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.4040816409
Short name T485
Test name
Test status
Simulation time 7773563834 ps
CPU time 35.77 seconds
Started Jun 07 07:15:49 PM PDT 24
Finished Jun 07 07:16:34 PM PDT 24
Peak memory 200440 kb
Host smart-9b1eb9b8-f2d6-4a8f-93f3-6320fa512015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040816409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.4040816409
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.3065038433
Short name T380
Test name
Test status
Simulation time 11058837604 ps
CPU time 151.77 seconds
Started Jun 07 07:15:50 PM PDT 24
Finished Jun 07 07:18:30 PM PDT 24
Peak memory 584232 kb
Host smart-12706878-2715-45ed-83e3-18fed85e8e80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3065038433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3065038433
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.2216618709
Short name T31
Test name
Test status
Simulation time 18625780 ps
CPU time 0.67 seconds
Started Jun 07 07:15:54 PM PDT 24
Finished Jun 07 07:16:04 PM PDT 24
Peak memory 196844 kb
Host smart-d358afe8-9f18-4f07-8db6-5569f8f2d5cf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216618709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2216618709
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1724473128
Short name T448
Test name
Test status
Simulation time 1357657419 ps
CPU time 14.44 seconds
Started Jun 07 07:15:54 PM PDT 24
Finished Jun 07 07:16:17 PM PDT 24
Peak memory 200380 kb
Host smart-2e716638-6e97-45de-a64d-c15e83c72505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724473128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1724473128
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.262032697
Short name T597
Test name
Test status
Simulation time 280482843 ps
CPU time 1.38 seconds
Started Jun 07 07:15:48 PM PDT 24
Finished Jun 07 07:15:58 PM PDT 24
Peak memory 200484 kb
Host smart-7ab3f320-296d-4ad6-a516-25204f52d4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262032697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.262032697
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.4002170400
Short name T43
Test name
Test status
Simulation time 7132465960 ps
CPU time 187.36 seconds
Started Jun 07 07:15:53 PM PDT 24
Finished Jun 07 07:19:09 PM PDT 24
Peak memory 236412 kb
Host smart-7d3d60ce-c168-4fd5-b2f1-4d4dff2af92a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002170400 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.4002170400
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.790419171
Short name T160
Test name
Test status
Simulation time 113149908 ps
CPU time 1.41 seconds
Started Jun 07 07:15:55 PM PDT 24
Finished Jun 07 07:16:06 PM PDT 24
Peak memory 200384 kb
Host smart-f1a12402-4df2-4e11-adc4-3560b018750c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790419171 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_hmac_vectors.790419171
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.2910021881
Short name T361
Test name
Test status
Simulation time 149152592011 ps
CPU time 568.31 seconds
Started Jun 07 07:15:54 PM PDT 24
Finished Jun 07 07:25:31 PM PDT 24
Peak memory 200452 kb
Host smart-f45a82df-fbd6-423f-a029-a72436ad3377
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910021881 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.2910021881
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.3035142772
Short name T252
Test name
Test status
Simulation time 843388536 ps
CPU time 15.76 seconds
Started Jun 07 07:15:52 PM PDT 24
Finished Jun 07 07:16:17 PM PDT 24
Peak memory 200392 kb
Host smart-9da45c26-4048-4bc7-b508-276d4e7ee24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035142772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3035142772
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.2671319601
Short name T507
Test name
Test status
Simulation time 59674904 ps
CPU time 0.58 seconds
Started Jun 07 07:15:50 PM PDT 24
Finished Jun 07 07:16:00 PM PDT 24
Peak memory 196396 kb
Host smart-46eca1cc-db91-4154-8678-db99c49f7cc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671319601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2671319601
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3868785186
Short name T573
Test name
Test status
Simulation time 3819235984 ps
CPU time 51.66 seconds
Started Jun 07 07:15:48 PM PDT 24
Finished Jun 07 07:16:49 PM PDT 24
Peak memory 223152 kb
Host smart-5dfe8897-40d5-402c-906d-7beb9edc02c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3868785186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3868785186
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.3134102100
Short name T577
Test name
Test status
Simulation time 3384215013 ps
CPU time 65.65 seconds
Started Jun 07 07:15:51 PM PDT 24
Finished Jun 07 07:17:06 PM PDT 24
Peak memory 200464 kb
Host smart-c04d1217-e930-4cb8-a26c-e5982e1721d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134102100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.3134102100
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1956350054
Short name T133
Test name
Test status
Simulation time 12102902269 ps
CPU time 736.19 seconds
Started Jun 07 07:15:54 PM PDT 24
Finished Jun 07 07:28:20 PM PDT 24
Peak memory 716796 kb
Host smart-1a9493f2-4b3f-4007-84b6-395ed5d5ec19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1956350054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1956350054
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.583706434
Short name T338
Test name
Test status
Simulation time 1634980827 ps
CPU time 49.79 seconds
Started Jun 07 07:15:50 PM PDT 24
Finished Jun 07 07:16:49 PM PDT 24
Peak memory 200480 kb
Host smart-9a704073-e0c8-404c-8eaf-4335eefb6b3a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583706434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.583706434
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2711874458
Short name T332
Test name
Test status
Simulation time 1228539858 ps
CPU time 75.65 seconds
Started Jun 07 07:15:49 PM PDT 24
Finished Jun 07 07:17:14 PM PDT 24
Peak memory 200324 kb
Host smart-395ad55b-2a7c-4ba6-a57a-88dd7bff16fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711874458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2711874458
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2012892177
Short name T77
Test name
Test status
Simulation time 66306460 ps
CPU time 2.58 seconds
Started Jun 07 07:15:51 PM PDT 24
Finished Jun 07 07:16:03 PM PDT 24
Peak memory 200436 kb
Host smart-cedb0eed-2b17-4c41-9c7d-f33cc2c55bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012892177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2012892177
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.1451440504
Short name T293
Test name
Test status
Simulation time 242217699133 ps
CPU time 1511.25 seconds
Started Jun 07 07:15:51 PM PDT 24
Finished Jun 07 07:41:12 PM PDT 24
Peak memory 731976 kb
Host smart-b3c748c0-764c-40b6-9229-86119101ef4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451440504 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1451440504
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.1583530182
Short name T498
Test name
Test status
Simulation time 247668337 ps
CPU time 1.24 seconds
Started Jun 07 07:15:50 PM PDT 24
Finished Jun 07 07:16:01 PM PDT 24
Peak memory 200436 kb
Host smart-7bfefa63-fb9d-4521-aba6-7701f1f8577c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583530182 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.1583530182
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.2778116183
Short name T80
Test name
Test status
Simulation time 28990146304 ps
CPU time 387.6 seconds
Started Jun 07 07:15:51 PM PDT 24
Finished Jun 07 07:22:28 PM PDT 24
Peak memory 200488 kb
Host smart-366063cb-7824-4c13-8334-ccf1b9315a71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778116183 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.2778116183
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.1050635634
Short name T44
Test name
Test status
Simulation time 1247152421 ps
CPU time 24.22 seconds
Started Jun 07 07:16:00 PM PDT 24
Finished Jun 07 07:16:34 PM PDT 24
Peak memory 200472 kb
Host smart-c29e877d-52d3-474b-8f12-656795a2fa5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050635634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1050635634
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.3585668246
Short name T484
Test name
Test status
Simulation time 14344549 ps
CPU time 0.61 seconds
Started Jun 07 07:15:52 PM PDT 24
Finished Jun 07 07:16:02 PM PDT 24
Peak memory 196400 kb
Host smart-467625e7-6b39-486e-89c2-aa2b8cb8f9c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585668246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3585668246
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.3936900850
Short name T596
Test name
Test status
Simulation time 3264343355 ps
CPU time 36.16 seconds
Started Jun 07 07:16:00 PM PDT 24
Finished Jun 07 07:16:46 PM PDT 24
Peak memory 218616 kb
Host smart-7dd4cbac-81dd-4885-9bcc-e9cb28f44e4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3936900850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3936900850
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.2875239328
Short name T6
Test name
Test status
Simulation time 715603657 ps
CPU time 10.1 seconds
Started Jun 07 07:15:54 PM PDT 24
Finished Jun 07 07:16:14 PM PDT 24
Peak memory 200348 kb
Host smart-76202c47-b316-4893-80c8-1cf4fa4d8107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875239328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2875239328
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1619571878
Short name T530
Test name
Test status
Simulation time 10889102065 ps
CPU time 650.45 seconds
Started Jun 07 07:15:55 PM PDT 24
Finished Jun 07 07:26:56 PM PDT 24
Peak memory 665364 kb
Host smart-bd169088-e67e-4bd4-8bca-5be7b9fd1dc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1619571878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1619571878
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.782815521
Short name T496
Test name
Test status
Simulation time 4925232158 ps
CPU time 86.81 seconds
Started Jun 07 07:16:01 PM PDT 24
Finished Jun 07 07:17:37 PM PDT 24
Peak memory 200492 kb
Host smart-08a2cf98-cf78-4a93-bdb3-be4af68e2078
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782815521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.782815521
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3078076944
Short name T86
Test name
Test status
Simulation time 1572007439 ps
CPU time 84.61 seconds
Started Jun 07 07:16:00 PM PDT 24
Finished Jun 07 07:17:35 PM PDT 24
Peak memory 200472 kb
Host smart-b758b729-7ef6-411c-9544-b988a8d391f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078076944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3078076944
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.3315594228
Short name T481
Test name
Test status
Simulation time 370792639 ps
CPU time 5.81 seconds
Started Jun 07 07:15:52 PM PDT 24
Finished Jun 07 07:16:07 PM PDT 24
Peak memory 200480 kb
Host smart-5328703e-e4b1-4114-9e23-3507472928b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315594228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3315594228
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.561487900
Short name T376
Test name
Test status
Simulation time 209857598 ps
CPU time 1.08 seconds
Started Jun 07 07:15:49 PM PDT 24
Finished Jun 07 07:15:59 PM PDT 24
Peak memory 200432 kb
Host smart-8661bfc1-20d2-4e96-a2a6-75a38abd1e93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561487900 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_hmac_vectors.561487900
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.64375189
Short name T38
Test name
Test status
Simulation time 158027360675 ps
CPU time 569.52 seconds
Started Jun 07 07:15:51 PM PDT 24
Finished Jun 07 07:25:30 PM PDT 24
Peak memory 200276 kb
Host smart-07d65119-8ac4-46ca-bbcf-d6eff3aa257a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64375189 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.64375189
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1933962441
Short name T156
Test name
Test status
Simulation time 1041252638 ps
CPU time 19.55 seconds
Started Jun 07 07:15:51 PM PDT 24
Finished Jun 07 07:16:20 PM PDT 24
Peak memory 200480 kb
Host smart-e8c68eb1-b369-4ffb-8da8-a121938f4294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933962441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1933962441
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.1558344039
Short name T141
Test name
Test status
Simulation time 22361296 ps
CPU time 0.57 seconds
Started Jun 07 07:15:59 PM PDT 24
Finished Jun 07 07:16:10 PM PDT 24
Peak memory 196044 kb
Host smart-03e45de5-9ab7-47e8-b07f-2290d8584bee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558344039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.1558344039
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.931434450
Short name T190
Test name
Test status
Simulation time 1301453554 ps
CPU time 38.41 seconds
Started Jun 07 07:15:59 PM PDT 24
Finished Jun 07 07:16:47 PM PDT 24
Peak memory 230068 kb
Host smart-801d93de-46af-4e4d-9b96-de350c541a66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=931434450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.931434450
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3696267276
Short name T519
Test name
Test status
Simulation time 2222948131 ps
CPU time 38.71 seconds
Started Jun 07 07:16:01 PM PDT 24
Finished Jun 07 07:16:49 PM PDT 24
Peak memory 200404 kb
Host smart-15ee7ce6-b684-438c-9239-9840f2af4b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696267276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3696267276
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.332267165
Short name T224
Test name
Test status
Simulation time 16988547958 ps
CPU time 1278.1 seconds
Started Jun 07 07:16:00 PM PDT 24
Finished Jun 07 07:37:28 PM PDT 24
Peak memory 751384 kb
Host smart-18f013bd-d71b-4878-9d17-892373350001
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=332267165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.332267165
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.1802359803
Short name T398
Test name
Test status
Simulation time 1135808534 ps
CPU time 61.17 seconds
Started Jun 07 07:15:59 PM PDT 24
Finished Jun 07 07:17:10 PM PDT 24
Peak memory 200408 kb
Host smart-448f8ad9-adf0-4885-9a47-3c60b9e313d1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802359803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1802359803
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.4196542143
Short name T400
Test name
Test status
Simulation time 2687096309 ps
CPU time 54.32 seconds
Started Jun 07 07:15:59 PM PDT 24
Finished Jun 07 07:17:03 PM PDT 24
Peak memory 200516 kb
Host smart-82a040f4-ab50-47ad-b4b3-2a33db0d201c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196542143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.4196542143
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1042399288
Short name T237
Test name
Test status
Simulation time 5328946744 ps
CPU time 15.21 seconds
Started Jun 07 07:16:01 PM PDT 24
Finished Jun 07 07:16:25 PM PDT 24
Peak memory 200452 kb
Host smart-d9dcddd9-1a66-4e80-be20-b8654cb4d708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042399288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1042399288
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3954125992
Short name T469
Test name
Test status
Simulation time 184337431248 ps
CPU time 1437.62 seconds
Started Jun 07 07:16:04 PM PDT 24
Finished Jun 07 07:40:10 PM PDT 24
Peak memory 702196 kb
Host smart-ab4034a1-ec37-4641-9f03-1dbbf92f4aae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954125992 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3954125992
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.598638910
Short name T234
Test name
Test status
Simulation time 331363400 ps
CPU time 1.46 seconds
Started Jun 07 07:15:58 PM PDT 24
Finished Jun 07 07:16:09 PM PDT 24
Peak memory 200440 kb
Host smart-10441acb-c9ae-4625-a6dd-d115ebcac61c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598638910 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.hmac_test_hmac_vectors.598638910
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.3416113421
Short name T185
Test name
Test status
Simulation time 95296292738 ps
CPU time 439.26 seconds
Started Jun 07 07:16:04 PM PDT 24
Finished Jun 07 07:23:32 PM PDT 24
Peak memory 200244 kb
Host smart-ca34f256-33cd-4072-9b00-14c0b6ad0c4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416113421 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.3416113421
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2397437692
Short name T579
Test name
Test status
Simulation time 392547324 ps
CPU time 7.7 seconds
Started Jun 07 07:16:03 PM PDT 24
Finished Jun 07 07:16:19 PM PDT 24
Peak memory 200456 kb
Host smart-2c0aa91d-1856-4419-ac49-8cc309cbfce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397437692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2397437692
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.1801249514
Short name T306
Test name
Test status
Simulation time 11897350 ps
CPU time 0.57 seconds
Started Jun 07 07:15:58 PM PDT 24
Finished Jun 07 07:16:08 PM PDT 24
Peak memory 195400 kb
Host smart-a97dea02-8d36-4846-9ada-fed813f2b8e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801249514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1801249514
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.922497784
Short name T174
Test name
Test status
Simulation time 288960103 ps
CPU time 10.54 seconds
Started Jun 07 07:16:01 PM PDT 24
Finished Jun 07 07:16:21 PM PDT 24
Peak memory 208564 kb
Host smart-d5340852-8abf-4317-80f6-1c2b40b77a2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=922497784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.922497784
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1388380002
Short name T256
Test name
Test status
Simulation time 660641756 ps
CPU time 37.28 seconds
Started Jun 07 07:16:01 PM PDT 24
Finished Jun 07 07:16:48 PM PDT 24
Peak memory 200420 kb
Host smart-ef0c1fa8-21ca-410b-925b-3c58bf8e640d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388380002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1388380002
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1299062140
Short name T474
Test name
Test status
Simulation time 2164849363 ps
CPU time 253.16 seconds
Started Jun 07 07:16:00 PM PDT 24
Finished Jun 07 07:20:23 PM PDT 24
Peak memory 652936 kb
Host smart-8ec34d3a-d5cd-4421-8ccd-aac916e807f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1299062140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1299062140
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.1485579474
Short name T440
Test name
Test status
Simulation time 23044441996 ps
CPU time 29.89 seconds
Started Jun 07 07:16:01 PM PDT 24
Finished Jun 07 07:16:40 PM PDT 24
Peak memory 200416 kb
Host smart-16477991-2c74-475f-9c5d-0a5a3685c04f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485579474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.1485579474
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2059213136
Short name T450
Test name
Test status
Simulation time 3887341719 ps
CPU time 55.95 seconds
Started Jun 07 07:16:00 PM PDT 24
Finished Jun 07 07:17:05 PM PDT 24
Peak memory 200476 kb
Host smart-bc7fd580-1ea0-4949-94c2-679df7ed5f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059213136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2059213136
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3728176866
Short name T167
Test name
Test status
Simulation time 61380728 ps
CPU time 1 seconds
Started Jun 07 07:16:01 PM PDT 24
Finished Jun 07 07:16:12 PM PDT 24
Peak memory 198252 kb
Host smart-dc36f73e-acd2-440c-8acf-9f8bab39c8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728176866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3728176866
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2739413638
Short name T70
Test name
Test status
Simulation time 679274846025 ps
CPU time 2600.89 seconds
Started Jun 07 07:16:03 PM PDT 24
Finished Jun 07 07:59:33 PM PDT 24
Peak memory 740432 kb
Host smart-335b292d-a8ba-40b3-97ae-a6fadd9f3605
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739413638 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2739413638
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.348894101
Short name T144
Test name
Test status
Simulation time 112981700 ps
CPU time 1.21 seconds
Started Jun 07 07:15:57 PM PDT 24
Finished Jun 07 07:16:09 PM PDT 24
Peak memory 200476 kb
Host smart-4d373998-cb83-4e06-b545-c5f053b978ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348894101 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.hmac_test_hmac_vectors.348894101
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.2059834816
Short name T311
Test name
Test status
Simulation time 34470231486 ps
CPU time 497.33 seconds
Started Jun 07 07:15:58 PM PDT 24
Finished Jun 07 07:24:26 PM PDT 24
Peak memory 200376 kb
Host smart-8b9e4db7-38d2-45e8-9439-7874ad672228
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059834816 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.2059834816
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.431141143
Short name T564
Test name
Test status
Simulation time 2010535952 ps
CPU time 29.16 seconds
Started Jun 07 07:16:02 PM PDT 24
Finished Jun 07 07:16:41 PM PDT 24
Peak memory 200424 kb
Host smart-642b277b-6faf-437e-93ca-69b548b0ff8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431141143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.431141143
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2477022773
Short name T357
Test name
Test status
Simulation time 23618364 ps
CPU time 0.62 seconds
Started Jun 07 07:16:09 PM PDT 24
Finished Jun 07 07:16:18 PM PDT 24
Peak memory 196356 kb
Host smart-088f17ac-65e9-47cb-8aa2-31cfd3cc6305
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477022773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2477022773
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2292481205
Short name T298
Test name
Test status
Simulation time 2563345667 ps
CPU time 61.72 seconds
Started Jun 07 07:16:04 PM PDT 24
Finished Jun 07 07:17:14 PM PDT 24
Peak memory 232976 kb
Host smart-2ada8ef8-33ca-4c52-91b1-4cdbfebe8f79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2292481205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2292481205
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.315472581
Short name T414
Test name
Test status
Simulation time 1840981931 ps
CPU time 26.95 seconds
Started Jun 07 07:15:59 PM PDT 24
Finished Jun 07 07:16:36 PM PDT 24
Peak memory 200412 kb
Host smart-88ba1e62-dbe3-4335-bc58-08367388d1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315472581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.315472581
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3979821812
Short name T281
Test name
Test status
Simulation time 19287403387 ps
CPU time 1433.91 seconds
Started Jun 07 07:16:01 PM PDT 24
Finished Jun 07 07:40:05 PM PDT 24
Peak memory 753372 kb
Host smart-aff135ae-6ec5-4d26-bd90-b03be7372893
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3979821812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3979821812
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.2920607128
Short name T172
Test name
Test status
Simulation time 14837067578 ps
CPU time 143.94 seconds
Started Jun 07 07:16:04 PM PDT 24
Finished Jun 07 07:18:36 PM PDT 24
Peak memory 200352 kb
Host smart-7919ae61-56cf-48ec-bf65-5f162a6adc42
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920607128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2920607128
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2379714171
Short name T4
Test name
Test status
Simulation time 36969870905 ps
CPU time 130.03 seconds
Started Jun 07 07:16:01 PM PDT 24
Finished Jun 07 07:18:21 PM PDT 24
Peak memory 200508 kb
Host smart-e35d45bf-a1bd-4d3d-b295-81a5424e54ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379714171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2379714171
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.718337816
Short name T390
Test name
Test status
Simulation time 100659926 ps
CPU time 1.29 seconds
Started Jun 07 07:15:59 PM PDT 24
Finished Jun 07 07:16:10 PM PDT 24
Peak memory 200412 kb
Host smart-209a9bc6-739a-40d2-aab2-5b0b27e76ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718337816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.718337816
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.456889602
Short name T72
Test name
Test status
Simulation time 343549000524 ps
CPU time 4729.24 seconds
Started Jun 07 07:16:11 PM PDT 24
Finished Jun 07 08:35:08 PM PDT 24
Peak memory 745660 kb
Host smart-22153cd6-f3cf-45ed-8cd0-961885d8d21b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456889602 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.456889602
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.3285112636
Short name T253
Test name
Test status
Simulation time 150692393 ps
CPU time 1.26 seconds
Started Jun 07 07:16:13 PM PDT 24
Finished Jun 07 07:16:21 PM PDT 24
Peak memory 200436 kb
Host smart-820b90bb-f377-44d4-909d-566761cc1af5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285112636 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.3285112636
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.617395740
Short name T532
Test name
Test status
Simulation time 8814201020 ps
CPU time 547.3 seconds
Started Jun 07 07:16:10 PM PDT 24
Finished Jun 07 07:25:24 PM PDT 24
Peak memory 200388 kb
Host smart-7c994365-2fc8-4eec-8dc2-0a3d5cb1df23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617395740 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.617395740
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2524278003
Short name T427
Test name
Test status
Simulation time 10645850879 ps
CPU time 84.15 seconds
Started Jun 07 07:16:10 PM PDT 24
Finished Jun 07 07:17:41 PM PDT 24
Peak memory 200488 kb
Host smart-95aa591b-b405-4e88-8cd9-915d0e745627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524278003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2524278003
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1704401205
Short name T429
Test name
Test status
Simulation time 93665048 ps
CPU time 0.59 seconds
Started Jun 07 07:16:12 PM PDT 24
Finished Jun 07 07:16:20 PM PDT 24
Peak memory 196088 kb
Host smart-fd585b72-cd1a-4ff4-8076-2b9253f65592
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704401205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1704401205
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.865497932
Short name T575
Test name
Test status
Simulation time 2619346441 ps
CPU time 37.98 seconds
Started Jun 07 07:16:09 PM PDT 24
Finished Jun 07 07:16:54 PM PDT 24
Peak memory 225044 kb
Host smart-cf9584f1-b919-4eeb-8a75-84ceb4509205
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=865497932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.865497932
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.2334196435
Short name T109
Test name
Test status
Simulation time 1132103752 ps
CPU time 61.97 seconds
Started Jun 07 07:16:08 PM PDT 24
Finished Jun 07 07:17:18 PM PDT 24
Peak memory 200396 kb
Host smart-523570e9-8ee9-4095-aa5d-aa1a207e022d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334196435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2334196435
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.602185005
Short name T559
Test name
Test status
Simulation time 34021097707 ps
CPU time 897.75 seconds
Started Jun 07 07:16:11 PM PDT 24
Finished Jun 07 07:31:16 PM PDT 24
Peak memory 720620 kb
Host smart-812e7f57-d78d-415c-b745-135b1dfc7dfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=602185005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.602185005
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.1233493401
Short name T149
Test name
Test status
Simulation time 9180892758 ps
CPU time 97.69 seconds
Started Jun 07 07:16:12 PM PDT 24
Finished Jun 07 07:17:57 PM PDT 24
Peak memory 200464 kb
Host smart-f0b5ca43-6a6d-4c11-b8c4-8d79081b9891
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233493401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1233493401
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.84427687
Short name T438
Test name
Test status
Simulation time 4715724422 ps
CPU time 35.01 seconds
Started Jun 07 07:16:09 PM PDT 24
Finished Jun 07 07:16:51 PM PDT 24
Peak memory 200488 kb
Host smart-c1afe81e-411c-4257-a6f3-e11f6edf711f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84427687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.84427687
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2633516766
Short name T324
Test name
Test status
Simulation time 241828584 ps
CPU time 2.05 seconds
Started Jun 07 07:16:12 PM PDT 24
Finished Jun 07 07:16:21 PM PDT 24
Peak memory 200380 kb
Host smart-3386c37d-9173-4f63-b495-c1cf553e50e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633516766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2633516766
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.615853251
Short name T561
Test name
Test status
Simulation time 11052022378 ps
CPU time 618.23 seconds
Started Jun 07 07:16:10 PM PDT 24
Finished Jun 07 07:26:36 PM PDT 24
Peak memory 665704 kb
Host smart-3827363f-7f9e-420f-9c30-bd8c58dd20da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615853251 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.615853251
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.2319926806
Short name T238
Test name
Test status
Simulation time 61090093 ps
CPU time 1.11 seconds
Started Jun 07 07:16:11 PM PDT 24
Finished Jun 07 07:16:19 PM PDT 24
Peak memory 200464 kb
Host smart-cb71a61f-615c-4192-becf-d9c1445621e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319926806 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.2319926806
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.2422176782
Short name T408
Test name
Test status
Simulation time 32513785423 ps
CPU time 466.48 seconds
Started Jun 07 07:16:07 PM PDT 24
Finished Jun 07 07:24:01 PM PDT 24
Peak memory 200416 kb
Host smart-c102ed41-bd4c-4d11-b691-57381e1d0ab2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422176782 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.2422176782
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.67930106
Short name T258
Test name
Test status
Simulation time 57039401952 ps
CPU time 99.85 seconds
Started Jun 07 07:16:12 PM PDT 24
Finished Jun 07 07:17:59 PM PDT 24
Peak memory 200488 kb
Host smart-0910a98f-eab4-4d23-8524-4a866d2ea2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67930106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.67930106
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1034984916
Short name T329
Test name
Test status
Simulation time 72954509 ps
CPU time 0.57 seconds
Started Jun 07 07:16:11 PM PDT 24
Finished Jun 07 07:16:19 PM PDT 24
Peak memory 196312 kb
Host smart-ec9566b4-c18d-4c94-a9ce-439874561d9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034984916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1034984916
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1103860585
Short name T401
Test name
Test status
Simulation time 170111917 ps
CPU time 6.72 seconds
Started Jun 07 07:16:13 PM PDT 24
Finished Jun 07 07:16:27 PM PDT 24
Peak memory 208180 kb
Host smart-bd39a90e-6a5c-4f8c-8baf-be11149e7125
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1103860585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1103860585
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3652963513
Short name T41
Test name
Test status
Simulation time 17081713515 ps
CPU time 22.6 seconds
Started Jun 07 07:16:09 PM PDT 24
Finished Jun 07 07:16:39 PM PDT 24
Peak memory 200404 kb
Host smart-b0fefd5e-05a3-4e91-9203-297a0c26dcb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652963513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3652963513
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3201924159
Short name T594
Test name
Test status
Simulation time 1865309657 ps
CPU time 171.85 seconds
Started Jun 07 07:16:09 PM PDT 24
Finished Jun 07 07:19:08 PM PDT 24
Peak memory 458604 kb
Host smart-5a40e4e9-599e-4921-8525-968311d07dd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3201924159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3201924159
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1772620841
Short name T195
Test name
Test status
Simulation time 2315540435 ps
CPU time 134.27 seconds
Started Jun 07 07:16:14 PM PDT 24
Finished Jun 07 07:18:35 PM PDT 24
Peak memory 200560 kb
Host smart-0a12f73e-05ef-43fe-8a29-cc2fc654933e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772620841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1772620841
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.3928699270
Short name T547
Test name
Test status
Simulation time 2292036863 ps
CPU time 72.21 seconds
Started Jun 07 07:16:14 PM PDT 24
Finished Jun 07 07:17:33 PM PDT 24
Peak memory 200620 kb
Host smart-210a0754-2a80-497a-a6fd-800960731ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928699270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3928699270
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3860437464
Short name T194
Test name
Test status
Simulation time 1196384156 ps
CPU time 9.65 seconds
Started Jun 07 07:16:11 PM PDT 24
Finished Jun 07 07:16:28 PM PDT 24
Peak memory 200484 kb
Host smart-9ff55753-4318-4a14-bc06-1d1999f7fd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860437464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3860437464
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2619082513
Short name T536
Test name
Test status
Simulation time 3101531347 ps
CPU time 32.08 seconds
Started Jun 07 07:16:12 PM PDT 24
Finished Jun 07 07:16:51 PM PDT 24
Peak memory 200480 kb
Host smart-d181e4bc-bbfb-4a02-bf1a-e27165dd00f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619082513 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2619082513
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.2878084698
Short name T359
Test name
Test status
Simulation time 96353810 ps
CPU time 0.99 seconds
Started Jun 07 07:16:09 PM PDT 24
Finished Jun 07 07:16:17 PM PDT 24
Peak memory 199952 kb
Host smart-ed5a3edd-34f3-44fd-bf32-6d37aa4cd082
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878084698 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.2878084698
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.4233386161
Short name T267
Test name
Test status
Simulation time 153846072083 ps
CPU time 486.03 seconds
Started Jun 07 07:16:13 PM PDT 24
Finished Jun 07 07:24:26 PM PDT 24
Peak memory 200556 kb
Host smart-8d147b4e-5902-4c83-bfb7-1c1a9052ad56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233386161 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.4233386161
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.823334230
Short name T225
Test name
Test status
Simulation time 750517485 ps
CPU time 33.78 seconds
Started Jun 07 07:16:11 PM PDT 24
Finished Jun 07 07:16:52 PM PDT 24
Peak memory 200372 kb
Host smart-2755b35b-206c-44cd-804e-c00362a635f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823334230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.823334230
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.244967473
Short name T180
Test name
Test status
Simulation time 14332035 ps
CPU time 0.6 seconds
Started Jun 07 07:16:20 PM PDT 24
Finished Jun 07 07:16:27 PM PDT 24
Peak memory 197060 kb
Host smart-d1d535c8-92f5-4982-a3eb-06e76de829d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244967473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.244967473
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3091417626
Short name T511
Test name
Test status
Simulation time 297464449 ps
CPU time 17.38 seconds
Started Jun 07 07:16:10 PM PDT 24
Finished Jun 07 07:16:35 PM PDT 24
Peak memory 227160 kb
Host smart-e166a3e7-2223-4d84-9c6a-19766269d0ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3091417626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3091417626
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.3541885268
Short name T431
Test name
Test status
Simulation time 43609228130 ps
CPU time 78.35 seconds
Started Jun 07 07:16:13 PM PDT 24
Finished Jun 07 07:17:39 PM PDT 24
Peak memory 200052 kb
Host smart-60938bd6-c4f5-40f9-bfe2-2d697505958d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541885268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3541885268
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1301422074
Short name T362
Test name
Test status
Simulation time 7699415529 ps
CPU time 1114.25 seconds
Started Jun 07 07:16:10 PM PDT 24
Finished Jun 07 07:34:51 PM PDT 24
Peak memory 768712 kb
Host smart-adaacc80-a579-453b-9118-55e6e10615e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1301422074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1301422074
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2330864164
Short name T345
Test name
Test status
Simulation time 1994518299 ps
CPU time 55.07 seconds
Started Jun 07 07:16:11 PM PDT 24
Finished Jun 07 07:17:13 PM PDT 24
Peak memory 200408 kb
Host smart-3ad7e43f-95df-407a-8480-f96b2d750157
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330864164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2330864164
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1448299249
Short name T159
Test name
Test status
Simulation time 2460594472 ps
CPU time 65.13 seconds
Started Jun 07 07:16:09 PM PDT 24
Finished Jun 07 07:17:21 PM PDT 24
Peak memory 200484 kb
Host smart-77991594-14a8-4a09-b57c-f73457f60c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448299249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1448299249
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.927120251
Short name T355
Test name
Test status
Simulation time 615545932 ps
CPU time 6.87 seconds
Started Jun 07 07:16:08 PM PDT 24
Finished Jun 07 07:16:23 PM PDT 24
Peak memory 200424 kb
Host smart-e2ff0d27-0ae1-4e78-afd4-ac0e8fa50d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927120251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.927120251
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.4265517093
Short name T105
Test name
Test status
Simulation time 686961640332 ps
CPU time 1700.9 seconds
Started Jun 07 07:16:19 PM PDT 24
Finished Jun 07 07:44:47 PM PDT 24
Peak memory 708284 kb
Host smart-11c41ef8-57be-4017-9740-e5c1ecf943b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265517093 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.4265517093
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.4013295278
Short name T473
Test name
Test status
Simulation time 424722801 ps
CPU time 1.25 seconds
Started Jun 07 07:16:20 PM PDT 24
Finished Jun 07 07:16:28 PM PDT 24
Peak memory 200392 kb
Host smart-ea3466d6-e607-4ca7-94eb-988bd78e037c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013295278 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.4013295278
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.3600008293
Short name T391
Test name
Test status
Simulation time 28876171300 ps
CPU time 411.11 seconds
Started Jun 07 07:16:22 PM PDT 24
Finished Jun 07 07:23:20 PM PDT 24
Peak memory 200400 kb
Host smart-857833c0-5494-4e5c-97c6-6b4a96b0af6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600008293 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.3600008293
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1187828731
Short name T505
Test name
Test status
Simulation time 2745497771 ps
CPU time 28.16 seconds
Started Jun 07 07:16:22 PM PDT 24
Finished Jun 07 07:16:57 PM PDT 24
Peak memory 200452 kb
Host smart-7c5a2783-57da-4450-9bd1-4341eb875c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187828731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1187828731
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.335133980
Short name T565
Test name
Test status
Simulation time 170329888 ps
CPU time 0.6 seconds
Started Jun 07 07:15:11 PM PDT 24
Finished Jun 07 07:15:14 PM PDT 24
Peak memory 196372 kb
Host smart-900c0da4-4a84-46a5-93a9-1c0963935f3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335133980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.335133980
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3474584385
Short name T220
Test name
Test status
Simulation time 2710931874 ps
CPU time 29.28 seconds
Started Jun 07 07:15:10 PM PDT 24
Finished Jun 07 07:15:42 PM PDT 24
Peak memory 215836 kb
Host smart-b9a13174-7903-4dde-a1da-a05f3c7efe5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3474584385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3474584385
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.2579221101
Short name T87
Test name
Test status
Simulation time 279768932 ps
CPU time 13.49 seconds
Started Jun 07 07:15:16 PM PDT 24
Finished Jun 07 07:15:33 PM PDT 24
Peak memory 200392 kb
Host smart-72893617-050e-44a2-ae73-c5299e5eb3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579221101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.2579221101
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.836987043
Short name T501
Test name
Test status
Simulation time 1769344888 ps
CPU time 440.4 seconds
Started Jun 07 07:15:10 PM PDT 24
Finished Jun 07 07:22:32 PM PDT 24
Peak memory 642952 kb
Host smart-f94a8afc-7ca8-46ca-9682-1cac54578a8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=836987043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.836987043
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2231775309
Short name T14
Test name
Test status
Simulation time 5169076629 ps
CPU time 65.16 seconds
Started Jun 07 07:15:10 PM PDT 24
Finished Jun 07 07:16:17 PM PDT 24
Peak memory 200452 kb
Host smart-ad33cefa-0b27-4b17-a4c1-af2c7365c809
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231775309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2231775309
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2655639725
Short name T348
Test name
Test status
Simulation time 6246371104 ps
CPU time 50.59 seconds
Started Jun 07 07:15:10 PM PDT 24
Finished Jun 07 07:16:03 PM PDT 24
Peak memory 200528 kb
Host smart-6d19b006-b04d-41bd-ae1e-1786a02f07af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655639725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2655639725
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2958293601
Short name T33
Test name
Test status
Simulation time 185900846 ps
CPU time 0.78 seconds
Started Jun 07 07:15:17 PM PDT 24
Finished Jun 07 07:15:21 PM PDT 24
Peak memory 218936 kb
Host smart-110eea62-eba9-4c9f-9e9d-03fd80af3cad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958293601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2958293601
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.400377536
Short name T374
Test name
Test status
Simulation time 209530743 ps
CPU time 4.17 seconds
Started Jun 07 07:15:14 PM PDT 24
Finished Jun 07 07:15:20 PM PDT 24
Peak memory 200416 kb
Host smart-49dd9a08-08aa-4303-93d2-fae822174efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400377536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.400377536
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1724397179
Short name T402
Test name
Test status
Simulation time 77069072660 ps
CPU time 1364.07 seconds
Started Jun 07 07:15:11 PM PDT 24
Finished Jun 07 07:37:57 PM PDT 24
Peak memory 717616 kb
Host smart-e95088ea-5a2c-4c7c-9d39-3977eadbd134
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724397179 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1724397179
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.1237556246
Short name T285
Test name
Test status
Simulation time 100275510 ps
CPU time 1.22 seconds
Started Jun 07 07:15:16 PM PDT 24
Finished Jun 07 07:15:20 PM PDT 24
Peak memory 200368 kb
Host smart-a4adc3cc-c474-4835-9f35-02e8493eacb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237556246 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.1237556246
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.1119859762
Short name T455
Test name
Test status
Simulation time 48033638153 ps
CPU time 450.17 seconds
Started Jun 07 07:15:12 PM PDT 24
Finished Jun 07 07:22:44 PM PDT 24
Peak memory 200504 kb
Host smart-20609aa6-3228-4375-b8a1-0bb1f1cdd02d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119859762 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.1119859762
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.4059892411
Short name T205
Test name
Test status
Simulation time 6788473081 ps
CPU time 67.95 seconds
Started Jun 07 07:15:16 PM PDT 24
Finished Jun 07 07:16:27 PM PDT 24
Peak memory 200420 kb
Host smart-6323b777-45ce-46ff-bf45-f7f6a3867d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059892411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.4059892411
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.3140047369
Short name T528
Test name
Test status
Simulation time 32413927 ps
CPU time 0.58 seconds
Started Jun 07 07:16:19 PM PDT 24
Finished Jun 07 07:16:26 PM PDT 24
Peak memory 195372 kb
Host smart-7148c394-7328-454d-91ab-374ae69af577
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140047369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.3140047369
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2267943536
Short name T50
Test name
Test status
Simulation time 1123725131 ps
CPU time 59.54 seconds
Started Jun 07 07:16:18 PM PDT 24
Finished Jun 07 07:17:24 PM PDT 24
Peak memory 231060 kb
Host smart-ac0990e9-66ab-4f07-899d-f699f4acf83d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2267943536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2267943536
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3338691107
Short name T531
Test name
Test status
Simulation time 210032188 ps
CPU time 10.98 seconds
Started Jun 07 07:16:20 PM PDT 24
Finished Jun 07 07:16:38 PM PDT 24
Peak memory 200316 kb
Host smart-3ff43104-9647-4406-9113-6df40ea6ff41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338691107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3338691107
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2732825009
Short name T472
Test name
Test status
Simulation time 3117865002 ps
CPU time 376.99 seconds
Started Jun 07 07:16:20 PM PDT 24
Finished Jun 07 07:22:44 PM PDT 24
Peak memory 637168 kb
Host smart-10d661fb-c266-440e-b46c-c6cc353c5c7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2732825009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2732825009
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.640903282
Short name T483
Test name
Test status
Simulation time 2646138825 ps
CPU time 139.64 seconds
Started Jun 07 07:16:22 PM PDT 24
Finished Jun 07 07:18:48 PM PDT 24
Peak memory 200456 kb
Host smart-55cf7794-47ec-4e22-bd33-169461c4ac46
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640903282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.640903282
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2202105541
Short name T212
Test name
Test status
Simulation time 6565025388 ps
CPU time 64.92 seconds
Started Jun 07 07:16:22 PM PDT 24
Finished Jun 07 07:17:34 PM PDT 24
Peak memory 200432 kb
Host smart-5dd06449-8102-488c-a4dd-dea30f8dd10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202105541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2202105541
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.91532894
Short name T81
Test name
Test status
Simulation time 183037116 ps
CPU time 2.7 seconds
Started Jun 07 07:16:19 PM PDT 24
Finished Jun 07 07:16:28 PM PDT 24
Peak memory 200464 kb
Host smart-a7f1bb86-07ba-4c6c-bcdb-135801bf2553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91532894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.91532894
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.441536543
Short name T508
Test name
Test status
Simulation time 1081691004 ps
CPU time 8.44 seconds
Started Jun 07 07:16:19 PM PDT 24
Finished Jun 07 07:16:35 PM PDT 24
Peak memory 200476 kb
Host smart-f1ddf82c-a766-430f-868d-660348e38945
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441536543 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.441536543
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.2006924813
Short name T140
Test name
Test status
Simulation time 195239579 ps
CPU time 1.1 seconds
Started Jun 07 07:16:18 PM PDT 24
Finished Jun 07 07:16:25 PM PDT 24
Peak memory 200244 kb
Host smart-645b0ce4-1c24-4cbd-aba1-6a7cafbb68b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006924813 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.2006924813
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.1604688007
Short name T466
Test name
Test status
Simulation time 8363673885 ps
CPU time 455.49 seconds
Started Jun 07 07:16:17 PM PDT 24
Finished Jun 07 07:23:59 PM PDT 24
Peak memory 200424 kb
Host smart-40a6f0a5-091e-40f0-b176-1ef1cab0f5ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604688007 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.1604688007
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3262604685
Short name T30
Test name
Test status
Simulation time 5994568727 ps
CPU time 53.28 seconds
Started Jun 07 07:16:19 PM PDT 24
Finished Jun 07 07:17:19 PM PDT 24
Peak memory 200476 kb
Host smart-b2366357-e6e2-4d4b-b631-a5bfb6c90aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262604685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3262604685
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1904417151
Short name T286
Test name
Test status
Simulation time 14060010 ps
CPU time 0.59 seconds
Started Jun 07 07:16:19 PM PDT 24
Finished Jun 07 07:16:27 PM PDT 24
Peak memory 195320 kb
Host smart-a0cfeef2-c23f-4351-88bd-4233544c8a68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904417151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1904417151
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1407917994
Short name T580
Test name
Test status
Simulation time 1059259052 ps
CPU time 49.2 seconds
Started Jun 07 07:16:20 PM PDT 24
Finished Jun 07 07:17:15 PM PDT 24
Peak memory 216796 kb
Host smart-e1bb2e80-f3d3-44cf-b839-dd308e3892f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1407917994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1407917994
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.4201723412
Short name T342
Test name
Test status
Simulation time 10663341362 ps
CPU time 55.77 seconds
Started Jun 07 07:16:19 PM PDT 24
Finished Jun 07 07:17:22 PM PDT 24
Peak memory 200436 kb
Host smart-5ee5f243-42b4-4339-aca9-f794319ef6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201723412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.4201723412
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2616855588
Short name T425
Test name
Test status
Simulation time 6409686411 ps
CPU time 407.3 seconds
Started Jun 07 07:16:22 PM PDT 24
Finished Jun 07 07:23:17 PM PDT 24
Peak memory 672940 kb
Host smart-3c9ac724-c3ed-4a61-b6a7-24919a27f81d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2616855588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2616855588
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3755879242
Short name T289
Test name
Test status
Simulation time 1298263981 ps
CPU time 18.53 seconds
Started Jun 07 07:16:20 PM PDT 24
Finished Jun 07 07:16:45 PM PDT 24
Peak memory 200456 kb
Host smart-6ba94b11-2178-494c-9dcb-c97d50f2836f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755879242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3755879242
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.2994489665
Short name T576
Test name
Test status
Simulation time 41153740826 ps
CPU time 95.03 seconds
Started Jun 07 07:16:22 PM PDT 24
Finished Jun 07 07:18:04 PM PDT 24
Peak memory 200456 kb
Host smart-02a06681-144a-4872-9be9-1fbebdfac69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994489665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.2994489665
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3061978843
Short name T263
Test name
Test status
Simulation time 631594503 ps
CPU time 3.45 seconds
Started Jun 07 07:16:19 PM PDT 24
Finished Jun 07 07:16:30 PM PDT 24
Peak memory 200428 kb
Host smart-e58a1222-7d35-4bbe-bc7c-38134fc2c6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061978843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3061978843
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.3138509566
Short name T394
Test name
Test status
Simulation time 209364562800 ps
CPU time 1131.36 seconds
Started Jun 07 07:16:19 PM PDT 24
Finished Jun 07 07:35:17 PM PDT 24
Peak memory 200532 kb
Host smart-70f106c8-60eb-4591-9952-9dcc975f1268
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138509566 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.3138509566
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.3421954604
Short name T585
Test name
Test status
Simulation time 264498502 ps
CPU time 1.11 seconds
Started Jun 07 07:16:21 PM PDT 24
Finished Jun 07 07:16:30 PM PDT 24
Peak memory 200220 kb
Host smart-f1447f7c-4f7a-4a4b-96c6-34a7e967fba8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421954604 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.3421954604
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.3661881992
Short name T318
Test name
Test status
Simulation time 105753248128 ps
CPU time 509.38 seconds
Started Jun 07 07:16:19 PM PDT 24
Finished Jun 07 07:24:56 PM PDT 24
Peak memory 200420 kb
Host smart-41066b3c-2362-4072-8fdf-3881dbe4ea9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661881992 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.3661881992
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.305845024
Short name T540
Test name
Test status
Simulation time 490123736 ps
CPU time 14.46 seconds
Started Jun 07 07:16:20 PM PDT 24
Finished Jun 07 07:16:41 PM PDT 24
Peak memory 200384 kb
Host smart-652f73e5-c017-4335-b5ef-b0c69e739e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305845024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.305845024
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1441790702
Short name T502
Test name
Test status
Simulation time 55182663 ps
CPU time 0.61 seconds
Started Jun 07 07:16:29 PM PDT 24
Finished Jun 07 07:16:38 PM PDT 24
Peak memory 196368 kb
Host smart-bac21e8a-6f0a-4407-b9e9-e3e51637ae3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441790702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1441790702
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1168149072
Short name T325
Test name
Test status
Simulation time 1964637348 ps
CPU time 25.55 seconds
Started Jun 07 07:16:20 PM PDT 24
Finished Jun 07 07:16:53 PM PDT 24
Peak memory 216820 kb
Host smart-1b1c3057-6480-4d2f-8709-10c44eac4c73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1168149072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1168149072
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.444920322
Short name T124
Test name
Test status
Simulation time 4905006864 ps
CPU time 52.3 seconds
Started Jun 07 07:16:19 PM PDT 24
Finished Jun 07 07:17:18 PM PDT 24
Peak memory 200452 kb
Host smart-4bc3578e-6f1e-43fc-8442-eb495489b766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444920322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.444920322
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2375613817
Short name T197
Test name
Test status
Simulation time 22170951 ps
CPU time 0.88 seconds
Started Jun 07 07:16:20 PM PDT 24
Finished Jun 07 07:16:27 PM PDT 24
Peak memory 199568 kb
Host smart-dd23bf3f-9655-47e7-8afe-af0ff686eed0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2375613817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2375613817
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.1875156157
Short name T423
Test name
Test status
Simulation time 7702690111 ps
CPU time 48.8 seconds
Started Jun 07 07:16:18 PM PDT 24
Finished Jun 07 07:17:14 PM PDT 24
Peak memory 200404 kb
Host smart-d4932ed2-ee0a-4031-8b0c-2d040cee2db4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875156157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1875156157
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2213413498
Short name T64
Test name
Test status
Simulation time 1063402904 ps
CPU time 19.37 seconds
Started Jun 07 07:16:19 PM PDT 24
Finished Jun 07 07:16:45 PM PDT 24
Peak memory 200488 kb
Host smart-e1d0a8f9-3d70-44f3-96d3-938b5bcebea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213413498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2213413498
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.4180427798
Short name T492
Test name
Test status
Simulation time 599247210 ps
CPU time 2.87 seconds
Started Jun 07 07:16:18 PM PDT 24
Finished Jun 07 07:16:28 PM PDT 24
Peak memory 200384 kb
Host smart-28d94b92-ef5b-4be3-b1ef-afc67a1708c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180427798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.4180427798
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.100191407
Short name T477
Test name
Test status
Simulation time 106743281 ps
CPU time 1.1 seconds
Started Jun 07 07:16:28 PM PDT 24
Finished Jun 07 07:16:37 PM PDT 24
Peak memory 200224 kb
Host smart-b02be15a-ff15-4a0a-a55d-dc6dbbbcd942
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100191407 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_hmac_vectors.100191407
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.1363369363
Short name T413
Test name
Test status
Simulation time 70279192008 ps
CPU time 464.66 seconds
Started Jun 07 07:16:26 PM PDT 24
Finished Jun 07 07:24:19 PM PDT 24
Peak memory 200424 kb
Host smart-153c60f1-20f1-49ec-9044-6f168ef515d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363369363 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.1363369363
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.2508786035
Short name T493
Test name
Test status
Simulation time 4634317799 ps
CPU time 44.1 seconds
Started Jun 07 07:16:27 PM PDT 24
Finished Jun 07 07:17:20 PM PDT 24
Peak memory 200468 kb
Host smart-d58ddf6b-a6a7-491d-899e-6eaed9cae29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508786035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.2508786035
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2380693012
Short name T372
Test name
Test status
Simulation time 14280685 ps
CPU time 0.62 seconds
Started Jun 07 07:16:28 PM PDT 24
Finished Jun 07 07:16:37 PM PDT 24
Peak memory 196404 kb
Host smart-186b358e-8319-4277-8d70-a1df8aeeb5a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380693012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2380693012
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3297504131
Short name T495
Test name
Test status
Simulation time 5905216815 ps
CPU time 31.2 seconds
Started Jun 07 07:16:28 PM PDT 24
Finished Jun 07 07:17:07 PM PDT 24
Peak memory 216548 kb
Host smart-1f910cf0-6cc7-4abb-bda9-1236a2800f7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3297504131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3297504131
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.2232546654
Short name T504
Test name
Test status
Simulation time 421665166 ps
CPU time 19.38 seconds
Started Jun 07 07:16:29 PM PDT 24
Finished Jun 07 07:16:56 PM PDT 24
Peak memory 200460 kb
Host smart-14eac148-0ea6-4d96-880b-7973260f627e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232546654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2232546654
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.3034815653
Short name T381
Test name
Test status
Simulation time 7301909757 ps
CPU time 422.7 seconds
Started Jun 07 07:16:28 PM PDT 24
Finished Jun 07 07:23:39 PM PDT 24
Peak memory 669220 kb
Host smart-38a8b411-3179-4a90-bfe3-6a7414dd4422
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3034815653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3034815653
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1417209734
Short name T464
Test name
Test status
Simulation time 23243199752 ps
CPU time 107.09 seconds
Started Jun 07 07:16:27 PM PDT 24
Finished Jun 07 07:18:22 PM PDT 24
Peak memory 200468 kb
Host smart-d32953e1-10a1-42aa-910b-bc187cb3d0e8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417209734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1417209734
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.1936603683
Short name T389
Test name
Test status
Simulation time 22115682020 ps
CPU time 110.21 seconds
Started Jun 07 07:16:29 PM PDT 24
Finished Jun 07 07:18:27 PM PDT 24
Peak memory 200436 kb
Host smart-2e71a84a-1156-442a-9cef-9cc2aabbd109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936603683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1936603683
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1592291937
Short name T543
Test name
Test status
Simulation time 136508419 ps
CPU time 2.75 seconds
Started Jun 07 07:16:28 PM PDT 24
Finished Jun 07 07:16:38 PM PDT 24
Peak memory 200424 kb
Host smart-6ba2787f-8cb4-4ca8-b531-db5d3ee8ca45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592291937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1592291937
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.4253251739
Short name T562
Test name
Test status
Simulation time 80383100459 ps
CPU time 594.84 seconds
Started Jun 07 07:16:30 PM PDT 24
Finished Jun 07 07:26:32 PM PDT 24
Peak memory 226672 kb
Host smart-b0cee745-6198-4a16-a2bf-83b8fd27ffe2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253251739 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.4253251739
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.1004691644
Short name T136
Test name
Test status
Simulation time 270724514 ps
CPU time 1.43 seconds
Started Jun 07 07:16:30 PM PDT 24
Finished Jun 07 07:16:39 PM PDT 24
Peak memory 200460 kb
Host smart-35f9f569-2052-45ba-abb8-31b18e88f852
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004691644 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.1004691644
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.1912689278
Short name T165
Test name
Test status
Simulation time 115386010861 ps
CPU time 500.49 seconds
Started Jun 07 07:16:29 PM PDT 24
Finished Jun 07 07:24:58 PM PDT 24
Peak memory 200364 kb
Host smart-c2ee3ada-f4ba-44d1-9fed-5f431a04f4d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912689278 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.1912689278
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.2705238345
Short name T193
Test name
Test status
Simulation time 6855163769 ps
CPU time 58.59 seconds
Started Jun 07 07:16:27 PM PDT 24
Finished Jun 07 07:17:33 PM PDT 24
Peak memory 200492 kb
Host smart-7dac70fd-5765-4291-bc2c-5a283ca5c2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705238345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2705238345
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.4063195827
Short name T393
Test name
Test status
Simulation time 75052639 ps
CPU time 0.65 seconds
Started Jun 07 07:16:42 PM PDT 24
Finished Jun 07 07:16:49 PM PDT 24
Peak memory 196360 kb
Host smart-9e5af662-cebe-439b-bffe-e4086fe34b33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063195827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.4063195827
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.77060835
Short name T421
Test name
Test status
Simulation time 1002329043 ps
CPU time 49.86 seconds
Started Jun 07 07:16:28 PM PDT 24
Finished Jun 07 07:17:26 PM PDT 24
Peak memory 216840 kb
Host smart-40081be8-abad-4016-b949-4910c7eaf9d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77060835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.77060835
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2791615714
Short name T299
Test name
Test status
Simulation time 2307274677 ps
CPU time 23.85 seconds
Started Jun 07 07:16:28 PM PDT 24
Finished Jun 07 07:17:00 PM PDT 24
Peak memory 200512 kb
Host smart-dfa6b554-dcac-4337-bf6f-9fff62800cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791615714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2791615714
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3969289401
Short name T569
Test name
Test status
Simulation time 539945147 ps
CPU time 126.91 seconds
Started Jun 07 07:16:27 PM PDT 24
Finished Jun 07 07:18:42 PM PDT 24
Peak memory 578200 kb
Host smart-ad35d16c-657d-4862-a343-3ff2b9c72f38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3969289401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3969289401
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.3977432730
Short name T468
Test name
Test status
Simulation time 726479934 ps
CPU time 40.53 seconds
Started Jun 07 07:16:28 PM PDT 24
Finished Jun 07 07:17:17 PM PDT 24
Peak memory 200316 kb
Host smart-6b6b897a-bd25-45de-b63e-1866b70e8ed1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977432730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3977432730
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1964548370
Short name T340
Test name
Test status
Simulation time 3731614896 ps
CPU time 104.39 seconds
Started Jun 07 07:16:27 PM PDT 24
Finished Jun 07 07:18:19 PM PDT 24
Peak memory 200516 kb
Host smart-d62fb93f-d702-438e-a20b-96d9c99addf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964548370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1964548370
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1458867142
Short name T449
Test name
Test status
Simulation time 1048926264 ps
CPU time 6.07 seconds
Started Jun 07 07:16:25 PM PDT 24
Finished Jun 07 07:16:39 PM PDT 24
Peak memory 200508 kb
Host smart-6373e1e1-2b10-4616-af1c-d17bc4175dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458867142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1458867142
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.3460645718
Short name T39
Test name
Test status
Simulation time 1481063132694 ps
CPU time 2250.72 seconds
Started Jun 07 07:16:44 PM PDT 24
Finished Jun 07 07:54:21 PM PDT 24
Peak memory 768076 kb
Host smart-8ed68c53-f0f3-44a7-90f6-bba4021210f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460645718 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.3460645718
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.3385570639
Short name T392
Test name
Test status
Simulation time 310489535 ps
CPU time 1.36 seconds
Started Jun 07 07:16:43 PM PDT 24
Finished Jun 07 07:16:51 PM PDT 24
Peak memory 200392 kb
Host smart-598e9743-170a-4a9c-b145-711039de08de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385570639 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.3385570639
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.3968355292
Short name T65
Test name
Test status
Simulation time 37578679330 ps
CPU time 451.27 seconds
Started Jun 07 07:16:27 PM PDT 24
Finished Jun 07 07:24:07 PM PDT 24
Peak memory 200420 kb
Host smart-a3025f2a-ab62-4ee5-a77f-542b14a8ba08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968355292 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.3968355292
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2154268435
Short name T592
Test name
Test status
Simulation time 2460331815 ps
CPU time 30.2 seconds
Started Jun 07 07:16:29 PM PDT 24
Finished Jun 07 07:17:07 PM PDT 24
Peak memory 200396 kb
Host smart-775aa77a-4ca9-4fcb-9eae-fe8de3e80388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154268435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2154268435
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2037308573
Short name T22
Test name
Test status
Simulation time 12643543 ps
CPU time 0.59 seconds
Started Jun 07 07:16:40 PM PDT 24
Finished Jun 07 07:16:48 PM PDT 24
Peak memory 196136 kb
Host smart-2ebd8560-2955-4c42-b024-cbaf37771f8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037308573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2037308573
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.3752320448
Short name T157
Test name
Test status
Simulation time 2475940162 ps
CPU time 29.1 seconds
Started Jun 07 07:16:42 PM PDT 24
Finished Jun 07 07:17:18 PM PDT 24
Peak memory 226888 kb
Host smart-c778b7d8-4540-48da-93ae-c88da5b7f624
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3752320448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3752320448
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.105327694
Short name T424
Test name
Test status
Simulation time 1124667026 ps
CPU time 28.74 seconds
Started Jun 07 07:16:42 PM PDT 24
Finished Jun 07 07:17:18 PM PDT 24
Peak memory 200444 kb
Host smart-35cbbcc3-d63e-4b2f-b101-cccd83d2b831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105327694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.105327694
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3558028084
Short name T447
Test name
Test status
Simulation time 5093929266 ps
CPU time 401.27 seconds
Started Jun 07 07:16:41 PM PDT 24
Finished Jun 07 07:23:29 PM PDT 24
Peak memory 483992 kb
Host smart-b9932d8b-85ee-4b83-a5a5-3c2b346458ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3558028084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3558028084
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3467321803
Short name T549
Test name
Test status
Simulation time 19834263867 ps
CPU time 138.46 seconds
Started Jun 07 07:16:43 PM PDT 24
Finished Jun 07 07:19:08 PM PDT 24
Peak memory 200340 kb
Host smart-59ed4479-0844-42b0-8a12-0cc0223ec5aa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467321803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3467321803
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.886264167
Short name T539
Test name
Test status
Simulation time 3235474778 ps
CPU time 99.16 seconds
Started Jun 07 07:16:44 PM PDT 24
Finished Jun 07 07:18:29 PM PDT 24
Peak memory 200484 kb
Host smart-da9337c5-3072-4f9a-af01-58882adf4d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886264167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.886264167
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2700757458
Short name T367
Test name
Test status
Simulation time 1399035895 ps
CPU time 9.03 seconds
Started Jun 07 07:16:42 PM PDT 24
Finished Jun 07 07:16:58 PM PDT 24
Peak memory 200432 kb
Host smart-22ea1f49-934a-4bc9-9d42-f6451f511a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700757458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2700757458
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.779718918
Short name T479
Test name
Test status
Simulation time 91159030001 ps
CPU time 1171.13 seconds
Started Jun 07 07:16:42 PM PDT 24
Finished Jun 07 07:36:20 PM PDT 24
Peak memory 200484 kb
Host smart-aeb142c7-5b53-4854-b635-cda0aa13da07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779718918 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.779718918
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.3988393863
Short name T586
Test name
Test status
Simulation time 56148655 ps
CPU time 1.09 seconds
Started Jun 07 07:16:43 PM PDT 24
Finished Jun 07 07:16:51 PM PDT 24
Peak memory 200384 kb
Host smart-05bb4329-d2d9-4315-93ca-5fdfef15355d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988393863 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.3988393863
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.2209100090
Short name T352
Test name
Test status
Simulation time 41574587702 ps
CPU time 583.71 seconds
Started Jun 07 07:16:43 PM PDT 24
Finished Jun 07 07:26:33 PM PDT 24
Peak memory 200416 kb
Host smart-6aab7cce-22a0-4e14-b0a2-cd35ad43253c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209100090 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.2209100090
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2806029310
Short name T550
Test name
Test status
Simulation time 1017615543 ps
CPU time 35.88 seconds
Started Jun 07 07:16:41 PM PDT 24
Finished Jun 07 07:17:24 PM PDT 24
Peak memory 200428 kb
Host smart-c6bdc589-19e7-4767-8b5b-f369024ac106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806029310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2806029310
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.947308884
Short name T213
Test name
Test status
Simulation time 28702677 ps
CPU time 0.63 seconds
Started Jun 07 07:16:41 PM PDT 24
Finished Jun 07 07:16:49 PM PDT 24
Peak memory 196384 kb
Host smart-817d295b-3c20-4021-b94c-304f73a54658
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947308884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.947308884
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.4218931951
Short name T375
Test name
Test status
Simulation time 2099315855 ps
CPU time 9.83 seconds
Started Jun 07 07:16:40 PM PDT 24
Finished Jun 07 07:16:57 PM PDT 24
Peak memory 216528 kb
Host smart-4a2039c2-efcc-4b0a-aa81-472934569971
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4218931951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.4218931951
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.3265814316
Short name T13
Test name
Test status
Simulation time 2863326528 ps
CPU time 55.73 seconds
Started Jun 07 07:16:43 PM PDT 24
Finished Jun 07 07:17:45 PM PDT 24
Peak memory 200544 kb
Host smart-792f8f7b-c0c4-42af-ac20-6078c8b3d4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265814316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3265814316
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3186094244
Short name T66
Test name
Test status
Simulation time 8303652085 ps
CPU time 1296.73 seconds
Started Jun 07 07:16:42 PM PDT 24
Finished Jun 07 07:38:26 PM PDT 24
Peak memory 772196 kb
Host smart-cf081573-4032-4a06-90dd-ea7a0f448237
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3186094244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3186094244
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2101075755
Short name T570
Test name
Test status
Simulation time 48021082558 ps
CPU time 133.34 seconds
Started Jun 07 07:16:40 PM PDT 24
Finished Jun 07 07:19:00 PM PDT 24
Peak memory 200568 kb
Host smart-fbff2f6b-84ef-4d7e-b16f-27a84b3e045f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101075755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2101075755
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3721468431
Short name T509
Test name
Test status
Simulation time 4352727850 ps
CPU time 125.47 seconds
Started Jun 07 07:16:42 PM PDT 24
Finished Jun 07 07:18:54 PM PDT 24
Peak memory 200536 kb
Host smart-0d552afc-1ad2-4571-b7cd-420d0df61503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721468431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3721468431
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.1590309684
Short name T419
Test name
Test status
Simulation time 272263525 ps
CPU time 1.83 seconds
Started Jun 07 07:16:40 PM PDT 24
Finished Jun 07 07:16:49 PM PDT 24
Peak memory 200340 kb
Host smart-5a81c448-f9be-4e69-8e15-a17a03813501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590309684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1590309684
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.61334438
Short name T452
Test name
Test status
Simulation time 177636643747 ps
CPU time 858.62 seconds
Started Jun 07 07:16:40 PM PDT 24
Finished Jun 07 07:31:05 PM PDT 24
Peak memory 231932 kb
Host smart-9291f46e-7b8d-4282-aba5-6c5bc497dae5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61334438 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.61334438
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.2276418866
Short name T366
Test name
Test status
Simulation time 479895251 ps
CPU time 1.29 seconds
Started Jun 07 07:16:43 PM PDT 24
Finished Jun 07 07:16:51 PM PDT 24
Peak memory 200236 kb
Host smart-db71d273-1b4c-4392-a13e-f6ae468dc1b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276418866 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.2276418866
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.2818676502
Short name T2
Test name
Test status
Simulation time 50556917796 ps
CPU time 470.08 seconds
Started Jun 07 07:16:41 PM PDT 24
Finished Jun 07 07:24:38 PM PDT 24
Peak memory 200388 kb
Host smart-88520da6-4d9c-43dc-a8de-a40e6020c645
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818676502 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.2818676502
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.3156694463
Short name T351
Test name
Test status
Simulation time 5338684551 ps
CPU time 26.07 seconds
Started Jun 07 07:16:39 PM PDT 24
Finished Jun 07 07:17:12 PM PDT 24
Peak memory 200424 kb
Host smart-6418bd9a-c892-40d9-9ab0-166866da0a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156694463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.3156694463
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.155425934
Short name T127
Test name
Test status
Simulation time 20618169 ps
CPU time 0.61 seconds
Started Jun 07 07:16:53 PM PDT 24
Finished Jun 07 07:17:01 PM PDT 24
Peak memory 197032 kb
Host smart-68d1c4b0-c259-41d6-b4d5-52c530dcb161
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155425934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.155425934
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.554639426
Short name T369
Test name
Test status
Simulation time 1703061261 ps
CPU time 26.78 seconds
Started Jun 07 07:16:43 PM PDT 24
Finished Jun 07 07:17:16 PM PDT 24
Peak memory 224936 kb
Host smart-b7a9da0d-caaf-4575-872f-1ca2699c0f2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=554639426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.554639426
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.810370057
Short name T365
Test name
Test status
Simulation time 908567826 ps
CPU time 49.37 seconds
Started Jun 07 07:16:40 PM PDT 24
Finished Jun 07 07:17:36 PM PDT 24
Peak memory 200392 kb
Host smart-9053bf5c-c12a-4a6f-a673-54cba1d58b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810370057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.810370057
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1434876066
Short name T417
Test name
Test status
Simulation time 2017371608 ps
CPU time 498.67 seconds
Started Jun 07 07:16:41 PM PDT 24
Finished Jun 07 07:25:07 PM PDT 24
Peak memory 665596 kb
Host smart-4b43e90d-6030-4e46-840d-57e0f0c45479
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1434876066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1434876066
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1922811524
Short name T151
Test name
Test status
Simulation time 7602994406 ps
CPU time 95.9 seconds
Started Jun 07 07:16:42 PM PDT 24
Finished Jun 07 07:18:25 PM PDT 24
Peak memory 200520 kb
Host smart-e1e6a587-a154-48b2-8a0c-dbbdccacd452
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922811524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1922811524
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2150302335
Short name T548
Test name
Test status
Simulation time 39828645454 ps
CPU time 155.03 seconds
Started Jun 07 07:16:41 PM PDT 24
Finished Jun 07 07:19:23 PM PDT 24
Peak memory 200512 kb
Host smart-9b937e93-e998-41a3-9bbe-46317a8ce09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150302335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2150302335
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.236287248
Short name T591
Test name
Test status
Simulation time 61614080 ps
CPU time 1.6 seconds
Started Jun 07 07:16:43 PM PDT 24
Finished Jun 07 07:16:51 PM PDT 24
Peak memory 200468 kb
Host smart-24945f0a-888e-4885-b3c0-a173c30e5e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236287248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.236287248
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.4179028046
Short name T291
Test name
Test status
Simulation time 4016582061 ps
CPU time 224.7 seconds
Started Jun 07 07:16:41 PM PDT 24
Finished Jun 07 07:20:33 PM PDT 24
Peak memory 200416 kb
Host smart-0a7b744a-9a45-4dc0-a521-c7feceb757d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179028046 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.4179028046
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.1616806957
Short name T470
Test name
Test status
Simulation time 224964642 ps
CPU time 1.39 seconds
Started Jun 07 07:16:43 PM PDT 24
Finished Jun 07 07:16:51 PM PDT 24
Peak memory 200428 kb
Host smart-cb5b945e-c6f4-42ca-aae2-fd3b486ae3b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616806957 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.1616806957
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.2173203378
Short name T399
Test name
Test status
Simulation time 27493250838 ps
CPU time 516.05 seconds
Started Jun 07 07:16:43 PM PDT 24
Finished Jun 07 07:25:25 PM PDT 24
Peak memory 200400 kb
Host smart-a87fbfca-13b2-4f01-8377-46d57c52c460
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173203378 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.2173203378
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.4210925019
Short name T182
Test name
Test status
Simulation time 24253918609 ps
CPU time 32.85 seconds
Started Jun 07 07:16:41 PM PDT 24
Finished Jun 07 07:17:21 PM PDT 24
Peak memory 200480 kb
Host smart-4211ab4e-b9f0-4461-9a2e-884bb86a28b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210925019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.4210925019
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.1493582887
Short name T250
Test name
Test status
Simulation time 10579381 ps
CPU time 0.53 seconds
Started Jun 07 07:16:50 PM PDT 24
Finished Jun 07 07:16:56 PM PDT 24
Peak memory 195232 kb
Host smart-95dc3227-51dd-478d-b1de-6eece0ed284d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493582887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1493582887
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.1134837016
Short name T60
Test name
Test status
Simulation time 6043455658 ps
CPU time 60.28 seconds
Started Jun 07 07:16:54 PM PDT 24
Finished Jun 07 07:18:02 PM PDT 24
Peak memory 225064 kb
Host smart-cfff6477-93c1-44d2-af7f-7a7c2cfb9421
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1134837016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1134837016
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.918450486
Short name T344
Test name
Test status
Simulation time 626280181 ps
CPU time 7.85 seconds
Started Jun 07 07:16:54 PM PDT 24
Finished Jun 07 07:17:08 PM PDT 24
Peak memory 200368 kb
Host smart-7a2d070d-11a1-4dde-bff6-d0b7ff1d1796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918450486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.918450486
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2460652966
Short name T103
Test name
Test status
Simulation time 3855220095 ps
CPU time 1104.86 seconds
Started Jun 07 07:16:50 PM PDT 24
Finished Jun 07 07:35:21 PM PDT 24
Peak memory 722140 kb
Host smart-5532e75f-3ca6-4cb5-b78d-097f7d103cc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2460652966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2460652966
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.1670732183
Short name T323
Test name
Test status
Simulation time 4197773402 ps
CPU time 29.48 seconds
Started Jun 07 07:16:54 PM PDT 24
Finished Jun 07 07:17:31 PM PDT 24
Peak memory 200452 kb
Host smart-ab4eddf4-724e-4517-9498-2b3420a718c0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670732183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.1670732183
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.674031831
Short name T260
Test name
Test status
Simulation time 2213197784 ps
CPU time 33.4 seconds
Started Jun 07 07:16:50 PM PDT 24
Finished Jun 07 07:17:29 PM PDT 24
Peak memory 200504 kb
Host smart-ff02d776-223a-4b1f-9e63-dbfd61543cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674031831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.674031831
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2711983051
Short name T544
Test name
Test status
Simulation time 1659143878 ps
CPU time 9.7 seconds
Started Jun 07 07:16:54 PM PDT 24
Finished Jun 07 07:17:10 PM PDT 24
Peak memory 200468 kb
Host smart-1311f182-aaa7-4168-b871-644b52d57567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711983051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2711983051
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.2977900748
Short name T243
Test name
Test status
Simulation time 104154486315 ps
CPU time 3290.95 seconds
Started Jun 07 07:16:53 PM PDT 24
Finished Jun 07 08:11:51 PM PDT 24
Peak memory 858564 kb
Host smart-824334a3-3fdc-49ba-8ba4-ea8c82095d77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977900748 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.2977900748
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.1975351836
Short name T272
Test name
Test status
Simulation time 498255057 ps
CPU time 1.08 seconds
Started Jun 07 07:16:53 PM PDT 24
Finished Jun 07 07:17:00 PM PDT 24
Peak memory 200264 kb
Host smart-0b91fdda-93bc-417e-aad6-1c226959dee4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975351836 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.1975351836
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.3678578012
Short name T188
Test name
Test status
Simulation time 31469880450 ps
CPU time 439.26 seconds
Started Jun 07 07:16:51 PM PDT 24
Finished Jun 07 07:24:16 PM PDT 24
Peak memory 200384 kb
Host smart-4cf8a3e2-52ee-44b8-83b3-b2e8562cebbd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678578012 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.3678578012
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.4036169387
Short name T346
Test name
Test status
Simulation time 10926202647 ps
CPU time 79.01 seconds
Started Jun 07 07:16:52 PM PDT 24
Finished Jun 07 07:18:17 PM PDT 24
Peak memory 200528 kb
Host smart-58b06a90-5a8f-47e7-9fb3-bb83b3806d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036169387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.4036169387
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2901693396
Short name T304
Test name
Test status
Simulation time 37778763 ps
CPU time 0.59 seconds
Started Jun 07 07:16:54 PM PDT 24
Finished Jun 07 07:17:02 PM PDT 24
Peak memory 195360 kb
Host smart-a23b3898-8941-4c32-b616-ca3e1129f51e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901693396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2901693396
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.2293780799
Short name T137
Test name
Test status
Simulation time 1913771874 ps
CPU time 51.86 seconds
Started Jun 07 07:16:52 PM PDT 24
Finished Jun 07 07:17:50 PM PDT 24
Peak memory 232072 kb
Host smart-490f7cb4-6f9d-452c-af5b-3ab049cd1c0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2293780799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.2293780799
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.296513126
Short name T415
Test name
Test status
Simulation time 4551117729 ps
CPU time 41.02 seconds
Started Jun 07 07:16:53 PM PDT 24
Finished Jun 07 07:17:41 PM PDT 24
Peak memory 200456 kb
Host smart-b707b950-9709-478b-b293-9883195b6872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296513126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.296513126
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3940575828
Short name T314
Test name
Test status
Simulation time 12041776635 ps
CPU time 459.4 seconds
Started Jun 07 07:16:52 PM PDT 24
Finished Jun 07 07:24:38 PM PDT 24
Peak memory 591900 kb
Host smart-f6094baa-c398-47cc-a1a9-6c6423d9e10f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3940575828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3940575828
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1380201543
Short name T581
Test name
Test status
Simulation time 10285661627 ps
CPU time 185.58 seconds
Started Jun 07 07:16:55 PM PDT 24
Finished Jun 07 07:20:07 PM PDT 24
Peak memory 200544 kb
Host smart-0a87bc9f-4fa9-437f-b88c-9784a30f5da6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380201543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1380201543
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3260246458
Short name T261
Test name
Test status
Simulation time 809197625 ps
CPU time 25.21 seconds
Started Jun 07 07:16:51 PM PDT 24
Finished Jun 07 07:17:22 PM PDT 24
Peak memory 200344 kb
Host smart-6af93cb5-8b86-40e1-a7a0-37e570499dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260246458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3260246458
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2981901420
Short name T233
Test name
Test status
Simulation time 465727657 ps
CPU time 7.7 seconds
Started Jun 07 07:16:51 PM PDT 24
Finished Jun 07 07:17:05 PM PDT 24
Peak memory 200444 kb
Host smart-0afc9134-49af-4a9c-b34b-eb26c69f1aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981901420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2981901420
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3131963809
Short name T211
Test name
Test status
Simulation time 32259078270 ps
CPU time 2257.94 seconds
Started Jun 07 07:16:51 PM PDT 24
Finished Jun 07 07:54:35 PM PDT 24
Peak memory 736500 kb
Host smart-9c05f5f7-faf1-46f1-a53f-7cf1303e2070
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131963809 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3131963809
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.2816156664
Short name T276
Test name
Test status
Simulation time 48431410 ps
CPU time 1.14 seconds
Started Jun 07 07:16:52 PM PDT 24
Finished Jun 07 07:16:59 PM PDT 24
Peak memory 200460 kb
Host smart-dd6db556-28df-403f-840d-4d8ba3bb13d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816156664 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.2816156664
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.1193556244
Short name T275
Test name
Test status
Simulation time 29659609359 ps
CPU time 420.2 seconds
Started Jun 07 07:16:49 PM PDT 24
Finished Jun 07 07:23:54 PM PDT 24
Peak memory 200508 kb
Host smart-2b2a4d77-fc02-496d-b64a-981337a770bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193556244 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.1193556244
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3024643959
Short name T337
Test name
Test status
Simulation time 10506576924 ps
CPU time 72.55 seconds
Started Jun 07 07:16:50 PM PDT 24
Finished Jun 07 07:18:08 PM PDT 24
Peak memory 200528 kb
Host smart-da69a954-1663-4b89-89da-97720cbdf352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024643959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3024643959
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2642463718
Short name T457
Test name
Test status
Simulation time 14223025 ps
CPU time 0.59 seconds
Started Jun 07 07:15:11 PM PDT 24
Finished Jun 07 07:15:14 PM PDT 24
Peak memory 195332 kb
Host smart-b28e73a6-6760-4112-af70-129b0f36e1ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642463718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2642463718
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.2045681311
Short name T512
Test name
Test status
Simulation time 257293405 ps
CPU time 14.98 seconds
Started Jun 07 07:15:13 PM PDT 24
Finished Jun 07 07:15:31 PM PDT 24
Peak memory 222980 kb
Host smart-79352431-1077-465a-91f6-12e9118a116e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2045681311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2045681311
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.1384726851
Short name T218
Test name
Test status
Simulation time 5548764314 ps
CPU time 57.66 seconds
Started Jun 07 07:15:18 PM PDT 24
Finished Jun 07 07:16:19 PM PDT 24
Peak memory 200512 kb
Host smart-f68a6588-a7a8-4c0d-b88e-b0add5b657e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384726851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.1384726851
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.119100695
Short name T582
Test name
Test status
Simulation time 3512565809 ps
CPU time 714.52 seconds
Started Jun 07 07:15:13 PM PDT 24
Finished Jun 07 07:27:10 PM PDT 24
Peak memory 663656 kb
Host smart-77eda940-a5ad-4e24-bef8-71b234e075ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=119100695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.119100695
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.3486480361
Short name T15
Test name
Test status
Simulation time 18562808360 ps
CPU time 168.59 seconds
Started Jun 07 07:15:15 PM PDT 24
Finished Jun 07 07:18:06 PM PDT 24
Peak memory 200544 kb
Host smart-0a2efea1-3079-4e83-82de-f7d31337f4ee
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486480361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3486480361
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3863875967
Short name T309
Test name
Test status
Simulation time 131650901 ps
CPU time 7.88 seconds
Started Jun 07 07:15:18 PM PDT 24
Finished Jun 07 07:15:28 PM PDT 24
Peak memory 200372 kb
Host smart-3be3c75b-cbae-436a-b3af-e054a7dbac57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863875967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3863875967
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.220310509
Short name T34
Test name
Test status
Simulation time 270818003 ps
CPU time 1.11 seconds
Started Jun 07 07:15:21 PM PDT 24
Finished Jun 07 07:15:26 PM PDT 24
Peak memory 219908 kb
Host smart-23ca8ece-d380-48a2-aadb-2db2696bc85d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220310509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.220310509
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.4017215642
Short name T142
Test name
Test status
Simulation time 354197348 ps
CPU time 3.67 seconds
Started Jun 07 07:15:17 PM PDT 24
Finished Jun 07 07:15:24 PM PDT 24
Peak memory 200368 kb
Host smart-2c321795-0210-4fad-85ef-42abfa5bf09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017215642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.4017215642
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2213894622
Short name T462
Test name
Test status
Simulation time 1010924670191 ps
CPU time 1191.79 seconds
Started Jun 07 07:15:14 PM PDT 24
Finished Jun 07 07:35:09 PM PDT 24
Peak memory 231276 kb
Host smart-f4e23f24-3dcb-43c0-9e7a-79b2f430b3a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213894622 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2213894622
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.3885048178
Short name T223
Test name
Test status
Simulation time 56046442 ps
CPU time 1.08 seconds
Started Jun 07 07:15:11 PM PDT 24
Finished Jun 07 07:15:15 PM PDT 24
Peak memory 200168 kb
Host smart-fb2b1e89-2298-4756-92ba-e4dee0103636
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885048178 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.3885048178
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.88919268
Short name T245
Test name
Test status
Simulation time 33387920794 ps
CPU time 440 seconds
Started Jun 07 07:15:10 PM PDT 24
Finished Jun 07 07:22:33 PM PDT 24
Peak memory 200384 kb
Host smart-359951f5-b089-4a24-8f04-069369635a88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88919268 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.88919268
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.938192187
Short name T518
Test name
Test status
Simulation time 9379609762 ps
CPU time 73.03 seconds
Started Jun 07 07:15:12 PM PDT 24
Finished Jun 07 07:16:28 PM PDT 24
Peak memory 200468 kb
Host smart-040e2432-a733-4b26-9691-45a7ad8f759a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938192187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.938192187
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3960083225
Short name T445
Test name
Test status
Simulation time 14900876 ps
CPU time 0.61 seconds
Started Jun 07 07:16:52 PM PDT 24
Finished Jun 07 07:16:59 PM PDT 24
Peak memory 196016 kb
Host smart-5ab8cb7b-611a-421d-b734-38bdefd5d5fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960083225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3960083225
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.593939170
Short name T497
Test name
Test status
Simulation time 142009850 ps
CPU time 6.68 seconds
Started Jun 07 07:16:51 PM PDT 24
Finished Jun 07 07:17:04 PM PDT 24
Peak memory 216720 kb
Host smart-9e17c531-34d2-422e-a453-c595f1884f34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=593939170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.593939170
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1621782699
Short name T29
Test name
Test status
Simulation time 795980700 ps
CPU time 45.55 seconds
Started Jun 07 07:16:53 PM PDT 24
Finished Jun 07 07:17:45 PM PDT 24
Peak memory 200356 kb
Host smart-50d3f06a-29f7-459c-b585-be58229f0c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621782699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1621782699
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1794939162
Short name T36
Test name
Test status
Simulation time 9153886934 ps
CPU time 605.41 seconds
Started Jun 07 07:16:54 PM PDT 24
Finished Jun 07 07:27:07 PM PDT 24
Peak memory 645328 kb
Host smart-ac4e3383-6d82-44d7-b637-3ac943b7b360
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1794939162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1794939162
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.1149634421
Short name T333
Test name
Test status
Simulation time 26050857768 ps
CPU time 81.59 seconds
Started Jun 07 07:16:51 PM PDT 24
Finished Jun 07 07:18:19 PM PDT 24
Peak memory 200416 kb
Host smart-55bbe1ba-d329-48fa-8d48-2ac76a0f6730
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149634421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.1149634421
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3571910888
Short name T216
Test name
Test status
Simulation time 2488582218 ps
CPU time 81.05 seconds
Started Jun 07 07:16:52 PM PDT 24
Finished Jun 07 07:18:19 PM PDT 24
Peak memory 200468 kb
Host smart-375fdec6-5048-4698-bc3d-5de2fea3904b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571910888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3571910888
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.3009559032
Short name T176
Test name
Test status
Simulation time 370285397 ps
CPU time 6.75 seconds
Started Jun 07 07:16:50 PM PDT 24
Finished Jun 07 07:17:02 PM PDT 24
Peak memory 200384 kb
Host smart-3ae07c9b-485c-429f-be87-0e3fa6b37037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009559032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.3009559032
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.4041714813
Short name T158
Test name
Test status
Simulation time 196705400 ps
CPU time 1.03 seconds
Started Jun 07 07:16:52 PM PDT 24
Finished Jun 07 07:16:59 PM PDT 24
Peak memory 200180 kb
Host smart-f177d863-4e16-41ab-b708-d876b34394da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041714813 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.4041714813
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.2618084743
Short name T405
Test name
Test status
Simulation time 36315580776 ps
CPU time 499.37 seconds
Started Jun 07 07:16:54 PM PDT 24
Finished Jun 07 07:25:21 PM PDT 24
Peak memory 200388 kb
Host smart-e9bcbced-3a24-404e-b4da-578b7fabcd5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618084743 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.2618084743
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.495388533
Short name T154
Test name
Test status
Simulation time 4689476398 ps
CPU time 70.04 seconds
Started Jun 07 07:16:55 PM PDT 24
Finished Jun 07 07:18:12 PM PDT 24
Peak memory 200616 kb
Host smart-4e1cc804-ae1a-486d-8bbe-aeb8a0278a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495388533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.495388533
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2332215799
Short name T246
Test name
Test status
Simulation time 67106971 ps
CPU time 0.56 seconds
Started Jun 07 07:16:50 PM PDT 24
Finished Jun 07 07:16:56 PM PDT 24
Peak memory 195324 kb
Host smart-e9c273c2-65ef-417d-8a29-f374362d3dfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332215799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2332215799
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.4235619873
Short name T8
Test name
Test status
Simulation time 3745589785 ps
CPU time 44.04 seconds
Started Jun 07 07:16:54 PM PDT 24
Finished Jun 07 07:17:45 PM PDT 24
Peak memory 219140 kb
Host smart-cc078df6-d057-4da2-a458-492502907ba0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4235619873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.4235619873
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3397728911
Short name T183
Test name
Test status
Simulation time 282051274 ps
CPU time 5.65 seconds
Started Jun 07 07:16:51 PM PDT 24
Finished Jun 07 07:17:02 PM PDT 24
Peak memory 200452 kb
Host smart-cff279f2-a2cb-4dc3-ba6d-570a019ecda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397728911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3397728911
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.161137211
Short name T85
Test name
Test status
Simulation time 2811200538 ps
CPU time 734.59 seconds
Started Jun 07 07:16:55 PM PDT 24
Finished Jun 07 07:29:17 PM PDT 24
Peak memory 747900 kb
Host smart-8efc8faf-7765-434a-8a18-9da460ba3010
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=161137211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.161137211
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3406765726
Short name T515
Test name
Test status
Simulation time 13543825825 ps
CPU time 113.66 seconds
Started Jun 07 07:16:54 PM PDT 24
Finished Jun 07 07:18:55 PM PDT 24
Peak memory 200544 kb
Host smart-72275356-8d00-4a2c-a604-2c36aa9363d3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406765726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3406765726
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.374351349
Short name T214
Test name
Test status
Simulation time 1736616980 ps
CPU time 9.33 seconds
Started Jun 07 07:16:50 PM PDT 24
Finished Jun 07 07:17:05 PM PDT 24
Peak memory 200424 kb
Host smart-87c0fb5d-0d7c-4ce0-852b-810ef0c3b603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374351349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.374351349
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.664543214
Short name T177
Test name
Test status
Simulation time 2115261565 ps
CPU time 9.2 seconds
Started Jun 07 07:16:51 PM PDT 24
Finished Jun 07 07:17:06 PM PDT 24
Peak memory 200416 kb
Host smart-3873e458-f8aa-4b77-ac8a-4ea8ada7b94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664543214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.664543214
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.3604189485
Short name T229
Test name
Test status
Simulation time 18396079731 ps
CPU time 257.79 seconds
Started Jun 07 07:16:53 PM PDT 24
Finished Jun 07 07:21:18 PM PDT 24
Peak memory 200532 kb
Host smart-44cfbf29-951b-4542-8575-07cfbb4538f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604189485 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3604189485
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.4238062833
Short name T125
Test name
Test status
Simulation time 34356258 ps
CPU time 1.31 seconds
Started Jun 07 07:16:55 PM PDT 24
Finished Jun 07 07:17:03 PM PDT 24
Peak memory 200488 kb
Host smart-43fef7f5-04e8-4a1c-a0c0-093085bf6480
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238062833 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.4238062833
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.239401988
Short name T426
Test name
Test status
Simulation time 15464084045 ps
CPU time 442.26 seconds
Started Jun 07 07:16:53 PM PDT 24
Finished Jun 07 07:24:22 PM PDT 24
Peak memory 200408 kb
Host smart-b19e6abf-94b3-4573-9e8c-b062ac356cd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239401988 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.239401988
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.4133475228
Short name T334
Test name
Test status
Simulation time 42624325885 ps
CPU time 65.49 seconds
Started Jun 07 07:16:53 PM PDT 24
Finished Jun 07 07:18:05 PM PDT 24
Peak memory 200480 kb
Host smart-af94a063-07bf-4e81-9051-11bd3d81c776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133475228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.4133475228
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2321692536
Short name T461
Test name
Test status
Simulation time 12452947 ps
CPU time 0.59 seconds
Started Jun 07 07:16:55 PM PDT 24
Finished Jun 07 07:17:02 PM PDT 24
Peak memory 195404 kb
Host smart-d5a545ec-7511-41b7-917a-295e135cb8e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321692536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2321692536
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.532043651
Short name T364
Test name
Test status
Simulation time 494178029 ps
CPU time 17.04 seconds
Started Jun 07 07:16:52 PM PDT 24
Finished Jun 07 07:17:15 PM PDT 24
Peak memory 214984 kb
Host smart-2c81c675-66ec-4848-ba1a-e19ce961c0eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=532043651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.532043651
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.3469600562
Short name T403
Test name
Test status
Simulation time 1768288132 ps
CPU time 36.59 seconds
Started Jun 07 07:16:52 PM PDT 24
Finished Jun 07 07:17:35 PM PDT 24
Peak memory 200396 kb
Host smart-cc5cff3f-efea-4f44-bd57-6bb3cbae4a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469600562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3469600562
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.185157717
Short name T517
Test name
Test status
Simulation time 2816633142 ps
CPU time 744.08 seconds
Started Jun 07 07:16:54 PM PDT 24
Finished Jun 07 07:29:25 PM PDT 24
Peak memory 729952 kb
Host smart-d8ab5fb9-c941-486f-931c-bcc40bbafdec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=185157717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.185157717
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.547504850
Short name T349
Test name
Test status
Simulation time 138118068 ps
CPU time 2.04 seconds
Started Jun 07 07:16:56 PM PDT 24
Finished Jun 07 07:17:05 PM PDT 24
Peak memory 200176 kb
Host smart-002fd855-526a-4f8d-b856-8a48ceb1f9bc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547504850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.547504850
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.139070649
Short name T310
Test name
Test status
Simulation time 717472561 ps
CPU time 40.83 seconds
Started Jun 07 07:16:54 PM PDT 24
Finished Jun 07 07:17:42 PM PDT 24
Peak memory 200532 kb
Host smart-639fea05-8cc0-4fa6-8082-5455b917ac98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139070649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.139070649
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.4074044923
Short name T480
Test name
Test status
Simulation time 49418581 ps
CPU time 1.32 seconds
Started Jun 07 07:16:55 PM PDT 24
Finished Jun 07 07:17:04 PM PDT 24
Peak memory 200484 kb
Host smart-64c013d6-6c3d-46a2-b1e3-706a26c79984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074044923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.4074044923
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.1465318344
Short name T428
Test name
Test status
Simulation time 9644577161 ps
CPU time 442.38 seconds
Started Jun 07 07:16:51 PM PDT 24
Finished Jun 07 07:24:20 PM PDT 24
Peak memory 200488 kb
Host smart-08e5d387-c373-42a4-af49-743c55c1596f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465318344 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1465318344
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.2127227744
Short name T335
Test name
Test status
Simulation time 349682960 ps
CPU time 1.44 seconds
Started Jun 07 07:16:54 PM PDT 24
Finished Jun 07 07:17:02 PM PDT 24
Peak memory 200348 kb
Host smart-c545f149-51bd-404c-a271-a7c1834ec86f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127227744 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.2127227744
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.1653578135
Short name T18
Test name
Test status
Simulation time 8508909307 ps
CPU time 471.13 seconds
Started Jun 07 07:16:51 PM PDT 24
Finished Jun 07 07:24:48 PM PDT 24
Peak memory 200472 kb
Host smart-db7fc370-6985-4883-b885-4fb5dfb87af1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653578135 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.1653578135
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3947307548
Short name T489
Test name
Test status
Simulation time 4018615502 ps
CPU time 28.35 seconds
Started Jun 07 07:16:55 PM PDT 24
Finished Jun 07 07:17:30 PM PDT 24
Peak memory 200464 kb
Host smart-e7d2ca25-da7e-42f6-874c-a89d1fe9e898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947307548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3947307548
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.149956187
Short name T436
Test name
Test status
Simulation time 13454231 ps
CPU time 0.6 seconds
Started Jun 07 07:17:02 PM PDT 24
Finished Jun 07 07:17:13 PM PDT 24
Peak memory 196044 kb
Host smart-4ab4c98b-fa4d-4e51-b50c-762778bfd446
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149956187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.149956187
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1797294530
Short name T215
Test name
Test status
Simulation time 1895667339 ps
CPU time 16.94 seconds
Started Jun 07 07:17:05 PM PDT 24
Finished Jun 07 07:17:33 PM PDT 24
Peak memory 208568 kb
Host smart-41b5b7a7-24e7-4a31-95f1-65aa2b44e487
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1797294530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1797294530
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2405773239
Short name T153
Test name
Test status
Simulation time 958193925 ps
CPU time 25.27 seconds
Started Jun 07 07:17:02 PM PDT 24
Finished Jun 07 07:17:37 PM PDT 24
Peak memory 200400 kb
Host smart-387a1910-8c52-4ff4-83ef-a08d2b61700b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405773239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2405773239
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.858144147
Short name T274
Test name
Test status
Simulation time 952210770 ps
CPU time 46.85 seconds
Started Jun 07 07:16:58 PM PDT 24
Finished Jun 07 07:17:52 PM PDT 24
Peak memory 338704 kb
Host smart-2059b674-29bf-4ff3-b0cc-ff2272d95ccd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=858144147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.858144147
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.4243260650
Short name T525
Test name
Test status
Simulation time 21604509144 ps
CPU time 88.59 seconds
Started Jun 07 07:17:00 PM PDT 24
Finished Jun 07 07:18:36 PM PDT 24
Peak memory 200440 kb
Host smart-bff44390-a987-45e4-82a7-e7b68f63e226
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243260650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.4243260650
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1434109413
Short name T370
Test name
Test status
Simulation time 1133777229 ps
CPU time 19.18 seconds
Started Jun 07 07:17:00 PM PDT 24
Finished Jun 07 07:17:27 PM PDT 24
Peak memory 200396 kb
Host smart-1fa6fd9b-ca67-435b-9a55-8ca18c079e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434109413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1434109413
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2968919355
Short name T303
Test name
Test status
Simulation time 369863492 ps
CPU time 3.43 seconds
Started Jun 07 07:17:03 PM PDT 24
Finished Jun 07 07:17:17 PM PDT 24
Peak memory 200384 kb
Host smart-5fa4f05e-7652-479a-9a96-1612e6457504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968919355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2968919355
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.892254136
Short name T320
Test name
Test status
Simulation time 15430103199 ps
CPU time 397.43 seconds
Started Jun 07 07:16:59 PM PDT 24
Finished Jun 07 07:23:44 PM PDT 24
Peak memory 236960 kb
Host smart-136c0a23-2b1d-41f7-8c7b-2677679d353d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892254136 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.892254136
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.649117169
Short name T63
Test name
Test status
Simulation time 31981770 ps
CPU time 1.36 seconds
Started Jun 07 07:17:04 PM PDT 24
Finished Jun 07 07:17:16 PM PDT 24
Peak memory 200376 kb
Host smart-d8b41536-48e8-4236-bf7b-26fdae88f59d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649117169 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_hmac_vectors.649117169
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.3102246221
Short name T382
Test name
Test status
Simulation time 42223268694 ps
CPU time 494.56 seconds
Started Jun 07 07:17:02 PM PDT 24
Finished Jun 07 07:25:26 PM PDT 24
Peak memory 200396 kb
Host smart-c4e09c2c-e9fe-46b2-a89b-00e8af961cb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102246221 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.3102246221
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1938659798
Short name T108
Test name
Test status
Simulation time 950261513 ps
CPU time 46.87 seconds
Started Jun 07 07:17:00 PM PDT 24
Finished Jun 07 07:17:55 PM PDT 24
Peak memory 200364 kb
Host smart-2a1691ec-3c85-47e7-bc3a-255f627ec574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938659798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1938659798
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1995966084
Short name T460
Test name
Test status
Simulation time 65793574 ps
CPU time 0.57 seconds
Started Jun 07 07:16:58 PM PDT 24
Finished Jun 07 07:17:07 PM PDT 24
Peak memory 196080 kb
Host smart-17c328f8-2c62-488a-a81c-2c1d46260451
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995966084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1995966084
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3850613187
Short name T560
Test name
Test status
Simulation time 507368227 ps
CPU time 26.7 seconds
Started Jun 07 07:17:00 PM PDT 24
Finished Jun 07 07:17:35 PM PDT 24
Peak memory 216520 kb
Host smart-bfbe3cdf-3357-4223-948c-298fb0660dd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3850613187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3850613187
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.558453669
Short name T360
Test name
Test status
Simulation time 1695950080 ps
CPU time 25.59 seconds
Started Jun 07 07:17:03 PM PDT 24
Finished Jun 07 07:17:40 PM PDT 24
Peak memory 200480 kb
Host smart-5d1ffc06-779d-44f7-bb01-f0371b49185d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558453669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.558453669
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.4040371242
Short name T454
Test name
Test status
Simulation time 4453276135 ps
CPU time 252.04 seconds
Started Jun 07 07:17:01 PM PDT 24
Finished Jun 07 07:21:23 PM PDT 24
Peak memory 612816 kb
Host smart-e775320d-5fb0-4d74-b989-30ef8dff0b99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4040371242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.4040371242
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3933765497
Short name T17
Test name
Test status
Simulation time 30176862968 ps
CPU time 271.46 seconds
Started Jun 07 07:16:59 PM PDT 24
Finished Jun 07 07:21:38 PM PDT 24
Peak memory 200520 kb
Host smart-9a8bd2d0-8a88-42ce-9b86-a49d3955c0e6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933765497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3933765497
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.3207370937
Short name T368
Test name
Test status
Simulation time 294959620 ps
CPU time 6.08 seconds
Started Jun 07 07:17:01 PM PDT 24
Finished Jun 07 07:17:16 PM PDT 24
Peak memory 200352 kb
Host smart-a83a9b18-f67b-4d90-b7e6-d06a923df098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207370937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3207370937
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2877383369
Short name T486
Test name
Test status
Simulation time 1237636718 ps
CPU time 10.59 seconds
Started Jun 07 07:17:06 PM PDT 24
Finished Jun 07 07:17:29 PM PDT 24
Peak memory 200460 kb
Host smart-fe89d292-aa68-4f57-a4be-ec8d4879f3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877383369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2877383369
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.1774095593
Short name T201
Test name
Test status
Simulation time 20701580562 ps
CPU time 1284.27 seconds
Started Jun 07 07:17:06 PM PDT 24
Finished Jun 07 07:38:42 PM PDT 24
Peak memory 487148 kb
Host smart-1917763b-31ed-4c0b-bd5d-d1574dc482dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774095593 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1774095593
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.430820158
Short name T222
Test name
Test status
Simulation time 119439007 ps
CPU time 1.33 seconds
Started Jun 07 07:17:00 PM PDT 24
Finished Jun 07 07:17:10 PM PDT 24
Peak memory 200472 kb
Host smart-208bf0c0-f43b-4448-817d-ff0be3211b9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430820158 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.hmac_test_hmac_vectors.430820158
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.1904395183
Short name T192
Test name
Test status
Simulation time 8600413687 ps
CPU time 445.46 seconds
Started Jun 07 07:16:58 PM PDT 24
Finished Jun 07 07:24:31 PM PDT 24
Peak memory 200292 kb
Host smart-08cd58af-331e-4c80-9f8f-fb364265b413
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904395183 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.1904395183
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1371055967
Short name T199
Test name
Test status
Simulation time 1259951785 ps
CPU time 52.19 seconds
Started Jun 07 07:17:03 PM PDT 24
Finished Jun 07 07:18:06 PM PDT 24
Peak memory 200468 kb
Host smart-2d72e3b0-6cb4-4871-9082-a320a15c39ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371055967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1371055967
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.4039148557
Short name T301
Test name
Test status
Simulation time 11851315 ps
CPU time 0.58 seconds
Started Jun 07 07:17:03 PM PDT 24
Finished Jun 07 07:17:14 PM PDT 24
Peak memory 196384 kb
Host smart-751c94ac-64b3-492c-82d0-c47e8a749912
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039148557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.4039148557
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2615583516
Short name T79
Test name
Test status
Simulation time 5088037313 ps
CPU time 35.76 seconds
Started Jun 07 07:17:02 PM PDT 24
Finished Jun 07 07:17:47 PM PDT 24
Peak memory 200524 kb
Host smart-110839d2-131c-404b-a298-7215075a637d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615583516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2615583516
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2370280601
Short name T138
Test name
Test status
Simulation time 9385806173 ps
CPU time 577.24 seconds
Started Jun 07 07:16:58 PM PDT 24
Finished Jun 07 07:26:42 PM PDT 24
Peak memory 602604 kb
Host smart-23da2a82-636d-4edd-af3d-794e4fa0e165
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2370280601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2370280601
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.158490673
Short name T558
Test name
Test status
Simulation time 8669250095 ps
CPU time 28.64 seconds
Started Jun 07 07:17:05 PM PDT 24
Finished Jun 07 07:17:45 PM PDT 24
Peak memory 200520 kb
Host smart-254c2b64-aff9-4dc2-9693-cb43cb98d0c7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158490673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.158490673
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.2050594993
Short name T230
Test name
Test status
Simulation time 5193825538 ps
CPU time 32.14 seconds
Started Jun 07 07:17:01 PM PDT 24
Finished Jun 07 07:17:42 PM PDT 24
Peak memory 200468 kb
Host smart-03b76887-31dc-4aad-9fc3-67367052c2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050594993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.2050594993
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1939003126
Short name T471
Test name
Test status
Simulation time 104981747 ps
CPU time 2.35 seconds
Started Jun 07 07:17:00 PM PDT 24
Finished Jun 07 07:17:10 PM PDT 24
Peak memory 200392 kb
Host smart-906650a3-6c77-4352-94d4-41cfa7f4bee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939003126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1939003126
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.1734777606
Short name T316
Test name
Test status
Simulation time 60529057156 ps
CPU time 1057.49 seconds
Started Jun 07 07:16:58 PM PDT 24
Finished Jun 07 07:34:42 PM PDT 24
Peak memory 754932 kb
Host smart-d39df5f9-0a0e-4d57-bb4e-007621d79db3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734777606 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1734777606
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.4216354513
Short name T418
Test name
Test status
Simulation time 70364262 ps
CPU time 1.44 seconds
Started Jun 07 07:17:03 PM PDT 24
Finished Jun 07 07:17:14 PM PDT 24
Peak memory 200480 kb
Host smart-7f5c4e39-82e4-4216-8cf2-57d3dabd4835
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216354513 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.4216354513
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.1125763742
Short name T268
Test name
Test status
Simulation time 29122221794 ps
CPU time 407.32 seconds
Started Jun 07 07:17:03 PM PDT 24
Finished Jun 07 07:24:01 PM PDT 24
Peak memory 200448 kb
Host smart-2cdd9994-a998-48b4-bc78-5a98063931a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125763742 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.1125763742
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.2222376973
Short name T198
Test name
Test status
Simulation time 1802683840 ps
CPU time 40.47 seconds
Started Jun 07 07:17:02 PM PDT 24
Finished Jun 07 07:17:51 PM PDT 24
Peak memory 200424 kb
Host smart-f722b5f5-8f80-497d-9843-5b5327a4bdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222376973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2222376973
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3596604558
Short name T542
Test name
Test status
Simulation time 28822627 ps
CPU time 0.59 seconds
Started Jun 07 07:17:35 PM PDT 24
Finished Jun 07 07:17:38 PM PDT 24
Peak memory 196172 kb
Host smart-84867887-144b-4aa9-b633-32a13698db30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596604558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3596604558
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.2331148644
Short name T556
Test name
Test status
Simulation time 680647205 ps
CPU time 38.36 seconds
Started Jun 07 07:17:37 PM PDT 24
Finished Jun 07 07:18:19 PM PDT 24
Peak memory 233224 kb
Host smart-ee331f03-edbc-4e66-8a05-6f8d7acbc822
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2331148644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2331148644
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.3277551044
Short name T526
Test name
Test status
Simulation time 1366116146 ps
CPU time 6.88 seconds
Started Jun 07 07:17:34 PM PDT 24
Finished Jun 07 07:17:44 PM PDT 24
Peak memory 200276 kb
Host smart-89f31049-b978-4041-aca7-3e818276e28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277551044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.3277551044
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.473359672
Short name T422
Test name
Test status
Simulation time 1635712085 ps
CPU time 105.34 seconds
Started Jun 07 07:17:35 PM PDT 24
Finished Jun 07 07:19:24 PM PDT 24
Peak memory 597632 kb
Host smart-8d8ea298-215c-4f3e-b124-29ccaf6d01ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=473359672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.473359672
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.4109441614
Short name T443
Test name
Test status
Simulation time 12236956649 ps
CPU time 153.39 seconds
Started Jun 07 07:17:08 PM PDT 24
Finished Jun 07 07:19:53 PM PDT 24
Peak memory 200492 kb
Host smart-82d0d99b-1655-458a-85dc-dc2e286840cd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109441614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.4109441614
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1180845691
Short name T283
Test name
Test status
Simulation time 26955805631 ps
CPU time 93.26 seconds
Started Jun 07 07:17:03 PM PDT 24
Finished Jun 07 07:18:47 PM PDT 24
Peak memory 200444 kb
Host smart-465ec259-c961-4721-abfe-3805b3ea1acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180845691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1180845691
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3769390338
Short name T209
Test name
Test status
Simulation time 229571988 ps
CPU time 4.1 seconds
Started Jun 07 07:17:06 PM PDT 24
Finished Jun 07 07:17:21 PM PDT 24
Peak memory 200412 kb
Host smart-738f6b78-32dd-4895-94e3-9ed1da885acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769390338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3769390338
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2228830317
Short name T69
Test name
Test status
Simulation time 20031131476 ps
CPU time 643.02 seconds
Started Jun 07 07:17:34 PM PDT 24
Finished Jun 07 07:28:19 PM PDT 24
Peak memory 712744 kb
Host smart-96da72d0-02bd-4198-ab61-321a42352355
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228830317 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2228830317
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.2178891937
Short name T384
Test name
Test status
Simulation time 224365369 ps
CPU time 1.22 seconds
Started Jun 07 07:17:36 PM PDT 24
Finished Jun 07 07:17:41 PM PDT 24
Peak memory 200440 kb
Host smart-163d833d-8b60-4015-96f1-0923f945ea65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178891937 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.2178891937
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.3354108366
Short name T270
Test name
Test status
Simulation time 7931421647 ps
CPU time 444.82 seconds
Started Jun 07 07:17:38 PM PDT 24
Finished Jun 07 07:25:07 PM PDT 24
Peak memory 200424 kb
Host smart-293a04a3-f0ec-4a9d-8615-5a75de673d6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354108366 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.3354108366
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.2421914714
Short name T163
Test name
Test status
Simulation time 1152645080 ps
CPU time 22.51 seconds
Started Jun 07 07:17:38 PM PDT 24
Finished Jun 07 07:18:05 PM PDT 24
Peak memory 200516 kb
Host smart-90f83bd2-5a87-45a4-89a1-5289fab4287b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421914714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2421914714
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1414695226
Short name T219
Test name
Test status
Simulation time 28958562 ps
CPU time 0.61 seconds
Started Jun 07 07:17:38 PM PDT 24
Finished Jun 07 07:17:43 PM PDT 24
Peak memory 195364 kb
Host smart-75aa2298-ba6f-42e3-9b5b-911c40c36e31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414695226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1414695226
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2230396068
Short name T499
Test name
Test status
Simulation time 546846321 ps
CPU time 13.5 seconds
Started Jun 07 07:17:38 PM PDT 24
Finished Jun 07 07:17:55 PM PDT 24
Peak memory 216792 kb
Host smart-47168483-baa0-402c-a434-7511eb6fbdf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2230396068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2230396068
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3262718494
Short name T533
Test name
Test status
Simulation time 874605535 ps
CPU time 48.92 seconds
Started Jun 07 07:17:29 PM PDT 24
Finished Jun 07 07:18:21 PM PDT 24
Peak memory 200384 kb
Host smart-a357a7e0-b03c-4b85-bc2b-00a5b00ff85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262718494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3262718494
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1549373286
Short name T441
Test name
Test status
Simulation time 3189196195 ps
CPU time 155.29 seconds
Started Jun 07 07:17:37 PM PDT 24
Finished Jun 07 07:20:16 PM PDT 24
Peak memory 599288 kb
Host smart-5770b7d0-0ebc-40d1-927e-555614feed37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1549373286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1549373286
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.566325482
Short name T251
Test name
Test status
Simulation time 6404684672 ps
CPU time 100.2 seconds
Started Jun 07 07:17:38 PM PDT 24
Finished Jun 07 07:19:22 PM PDT 24
Peak memory 200492 kb
Host smart-f6b125e9-f177-4242-bf40-cebee70bd290
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566325482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.566325482
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.4115651980
Short name T42
Test name
Test status
Simulation time 602055243 ps
CPU time 34.43 seconds
Started Jun 07 07:17:35 PM PDT 24
Finished Jun 07 07:18:12 PM PDT 24
Peak memory 200352 kb
Host smart-2b8869aa-e2cc-41af-8d76-bd99eda8d9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115651980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.4115651980
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3689023993
Short name T3
Test name
Test status
Simulation time 811799079 ps
CPU time 7.33 seconds
Started Jun 07 07:17:39 PM PDT 24
Finished Jun 07 07:17:50 PM PDT 24
Peak memory 200412 kb
Host smart-2aad7728-3bf6-4d1c-a13c-ea23dd48cc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689023993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3689023993
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.1331668324
Short name T249
Test name
Test status
Simulation time 128513430953 ps
CPU time 604.38 seconds
Started Jun 07 07:17:37 PM PDT 24
Finished Jun 07 07:27:45 PM PDT 24
Peak memory 200408 kb
Host smart-da52cf0d-4631-4007-a382-019fb76ff1c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331668324 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.1331668324
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.3114693341
Short name T186
Test name
Test status
Simulation time 140630377 ps
CPU time 1.13 seconds
Started Jun 07 07:17:36 PM PDT 24
Finished Jun 07 07:17:41 PM PDT 24
Peak memory 200412 kb
Host smart-7852077c-dd4a-4d59-8bbc-36e113a24f22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114693341 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.3114693341
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.3468778183
Short name T434
Test name
Test status
Simulation time 8179798724 ps
CPU time 447.08 seconds
Started Jun 07 07:17:37 PM PDT 24
Finished Jun 07 07:25:08 PM PDT 24
Peak memory 200332 kb
Host smart-4f9d3874-3601-4411-a448-5ebf8faf0081
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468778183 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.3468778183
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.493105904
Short name T129
Test name
Test status
Simulation time 103787015 ps
CPU time 3.34 seconds
Started Jun 07 07:17:36 PM PDT 24
Finished Jun 07 07:17:42 PM PDT 24
Peak memory 200404 kb
Host smart-bcfcd9e7-7228-4aa6-8a28-7e965ef2975b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493105904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.493105904
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1149215860
Short name T184
Test name
Test status
Simulation time 13643261 ps
CPU time 0.58 seconds
Started Jun 07 07:17:51 PM PDT 24
Finished Jun 07 07:18:01 PM PDT 24
Peak memory 196324 kb
Host smart-75360b85-92d5-49e0-81fd-2baed54a070f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149215860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1149215860
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.4120783415
Short name T336
Test name
Test status
Simulation time 21248321 ps
CPU time 1.35 seconds
Started Jun 07 07:17:37 PM PDT 24
Finished Jun 07 07:17:43 PM PDT 24
Peak memory 200188 kb
Host smart-939d5ad2-c8aa-4c68-9e7a-74b010722749
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4120783415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.4120783415
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3380859937
Short name T83
Test name
Test status
Simulation time 9369134087 ps
CPU time 40.81 seconds
Started Jun 07 07:17:37 PM PDT 24
Finished Jun 07 07:18:22 PM PDT 24
Peak memory 200460 kb
Host smart-dc9f4d6b-d775-4d36-9b09-75f3beedbe95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380859937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3380859937
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.1878171138
Short name T476
Test name
Test status
Simulation time 1535004491 ps
CPU time 399.85 seconds
Started Jun 07 07:17:36 PM PDT 24
Finished Jun 07 07:24:19 PM PDT 24
Peak memory 652024 kb
Host smart-6bd9e4a2-93eb-4935-876e-986b1b8ac63b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1878171138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1878171138
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1944780067
Short name T347
Test name
Test status
Simulation time 4423205944 ps
CPU time 66.37 seconds
Started Jun 07 07:17:36 PM PDT 24
Finished Jun 07 07:18:46 PM PDT 24
Peak memory 200456 kb
Host smart-cc96121b-57b5-4f18-96a4-309b579e71dd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944780067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1944780067
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2262693887
Short name T266
Test name
Test status
Simulation time 1766561109 ps
CPU time 13 seconds
Started Jun 07 07:17:37 PM PDT 24
Finished Jun 07 07:17:54 PM PDT 24
Peak memory 200520 kb
Host smart-d0e24f0d-26fd-42e0-8891-4fd379860790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262693887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2262693887
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2396668382
Short name T235
Test name
Test status
Simulation time 120868698 ps
CPU time 2.95 seconds
Started Jun 07 07:17:36 PM PDT 24
Finished Jun 07 07:17:42 PM PDT 24
Peak memory 200440 kb
Host smart-ff3fdc52-32f3-45fa-a614-e74f863f8386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396668382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2396668382
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2346665690
Short name T522
Test name
Test status
Simulation time 358187870764 ps
CPU time 3251.4 seconds
Started Jun 07 07:17:36 PM PDT 24
Finished Jun 07 08:11:51 PM PDT 24
Peak memory 731952 kb
Host smart-10ef96f6-4563-47c5-89f5-a3038e5a7840
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346665690 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2346665690
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.182626458
Short name T1
Test name
Test status
Simulation time 65449327 ps
CPU time 1.43 seconds
Started Jun 07 07:17:35 PM PDT 24
Finished Jun 07 07:17:39 PM PDT 24
Peak memory 200472 kb
Host smart-c7ba1323-b2a9-4b25-8a3b-6f9cdb034328
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182626458 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_hmac_vectors.182626458
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.4258507861
Short name T247
Test name
Test status
Simulation time 18374665356 ps
CPU time 495.94 seconds
Started Jun 07 07:17:37 PM PDT 24
Finished Jun 07 07:25:57 PM PDT 24
Peak memory 200424 kb
Host smart-59edad4c-d830-41a3-9984-82c3e59304da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258507861 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.4258507861
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2188069328
Short name T217
Test name
Test status
Simulation time 2193349082 ps
CPU time 24.36 seconds
Started Jun 07 07:17:37 PM PDT 24
Finished Jun 07 07:18:06 PM PDT 24
Peak memory 200492 kb
Host smart-18c6c542-a4d0-4693-aad3-632cb2ed5159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188069328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2188069328
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2032215353
Short name T269
Test name
Test status
Simulation time 11237964 ps
CPU time 0.57 seconds
Started Jun 07 07:17:51 PM PDT 24
Finished Jun 07 07:17:59 PM PDT 24
Peak memory 195352 kb
Host smart-7f6a2552-5d8f-4433-8b2f-0277cf0b2b6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032215353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2032215353
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.845726431
Short name T328
Test name
Test status
Simulation time 1856571381 ps
CPU time 54.04 seconds
Started Jun 07 07:17:55 PM PDT 24
Finished Jun 07 07:19:00 PM PDT 24
Peak memory 233096 kb
Host smart-ec163638-984d-4b18-ad97-27ce2f88c3b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=845726431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.845726431
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3866816985
Short name T378
Test name
Test status
Simulation time 2458914826 ps
CPU time 54.42 seconds
Started Jun 07 07:17:53 PM PDT 24
Finished Jun 07 07:18:57 PM PDT 24
Peak memory 200476 kb
Host smart-d482de01-e87a-478e-af66-0cfb95014c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866816985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3866816985
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2627019459
Short name T358
Test name
Test status
Simulation time 18544903367 ps
CPU time 1241.6 seconds
Started Jun 07 07:17:53 PM PDT 24
Finished Jun 07 07:38:44 PM PDT 24
Peak memory 784952 kb
Host smart-be259b2b-9b32-4fbb-9db2-02335e93fa6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2627019459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2627019459
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.1409535366
Short name T317
Test name
Test status
Simulation time 4040890834 ps
CPU time 113.98 seconds
Started Jun 07 07:17:53 PM PDT 24
Finished Jun 07 07:19:57 PM PDT 24
Peak memory 200440 kb
Host smart-87deb481-122e-4e62-8764-b040c31c42c4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409535366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1409535366
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.3741269664
Short name T67
Test name
Test status
Simulation time 661330355 ps
CPU time 12.16 seconds
Started Jun 07 07:17:52 PM PDT 24
Finished Jun 07 07:18:14 PM PDT 24
Peak memory 200436 kb
Host smart-2d141264-fc77-40b2-82be-0ba7428b7162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741269664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3741269664
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3182534196
Short name T595
Test name
Test status
Simulation time 156926158 ps
CPU time 6.02 seconds
Started Jun 07 07:17:52 PM PDT 24
Finished Jun 07 07:18:07 PM PDT 24
Peak memory 200416 kb
Host smart-20d13c4e-a019-4038-a822-400086d0e6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182534196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3182534196
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2218307897
Short name T294
Test name
Test status
Simulation time 22232934081 ps
CPU time 847.34 seconds
Started Jun 07 07:17:55 PM PDT 24
Finished Jun 07 07:32:13 PM PDT 24
Peak memory 619672 kb
Host smart-bb739652-0a36-4edd-bfc8-f523c7822303
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218307897 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2218307897
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.1538246415
Short name T169
Test name
Test status
Simulation time 91851630 ps
CPU time 1.22 seconds
Started Jun 07 07:17:54 PM PDT 24
Finished Jun 07 07:18:06 PM PDT 24
Peak memory 200420 kb
Host smart-1921f9b7-7031-47c2-b53e-c426abd3610e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538246415 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.1538246415
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.495906910
Short name T148
Test name
Test status
Simulation time 113235999989 ps
CPU time 520.15 seconds
Started Jun 07 07:17:55 PM PDT 24
Finished Jun 07 07:26:46 PM PDT 24
Peak memory 200360 kb
Host smart-615008bb-6113-4cf5-b02b-d63f7123e61b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495906910 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.495906910
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1210255363
Short name T175
Test name
Test status
Simulation time 596815978 ps
CPU time 28 seconds
Started Jun 07 07:17:56 PM PDT 24
Finished Jun 07 07:18:34 PM PDT 24
Peak memory 200428 kb
Host smart-bb6ce3b8-2f95-41fc-a950-b901d5b888fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210255363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1210255363
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.3138329819
Short name T257
Test name
Test status
Simulation time 21330821 ps
CPU time 0.6 seconds
Started Jun 07 07:15:26 PM PDT 24
Finished Jun 07 07:15:34 PM PDT 24
Peak memory 196016 kb
Host smart-7e37c54f-19b2-43af-9e32-806c8e8e992a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138329819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3138329819
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2839239079
Short name T244
Test name
Test status
Simulation time 6641639641 ps
CPU time 36.41 seconds
Started Jun 07 07:15:20 PM PDT 24
Finished Jun 07 07:15:59 PM PDT 24
Peak memory 208632 kb
Host smart-7315c4cb-e0b6-4df3-83d2-0efba89e7a4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2839239079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2839239079
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.2269031618
Short name T523
Test name
Test status
Simulation time 963789991 ps
CPU time 12.43 seconds
Started Jun 07 07:15:22 PM PDT 24
Finished Jun 07 07:15:38 PM PDT 24
Peak memory 200372 kb
Host smart-a2d93dd6-9347-4f8a-95e2-bf3c0367258a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269031618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.2269031618
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.886946943
Short name T292
Test name
Test status
Simulation time 1798150603 ps
CPU time 390.84 seconds
Started Jun 07 07:15:24 PM PDT 24
Finished Jun 07 07:22:01 PM PDT 24
Peak memory 484448 kb
Host smart-a5542915-c237-4d1a-b01b-12bd9459dc54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=886946943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.886946943
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.117244130
Short name T305
Test name
Test status
Simulation time 8692782789 ps
CPU time 110.76 seconds
Started Jun 07 07:15:23 PM PDT 24
Finished Jun 07 07:17:19 PM PDT 24
Peak memory 200492 kb
Host smart-c461c033-4c03-463f-aaca-5da762648c44
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117244130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.117244130
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.1288635363
Short name T439
Test name
Test status
Simulation time 16110126487 ps
CPU time 80.65 seconds
Started Jun 07 07:15:13 PM PDT 24
Finished Jun 07 07:16:36 PM PDT 24
Peak memory 200464 kb
Host smart-9fa8746b-2ea1-4f74-9099-2d7726f7fd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288635363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1288635363
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1035160204
Short name T89
Test name
Test status
Simulation time 36625305 ps
CPU time 1.25 seconds
Started Jun 07 07:15:18 PM PDT 24
Finished Jun 07 07:15:22 PM PDT 24
Peak memory 200384 kb
Host smart-7cf83dcb-9cea-48fa-9796-118d9cb5b412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035160204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1035160204
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.861490135
Short name T553
Test name
Test status
Simulation time 27509752177 ps
CPU time 739.13 seconds
Started Jun 07 07:15:24 PM PDT 24
Finished Jun 07 07:27:49 PM PDT 24
Peak memory 529596 kb
Host smart-62eaebdd-5686-4caa-8e69-dad63deeee8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861490135 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.861490135
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.2920213067
Short name T227
Test name
Test status
Simulation time 43369954 ps
CPU time 1.13 seconds
Started Jun 07 07:15:22 PM PDT 24
Finished Jun 07 07:15:28 PM PDT 24
Peak memory 200240 kb
Host smart-2bdd5502-99a8-488f-93f0-cfa56fdba368
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920213067 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.2920213067
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.1995311697
Short name T587
Test name
Test status
Simulation time 27331837742 ps
CPU time 507.4 seconds
Started Jun 07 07:15:27 PM PDT 24
Finished Jun 07 07:24:01 PM PDT 24
Peak memory 200444 kb
Host smart-74d121fe-ca2c-4a0c-9a08-3622a13eb4e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995311697 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.1995311697
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.259877300
Short name T132
Test name
Test status
Simulation time 3574906979 ps
CPU time 55.38 seconds
Started Jun 07 07:15:26 PM PDT 24
Finished Jun 07 07:16:28 PM PDT 24
Peak memory 200472 kb
Host smart-192f33c7-eb4d-455b-a8f5-1de4b0965e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259877300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.259877300
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1518271913
Short name T313
Test name
Test status
Simulation time 15173716 ps
CPU time 0.63 seconds
Started Jun 07 07:15:26 PM PDT 24
Finished Jun 07 07:15:33 PM PDT 24
Peak memory 196352 kb
Host smart-fa21cfe8-1e26-49f8-af6e-8ca00bdcb165
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518271913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1518271913
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3621690628
Short name T388
Test name
Test status
Simulation time 2663603154 ps
CPU time 55.11 seconds
Started Jun 07 07:15:24 PM PDT 24
Finished Jun 07 07:16:25 PM PDT 24
Peak memory 231208 kb
Host smart-68b5a6c9-4cbf-4b0f-9312-841221f4cc9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3621690628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3621690628
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.2605555741
Short name T538
Test name
Test status
Simulation time 721574973 ps
CPU time 33.79 seconds
Started Jun 07 07:15:24 PM PDT 24
Finished Jun 07 07:16:04 PM PDT 24
Peak memory 200396 kb
Host smart-cda064f4-cb53-4737-a8da-f50ce6b99e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605555741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2605555741
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3395597892
Short name T287
Test name
Test status
Simulation time 19284976024 ps
CPU time 402.25 seconds
Started Jun 07 07:15:23 PM PDT 24
Finished Jun 07 07:22:11 PM PDT 24
Peak memory 656160 kb
Host smart-fdfb1951-f300-455b-a62c-3fad89021dd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3395597892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3395597892
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.2486177108
Short name T155
Test name
Test status
Simulation time 3059155064 ps
CPU time 152.81 seconds
Started Jun 07 07:15:22 PM PDT 24
Finished Jun 07 07:18:00 PM PDT 24
Peak memory 200484 kb
Host smart-25785cb9-e5bc-4b18-b469-598b6ccc8dc1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486177108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2486177108
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1031756167
Short name T590
Test name
Test status
Simulation time 636252717 ps
CPU time 13.65 seconds
Started Jun 07 07:15:28 PM PDT 24
Finished Jun 07 07:15:48 PM PDT 24
Peak memory 200412 kb
Host smart-4799a880-f7d5-4d54-944f-f27ee9cb56dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031756167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1031756167
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3136057374
Short name T524
Test name
Test status
Simulation time 404484080 ps
CPU time 4.67 seconds
Started Jun 07 07:15:22 PM PDT 24
Finished Jun 07 07:15:31 PM PDT 24
Peak memory 200428 kb
Host smart-e1d3b0fd-831e-46aa-aeeb-3b68ac336767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136057374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3136057374
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.3460855174
Short name T101
Test name
Test status
Simulation time 11864894961 ps
CPU time 1814.93 seconds
Started Jun 07 07:15:25 PM PDT 24
Finished Jun 07 07:45:46 PM PDT 24
Peak memory 792276 kb
Host smart-763d3ebb-1f0e-454f-8e93-afd929e161ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460855174 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3460855174
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.619669042
Short name T319
Test name
Test status
Simulation time 30133345 ps
CPU time 1.12 seconds
Started Jun 07 07:15:21 PM PDT 24
Finished Jun 07 07:15:25 PM PDT 24
Peak memory 200252 kb
Host smart-3e33cf39-228d-4fec-9d75-0933cadcf6d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619669042 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_hmac_vectors.619669042
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.700829895
Short name T444
Test name
Test status
Simulation time 10425567943 ps
CPU time 548.01 seconds
Started Jun 07 07:15:23 PM PDT 24
Finished Jun 07 07:24:36 PM PDT 24
Peak memory 200404 kb
Host smart-80c8a6aa-fc3f-41bf-8c9e-0ee5c76671d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700829895 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.700829895
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2999598545
Short name T409
Test name
Test status
Simulation time 3992454748 ps
CPU time 75.77 seconds
Started Jun 07 07:15:22 PM PDT 24
Finished Jun 07 07:16:43 PM PDT 24
Peak memory 200476 kb
Host smart-64c9729e-bf05-4998-a1b7-caf02b96e33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999598545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2999598545
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3836316147
Short name T326
Test name
Test status
Simulation time 44784836 ps
CPU time 0.62 seconds
Started Jun 07 07:15:22 PM PDT 24
Finished Jun 07 07:15:28 PM PDT 24
Peak memory 196388 kb
Host smart-e15024cc-f0ee-4e9b-9e89-af030fcbad00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836316147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3836316147
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.4048457562
Short name T312
Test name
Test status
Simulation time 407172095 ps
CPU time 18.97 seconds
Started Jun 07 07:15:23 PM PDT 24
Finished Jun 07 07:15:47 PM PDT 24
Peak memory 200452 kb
Host smart-e7e2857e-ddaa-45b4-9d1e-43d154fdec9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4048457562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.4048457562
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.4185502938
Short name T545
Test name
Test status
Simulation time 1296493533 ps
CPU time 10.21 seconds
Started Jun 07 07:15:23 PM PDT 24
Finished Jun 07 07:15:38 PM PDT 24
Peak memory 200400 kb
Host smart-93a6030c-c343-47e0-802c-9579363dde24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185502938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.4185502938
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.997169569
Short name T397
Test name
Test status
Simulation time 5369750350 ps
CPU time 123.23 seconds
Started Jun 07 07:15:21 PM PDT 24
Finished Jun 07 07:17:29 PM PDT 24
Peak memory 432328 kb
Host smart-a1464545-8b5e-4fde-ab7c-ef51d0933d39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=997169569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.997169569
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1850694714
Short name T435
Test name
Test status
Simulation time 11968962927 ps
CPU time 37.22 seconds
Started Jun 07 07:15:22 PM PDT 24
Finished Jun 07 07:16:03 PM PDT 24
Peak memory 200444 kb
Host smart-d6101960-20d6-4714-86b9-0d7a8b019e97
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850694714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1850694714
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.254356633
Short name T150
Test name
Test status
Simulation time 2995024378 ps
CPU time 45.14 seconds
Started Jun 07 07:15:23 PM PDT 24
Finished Jun 07 07:16:14 PM PDT 24
Peak memory 200492 kb
Host smart-53c706bb-df15-49dc-ae17-7fb62ad5902a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254356633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.254356633
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.576983649
Short name T510
Test name
Test status
Simulation time 505313078 ps
CPU time 7.69 seconds
Started Jun 07 07:15:23 PM PDT 24
Finished Jun 07 07:15:36 PM PDT 24
Peak memory 200432 kb
Host smart-beafec80-132e-4b4a-bef8-0b8e0637f6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576983649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.576983649
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1916461956
Short name T271
Test name
Test status
Simulation time 20976307547 ps
CPU time 1165.71 seconds
Started Jun 07 07:15:21 PM PDT 24
Finished Jun 07 07:34:51 PM PDT 24
Peak memory 210732 kb
Host smart-a45eb685-5863-4f22-b421-b5cc196a44b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916461956 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1916461956
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.3188299239
Short name T206
Test name
Test status
Simulation time 136770256 ps
CPU time 1.2 seconds
Started Jun 07 07:15:28 PM PDT 24
Finished Jun 07 07:15:35 PM PDT 24
Peak memory 200372 kb
Host smart-ba61294c-818b-4732-9a1d-b53482d6c092
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188299239 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.3188299239
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.2061862402
Short name T416
Test name
Test status
Simulation time 195127214234 ps
CPU time 615.7 seconds
Started Jun 07 07:15:22 PM PDT 24
Finished Jun 07 07:25:43 PM PDT 24
Peak memory 200508 kb
Host smart-e7d14b4e-8620-45fc-800e-01bd0e9e9e4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061862402 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.2061862402
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.4047814634
Short name T537
Test name
Test status
Simulation time 1228203495 ps
CPU time 28.09 seconds
Started Jun 07 07:15:24 PM PDT 24
Finished Jun 07 07:15:58 PM PDT 24
Peak memory 200404 kb
Host smart-a4281854-359a-4993-9249-5c8de1edaefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047814634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.4047814634
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2222460967
Short name T535
Test name
Test status
Simulation time 24750962 ps
CPU time 0.6 seconds
Started Jun 07 07:15:22 PM PDT 24
Finished Jun 07 07:15:28 PM PDT 24
Peak memory 196296 kb
Host smart-152d07cd-8a99-4ffe-93b4-8ab03f8d2ea0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222460967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2222460967
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1108273095
Short name T5
Test name
Test status
Simulation time 2605980398 ps
CPU time 29.18 seconds
Started Jun 07 07:15:24 PM PDT 24
Finished Jun 07 07:16:00 PM PDT 24
Peak memory 216892 kb
Host smart-549c81ca-1dbc-4685-9b6e-d4dd3e12cd62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1108273095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1108273095
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1353979841
Short name T284
Test name
Test status
Simulation time 2387230095 ps
CPU time 33.24 seconds
Started Jun 07 07:15:17 PM PDT 24
Finished Jun 07 07:15:53 PM PDT 24
Peak memory 200468 kb
Host smart-86b5c02d-3737-4948-ade0-94c75dd9a5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353979841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1353979841
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3143291667
Short name T187
Test name
Test status
Simulation time 8359191710 ps
CPU time 404.79 seconds
Started Jun 07 07:15:24 PM PDT 24
Finished Jun 07 07:22:14 PM PDT 24
Peak memory 653376 kb
Host smart-18388876-c695-42b0-ac1b-2302aa63ebdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3143291667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3143291667
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.1094569206
Short name T354
Test name
Test status
Simulation time 2747903848 ps
CPU time 26.58 seconds
Started Jun 07 07:15:28 PM PDT 24
Finished Jun 07 07:16:01 PM PDT 24
Peak memory 200428 kb
Host smart-702f10a1-159c-44a2-9bc0-a436658463a1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094569206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1094569206
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.2264021422
Short name T386
Test name
Test status
Simulation time 215063863 ps
CPU time 3.78 seconds
Started Jun 07 07:15:26 PM PDT 24
Finished Jun 07 07:15:37 PM PDT 24
Peak memory 200204 kb
Host smart-7a8314b8-35fc-4ca2-87f7-d1436cac3708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264021422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.2264021422
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3976518837
Short name T135
Test name
Test status
Simulation time 418505954 ps
CPU time 3.39 seconds
Started Jun 07 07:15:24 PM PDT 24
Finished Jun 07 07:15:33 PM PDT 24
Peak memory 200372 kb
Host smart-21b91e8b-144b-4a36-b9ce-97e5107d1deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976518837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3976518837
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2027175696
Short name T239
Test name
Test status
Simulation time 133337291499 ps
CPU time 1826.06 seconds
Started Jun 07 07:15:21 PM PDT 24
Finished Jun 07 07:45:51 PM PDT 24
Peak memory 284336 kb
Host smart-dcd16be4-4df9-4ba1-b3e6-96d77a4511c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027175696 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2027175696
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.1495985938
Short name T131
Test name
Test status
Simulation time 53177219 ps
CPU time 1.09 seconds
Started Jun 07 07:15:23 PM PDT 24
Finished Jun 07 07:15:29 PM PDT 24
Peak memory 200160 kb
Host smart-2df2939d-a6f5-4dbf-abf0-16016c133655
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495985938 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.1495985938
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.3199385659
Short name T490
Test name
Test status
Simulation time 9568738014 ps
CPU time 510.58 seconds
Started Jun 07 07:15:26 PM PDT 24
Finished Jun 07 07:24:04 PM PDT 24
Peak memory 200448 kb
Host smart-6015a87e-21e5-4ec5-a98f-fbd8509264ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199385659 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.3199385659
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.805053958
Short name T278
Test name
Test status
Simulation time 15600322 ps
CPU time 0.8 seconds
Started Jun 07 07:15:23 PM PDT 24
Finished Jun 07 07:15:28 PM PDT 24
Peak memory 198292 kb
Host smart-c382a8e7-477e-4eaf-b680-cca220515978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805053958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.805053958
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/88.hmac_stress_all_with_rand_reset.1776694684
Short name T28
Test name
Test status
Simulation time 101089794682 ps
CPU time 1239.55 seconds
Started Jun 07 07:17:56 PM PDT 24
Finished Jun 07 07:38:48 PM PDT 24
Peak memory 478412 kb
Host smart-a31f246d-f9fd-4675-91e9-e62420d5a1b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1776694684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.hmac_stress_all_with_rand_reset.1776694684
Directory /workspace/88.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1273026245
Short name T385
Test name
Test status
Simulation time 16534544 ps
CPU time 0.59 seconds
Started Jun 07 07:15:34 PM PDT 24
Finished Jun 07 07:15:41 PM PDT 24
Peak memory 196356 kb
Host smart-81bba1e0-666d-4702-aeb2-0b4644a27ecd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273026245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1273026245
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2029506499
Short name T232
Test name
Test status
Simulation time 70525083 ps
CPU time 1.9 seconds
Started Jun 07 07:15:22 PM PDT 24
Finished Jun 07 07:15:28 PM PDT 24
Peak memory 200464 kb
Host smart-229fbd90-7dfb-4b1c-88c9-beb9dc73c059
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2029506499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2029506499
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.908077586
Short name T572
Test name
Test status
Simulation time 1099141067 ps
CPU time 54.36 seconds
Started Jun 07 07:15:23 PM PDT 24
Finished Jun 07 07:16:23 PM PDT 24
Peak memory 200352 kb
Host smart-e4780500-083c-4de0-8817-e2022b895f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908077586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.908077586
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.993423655
Short name T178
Test name
Test status
Simulation time 4009622385 ps
CPU time 1035.25 seconds
Started Jun 07 07:15:27 PM PDT 24
Finished Jun 07 07:32:49 PM PDT 24
Peak memory 771992 kb
Host smart-b92f9dae-80a0-4699-abb6-844694b0e636
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=993423655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.993423655
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.2492462791
Short name T288
Test name
Test status
Simulation time 16560333238 ps
CPU time 154.68 seconds
Started Jun 07 07:15:22 PM PDT 24
Finished Jun 07 07:18:02 PM PDT 24
Peak memory 200496 kb
Host smart-471ef9c2-f3d1-4d7f-8ba8-c11d24b7e4ae
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492462791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2492462791
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.2706285666
Short name T173
Test name
Test status
Simulation time 5346757632 ps
CPU time 104.13 seconds
Started Jun 07 07:15:26 PM PDT 24
Finished Jun 07 07:17:17 PM PDT 24
Peak memory 200452 kb
Host smart-97ea0223-ff34-491a-9663-505298ca03fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706285666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2706285666
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.100436242
Short name T295
Test name
Test status
Simulation time 1260176849 ps
CPU time 8.96 seconds
Started Jun 07 07:15:23 PM PDT 24
Finished Jun 07 07:15:36 PM PDT 24
Peak memory 200384 kb
Host smart-29e41593-5db4-49db-935c-7aec4c91f224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100436242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.100436242
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1165376058
Short name T262
Test name
Test status
Simulation time 49145141349 ps
CPU time 822.15 seconds
Started Jun 07 07:15:31 PM PDT 24
Finished Jun 07 07:29:19 PM PDT 24
Peak memory 216104 kb
Host smart-3c777523-cdd8-456f-b238-9d551c949b2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165376058 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1165376058
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.1647213511
Short name T171
Test name
Test status
Simulation time 117878671 ps
CPU time 1.28 seconds
Started Jun 07 07:15:28 PM PDT 24
Finished Jun 07 07:15:36 PM PDT 24
Peak memory 200240 kb
Host smart-21a95e20-f321-4d5a-bc5e-f206c21f7c41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647213511 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.1647213511
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.445484441
Short name T254
Test name
Test status
Simulation time 158120744074 ps
CPU time 525.25 seconds
Started Jun 07 07:15:24 PM PDT 24
Finished Jun 07 07:24:15 PM PDT 24
Peak memory 200400 kb
Host smart-3d3e1603-5210-4596-87a4-fcd301876631
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445484441 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.445484441
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.1591901176
Short name T566
Test name
Test status
Simulation time 4037876809 ps
CPU time 67.82 seconds
Started Jun 07 07:15:26 PM PDT 24
Finished Jun 07 07:16:41 PM PDT 24
Peak memory 200492 kb
Host smart-ca7eb99c-68e7-49e4-932f-e1e2ad56b15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591901176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1591901176
Directory /workspace/9.hmac_wipe_secret/latest
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