Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15397583	1			T1	96		T2	617		T4	30483
all_values[1]	15397583	1			T1	96		T2	617		T4	30483
all_values[2]	15397583	1			T1	96		T2	617		T4	30483

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

187551

1

T1

2

T4

3409

T5

2

auto[1]

46005198

1

T1

286

T2

1851

T4

88040

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38500419

1

T1

236

T2

1789

T4

64858

auto[1]

7692330

1

T1

52

T2

62

T4

26591

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	71274	1			T9	2		T20	2		T88	16
all_values[0]	auto[0]	auto[1]	350	1			T71	2		T25	2		T89	2
all_values[0]	auto[1]	auto[0]	15287786	1			T1	64		T2	575		T4	30477
all_values[0]	auto[1]	auto[1]	38173	1			T1	32		T2	42		T4	6
all_values[1]	auto[0]	auto[0]	63930	1			T1	2		T7	428		T101	844
all_values[1]	auto[0]	auto[1]	159	1			T26	1		T36	5		T11	8
all_values[1]	auto[1]	auto[0]	15333204	1			T1	94		T2	617		T4	30483
all_values[1]	auto[1]	auto[1]	290	1			T26	1		T27	2		T40	4
all_values[2]	auto[0]	auto[0]	29924	1			T4	1		T5	2		T70	1
all_values[2]	auto[0]	auto[1]	21914	1			T4	3408		T70	2		T88	15
all_values[2]	auto[1]	auto[0]	7714301	1			T1	76		T2	597		T4	3897
all_values[2]	auto[1]	auto[1]	7631444	1			T1	20		T2	20		T4	23177